[all-commits] [llvm/llvm-project] 785b16: [RISCV][GISel] Support G_MERGE_VALUES/G_UNMERGE_VA...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 785b16ad04a741dce65ebaa11ee86d9dd19dd699
      https://github.com/llvm/llvm-project/commit/785b16ad04a741dce65ebaa11ee86d9dd19dd699
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2025-01-07 (Tue, 07 Jan 2025)

  Changed paths:
    M llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
    M llvm/lib/Target/RISCV/RISCVInstrInfoD.td
    M llvm/test/CodeGen/RISCV/GlobalISel/double-zfa.ll

  Log Message:
  -----------
  [RISCV][GISel] Support G_MERGE_VALUES/G_UNMERGE_VALUES with Zfa. (#120379)

Without Zfa we use pseudos that are lowered to a stack load/store. With
Zfa we have instructions that can move a pair of registers to an FPR. Or
move the high or low half of an FPR to a GPR.

I've used a GINodeEquiv to make use of 3 of the 4 tablegen patterns. The
split case with Zfa requires 2 instructions which I'm doing through
custom isel like we do in SelectionDAG.



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