[all-commits] [llvm/llvm-project] 1729e6: [AArch64] Improve bf16 fp_extend lowering. (#118966)

[David Green via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 1729e6e742ba9f6f210550000ace4bec72530c2e
      https://github.com/llvm/llvm-project/commit/1729e6e742ba9f6f210550000ace4bec72530c2e
  Author: David Green <david.green at arm.com>
  Date:   2025-01-07 (Tue, 07 Jan 2025)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
    M llvm/lib/Target/AArch64/AArch64InstrInfo.td
    M llvm/test/CodeGen/AArch64/arm64-fast-isel-conversion-fallback.ll
    M llvm/test/CodeGen/AArch64/atomicrmw-fadd.ll
    M llvm/test/CodeGen/AArch64/atomicrmw-fmax.ll
    M llvm/test/CodeGen/AArch64/atomicrmw-fmin.ll
    M llvm/test/CodeGen/AArch64/atomicrmw-fsub.ll
    M llvm/test/CodeGen/AArch64/bf16-instructions.ll
    M llvm/test/CodeGen/AArch64/bf16-v8-instructions.ll
    M llvm/test/CodeGen/AArch64/cvt-fp-int-fp.ll
    M llvm/test/CodeGen/AArch64/round-fptosi-sat-scalar.ll

  Log Message:
  -----------
  [AArch64] Improve bf16 fp_extend lowering. (#118966)

A bf16 fp_extend is just a shift into the higher bits. This changes the
lowering from using a relatively ugly tablegen pattern, to ISel
generating the shift using an extended vector. This is cleaner and
should optimize better. StrictFP goes through the same route as it
cannot round or set flags.



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