[all-commits] [llvm/llvm-project] 8cd94e: [mlir][Affine] Add nsw to lowering of `AffineMulEx...

[MaheshRavishankar via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 8cd94e0b6d18b6b454431ba9481c2489b480baf4
      https://github.com/llvm/llvm-project/commit/8cd94e0b6d18b6b454431ba9481c2489b480baf4
  Author: MaheshRavishankar <1663364+MaheshRavishankar at users.noreply.github.com>
  Date:   2025-01-06 (Mon, 06 Jan 2025)

  Changed paths:
    M mlir/lib/Dialect/Affine/Utils/Utils.cpp
    M mlir/test/Conversion/AffineToStandard/lower-affine-to-vector.mlir
    M mlir/test/Conversion/AffineToStandard/lower-affine.mlir
    M mlir/test/Conversion/MemRefToLLVM/expand-then-convert-to-llvm.mlir
    M mlir/test/Dialect/LLVM/lower-to-llvm-e2e-with-target-tag.mlir
    M mlir/test/Dialect/LLVM/lower-to-llvm-e2e-with-top-level-named-sequence.mlir

  Log Message:
  -----------
  [mlir][Affine] Add nsw to lowering of `AffineMulExpr`. (#121535)

Since index operations have no set bitwidth, it is ill-defined to use
signed/unsigned wrapping behavior. The corollary to which is that it is
always safe to add nsw/nuw to lowering of affine ops.

Also add a folder to fold `div(s|u)i (mul (a, v), v) -> a`

Signed-off-by: MaheshRavishankar <mravisha at amd.com>



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