[all-commits] [llvm/llvm-project] 6cf5ac: RegAllocGreedy: Fix subrange based instruction spl...

[Matt Arsenault via All-commits]

  Branch: refs/heads/users/arsenm/greedy-fix-subrange-instruction-split-logic
  Home:   https://github.com/llvm/llvm-project
  Commit: 6cf5acc3a55848f6f323d8798db8a32146c26a89
      https://github.com/llvm/llvm-project/commit/6cf5acc3a55848f6f323d8798db8a32146c26a89
  Author: Matt Arsenault <Matthew.Arsenault at amd.com>
  Date:   2025-01-06 (Mon, 06 Jan 2025)

  Changed paths:
    M llvm/lib/CodeGen/RegAllocGreedy.cpp
    M llvm/test/CodeGen/AMDGPU/gfx-callable-return-types.ll
    A llvm/test/CodeGen/AMDGPU/inflated-reg-class-snippet-copy-inst-reads-lane-subset-use-after-free.mir
    M llvm/test/CodeGen/AMDGPU/inflated-reg-class-snippet-copy-use-after-free.mir
    M llvm/test/CodeGen/AMDGPU/remat-smrd.mir
    M llvm/test/CodeGen/AMDGPU/splitkit-copy-live-lanes.mir
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-interleaved-access.ll
    M llvm/test/CodeGen/RISCV/rvv/vector-deinterleave-load.ll
    M llvm/test/CodeGen/RISCV/rvv/vector-deinterleave.ll

  Log Message:
  -----------
  RegAllocGreedy: Fix subrange based instruction split logic

Fix the logic for readsLaneSubset. Check at the correct point
for the use operands of the instruction, instead of the result.
Only consider the use register operands, and stop considering
whether the subranges are actually live at this point.

This avoids some unproductive splits. This also happens to avoid
a use after free due to a split of an unspillable register. That
issue still exists if the instruction does not reference the full
set of register lanes.



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