[all-commits] [llvm/llvm-project] 4dfea2: [ExpandMemCmp][AArch64][PowerPC][RISCV][X86] Use l...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 4dfea22e771a0944b3b313f2790a616fa79257e1
      https://github.com/llvm/llvm-project/commit/4dfea22e771a0944b3b313f2790a616fa79257e1
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2025-01-03 (Fri, 03 Jan 2025)

  Changed paths:
    M llvm/lib/CodeGen/ExpandMemCmp.cpp
    M llvm/test/CodeGen/AArch64/machine-licm-hoist-load.ll
    M llvm/test/CodeGen/AArch64/memcmp.ll
    M llvm/test/CodeGen/PowerPC/memcmp.ll
    M llvm/test/CodeGen/PowerPC/memcmpIR.ll
    M llvm/test/CodeGen/RISCV/memcmp-optsize.ll
    M llvm/test/CodeGen/RISCV/memcmp.ll
    M llvm/test/CodeGen/X86/memcmp-more-load-pairs-x32.ll
    M llvm/test/CodeGen/X86/memcmp-more-load-pairs.ll
    M llvm/test/CodeGen/X86/memcmp-optsize-x32.ll
    M llvm/test/CodeGen/X86/memcmp-optsize.ll
    M llvm/test/CodeGen/X86/memcmp-pgso-x32.ll
    M llvm/test/CodeGen/X86/memcmp-pgso.ll
    M llvm/test/CodeGen/X86/memcmp-x32.ll
    M llvm/test/CodeGen/X86/memcmp.ll
    M llvm/test/Transforms/ExpandMemCmp/AArch64/memcmp.ll
    M llvm/test/Transforms/ExpandMemCmp/X86/memcmp-x32.ll
    M llvm/test/Transforms/ExpandMemCmp/X86/memcmp.ll

  Log Message:
  -----------
  [ExpandMemCmp][AArch64][PowerPC][RISCV][X86] Use llvm.ucmp instead of (sub (zext (icmp ugt)), (zext (icmp ult))). (#121530)

AArch64 and PowerPC look like a improvements.
RISC-V is neutral.
X86 trades a dependency breaking xor before a seta for a movsx after a
sbbb. Depending on how the result is used, this movsx might go away.



To unsubscribe from these emails, change your notification settings at https://github.com/llvm/llvm-project/settings/notifications