[all-commits] [llvm/llvm-project] 11e482: RegAllocGreedy: Add dummy priority advisor for wri...

[Matt Arsenault via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 11e482c4a32be6a315e5bf2ae7599cf10eb84836
      https://github.com/llvm/llvm-project/commit/11e482c4a32be6a315e5bf2ae7599cf10eb84836
  Author: Matt Arsenault <Matthew.Arsenault at amd.com>
  Date:   2025-01-02 (Thu, 02 Jan 2025)

  Changed paths:
    M llvm/lib/CodeGen/RegAllocGreedy.cpp
    M llvm/lib/CodeGen/RegAllocPriorityAdvisor.cpp
    M llvm/lib/CodeGen/RegAllocPriorityAdvisor.h
    A llvm/test/CodeGen/AMDGPU/dummy-regalloc-priority-advisor.mir

  Log Message:
  -----------
  RegAllocGreedy: Add dummy priority advisor for writing MIR tests (#121207)

I regularly struggle reproducing failures in greedy due to changes
in priority when resuming the allocation from MIR vs. a complete
compilation starting at IR. That is, the fix in
e0919b189bf2df4f97f22ba40260ab5153988b14 did not really fix the
problem of the instruction distance mattering.

Add a way to bypass all of the priority heuristics for MIR tests,
by prioritizing only by virtual register number. Could also
give this a more specific name, like PrioritizeLowVirtRegNumber



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