[all-commits] [llvm/llvm-project] f59096: [RISCV] Implement RISCVTTIImpl::getPreferredAddres...
Philipp van Kempen via All-commits
all-commits at lists.llvm.org
Mon Dec 30 18:56:49 PST 2024
Branch: refs/heads/main
Home: https://github.com/llvm/llvm-project
Commit: f590963db836ccbf7c547a3dea9dc719f24444d1
https://github.com/llvm/llvm-project/commit/f590963db836ccbf7c547a3dea9dc719f24444d1
Author: Philipp van Kempen <philipp.van-kempen at tum.de>
Date: 2024-12-31 (Tue, 31 Dec 2024)
Changed paths:
M llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
M llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h
A llvm/test/CodeGen/RISCV/xcvmem-heuristic.ll
Log Message:
-----------
[RISCV] Implement RISCVTTIImpl::getPreferredAddressingMode for HasVendorXCVmem (#120533)
For a simple matmult kernel this heuristic reduces the length of the
critical basic block from 15 to 20 instructions, resulting in a 20%
speedup.
**Without heuristic:**
```
13688: 001b838b cv.lb t2, (s7), 0x1
1368c: 09cdbcab cv.lb s9, t3(s11)
13690: 089db62b cv.lb a2, s1(s11)
13694: 092dbdab cv.lb s11, s2(s11)
13698: 001d028b cv.lb t0, (s10), 0x1
1369c: 00f282b3 add t0, t0, a5
136a0: 9072b52b cv.mac a0, t0, t2
136a4: 9192bfab cv.mac t6, t0, s9
136a8: 90c2beab cv.mac t4, t0, a2
136ac: 91b2bf2b cv.mac t5, t0, s11
136b0: fffc0c13 addi s8, s8, -0x1
136b4: 018e0633 add a2, t3, s8
136b8: 91b2b0ab cv.mac ra, t0, s11
136bc: 000b8d93 mv s11, s7
136c0: fc0614e3 bnez a2, 0x13688 <muriscv_nn_vec_mat_mult_t_s8+0x2f0>
#instrs = 15
```
**With heuristic:**
```
7bc0: 001c860b cv.lb a2, (s9), 0x1
7bc4: 001e0d0b cv.lb s10, (t3), 0x1
7bc8: 001e808b cv.lb ra, (t4), 0x1
7bcc: 0015038b cv.lb t2, (a0), 0x1
7bd0: 001c028b cv.lb t0, (s8), 0x1
7bd4: 00f282b3 add t0, t0, a5
7bd8: 90c2bfab cv.mac t6, t0, a2
7bdc: 91a2b92b cv.mac s2, t0, s10
7be0: 9012b5ab cv.mac a1, t0, ra
7be4: 9072b9ab cv.mac s3, t0, t2
7be8: 9072b72b cv.mac a4, t0, t2
7bec: fc851ae3 bne a0, s0, 0x7bc0 <muriscv_nn_vec_mat_mult_t_s8+0x338>
#instrs = 12
improvement = 1 - 12/15 = 0.2 = 20%
```
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