[all-commits] [llvm/llvm-project] c557ce: [RISCV] Use add_like_non_imm12 in XTheadba pattern...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: c557ce9f27feccdbda3588555fcb3303d1f81935
      https://github.com/llvm/llvm-project/commit/c557ce9f27feccdbda3588555fcb3303d1f81935
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2024-12-29 (Sun, 29 Dec 2024)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVInstrInfoXTHead.td
    M llvm/test/CodeGen/RISCV/rv64xtheadba.ll

  Log Message:
  -----------
  [RISCV] Use add_like_non_imm12 in XTheadba patterns to match Zba.


  Commit: 82ffdf317ee52e8679d58361dfe39930600839d1
      https://github.com/llvm/llvm-project/commit/82ffdf317ee52e8679d58361dfe39930600839d1
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2024-12-29 (Sun, 29 Dec 2024)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVInstrInfoXTHead.td

  Log Message:
  -----------
  [RISCV] Swap rs1 and rs2 names in TH_ADDSL patterns. NFC

The names should match the operand order of the final instruction.
I assume these patterns were somewhat copied from Zba where rs1 is
shifted, but for th.addsl, rs2 is shifted.


Compare: https://github.com/llvm/llvm-project/compare/6a769638b840...82ffdf317ee5

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