[all-commits] [llvm/llvm-project] 7f3428: [VPlan] Compute induction end values in VPlan. (#1...

[Florian Hahn via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 7f3428d3ed71d87a2088b77b6cab9f3d86544234
      https://github.com/llvm/llvm-project/commit/7f3428d3ed71d87a2088b77b6cab9f3d86544234
  Author: Florian Hahn <flo at fhahn.com>
  Date:   2024-12-29 (Sun, 29 Dec 2024)

  Changed paths:
    M llvm/lib/Transforms/Vectorize/LoopVectorizationPlanner.h
    M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
    M llvm/test/Transforms/LoopVectorize/AArch64/clamped-trip-count.ll
    M llvm/test/Transforms/LoopVectorize/AArch64/conditional-branches-cost.ll
    M llvm/test/Transforms/LoopVectorize/AArch64/epilog-vectorization-widen-inductions.ll
    M llvm/test/Transforms/LoopVectorize/AArch64/fixed-order-recurrence.ll
    M llvm/test/Transforms/LoopVectorize/AArch64/force-target-instruction-cost.ll
    M llvm/test/Transforms/LoopVectorize/AArch64/induction-costs-sve.ll
    M llvm/test/Transforms/LoopVectorize/AArch64/induction-costs.ll
    M llvm/test/Transforms/LoopVectorize/AArch64/intrinsiccost.ll
    M llvm/test/Transforms/LoopVectorize/AArch64/low_trip_count_predicates.ll
    M llvm/test/Transforms/LoopVectorize/AArch64/mul-simplification.ll
    M llvm/test/Transforms/LoopVectorize/AArch64/reduction-recurrence-costs-sve.ll
    M llvm/test/Transforms/LoopVectorize/AArch64/scalable-avoid-scalarization.ll
    M llvm/test/Transforms/LoopVectorize/AArch64/scalable-strict-fadd.ll
    M llvm/test/Transforms/LoopVectorize/AArch64/sve-epilog-vect.ll
    M llvm/test/Transforms/LoopVectorize/AArch64/sve-inductions-unusual-types.ll
    M llvm/test/Transforms/LoopVectorize/AArch64/sve-interleaved-accesses.ll
    M llvm/test/Transforms/LoopVectorize/AArch64/sve-live-out-pointer-induction.ll
    M llvm/test/Transforms/LoopVectorize/AArch64/sve-tail-folding-forced.ll
    M llvm/test/Transforms/LoopVectorize/AArch64/sve-tail-folding.ll
    M llvm/test/Transforms/LoopVectorize/AArch64/sve-widen-gep.ll
    M llvm/test/Transforms/LoopVectorize/AArch64/sve-widen-phi.ll
    M llvm/test/Transforms/LoopVectorize/AArch64/sve2-histcnt-vplan.ll
    M llvm/test/Transforms/LoopVectorize/AArch64/synthesize-mask-for-call.ll
    M llvm/test/Transforms/LoopVectorize/AArch64/widen-call-with-intrinsic-or-libfunc.ll
    M llvm/test/Transforms/LoopVectorize/PowerPC/exit-branch-cost.ll
    M llvm/test/Transforms/LoopVectorize/RISCV/blend-any-of-reduction-cost.ll
    M llvm/test/Transforms/LoopVectorize/RISCV/blocks-with-dead-instructions.ll
    M llvm/test/Transforms/LoopVectorize/RISCV/dead-ops-cost.ll
    M llvm/test/Transforms/LoopVectorize/RISCV/first-order-recurrence-scalable-vf1.ll
    M llvm/test/Transforms/LoopVectorize/RISCV/induction-costs.ll
    M llvm/test/Transforms/LoopVectorize/RISCV/masked_gather_scatter.ll
    M llvm/test/Transforms/LoopVectorize/RISCV/riscv-vector-reverse.ll
    M llvm/test/Transforms/LoopVectorize/RISCV/strided-accesses.ll
    M llvm/test/Transforms/LoopVectorize/RISCV/vectorize-force-tail-with-evl-reverse-load-store.ll
    M llvm/test/Transforms/LoopVectorize/RISCV/vectorize-force-tail-with-evl-uniform-store.ll
    M llvm/test/Transforms/LoopVectorize/RISCV/vplan-vp-intrinsics-reduction.ll
    M llvm/test/Transforms/LoopVectorize/SystemZ/predicated-first-order-recurrence.ll
    M llvm/test/Transforms/LoopVectorize/X86/conversion-cost.ll
    M llvm/test/Transforms/LoopVectorize/X86/cost-model.ll
    M llvm/test/Transforms/LoopVectorize/X86/epilog-vectorization-inductions.ll
    M llvm/test/Transforms/LoopVectorize/X86/fixed-order-recurrence.ll
    M llvm/test/Transforms/LoopVectorize/X86/float-induction-x86.ll
    M llvm/test/Transforms/LoopVectorize/X86/gather_scatter.ll
    M llvm/test/Transforms/LoopVectorize/X86/induction-costs.ll
    M llvm/test/Transforms/LoopVectorize/X86/intrinsiccost.ll
    M llvm/test/Transforms/LoopVectorize/X86/optsize.ll
    M llvm/test/Transforms/LoopVectorize/X86/pr109581-unused-blend.ll
    M llvm/test/Transforms/LoopVectorize/X86/pr72969.ll
    M llvm/test/Transforms/LoopVectorize/X86/scatter_crash.ll
    M llvm/test/Transforms/LoopVectorize/X86/small-size.ll
    M llvm/test/Transforms/LoopVectorize/branch-weights.ll
    M llvm/test/Transforms/LoopVectorize/epilog-vectorization-any-of-reductions.ll
    M llvm/test/Transforms/LoopVectorize/first-order-recurrence-chains-vplan.ll
    M llvm/test/Transforms/LoopVectorize/first-order-recurrence-chains.ll
    M llvm/test/Transforms/LoopVectorize/first-order-recurrence-complex.ll
    M llvm/test/Transforms/LoopVectorize/first-order-recurrence-sink-replicate-region.ll
    M llvm/test/Transforms/LoopVectorize/first-order-recurrence.ll
    M llvm/test/Transforms/LoopVectorize/induction.ll
    M llvm/test/Transforms/LoopVectorize/interleave-and-scalarize-only.ll
    M llvm/test/Transforms/LoopVectorize/interleaved-accesses.ll
    M llvm/test/Transforms/LoopVectorize/invariant-store-vectorization.ll
    M llvm/test/Transforms/LoopVectorize/iv-select-cmp-nested-loop.ll
    M llvm/test/Transforms/LoopVectorize/optimal-epilog-vectorization.ll
    M llvm/test/Transforms/LoopVectorize/pr59319-loop-access-info-invalidation.ll
    M llvm/test/Transforms/LoopVectorize/pr66616.ll
    M llvm/test/Transforms/LoopVectorize/reduction-align.ll
    M llvm/test/Transforms/LoopVectorize/reduction-inloop-cond.ll
    M llvm/test/Transforms/LoopVectorize/scalable-inductions.ll
    M llvm/test/Transforms/LoopVectorize/select-reduction.ll
    M llvm/test/Transforms/LoopVectorize/store-reduction-results-in-tail-folded-loop.ll
    M llvm/test/Transforms/LoopVectorize/uncountable-early-exit-vplan.ll
    M llvm/test/Transforms/LoopVectorize/vplan-iv-transforms.ll
    M llvm/test/Transforms/LoopVectorize/vplan-predicate-switch.ll
    M llvm/test/Transforms/LoopVectorize/vplan-printing-before-execute.ll
    M llvm/test/Transforms/LoopVectorize/vplan-printing.ll
    M llvm/test/Transforms/LoopVectorize/vplan-sink-scalars-and-merge-vf1.ll
    M llvm/test/Transforms/LoopVectorize/vplan-sink-scalars-and-merge.ll
    M llvm/test/Transforms/PhaseOrdering/ARM/arm_mult_q15.ll

  Log Message:
  -----------
  [VPlan] Compute induction end values in VPlan. (#112145)

Use createDerivedIV to compute IV end values directly in VPlan, instead
of creating them up-front.

This allows updating IV users outside the loop as follow-up.

Depends on https://github.com/llvm/llvm-project/pull/110004 and
https://github.com/llvm/llvm-project/pull/109975.

PR: https://github.com/llvm/llvm-project/pull/112145



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