[all-commits] [llvm/llvm-project] b2073f: [AArch64] Prefer SVE2.2 zeroing forms of certain i...

[Momchil Velikov via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: b2073fb9b9282c0f59861a137660f6a0782d7468
      https://github.com/llvm/llvm-project/commit/b2073fb9b9282c0f59861a137660f6a0782d7468
  Author: Momchil Velikov <momchil.velikov at arm.com>
  Date:   2024-12-24 (Tue, 24 Dec 2024)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
    M llvm/lib/Target/AArch64/AArch64InstrInfo.td
    M llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
    M llvm/lib/Target/AArch64/SVEInstrFormats.td
    M llvm/test/CodeGen/AArch64/zeroing-forms-abs-neg.ll
    M llvm/test/CodeGen/AArch64/zeroing-forms-fcvt-bfcvt.ll
    M llvm/test/CodeGen/AArch64/zeroing-forms-fcvtlt-fcvtx.ll
    M llvm/test/CodeGen/AArch64/zeroing-forms-fcvtzsu.ll

  Log Message:
  -----------
  [AArch64] Prefer SVE2.2 zeroing forms of certain instructions with an all-true predicate (#120595)

When the predicate of a destructive operation is known to be all-true,
for example

    fabs z0.s, p0/m, z1.s

then the entire output register is written and we can use a zeroing
(instead of a merging) form of the instruction, for example

    fabs z0.s, p0/z, z1.s

thus eliminate the dependency on the input-output destination register
without the need to insert a `movprfx`.

This patch complements (and in the case of
https://github.com/llvm/llvm-project/commit/2b3266c1701f315d7e89c81977800001563afacb,
fixes a regression) the following:

https://github.com/llvm/llvm-project/commit/7f4414b2a1a4d9f802a03f56894c406f0fe3e9a9
[AArch64] Generate zeroing forms of certain SVE2.2 instructions (4/11)
(https://github.com/llvm/llvm-project/pull/116830)

https://github.com/llvm/llvm-project/commit/2474cf7ad123ea14308293a2237e3552cddb1136
[AArch64] Generate zeroing forms of certain SVE2.2 instructions (3/11)
(https://github.com/llvm/llvm-project/pull/116829)

https://github.com/llvm/llvm-project/commit/6f285d31159501050de5563b1a844a3e1ac79a03
[AArch64] Generate zeroing forms of certain SVE2.2 instructions (2/11)
(https://github.com/llvm/llvm-project/pull/116828)

https://github.com/llvm/llvm-project/commit/2b3266c1701f315d7e89c81977800001563afacb
[AArch64] Generate zeroing forms of certain SVE2.2 instructions (1/11)
(https://github.com/llvm/llvm-project/pull/116259)



To unsubscribe from these emails, change your notification settings at https://github.com/llvm/llvm-project/settings/notifications