[all-commits] [llvm/llvm-project] adb849: [RISCV][NFCI] Rename rv32+rv64 testcases (#120717)

[Sam Elliott via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: adb849e79f144e132b169268a2784202d24e80ca
      https://github.com/llvm/llvm-project/commit/adb849e79f144e132b169268a2784202d24e80ca
  Author: Sam Elliott <quic_aelliott at quicinc.com>
  Date:   2024-12-23 (Mon, 23 Dec 2024)

  Changed paths:
    R llvm/test/MC/RISCV/rv32c-valid.s
    R llvm/test/MC/RISCV/rv32d-valid.s
    R llvm/test/MC/RISCV/rv32e-invalid.s
    R llvm/test/MC/RISCV/rv32e-valid.s
    R llvm/test/MC/RISCV/rv32f-valid.s
    R llvm/test/MC/RISCV/rv32i-valid.s
    R llvm/test/MC/RISCV/rv32ih-aliases-valid.s
    R llvm/test/MC/RISCV/rv32ih-valid.s
    R llvm/test/MC/RISCV/rv32m-valid.s
    R llvm/test/MC/RISCV/rv32xtheadbs-valid.s
    R llvm/test/MC/RISCV/rv32zaamo-valid.s
    R llvm/test/MC/RISCV/rv32zacas-valid.s
    R llvm/test/MC/RISCV/rv32zalasr-valid.s
    R llvm/test/MC/RISCV/rv32zalrsc-valid.s
    R llvm/test/MC/RISCV/rv32zba-valid.s
    R llvm/test/MC/RISCV/rv32zbb-valid.s
    R llvm/test/MC/RISCV/rv32zbc-valid.s
    R llvm/test/MC/RISCV/rv32zbkb-valid.s
    R llvm/test/MC/RISCV/rv32zbkc-valid.s
    R llvm/test/MC/RISCV/rv32zbkx-valid.s
    R llvm/test/MC/RISCV/rv32zbs-valid.s
    R llvm/test/MC/RISCV/rv32zcb-invalid.s
    R llvm/test/MC/RISCV/rv32zcb-valid.s
    R llvm/test/MC/RISCV/rv32zcmt-invalid.s
    R llvm/test/MC/RISCV/rv32zcmt-valid.s
    R llvm/test/MC/RISCV/rv32zdinx-valid.s
    R llvm/test/MC/RISCV/rv32zfbfmin-invalid.s
    R llvm/test/MC/RISCV/rv32zfbfmin-valid.s
    R llvm/test/MC/RISCV/rv32zfh-valid.s
    R llvm/test/MC/RISCV/rv32zfhmin-invalid.s
    R llvm/test/MC/RISCV/rv32zfhmin-valid.s
    R llvm/test/MC/RISCV/rv32zfinx-valid.s
    R llvm/test/MC/RISCV/rv32zhinx-valid.s
    R llvm/test/MC/RISCV/rv32zhinxmin-valid.s
    R llvm/test/MC/RISCV/rv32zicbom-invalid.s
    R llvm/test/MC/RISCV/rv32zicbom-valid.s
    R llvm/test/MC/RISCV/rv32zicbop-invalid.s
    R llvm/test/MC/RISCV/rv32zicbop-valid.s
    R llvm/test/MC/RISCV/rv32zicboz-invalid.s
    R llvm/test/MC/RISCV/rv32zicboz-valid.s
    R llvm/test/MC/RISCV/rv32zicond-invalid.s
    R llvm/test/MC/RISCV/rv32zicond-valid.s
    R llvm/test/MC/RISCV/rv32zihintntl-invalid.s
    R llvm/test/MC/RISCV/rv32zihintntl-valid.s
    R llvm/test/MC/RISCV/rv32zihintntlc-invalid.s
    R llvm/test/MC/RISCV/rv32zihintntlc-valid.s
    R llvm/test/MC/RISCV/rv32zihintpause-valid.s
    R llvm/test/MC/RISCV/rv32zknh-valid.s
    R llvm/test/MC/RISCV/rv32zksed-valid.s
    R llvm/test/MC/RISCV/rv32zksh-valid.s
    A llvm/test/MC/RISCV/rvc-valid.s
    A llvm/test/MC/RISCV/rvd-valid.s
    A llvm/test/MC/RISCV/rve-invalid.s
    A llvm/test/MC/RISCV/rve-valid.s
    A llvm/test/MC/RISCV/rvf-valid.s
    A llvm/test/MC/RISCV/rvi-valid.s
    A llvm/test/MC/RISCV/rvih-aliases-valid.s
    A llvm/test/MC/RISCV/rvih-valid.s
    A llvm/test/MC/RISCV/rvm-valid.s
    A llvm/test/MC/RISCV/rvxtheadbs-valid.s
    A llvm/test/MC/RISCV/rvzaamo-valid.s
    A llvm/test/MC/RISCV/rvzacas-valid.s
    A llvm/test/MC/RISCV/rvzalasr-valid.s
    A llvm/test/MC/RISCV/rvzalrsc-valid.s
    A llvm/test/MC/RISCV/rvzba-valid.s
    A llvm/test/MC/RISCV/rvzbb-valid.s
    A llvm/test/MC/RISCV/rvzbc-valid.s
    A llvm/test/MC/RISCV/rvzbkb-valid.s
    A llvm/test/MC/RISCV/rvzbkc-valid.s
    A llvm/test/MC/RISCV/rvzbkx-valid.s
    A llvm/test/MC/RISCV/rvzbs-valid.s
    A llvm/test/MC/RISCV/rvzcb-invalid.s
    A llvm/test/MC/RISCV/rvzcb-valid.s
    A llvm/test/MC/RISCV/rvzcmt-invalid.s
    A llvm/test/MC/RISCV/rvzcmt-valid.s
    A llvm/test/MC/RISCV/rvzdinx-valid.s
    A llvm/test/MC/RISCV/rvzfbfmin-invalid.s
    A llvm/test/MC/RISCV/rvzfbfmin-valid.s
    A llvm/test/MC/RISCV/rvzfh-valid.s
    A llvm/test/MC/RISCV/rvzfhmin-invalid.s
    A llvm/test/MC/RISCV/rvzfhmin-valid.s
    A llvm/test/MC/RISCV/rvzfinx-valid.s
    A llvm/test/MC/RISCV/rvzhinx-valid.s
    A llvm/test/MC/RISCV/rvzhinxmin-valid.s
    A llvm/test/MC/RISCV/rvzicbom-invalid.s
    A llvm/test/MC/RISCV/rvzicbom-valid.s
    A llvm/test/MC/RISCV/rvzicbop-invalid.s
    A llvm/test/MC/RISCV/rvzicbop-valid.s
    A llvm/test/MC/RISCV/rvzicboz-invalid.s
    A llvm/test/MC/RISCV/rvzicboz-valid.s
    A llvm/test/MC/RISCV/rvzicond-invalid.s
    A llvm/test/MC/RISCV/rvzicond-valid.s
    A llvm/test/MC/RISCV/rvzihintntl-invalid.s
    A llvm/test/MC/RISCV/rvzihintntl-valid.s
    A llvm/test/MC/RISCV/rvzihintntlc-invalid.s
    A llvm/test/MC/RISCV/rvzihintntlc-valid.s
    A llvm/test/MC/RISCV/rvzihintpause-valid.s
    A llvm/test/MC/RISCV/rvzknh-valid.s
    A llvm/test/MC/RISCV/rvzksed-valid.s
    A llvm/test/MC/RISCV/rvzksh-valid.s

  Log Message:
  -----------
  [RISCV][NFCI] Rename rv32+rv64 testcases (#120717)

All these testcases were called `rv32<something>.s`, but had equivalent
RUN lines for both riscv32 and riscv64. This made it hard to add tests
which are only valid on one of riscv32 or riscv64.

This change makes the tests follow a naming convention:
- `rv32*.s` means a test for riscv32-specific behaviour
- `rv64*.s` means a test for riscv64-specific behaviour
- `rv*.s` (without 64 or 32) means a test for both base architectures -
the majority of tests/behaviour.

This should make it easier to add and name extension-specific tests
which do depend on the base architecture.



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