[all-commits] [llvm/llvm-project] 2e3003: [TRI][RISCV] Add methods to get common register cl...

[Pengcheng Wang via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 2e3003211fea12aa492fa6ecc4a26f4fb1e7c8b9
      https://github.com/llvm/llvm-project/commit/2e3003211fea12aa492fa6ecc4a26f4fb1e7c8b9
  Author: Pengcheng Wang <wangpengcheng.pp at bytedance.com>
  Date:   2024-12-23 (Mon, 23 Dec 2024)

  Changed paths:
    M llvm/include/llvm/CodeGen/TargetRegisterInfo.h
    M llvm/lib/CodeGen/TargetRegisterInfo.cpp
    M llvm/lib/Target/RISCV/RISCVInstrInfo.cpp

  Log Message:
  -----------
  [TRI][RISCV] Add methods to get common register class of two registers (#118435)

Here we add two methods `getCommonMinimalPhysRegClass` and a LLT
version `getCommonMinimalPhysRegClassLLT`, which return the most
sub register class of the right type that contains these two input
registers.

We don't overload the `getMinimalPhysRegClass` as there will be
ambiguities.

We use it to simplify some code in RISC-V target.



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