[all-commits] [llvm/llvm-project] e934a3: [RISC-V] Base scheduling model for tt-ascalon-d8 (...

[Petr Penzin via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: e934a39e01b9eedd8091cc1505be3a4ad5cad12b
      https://github.com/llvm/llvm-project/commit/e934a39e01b9eedd8091cc1505be3a4ad5cad12b
  Author: Petr Penzin <ppenzin at tenstorrent.com>
  Date:   2024-12-20 (Fri, 20 Dec 2024)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCV.td
    M llvm/lib/Target/RISCV/RISCVProcessors.td
    A llvm/lib/Target/RISCV/RISCVSchedTTAscalonD8.td
    A llvm/test/tools/llvm-mca/RISCV/tt-ascalon-d8/fp.s
    A llvm/test/tools/llvm-mca/RISCV/tt-ascalon-d8/fx.s

  Log Message:
  -----------
  [RISC-V] Base scheduling model for tt-ascalon-d8 (#120160)

First part of tt-ascalon-d8 scheduling model, only containing scalar
ops. Scheduling for vector instructions will be added in a follow-up
patch.

---------

Co-authored-by: Anton Blanchard <antonb at tenstorrent.com>
Co-authored-by: Pengcheng Wang <wangpengcheng.pp at bytedance.com>



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