[all-commits] [llvm/llvm-project] d2b8ac: [RISCV] Swap the order of SEWGreaterThanOrEqualAnd...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: d2b8acc10464e1f0f6e043f1a92cefc2f3b9d30f
      https://github.com/llvm/llvm-project/commit/d2b8acc10464e1f0f6e043f1a92cefc2f3b9d30f
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2024-12-20 (Fri, 20 Dec 2024)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
    A llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-zve64f.mir

  Log Message:
  -----------
  [RISCV] Swap the order of SEWGreaterThanOrEqualAndLessThan64 and SEWGreaterThanOrEqual. (#120649)

SEWGreaterThanOrEqualAndLessThan64 is a stricter constraint so it should
have a higher value than SEWGreaterThanOrEqual.

Found by our random test generator.



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