[all-commits] [llvm/llvm-project] 5e2259: [AArch64] Verify consecutive vector registers in t...

[Guy David via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 5e22597aa01d719b7fed79c45cdf240ed196bd68
      https://github.com/llvm/llvm-project/commit/5e22597aa01d719b7fed79c45cdf240ed196bd68
  Author: Guy David <49722543+guy-david at users.noreply.github.com>
  Date:   2024-12-20 (Fri, 20 Dec 2024)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64InstrFormats.td
    M llvm/lib/Target/AArch64/AArch64RegisterInfo.td
    M llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
    M llvm/test/MC/AArch64/neon-diagnostics.s

  Log Message:
  -----------
  [AArch64] Verify consecutive vector registers in tbl, tbx (#120262)

Table lookup instructions expect the vectors that define the table
itself to be consecutive (wraparound allowed).
Relevant documentation:

https://developer.arm.com/documentation/100069/0606/SIMD-Vector-Instructions/TBL--vector-



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