[all-commits] [llvm/llvm-project] 53d080: [mlir][Arith] Remove `arith-to-llvm` from `func-to...
Florian Mayer via All-commits
all-commits at lists.llvm.org
Fri Dec 20 08:22:29 PST 2024
Branch: refs/heads/users/fmayer/spr/vectorizer-precommit-test-for-miscompilation
Home: https://github.com/llvm/llvm-project
Commit: 53d080c5b5dfbb46eb81d189736864f5b6196492
https://github.com/llvm/llvm-project/commit/53d080c5b5dfbb46eb81d189736864f5b6196492
Author: Matthias Springer <me at m-sp.org>
Date: 2024-12-20 (Fri, 20 Dec 2024)
Changed paths:
M mlir/lib/Conversion/FuncToLLVM/FuncToLLVM.cpp
M mlir/test/Dialect/ArmSVE/legalize-for-llvm.mlir
M mlir/test/lib/Dialect/LLVM/TestLowerToLLVM.cpp
M mlir/test/mlir-cpu-runner/math-polynomial-approx.mlir
M mlir/test/mlir-cpu-runner/test-expand-math-approx.mlir
M mlir/test/python/execution_engine.py
M mlir/tools/mlir-vulkan-runner/mlir-vulkan-runner.cpp
Log Message:
-----------
[mlir][Arith] Remove `arith-to-llvm` from `func-to-llvm` (#120548)
Do not run `arith-to-llvm` as part of `func-to-llvm`. This commit partly
fixes #70982.
Also simplify the pass pipeline for two math dialect integration tests.
Note for LLVM integration: If you see failures, add `arith-to-llvm` to your pass pipeline.
Commit: d0b7633d7ad566579bfb794f95cce9aef294c92b
https://github.com/llvm/llvm-project/commit/d0b7633d7ad566579bfb794f95cce9aef294c92b
Author: Timothy Hoffman <4001421+tim-hoffman at users.noreply.github.com>
Date: 2024-12-20 (Fri, 20 Dec 2024)
Changed paths:
M mlir/docs/DefiningDialects/AttributesAndTypes.md
M mlir/docs/PatternRewriter.md
M mlir/docs/SymbolsAndSymbolTables.md
M mlir/include/mlir/IR/DialectImplementation.h
M mlir/include/mlir/IR/OpBase.td
M mlir/include/mlir/Tools/mlir-opt/MlirOptMain.h
Log Message:
-----------
[mlir] [doc] fix typos in documentation (#120179)
This PR fixes typos within documentation in various files.
Most changes are trivial. The one interesting change is the
documentation for `custom<X>` in `assemblyFormat` that used the wrong
return type. The return type from the `parseX` function should be
`ParseResult` rather than `LogicalResult`. The `ParseResult` type is
necessary due to tablegen generating code like the following within an
Op `parse()` function:
```
auto odsResult = parseInferredArrayType(parser, elementsTypes, elementsOperands, resultRawTypes[0]);
if (odsResult) return ::mlir::failure();
```
This will fail to compile if `parseInferredArrayType()` returns
`LogicalResult`. See also `parsePrettyLLVMType()` in LLVMTypes.h,
`parseSingleBlockRegion()` in IRDL.cpp, `parseDynamicIndexList()` in
ViewLikeInterface.cpp, etc.
Commit: d8a5fae6913a0f6c7e3c814315c1a11fcfd609a1
https://github.com/llvm/llvm-project/commit/d8a5fae6913a0f6c7e3c814315c1a11fcfd609a1
Author: Hervé Poussineau <hpoussin at reactos.org>
Date: 2024-12-20 (Fri, 20 Dec 2024)
Changed paths:
M llvm/lib/Target/Mips/MCTargetDesc/CMakeLists.txt
M llvm/lib/Target/Mips/MCTargetDesc/MipsAsmBackend.cpp
M llvm/lib/Target/Mips/MCTargetDesc/MipsMCAsmInfo.cpp
M llvm/lib/Target/Mips/MCTargetDesc/MipsMCAsmInfo.h
M llvm/lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.cpp
M llvm/lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.h
A llvm/lib/Target/Mips/MCTargetDesc/MipsWinCOFFObjectWriter.cpp
A llvm/lib/Target/Mips/MCTargetDesc/MipsWinCOFFStreamer.cpp
M llvm/lib/Target/Mips/MipsTargetMachine.cpp
M llvm/test/CodeGen/Mips/Fast-ISel/br1.ll
M llvm/test/CodeGen/Mips/Fast-ISel/icmpbr1.ll
M llvm/test/CodeGen/Mips/addressing-mode.ll
M llvm/test/CodeGen/Mips/atomic-min-max-64.ll
M llvm/test/CodeGen/Mips/atomic-min-max.ll
M llvm/test/CodeGen/Mips/brconeq.ll
M llvm/test/CodeGen/Mips/brconeqk.ll
M llvm/test/CodeGen/Mips/brconeqz.ll
M llvm/test/CodeGen/Mips/brconge.ll
M llvm/test/CodeGen/Mips/brcongt.ll
M llvm/test/CodeGen/Mips/brconle.ll
M llvm/test/CodeGen/Mips/brconlt.ll
M llvm/test/CodeGen/Mips/brconne.ll
M llvm/test/CodeGen/Mips/brconnek.ll
M llvm/test/CodeGen/Mips/brconnez.ll
M llvm/test/CodeGen/Mips/cconv/memory-layout.ll
M llvm/test/CodeGen/Mips/cfi_offset.ll
M llvm/test/CodeGen/Mips/dins.ll
M llvm/test/CodeGen/Mips/dsp-r1.ll
M llvm/test/CodeGen/Mips/eh-return32.ll
M llvm/test/CodeGen/Mips/eh-return64.ll
M llvm/test/CodeGen/Mips/emit-big-cst.ll
M llvm/test/CodeGen/Mips/ex2.ll
M llvm/test/CodeGen/Mips/fpbr.ll
M llvm/test/CodeGen/Mips/frame-address.ll
M llvm/test/CodeGen/Mips/jumptable_labels.ll
M llvm/test/CodeGen/Mips/llvm-ir/add.ll
M llvm/test/CodeGen/Mips/llvm-ir/indirectbr.ll
M llvm/test/CodeGen/Mips/llvm-ir/select-int.ll
M llvm/test/CodeGen/Mips/load-store-left-right.ll
M llvm/test/CodeGen/Mips/mcount.ll
M llvm/test/CodeGen/Mips/micromips-sizereduction/micromips-lbu16-lhu16-sb16-sh16.ll
M llvm/test/CodeGen/Mips/mips64directive.ll
M llvm/test/CodeGen/Mips/msa/2r.ll
M llvm/test/CodeGen/Mips/msa/2r_vector_scalar.ll
M llvm/test/CodeGen/Mips/msa/2rf.ll
M llvm/test/CodeGen/Mips/msa/2rf_exup.ll
M llvm/test/CodeGen/Mips/msa/2rf_float_int.ll
M llvm/test/CodeGen/Mips/msa/2rf_fq.ll
M llvm/test/CodeGen/Mips/msa/2rf_int_float.ll
M llvm/test/CodeGen/Mips/msa/2rf_tq.ll
M llvm/test/CodeGen/Mips/msa/3r-a.ll
M llvm/test/CodeGen/Mips/msa/3r-b.ll
M llvm/test/CodeGen/Mips/msa/3r-c.ll
M llvm/test/CodeGen/Mips/msa/3r-d.ll
M llvm/test/CodeGen/Mips/msa/3r-i.ll
M llvm/test/CodeGen/Mips/msa/3r-m.ll
M llvm/test/CodeGen/Mips/msa/3r-p.ll
M llvm/test/CodeGen/Mips/msa/3r-s.ll
M llvm/test/CodeGen/Mips/msa/3r-v.ll
M llvm/test/CodeGen/Mips/msa/3r_4r.ll
M llvm/test/CodeGen/Mips/msa/3r_4r_widen.ll
M llvm/test/CodeGen/Mips/msa/3r_splat.ll
M llvm/test/CodeGen/Mips/msa/3rf.ll
M llvm/test/CodeGen/Mips/msa/3rf_4rf.ll
M llvm/test/CodeGen/Mips/msa/3rf_4rf_q.ll
M llvm/test/CodeGen/Mips/msa/3rf_exdo.ll
M llvm/test/CodeGen/Mips/msa/3rf_float_int.ll
M llvm/test/CodeGen/Mips/msa/3rf_int_float.ll
M llvm/test/CodeGen/Mips/msa/3rf_q.ll
M llvm/test/CodeGen/Mips/msa/arithmetic_float.ll
M llvm/test/CodeGen/Mips/msa/bit.ll
M llvm/test/CodeGen/Mips/msa/bitcast.ll
M llvm/test/CodeGen/Mips/msa/compare.ll
M llvm/test/CodeGen/Mips/msa/compare_float.ll
M llvm/test/CodeGen/Mips/msa/elm_copy.ll
M llvm/test/CodeGen/Mips/msa/elm_cxcmsa.ll
M llvm/test/CodeGen/Mips/msa/elm_insv.ll
M llvm/test/CodeGen/Mips/msa/elm_move.ll
M llvm/test/CodeGen/Mips/msa/elm_shift_slide.ll
M llvm/test/CodeGen/Mips/msa/endian.ll
M llvm/test/CodeGen/Mips/msa/frameindex.ll
M llvm/test/CodeGen/Mips/msa/i10.ll
M llvm/test/CodeGen/Mips/msa/i5-a.ll
M llvm/test/CodeGen/Mips/msa/i5-c.ll
M llvm/test/CodeGen/Mips/msa/i5-m.ll
M llvm/test/CodeGen/Mips/msa/i5_ld_st.ll
M llvm/test/CodeGen/Mips/msa/i8.ll
M llvm/test/CodeGen/Mips/msa/remat-ldi.ll
M llvm/test/CodeGen/Mips/msa/shift-dagcombine.ll
M llvm/test/CodeGen/Mips/msa/shift_constant_pool.ll
M llvm/test/CodeGen/Mips/msa/special.ll
M llvm/test/CodeGen/Mips/msa/spill.ll
M llvm/test/CodeGen/Mips/msa/vec.ll
M llvm/test/CodeGen/Mips/msa/vecs10.ll
M llvm/test/CodeGen/Mips/octeon.ll
M llvm/test/CodeGen/Mips/prevent-hoisting.ll
M llvm/test/CodeGen/Mips/selTBteqzCmpi.ll
M llvm/test/CodeGen/Mips/selTBtnezCmpi.ll
M llvm/test/CodeGen/Mips/selTBtnezSlti.ll
M llvm/test/CodeGen/Mips/seleq.ll
M llvm/test/CodeGen/Mips/seleqk.ll
M llvm/test/CodeGen/Mips/selgek.ll
M llvm/test/CodeGen/Mips/selgt.ll
M llvm/test/CodeGen/Mips/selle.ll
M llvm/test/CodeGen/Mips/selltk.ll
M llvm/test/CodeGen/Mips/selne.ll
M llvm/test/CodeGen/Mips/selnek.ll
M llvm/test/CodeGen/Mips/selpat.ll
M llvm/test/CodeGen/Mips/unalignedload.ll
M llvm/test/DebugInfo/Mips/tls.ll
A llvm/test/MC/Mips/coff-basic.ll
A llvm/test/MC/Mips/coff-relocs.ll
Log Message:
-----------
[MC][Mips] Add MipsWinCOFFObjectWriter/MipsWinCOFFStreamer (#114611)
llc is now able to create MIPS COFF files for simple cases.
Commit: fe85c71a7b556b3cef1528399b123538e6b3dd4b
https://github.com/llvm/llvm-project/commit/fe85c71a7b556b3cef1528399b123538e6b3dd4b
Author: Mikhail Goncharov <goncharov.mikhail at gmail.com>
Date: 2024-12-20 (Fri, 20 Dec 2024)
Changed paths:
M utils/bazel/llvm-project-overlay/mlir/BUILD.bazel
M utils/bazel/llvm-project-overlay/mlir/test/BUILD.bazel
Log Message:
-----------
[bazel] port 53d080c5b5dfbb46eb81d189736864f5b6196492
Commit: 81e63f9e0c4b86ca1a00be7aeeffb1519a74226e
https://github.com/llvm/llvm-project/commit/81e63f9e0c4b86ca1a00be7aeeffb1519a74226e
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-12-20 (Fri, 20 Dec 2024)
Changed paths:
M llvm/lib/Target/X86/X86TargetTransformInfo.cpp
M llvm/test/Analysis/CostModel/X86/shuffle-concat_subvector-codesize.ll
M llvm/test/Analysis/CostModel/X86/shuffle-concat_subvector-latency.ll
M llvm/test/Analysis/CostModel/X86/shuffle-concat_subvector-sizelatency.ll
M llvm/test/Analysis/CostModel/X86/shuffle-concat_subvector.ll
M llvm/test/Analysis/CostModel/X86/shuffle-insert_subvector-codesize.ll
M llvm/test/Analysis/CostModel/X86/shuffle-insert_subvector-latency.ll
M llvm/test/Analysis/CostModel/X86/shuffle-insert_subvector-sizelatency.ll
M llvm/test/Analysis/CostModel/X86/shuffle-insert_subvector.ll
M llvm/test/Analysis/CostModel/X86/shuffle-two-src-codesize.ll
M llvm/test/Analysis/CostModel/X86/shuffle-two-src-fp16-codesize.ll
M llvm/test/Analysis/CostModel/X86/shuffle-two-src-fp16-latency.ll
M llvm/test/Analysis/CostModel/X86/shuffle-two-src-fp16-sizelatency.ll
M llvm/test/Analysis/CostModel/X86/shuffle-two-src-fp16.ll
M llvm/test/Analysis/CostModel/X86/shuffle-two-src-latency.ll
M llvm/test/Analysis/CostModel/X86/shuffle-two-src-sizelatency.ll
M llvm/test/Analysis/CostModel/X86/shuffle-two-src.ll
M llvm/test/Transforms/PhaseOrdering/X86/pr94546.ll
M llvm/test/Transforms/SLPVectorizer/X86/horizontal-minmax.ll
M llvm/test/Transforms/SLPVectorizer/X86/minbitwidth-transformed-operand.ll
M llvm/test/Transforms/VectorCombine/X86/shuffle-of-casts.ll
M llvm/test/Transforms/VectorCombine/X86/shuffle-of-shuffles.ll
Log Message:
-----------
[CostModel][X86] getShuffleCost - use processShuffleMasks to split SK_PermuteTwoSrc shuffles to legal types (#120599)
processShuffleMasks can now correctly handle 2 src shuffles, so we can use the existing SK_PermuteSingleSrc splitting cost logic to handle SK_PermuteTwoSrc as well and correctly recognise the number of active subvectors per legalised shuffle.
Commit: e10cb443a1ba30cd1368907df246e968b7508278
https://github.com/llvm/llvm-project/commit/e10cb443a1ba30cd1368907df246e968b7508278
Author: Hans Wennborg <hans at chromium.org>
Date: 2024-12-20 (Fri, 20 Dec 2024)
Changed paths:
M compiler-rt/lib/sanitizer_common/CMakeLists.txt
M compiler-rt/lib/sanitizer_common/sanitizer_common_interface.inc
R compiler-rt/lib/sanitizer_common/sanitizer_contiguous_container.cpp
Log Message:
-----------
Revert "[compiler-rt] Add weak defs for .*contiguous_container.* functions (#120376)"
This reverts commit a73ca291547cf4f5822a3029dd56315354557517.
Commit: 69ebac7ad6ae1db9bb19cf3a19ea978af6034ca3
https://github.com/llvm/llvm-project/commit/69ebac7ad6ae1db9bb19cf3a19ea978af6034ca3
Author: Hans Wennborg <hans at hanshq.net>
Date: 2024-12-20 (Fri, 20 Dec 2024)
Changed paths:
M compiler-rt/lib/interception/interception_win.cpp
Log Message:
-----------
[win/asan] Don't intercept memset etc. in ntdll (#120397)
When ntdll was added to the list of of "interesting DLLs" list (in
d58230b9dcb3b312a2da8f874daa0cc8dc27da9b), the intention was not to
intercept the "mini CRT" functions it exports. OverrideFunction would
only intercept the *first* function it found when searching the list of
DLLs, and ntdll was put last in that list.
However, after 42cdfbcf3e92466754c175cb0e1e237e9f66749e,
OverrideFunction intercepts *all* matching functions in those DLLs. As
a side-effect, the runtime would now intercept functions like memset
etc. also in ntdll.
This causes a problem when ntdll-internal functions like
RtlDispatchException call the intercepted memset, which tries to
inspect uncommitted shadow memory, raising an exception, and getting
stuck in that loop until the stack overflows.
Since we never intended to intercept ntdll's memset etc., the simplest
fix seems to be to actively ignore ntdll when intercepting those
functions.
Fixes #114793
Commit: b03a09e74fa38eceddbc314c4f896a935224f453
https://github.com/llvm/llvm-project/commit/b03a09e74fa38eceddbc314c4f896a935224f453
Author: Matthias Springer <me at m-sp.org>
Date: 2024-12-20 (Fri, 20 Dec 2024)
Changed paths:
M mlir/lib/Dialect/SparseTensor/Pipelines/SparseTensorPipelines.cpp
M mlir/test/Integration/Dialect/Async/CPU/microbench-linalg-async-parallel-for.mlir
M mlir/test/Integration/Dialect/Async/CPU/microbench-scf-async-parallel-for.mlir
M mlir/test/Integration/Dialect/Async/CPU/test-async-parallel-for-1d.mlir
M mlir/test/Integration/Dialect/Async/CPU/test-async-parallel-for-2d.mlir
M mlir/test/Integration/Dialect/Complex/CPU/correctness.mlir
M mlir/test/Integration/Dialect/ControlFlow/assert.mlir
M mlir/test/Integration/Dialect/LLVMIR/CPU/X86/test-inline-asm-vector.mlir
M mlir/test/Integration/Dialect/LLVMIR/CPU/test-vp-intrinsic.mlir
M mlir/test/Integration/Dialect/Linalg/CPU/runtime-verification.mlir
M mlir/test/Integration/Dialect/MemRef/cast-runtime-verification.mlir
M mlir/test/Integration/Dialect/MemRef/load-runtime-verification.mlir
M mlir/test/Integration/Dialect/MemRef/memref_abi.c
M mlir/test/Integration/Dialect/MemRef/reinterpret-cast-runtime-verification.mlir
M mlir/test/Integration/Dialect/MemRef/subview-runtime-verification.mlir
M mlir/test/Integration/Dialect/Standard/CPU/test-ceil-floor-pos-neg.mlir
M mlir/test/Integration/Dialect/Vector/CPU/0-d-vectors.mlir
M mlir/test/Integration/Dialect/Vector/CPU/broadcast.mlir
M mlir/test/Integration/Dialect/Vector/CPU/compress.mlir
M mlir/test/Integration/Dialect/Vector/CPU/constant-mask.mlir
M mlir/test/Integration/Dialect/Vector/CPU/contraction.mlir
M mlir/test/Integration/Dialect/Vector/CPU/create-mask-v4i1.mlir
M mlir/test/Integration/Dialect/Vector/CPU/create-mask.mlir
M mlir/test/Integration/Dialect/Vector/CPU/expand.mlir
M mlir/test/Integration/Dialect/Vector/CPU/extract-strided-slice.mlir
M mlir/test/Integration/Dialect/Vector/CPU/flat-transpose-col.mlir
M mlir/test/Integration/Dialect/Vector/CPU/flat-transpose-row.mlir
M mlir/test/Integration/Dialect/Vector/CPU/fma.mlir
M mlir/test/Integration/Dialect/Vector/CPU/gather.mlir
M mlir/test/Integration/Dialect/Vector/CPU/index-vectors.mlir
M mlir/test/Integration/Dialect/Vector/CPU/insert-strided-slice.mlir
M mlir/test/Integration/Dialect/Vector/CPU/maskedload.mlir
M mlir/test/Integration/Dialect/Vector/CPU/maskedstore.mlir
M mlir/test/Integration/Dialect/Vector/CPU/matrix-multiply-col.mlir
M mlir/test/Integration/Dialect/Vector/CPU/matrix-multiply-row.mlir
M mlir/test/Integration/Dialect/Vector/CPU/outerproduct-f32.mlir
M mlir/test/Integration/Dialect/Vector/CPU/outerproduct-i64.mlir
M mlir/test/Integration/Dialect/Vector/CPU/print-fp.mlir
M mlir/test/Integration/Dialect/Vector/CPU/print-int.mlir
M mlir/test/Integration/Dialect/Vector/CPU/realloc.mlir
M mlir/test/Integration/Dialect/Vector/CPU/reductions-f32-reassoc.mlir
M mlir/test/Integration/Dialect/Vector/CPU/reductions-f32.mlir
M mlir/test/Integration/Dialect/Vector/CPU/reductions-f64-reassoc.mlir
M mlir/test/Integration/Dialect/Vector/CPU/reductions-f64.mlir
M mlir/test/Integration/Dialect/Vector/CPU/reductions-i32.mlir
M mlir/test/Integration/Dialect/Vector/CPU/reductions-i4.mlir
M mlir/test/Integration/Dialect/Vector/CPU/reductions-i64.mlir
M mlir/test/Integration/Dialect/Vector/CPU/reductions-si4.mlir
M mlir/test/Integration/Dialect/Vector/CPU/reductions-ui4.mlir
M mlir/test/Integration/Dialect/Vector/CPU/scan.mlir
M mlir/test/Integration/Dialect/Vector/CPU/scatter.mlir
M mlir/test/Integration/Dialect/Vector/CPU/shape-cast.mlir
M mlir/test/Integration/Dialect/Vector/CPU/shuffle.mlir
M mlir/test/Integration/Dialect/Vector/CPU/shuffle16x16.mlir
M mlir/test/Integration/Dialect/Vector/CPU/sparse-dot-matvec.mlir
M mlir/test/Integration/Dialect/Vector/CPU/sparse-saxpy-jagged-matvec.mlir
M mlir/test/Integration/Dialect/Vector/CPU/transfer-read-1d.mlir
M mlir/test/Integration/Dialect/Vector/CPU/transfer-read-2d.mlir
M mlir/test/Integration/Dialect/Vector/CPU/transfer-read-3d.mlir
M mlir/test/Integration/Dialect/Vector/CPU/transfer-read.mlir
M mlir/test/Integration/Dialect/Vector/CPU/transfer-to-loops.mlir
M mlir/test/Integration/Dialect/Vector/CPU/transfer-write.mlir
M mlir/test/Integration/Dialect/Vector/CPU/transpose.mlir
M mlir/test/Integration/GPU/CUDA/async.mlir
M mlir/test/python/integration/dialects/linalg/opsrun.py
Log Message:
-----------
[mlir] Fix integration tests after #120548 (#120706)
This should have been part of #120548.
Commit: 091448e3c17bc8e7812dd7b571c852576d648977
https://github.com/llvm/llvm-project/commit/091448e3c17bc8e7812dd7b571c852576d648977
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-12-20 (Fri, 20 Dec 2024)
Changed paths:
M llvm/lib/Target/X86/X86TargetTransformInfo.cpp
M llvm/test/Analysis/CostModel/X86/shuffle-concat_subvector-codesize.ll
M llvm/test/Analysis/CostModel/X86/shuffle-concat_subvector-latency.ll
M llvm/test/Analysis/CostModel/X86/shuffle-concat_subvector-sizelatency.ll
M llvm/test/Analysis/CostModel/X86/shuffle-concat_subvector.ll
M llvm/test/Analysis/CostModel/X86/shuffle-insert_subvector-codesize.ll
M llvm/test/Analysis/CostModel/X86/shuffle-insert_subvector-latency.ll
M llvm/test/Analysis/CostModel/X86/shuffle-insert_subvector-sizelatency.ll
M llvm/test/Analysis/CostModel/X86/shuffle-insert_subvector.ll
M llvm/test/Analysis/CostModel/X86/shuffle-two-src-codesize.ll
M llvm/test/Analysis/CostModel/X86/shuffle-two-src-fp16-codesize.ll
M llvm/test/Analysis/CostModel/X86/shuffle-two-src-fp16-latency.ll
M llvm/test/Analysis/CostModel/X86/shuffle-two-src-fp16-sizelatency.ll
M llvm/test/Analysis/CostModel/X86/shuffle-two-src-fp16.ll
M llvm/test/Analysis/CostModel/X86/shuffle-two-src-latency.ll
M llvm/test/Analysis/CostModel/X86/shuffle-two-src-sizelatency.ll
M llvm/test/Analysis/CostModel/X86/shuffle-two-src.ll
M llvm/test/Transforms/PhaseOrdering/X86/pr94546.ll
M llvm/test/Transforms/SLPVectorizer/X86/horizontal-minmax.ll
M llvm/test/Transforms/SLPVectorizer/X86/minbitwidth-transformed-operand.ll
M llvm/test/Transforms/VectorCombine/X86/shuffle-of-casts.ll
M llvm/test/Transforms/VectorCombine/X86/shuffle-of-shuffles.ll
Log Message:
-----------
Revert "[CostModel][X86] getShuffleCost - use processShuffleMasks to split SK_PermuteTwoSrc shuffles to legal types" (#120707)
Reverts llvm/llvm-project#120599 - some recent tests are currently failing
Commit: 2405c5fb3ed49b928bb2816ace7b67c8979cd9d7
https://github.com/llvm/llvm-project/commit/2405c5fb3ed49b928bb2816ace7b67c8979cd9d7
Author: wenzhoumei <wenzhoumei7 at gmail.com>
Date: 2024-12-20 (Fri, 20 Dec 2024)
Changed paths:
M llvm/include/llvm/BinaryFormat/ELF.h
Log Message:
-----------
[llvm-readelf] Update outdated URL (#120498)
This updates a comment pointing to the list of registered machine
architectures in the ELF gABI as the URL in the old comment is no longer
valid.
Commit: 0b5b09b67c572867d88bbf5b41bcc5e722ec653a
https://github.com/llvm/llvm-project/commit/0b5b09b67c572867d88bbf5b41bcc5e722ec653a
Author: Shubham Sandeep Rastogi <srastogi22 at apple.com>
Date: 2024-12-20 (Fri, 20 Dec 2024)
Changed paths:
M llvm/include/llvm/Passes/DroppedVariableStats.h
A llvm/include/llvm/Passes/DroppedVariableStatsIR.h
M llvm/include/llvm/Passes/StandardInstrumentations.h
M llvm/lib/Passes/CMakeLists.txt
R llvm/lib/Passes/DroppedVariableStats.cpp
A llvm/lib/Passes/DroppedVariableStatsIR.cpp
M llvm/unittests/IR/CMakeLists.txt
Log Message:
-----------
[NFC] Move DroppedVariableStats to its own file (#120711)
Move DroppedVariableStats code to its own file and change the class to
have an extensible design so that we can use it to add dropped
statistics to MIR passes and the instruction selector.
Also moved class DroppedVariableStatsIR to its own file.
Reland 2de78815604e9027efd93cac27c517bf732587d2
Commit: 2fa2c2197ddbf2f06c78b6d271782a8762b13b57
https://github.com/llvm/llvm-project/commit/2fa2c2197ddbf2f06c78b6d271782a8762b13b57
Author: David Spickett <david.spickett at linaro.org>
Date: 2024-12-20 (Fri, 20 Dec 2024)
Changed paths:
M llvm/docs/MemTagSanitizer.rst
Log Message:
-----------
[llvm][docs] MemTagSanitizer is only supported on AArch64 Android (#120545)
```
$ ./bin/clang /tmp/test.c -o /tmp/test.o -target aarch64-linux -march=armv8+memtag -fsanitize=memtag-stack
clang: error: unsupported option '-fsanitize=memtag*' for target 'aarch64-unknown-linux'
```
But this works:
```
$ ./bin/clang /tmp/test.c -o /tmp/test.o --target=aarch64-linux-android -march=armv8+memtag -fsanitize=memtag-stack
```
Due to this check in Clang:
https://github.com/llvm/llvm-project/blob/2210da3b823ccf21fc634c858827c9f12c864b51/clang/lib/Driver/ToolChains/CommonArgs.cpp#L1651
Likely because the required notes and dynamic loader support only exist
for Android.
You can get around this, sort of, by not linking the file. However this
means you have to provide your own way of loading it, so it doesn't
change the statement that this feature is Android only.
https://github.com/llvm/llvm-project/issues/64692 also confirms that the
intent is to only support Android at this time.
And while I'm here, suggest an additive set of flags that can also be
used.
Commit: d66f653c8db90d0c643f8f2740bbdc01bf647f18
https://github.com/llvm/llvm-project/commit/d66f653c8db90d0c643f8f2740bbdc01bf647f18
Author: Pengcheng Wang <wangpengcheng.pp at bytedance.com>
Date: 2024-12-20 (Fri, 20 Dec 2024)
Changed paths:
M llvm/lib/CodeGen/MachinePipeliner.cpp
Log Message:
-----------
[MachinePipeliner] Skip reserved registers when computing register pressure (#120694)
We used to skip fixed registers, but fixed registers are not enough
because there are some runtime unusable registers like registers
reserved by `-ffixed-xxx` options.
Here we change to use reserved registers so that the estimated
pressure is more accurate.
Commit: 1e18815fdc13bb1f8b0b87acd8abf62b5cf70d53
https://github.com/llvm/llvm-project/commit/1e18815fdc13bb1f8b0b87acd8abf62b5cf70d53
Author: Chenhui Huang <huangchenhui.yellow at bytedance.com>
Date: 2024-12-20 (Fri, 20 Dec 2024)
Changed paths:
M mlir/lib/Dialect/Shape/IR/Shape.cpp
M mlir/test/Dialect/Shape/canonicalize.mlir
Log Message:
-----------
[MLIR] fix shape.broadcast canonicalize with all empty shape operands (#118941)
Example: all the operands of `shape.broadcast` are empty tensors.
```
func.func @all_empty(%arg0: tensor<f32>) -> tensor<0xindex> {
%1 = shape.shape_of %arg0 : tensor<f32> -> tensor<0xindex>
%2 = shape.const_shape [] : tensor<0xindex>
%3 = shape.broadcast %1, %2, %1 : tensor<0xindex>, tensor<0xindex>, tensor<0xindex> -> tensor<0xindex>
return %3 : tensor<0xindex>
}
```
One can reproduce crash when canonicalize with *down-top* order, cmd
like this:
`mlir-opt -split-input-file -allow-unregistered-dialect
-canonicalize="test-convergence top-down=0" %s`
The root cause is when all operands are empty tensor,
`RemoveEmptyShapeOperandsPattern` would filter out all operands.
Co-authored-by: Kai Sasaki <lewuathe at gmail.com>
Commit: 611401c11594871aa5c7692cd17a7f12b6fbe660
https://github.com/llvm/llvm-project/commit/611401c11594871aa5c7692cd17a7f12b6fbe660
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-12-20 (Fri, 20 Dec 2024)
Changed paths:
M llvm/lib/Target/X86/X86TargetTransformInfo.cpp
M llvm/test/Analysis/CostModel/X86/shuffle-concat_subvector-codesize.ll
M llvm/test/Analysis/CostModel/X86/shuffle-concat_subvector-latency.ll
M llvm/test/Analysis/CostModel/X86/shuffle-concat_subvector-sizelatency.ll
M llvm/test/Analysis/CostModel/X86/shuffle-concat_subvector.ll
M llvm/test/Analysis/CostModel/X86/shuffle-insert_subvector-codesize.ll
M llvm/test/Analysis/CostModel/X86/shuffle-insert_subvector-latency.ll
M llvm/test/Analysis/CostModel/X86/shuffle-insert_subvector-sizelatency.ll
M llvm/test/Analysis/CostModel/X86/shuffle-insert_subvector.ll
M llvm/test/Analysis/CostModel/X86/shuffle-two-src-codesize.ll
M llvm/test/Analysis/CostModel/X86/shuffle-two-src-fp16-codesize.ll
M llvm/test/Analysis/CostModel/X86/shuffle-two-src-fp16-latency.ll
M llvm/test/Analysis/CostModel/X86/shuffle-two-src-fp16-sizelatency.ll
M llvm/test/Analysis/CostModel/X86/shuffle-two-src-fp16.ll
M llvm/test/Analysis/CostModel/X86/shuffle-two-src-latency.ll
M llvm/test/Analysis/CostModel/X86/shuffle-two-src-sizelatency.ll
M llvm/test/Analysis/CostModel/X86/shuffle-two-src.ll
M llvm/test/Transforms/PhaseOrdering/X86/hadd.ll
M llvm/test/Transforms/PhaseOrdering/X86/pr94546.ll
M llvm/test/Transforms/SLPVectorizer/X86/horizontal-minmax.ll
M llvm/test/Transforms/SLPVectorizer/X86/minbitwidth-transformed-operand.ll
M llvm/test/Transforms/VectorCombine/X86/shuffle-of-casts.ll
M llvm/test/Transforms/VectorCombine/X86/shuffle-of-shuffles.ll
Log Message:
-----------
[CostModel][X86] getShuffleCost - use processShuffleMasks to split SK_PermuteTwoSrc shuffles to legal types (#120599)
processShuffleMasks can now correctly handle 2 src shuffles, so we can use the existing SK_PermuteSingleSrc splitting cost logic to handle SK_PermuteTwoSrc as well and correctly recognise the number of active subvectors per legalised shuffle.
Commit: ff93ca7d6c487108a65d3ad15c3392235fd9c190
https://github.com/llvm/llvm-project/commit/ff93ca7d6c487108a65d3ad15c3392235fd9c190
Author: hanbeom <kese111 at gmail.com>
Date: 2024-12-20 (Fri, 20 Dec 2024)
Changed paths:
M llvm/lib/Transforms/Vectorize/VectorCombine.cpp
M llvm/test/Transforms/VectorCombine/X86/extract-fneg-insert.ll
Log Message:
-----------
[VectorCombine] Combine scalar fneg with insert/extract to vector fneg when length is different (#120461)
insertelt DestVec, (fneg (extractelt SrcVec, Index)), Index
-> shuffle DestVec, (shuffle (fneg SrcVec), poison, SrcMask), Mask
Original combining left the combine between vectors of different lengths as a TODO. this commit do that. (see
#[https://github.com/llvm/llvm-project/commit/baab4aa1ba5f68634b4936375e19c8686b1b474a])
Commit: 708e1437ff82181dc42f7b43f95428bfd0a9e8ff
https://github.com/llvm/llvm-project/commit/708e1437ff82181dc42f7b43f95428bfd0a9e8ff
Author: LLVM GN Syncbot <llvmgnsyncbot at gmail.com>
Date: 2024-12-20 (Fri, 20 Dec 2024)
Changed paths:
M llvm/utils/gn/secondary/llvm/lib/Passes/BUILD.gn
Log Message:
-----------
[gn build] Port 0b5b09b67c57
Commit: 42bc7bf40a13227110a95079b108615a85cddd7d
https://github.com/llvm/llvm-project/commit/42bc7bf40a13227110a95079b108615a85cddd7d
Author: LLVM GN Syncbot <llvmgnsyncbot at gmail.com>
Date: 2024-12-20 (Fri, 20 Dec 2024)
Changed paths:
M llvm/utils/gn/secondary/llvm/lib/Target/Mips/MCTargetDesc/BUILD.gn
Log Message:
-----------
[gn build] Port d8a5fae6913a
Commit: 919aead1db64b2f1444842bc75a3af7836238671
https://github.com/llvm/llvm-project/commit/919aead1db64b2f1444842bc75a3af7836238671
Author: Thirumalai Shaktivel <74826228+Thirumalai-Shaktivel at users.noreply.github.com>
Date: 2024-12-20 (Fri, 20 Dec 2024)
Changed paths:
M flang/lib/Lower/OpenMP/OpenMP.cpp
R flang/test/Lower/OpenMP/Todo/task_untied.f90
M flang/test/Lower/OpenMP/task.f90
M mlir/lib/Target/LLVMIR/Dialect/OpenMP/OpenMPToLLVMIRTranslation.cpp
M mlir/test/Target/LLVMIR/openmp-llvm.mlir
M mlir/test/Target/LLVMIR/openmp-todo.mlir
Log Message:
-----------
[Flang OpenMP] Add LLVM translation support for UNTIED in Task (#115283)
Implementation details:
The UNTIED clause is recognized by setting the flag=0 for the default
case or performing logical OR to flag if other clauses are specified,
and this flag is passed as an argument to the `__kmpc_omp_task_alloc`
runtime call.
Commit: c2bd5c25b3634e55089d34afe922aa38eee743e2
https://github.com/llvm/llvm-project/commit/c2bd5c25b3634e55089d34afe922aa38eee743e2
Author: SpencerAbson <Spencer.Abson at arm.com>
Date: 2024-12-20 (Fri, 20 Dec 2024)
Changed paths:
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
M llvm/lib/Target/AArch64/AArch64InstrInfo.td
M llvm/test/CodeGen/AArch64/aarch64-neon-vector-insert-uaddlv.ll
A llvm/test/CodeGen/AArch64/neon-ins-trunc-elt.ll
M llvm/test/CodeGen/AArch64/sve-doublereduct.ll
M llvm/test/CodeGen/AArch64/sve-extract-element.ll
M llvm/test/CodeGen/AArch64/sve-extract-fixed-vector.ll
M llvm/test/CodeGen/AArch64/sve-fixed-length-int-reduce.ll
M llvm/test/CodeGen/AArch64/sve-int-reduce.ll
M llvm/test/CodeGen/AArch64/sve-split-int-reduce.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-reduce.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-reductions.ll
M llvm/test/CodeGen/AArch64/sve-vecreduce-dot.ll
M llvm/test/CodeGen/AArch64/uaddlv-vaddlp-combine.ll
M llvm/test/CodeGen/AArch64/vec-combine-compare-to-bitmask.ll
M llvm/test/CodeGen/AArch64/vecreduce-bool.ll
Log Message:
-----------
[AArch64] Avoid GPR trip when moving truncated i32 vector elements (#114541)
This patch implements a DAG combine whereby
```
a: v2i64 = ...
b: i64 = extract_vector_elt a, Constant:i64<n>
c: i32 = truncate b
```
Becomes
```
a: v2i64 = ...
b: v4i32 = AArch64ISD::NVCAST a
c: i32 = extract_vector_elt c, Constant:i64<2n>
```
The primary goal of this work is to enable the use of [INS
(element)](https://developer.arm.com/documentation/ddi0602/2024-09/SIMD-FP-Instructions/INS--element---Insert-vector-element-from-another-vector-element-?lang=en)
when moving a truncated i32 element between vectors. This combine
canonicalises the structure of the DAG for all legal instances of the
pattern above (by removing the explicit `trunc` operator in this
specific case), allowing us to take advantage of existing ISEL patterns
for this behavior.
Commit: cf0bc8d0321a55f3f166131ec3fe45cdef7d5e3c
https://github.com/llvm/llvm-project/commit/cf0bc8d0321a55f3f166131ec3fe45cdef7d5e3c
Author: Dhruv Srivastava <dhruv.srivastava at ibm.com>
Date: 2024-12-20 (Fri, 20 Dec 2024)
Changed paths:
M lldb/source/Host/posix/ProcessLauncherPosixFork.cpp
Log Message:
-----------
[lldb][AIX] Adding AIX version of ptrace64 (#120390)
This PR is in reference to porting LLDB on AIX.
Link to discussions on llvm discourse and github:
1. https://discourse.llvm.org/t/port-lldb-to-ibm-aix/80640
2. https://github.com/llvm/llvm-project/issues/101657
The complete changes for porting are present in this draft PR:
https://github.com/llvm/llvm-project/pull/102601
Adding changes for minimal build for lldb binary on AIX. ptrace64 is
needed to debug 64-bit AIX debuggee, and its format is different than
the traditional ptrace on other platforms: [AIX
ptrace](https://www.ibm.com/docs/en/aix/7.3?topic=p-ptrace-ptracex-ptrace64-subroutine)
Commit: 6fd267d79b9bf3739c59662a7c09d78a6e09c94f
https://github.com/llvm/llvm-project/commit/6fd267d79b9bf3739c59662a7c09d78a6e09c94f
Author: Michael Buch <michaelbuch12 at gmail.com>
Date: 2024-12-20 (Fri, 20 Dec 2024)
Changed paths:
M lldb/source/Plugins/SymbolFile/DWARF/DWARFASTParserClang.cpp
M lldb/source/Plugins/SymbolFile/DWARF/DWARFASTParserClang.h
Log Message:
-----------
[lldb][DWARFASTParserClang][NFC] Remove unused parameter to CompleteRecordType (#120456)
Became unused since the recent
https://github.com/llvm/llvm-project/pull/110648
Commit: 84f0098ad103897112d3052fffbb244cd9db4815
https://github.com/llvm/llvm-project/commit/84f0098ad103897112d3052fffbb244cd9db4815
Author: Mikhail Goncharov <goncharov.mikhail at gmail.com>
Date: 2024-12-20 (Fri, 20 Dec 2024)
Changed paths:
M utils/bazel/llvm-project-overlay/mlir/BUILD.bazel
Log Message:
-----------
[bazel] port b03a09e74fa38eceddbc314c4f896a935224f453
Commit: 9a1837f9b0d3c74cd35fd1af5f7587f31391ba82
https://github.com/llvm/llvm-project/commit/9a1837f9b0d3c74cd35fd1af5f7587f31391ba82
Author: Dhruv Srivastava <dhruv.srivastava at ibm.com>
Date: 2024-12-20 (Fri, 20 Dec 2024)
Changed paths:
M lldb/tools/driver/CMakeLists.txt
Log Message:
-----------
[lldb][AIX] Introducing _ALL_SOURCE macro into driver CMakeLists (#120607)
This PR is in reference to porting LLDB on AIX.
Link to discussions on llvm discourse and github:
1. https://discourse.llvm.org/t/port-lldb-to-ibm-aix/80640
2. https://github.com/llvm/llvm-project/issues/101657
The complete changes for porting are present in this draft PR:
https://github.com/llvm/llvm-project/pull/102601
Adding changes for minimal build for lldb binary on AIX:
The `struct winsize` needed by `lldb/tools/driver/Driver.cpp` is only
recognised in AIX under the AIX specific `_ALL_SOURCE` macro, hence its
enablement is required here.
Commit: 385b144c9477de6a4598bd08ce4f2883aeb236b9
https://github.com/llvm/llvm-project/commit/385b144c9477de6a4598bd08ce4f2883aeb236b9
Author: Dhruv Srivastava <dhruv.srivastava at ibm.com>
Date: 2024-12-20 (Fri, 20 Dec 2024)
Changed paths:
M lldb/include/lldb/Host/linux/HostInfoLinux.h
M lldb/include/lldb/Host/posix/HostInfoPosix.h
M lldb/source/Host/linux/HostInfoLinux.cpp
M lldb/source/Host/posix/HostInfoPosix.cpp
Log Message:
-----------
[lldb][Linux] Moving generic APIs from HostInfoLinux to HostInfoPosix (#119694)
This change is related merging some of the APIs in HostInfoLinux into
HostInfoPosix.
Here is the reference PR comment:
https://github.com/llvm/llvm-project/pull/117906#discussion_r1865427495,
https://github.com/llvm/llvm-project/pull/117906#discussion_r1861616945
Commit: 8dc23efbe6c584c06d6472c6f1b679b5ca861b07
https://github.com/llvm/llvm-project/commit/8dc23efbe6c584c06d6472c6f1b679b5ca861b07
Author: James Chesterman <James.Chesterman at arm.com>
Date: 2024-12-20 (Fri, 20 Dec 2024)
Changed paths:
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
Log Message:
-----------
[NFC][AArch64][SVE] Rename variables in partial reduction lowering functions (#120589)
Commit: d7ddc976d544528fe7f16882f5bec66c3b2a7884
https://github.com/llvm/llvm-project/commit/d7ddc976d544528fe7f16882f5bec66c3b2a7884
Author: Wang Pengcheng <wangpengcheng.pp at bytedance.com>
Date: 2024-12-20 (Fri, 20 Dec 2024)
Changed paths:
M llvm/lib/CodeGen/MachinePipeliner.cpp
Log Message:
-----------
[MachinePipeliner] Remove unused private field MF
Commit: 000febd0290698728abd9e23da6b27969c529177
https://github.com/llvm/llvm-project/commit/000febd0290698728abd9e23da6b27969c529177
Author: Michael Buch <michaelbuch12 at gmail.com>
Date: 2024-12-20 (Fri, 20 Dec 2024)
Changed paths:
A lldb/test/Shell/Expr/TestObjCHiddenIvars.test
Log Message:
-----------
[lldb][test] Add test-coverage for DW_AT_APPLE_objc_complete_type parsing (#120279)
When given a DIE for an Objective-C interface (which doesn't have a
`DW_AT_APPLE_objc_complete_type`), the `DWARFASTParserClang` will try to
find the DIE which corresponds to the implementation to complete the
interface DIE. The code is here:
https://github.com/llvm/llvm-project/blob/d2e7ee77d33e8b3be3b1d4e9bc5bc4c60b62b554/lldb/source/Plugins/SymbolFile/DWARF/DWARFASTParserClang.cpp#L1718-L1738
However, this was currently not exercised in our test-suite (removing
the code above didn't fail any LLDB test).
This patch adds a test which exercises this codepath (it will fail if we
don't fetch the implementation DIE in the `DWARFASTParserClang`).
Something that's not currently clear to me is why `frame var *f`
succeeds even without the `DW_AT_APPLE_objc_complete_type`
infrastructure. If it's using the ObjC runtime, we should make `expr` do
the same, in which case we can remove this code from
`DWARFASTParserClang`.
Commit: e4db3f0d97681a10a76e71465f1379801cd45f54
https://github.com/llvm/llvm-project/commit/e4db3f0d97681a10a76e71465f1379801cd45f54
Author: serge-sans-paille <sguelton at mozilla.com>
Date: 2024-12-20 (Fri, 20 Dec 2024)
Changed paths:
M llvm/lib/Analysis/MemoryBuiltins.cpp
M llvm/test/Transforms/LowerConstantIntrinsics/builtin-object-size-phi.ll
M llvm/test/Transforms/LowerConstantIntrinsics/builtin-object-size-range.ll
M llvm/test/Transforms/LowerConstantIntrinsics/objectsize_basic.ll
Log Message:
-----------
[llvm] Bail out when meeting pointer with negative offset in approximated mode instead of … (#120424)
…generating empty location
Fix the regression detected by
https://github.com/llvm/llvm-test-suite/pull/188
Commit: 451a80ccc034799151d3a82c15e320cdde5a2e04
https://github.com/llvm/llvm-project/commit/451a80ccc034799151d3a82c15e320cdde5a2e04
Author: Martin Storsjö <martin at martin.st>
Date: 2024-12-20 (Fri, 20 Dec 2024)
Changed paths:
M llvm/docs/TestSuiteGuide.md
Log Message:
-----------
[docs] Mention ffmpeg and dav1d in llvm-test-suite (#120570)
Since https://github.com/llvm/llvm-test-suite/pull/182 and
https://github.com/llvm/llvm-test-suite/pull/188, these projects can now
be added as external projects within llvm-test-suite.
Commit: cf7b3f8d827abba49930202e51702714349c716d
https://github.com/llvm/llvm-project/commit/cf7b3f8d827abba49930202e51702714349c716d
Author: William Tran-Viet <wtranviet at proton.me>
Date: 2024-12-20 (Fri, 20 Dec 2024)
Changed paths:
M clang/include/clang/Basic/DiagnosticSemaKinds.td
M clang/lib/Sema/SemaExprMember.cpp
M clang/test/SemaCXX/vector-bool.cpp
Log Message:
-----------
Fix double-quotes in diagnostic when attempting to access a ext_vector of bools (#118186)
Fixes #116932
- Remove the quotation marks in the diagnostic message for
err_ext_vector_component_name_illegal
- Pass in the quotation marks directly when reporting an illegal vector
component name inside `CheckExtVectorComponent`
- Add an offset to the `OpLoc` passed into `S.Diag` so the error message
arrow points directly to the offending illegal component rather than to
the '.' at the start of the component identifier.
- Modify the `vector-bool.cpp` element-wise access test case so it
(correctly) now only expects a single set of quotes.
Commit: eb6c4197d5263ed2e086925b2b2f032a19442d2b
https://github.com/llvm/llvm-project/commit/eb6c4197d5263ed2e086925b2b2f032a19442d2b
Author: Matthias Springer <me at m-sp.org>
Date: 2024-12-20 (Fri, 20 Dec 2024)
Changed paths:
M flang/lib/Optimizer/CodeGen/CodeGen.cpp
M mlir/include/mlir/Conversion/Passes.td
M mlir/lib/Conversion/ControlFlowToLLVM/ControlFlowToLLVM.cpp
M mlir/lib/Conversion/FuncToLLVM/FuncToLLVM.cpp
M mlir/lib/Dialect/SparseTensor/Pipelines/SparseTensorPipelines.cpp
A mlir/test/Conversion/ControlFlowToLLVM/branch.mlir
R mlir/test/Conversion/ControlFlowToLLVM/invalid.mlir
A mlir/test/Conversion/ControlFlowToLLVM/switch.mlir
M mlir/test/Conversion/FuncToLLVM/convert-funcs.mlir
M mlir/test/Conversion/FuncToLLVM/func-memref.mlir
M mlir/test/Conversion/FuncToLLVM/func-to-llvm.mlir
M mlir/test/Integration/Dialect/Async/CPU/microbench-linalg-async-parallel-for.mlir
M mlir/test/Integration/Dialect/Async/CPU/microbench-scf-async-parallel-for.mlir
M mlir/test/Integration/Dialect/Async/CPU/test-async-parallel-for-1d.mlir
M mlir/test/Integration/Dialect/Async/CPU/test-async-parallel-for-2d.mlir
M mlir/test/Integration/Dialect/Complex/CPU/correctness.mlir
M mlir/test/Integration/Dialect/LLVMIR/CPU/X86/test-inline-asm-vector.mlir
M mlir/test/Integration/Dialect/Linalg/CPU/matmul-vs-matvec.mlir
M mlir/test/Integration/Dialect/Linalg/CPU/runtime-verification.mlir
M mlir/test/Integration/Dialect/Linalg/CPU/test-conv-1d-call.mlir
M mlir/test/Integration/Dialect/Linalg/CPU/test-conv-1d-nwc-wcf-call.mlir
M mlir/test/Integration/Dialect/Linalg/CPU/test-conv-2d-call.mlir
M mlir/test/Integration/Dialect/Linalg/CPU/test-conv-2d-nhwc-hwcf-call.mlir
M mlir/test/Integration/Dialect/Linalg/CPU/test-conv-3d-call.mlir
M mlir/test/Integration/Dialect/Linalg/CPU/test-conv-3d-ndhwc-dhwcf-call.mlir
M mlir/test/Integration/Dialect/Linalg/CPU/test-one-shot-bufferize.mlir
M mlir/test/Integration/Dialect/Linalg/CPU/test-padtensor.mlir
M mlir/test/Integration/Dialect/Linalg/CPU/test-tensor-matmul.mlir
M mlir/test/Integration/Dialect/MemRef/memref_abi.c
M mlir/test/Integration/Dialect/Standard/CPU/test-ceil-floor-pos-neg.mlir
M mlir/test/Integration/Dialect/Vector/CPU/0-d-vectors.mlir
M mlir/test/Integration/Dialect/Vector/CPU/broadcast.mlir
M mlir/test/Integration/Dialect/Vector/CPU/compress.mlir
M mlir/test/Integration/Dialect/Vector/CPU/constant-mask.mlir
M mlir/test/Integration/Dialect/Vector/CPU/contraction.mlir
M mlir/test/Integration/Dialect/Vector/CPU/create-mask-v4i1.mlir
M mlir/test/Integration/Dialect/Vector/CPU/create-mask.mlir
M mlir/test/Integration/Dialect/Vector/CPU/expand.mlir
M mlir/test/Integration/Dialect/Vector/CPU/extract-strided-slice.mlir
M mlir/test/Integration/Dialect/Vector/CPU/flat-transpose-col.mlir
M mlir/test/Integration/Dialect/Vector/CPU/flat-transpose-row.mlir
M mlir/test/Integration/Dialect/Vector/CPU/fma.mlir
M mlir/test/Integration/Dialect/Vector/CPU/gather.mlir
M mlir/test/Integration/Dialect/Vector/CPU/index-vectors.mlir
M mlir/test/Integration/Dialect/Vector/CPU/insert-strided-slice.mlir
M mlir/test/Integration/Dialect/Vector/CPU/maskedload.mlir
M mlir/test/Integration/Dialect/Vector/CPU/maskedstore.mlir
M mlir/test/Integration/Dialect/Vector/CPU/matrix-multiply-col.mlir
M mlir/test/Integration/Dialect/Vector/CPU/matrix-multiply-row.mlir
M mlir/test/Integration/Dialect/Vector/CPU/outerproduct-f32.mlir
M mlir/test/Integration/Dialect/Vector/CPU/outerproduct-i64.mlir
M mlir/test/Integration/Dialect/Vector/CPU/print-fp.mlir
M mlir/test/Integration/Dialect/Vector/CPU/print-int.mlir
M mlir/test/Integration/Dialect/Vector/CPU/realloc.mlir
M mlir/test/Integration/Dialect/Vector/CPU/reductions-f32-reassoc.mlir
M mlir/test/Integration/Dialect/Vector/CPU/reductions-f32.mlir
M mlir/test/Integration/Dialect/Vector/CPU/reductions-f64-reassoc.mlir
M mlir/test/Integration/Dialect/Vector/CPU/reductions-f64.mlir
M mlir/test/Integration/Dialect/Vector/CPU/reductions-i32.mlir
M mlir/test/Integration/Dialect/Vector/CPU/reductions-i4.mlir
M mlir/test/Integration/Dialect/Vector/CPU/reductions-i64.mlir
M mlir/test/Integration/Dialect/Vector/CPU/reductions-si4.mlir
M mlir/test/Integration/Dialect/Vector/CPU/reductions-ui4.mlir
M mlir/test/Integration/Dialect/Vector/CPU/scan.mlir
M mlir/test/Integration/Dialect/Vector/CPU/scatter.mlir
M mlir/test/Integration/Dialect/Vector/CPU/shape-cast.mlir
M mlir/test/Integration/Dialect/Vector/CPU/shuffle.mlir
M mlir/test/Integration/Dialect/Vector/CPU/shuffle16x16.mlir
M mlir/test/Integration/Dialect/Vector/CPU/sparse-dot-matvec.mlir
M mlir/test/Integration/Dialect/Vector/CPU/sparse-saxpy-jagged-matvec.mlir
M mlir/test/Integration/Dialect/Vector/CPU/transfer-read-1d.mlir
M mlir/test/Integration/Dialect/Vector/CPU/transfer-read-2d.mlir
M mlir/test/Integration/Dialect/Vector/CPU/transfer-read-3d.mlir
M mlir/test/Integration/Dialect/Vector/CPU/transfer-read.mlir
M mlir/test/Integration/Dialect/Vector/CPU/transfer-to-loops.mlir
M mlir/test/Integration/Dialect/Vector/CPU/transfer-write.mlir
M mlir/test/Integration/Dialect/Vector/CPU/transpose.mlir
M mlir/test/lib/Dialect/LLVM/TestLowerToLLVM.cpp
M mlir/test/mlir-cpu-runner/async-error.mlir
M mlir/test/mlir-cpu-runner/async-group.mlir
M mlir/test/mlir-cpu-runner/async-value.mlir
M mlir/test/mlir-cpu-runner/async.mlir
M mlir/test/mlir-cpu-runner/bare-ptr-call-conv.mlir
M mlir/test/mlir-cpu-runner/copy.mlir
M mlir/test/mlir-cpu-runner/memref-reinterpret-cast.mlir
M mlir/test/mlir-cpu-runner/memref-reshape.mlir
M mlir/test/mlir-cpu-runner/sgemm-naive-codegen.mlir
M mlir/test/mlir-cpu-runner/unranked-memref.mlir
M mlir/test/mlir-cpu-runner/utils.mlir
M mlir/test/python/execution_engine.py
M mlir/test/python/integration/dialects/linalg/opsrun.py
M mlir/tools/mlir-vulkan-runner/mlir-vulkan-runner.cpp
Log Message:
-----------
[mlir][CF] Split `cf-to-llvm` from `func-to-llvm` (#120580)
Do not run `cf-to-llvm` as part of `func-to-llvm`. This commit fixes
https://github.com/llvm/llvm-project/issues/70982.
This commit changes the way how `func.func` ops are lowered to LLVM.
Previously, the signature of the entire region (i.e., entry block and
all other blocks in the `func.func` op) was converted as part of the
`func.func` lowering pattern.
Now, only the entry block is converted. The remaining block signatures
are converted together with `cf.br` and `cf.cond_br` as part of
`cf-to-llvm`. All unstructured control flow is not converted as part of
a single pass (`cf-to-llvm`). `func-to-llvm` no longer deals with
unstructured control flow.
Also add more test cases for control flow dialect ops.
Note: This PR is in preparation of #120431, which adds an additional
GPU-specific lowering for `cf.assert`. This was a problem because
`cf.assert` used to be converted as part of `func-to-llvm`.
Note for LLVM integration: If you see failures, add
`-convert-cf-to-llvm` to your pass pipeline.
Commit: 1738b75b615497b880d5a9e4a1b769e9ff001d23
https://github.com/llvm/llvm-project/commit/1738b75b615497b880d5a9e4a1b769e9ff001d23
Author: Nikita Popov <npopov at redhat.com>
Date: 2024-12-20 (Fri, 20 Dec 2024)
Changed paths:
M llvm/Maintainers.md
Log Message:
-----------
[LLVM] Update InstCombine maintainers (#120408)
> See [developer
policy](https://llvm.org/docs/DeveloperPolicy.html#maintainers) for
context on the maintainers terminology.
We currently list @majnemer as the maintainer for InstCombine. While
David does still occasionally contribute in this area, most of the
contributions/reviews come from other people nowadays.
I'd like to propose @dtcxzyw and myself as the new maintainers for this
area. I've also expanded it to include InstSimplify and ValueTracking,
and these tend to all go together.
Commit: e11d49cbf5a210ea312f891d9dff6b4bf6433d57
https://github.com/llvm/llvm-project/commit/e11d49cbf5a210ea312f891d9dff6b4bf6433d57
Author: Alexey Moksyakov <yavtuk at yandex.ru>
Date: 2024-12-20 (Fri, 20 Dec 2024)
Changed paths:
M bolt/lib/Core/Relocation.cpp
M bolt/lib/Target/AArch64/AArch64MCPlusBuilder.cpp
Log Message:
-----------
[BOLT][AArch64] Adds tls relocations support (#117465)
Co-authored-by: yavtuk <yavtuk at ya.ru>
Commit: 0dc086a787a49d7514f713d0ee0b709fc28bb702
https://github.com/llvm/llvm-project/commit/0dc086a787a49d7514f713d0ee0b709fc28bb702
Author: Matthias Springer <me at m-sp.org>
Date: 2024-12-20 (Fri, 20 Dec 2024)
Changed paths:
M mlir/test/Integration/GPU/CUDA/async.mlir
Log Message:
-----------
[mlir] Fix integration tests after #120580 (#120729)
This commit should have been part of #120580.
Commit: 4eba40c604c75b5c5561ffd6e009dbbb5a4f0b4b
https://github.com/llvm/llvm-project/commit/4eba40c604c75b5c5561ffd6e009dbbb5a4f0b4b
Author: Yingwei Zheng <dtcxzyw2333 at gmail.com>
Date: 2024-12-20 (Fri, 20 Dec 2024)
Changed paths:
M llvm/lib/Analysis/ConstraintSystem.cpp
Log Message:
-----------
[ConstraintElim] Remove dead code. NFC. (#118983)
`R2` should be always greater than `R1` here because both `R1` and `R2` are not modified inside the loop.
Commit: a9034d0b7ff3b0bf90239f6b46ada7f3490b6904
https://github.com/llvm/llvm-project/commit/a9034d0b7ff3b0bf90239f6b46ada7f3490b6904
Author: Jonas Toth <development at jonas-toth.eu>
Date: 2024-12-20 (Fri, 20 Dec 2024)
Changed paths:
M clang-tools-extra/docs/clang-tidy/checks/cppcoreguidelines/narrowing-conversions.rst
Log Message:
-----------
[clang-tidy][docs] improve documentation on cppcoreguidelines-narrowing-conversions (#111510) (#118209)
This PR improves the docs for this check to include an example of hidden
narrowing conversions from the integer promotion rules in arithmetic.
Commit: c5434804eeea643f0420bc5fd83dd4977731f4d2
https://github.com/llvm/llvm-project/commit/c5434804eeea643f0420bc5fd83dd4977731f4d2
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-12-20 (Fri, 20 Dec 2024)
Changed paths:
M llvm/lib/Transforms/Vectorize/VectorCombine.cpp
Log Message:
-----------
[VectorCombine] foldInsExtVectorToShuffle - add debug message for match + cost-comparison
Helps with debugging to show to that the fold found the match, and shows the old + new costs to indicate whether the fold was/wasn't profitable.
Commit: 5f0db7c11264fa235d73730b2b93a31407dfbef3
https://github.com/llvm/llvm-project/commit/5f0db7c11264fa235d73730b2b93a31407dfbef3
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-12-20 (Fri, 20 Dec 2024)
Changed paths:
M llvm/lib/Transforms/Vectorize/VectorCombine.cpp
Log Message:
-----------
[VectorCombine] Add "VECTORCOMBINE on <FUNCTION_NAME>" title debug message to help finding vectorcombine stages in the debug log
Commit: 42873e0cf107045b76d0fc221cdb838cdb0766bf
https://github.com/llvm/llvm-project/commit/42873e0cf107045b76d0fc221cdb838cdb0766bf
Author: Mikhail Goncharov <goncharov.mikhail at gmail.com>
Date: 2024-12-20 (Fri, 20 Dec 2024)
Changed paths:
M utils/bazel/llvm-project-overlay/mlir/BUILD.bazel
M utils/bazel/llvm-project-overlay/mlir/test/BUILD.bazel
Log Message:
-----------
[bazel] port eb6c4197d5263ed2e086925b2b2f032a19442d2b
Commit: 54309b1c2f7a9acdb91ae1735cf4eb0877eadfc0
https://github.com/llvm/llvm-project/commit/54309b1c2f7a9acdb91ae1735cf4eb0877eadfc0
Author: Jan Voung <jvoung at google.com>
Date: 2024-12-20 (Fri, 20 Dec 2024)
Changed paths:
A clang/include/clang/Analysis/FlowSensitive/SmartPointerAccessorCaching.h
M clang/lib/Analysis/FlowSensitive/CMakeLists.txt
A clang/lib/Analysis/FlowSensitive/SmartPointerAccessorCaching.cpp
M clang/unittests/Analysis/FlowSensitive/CMakeLists.txt
A clang/unittests/Analysis/FlowSensitive/SmartPointerAccessorCachingTest.cpp
Log Message:
-----------
[clang][dataflow] Add matchers for smart pointer accessors to be cached (#120102)
This is part 1 of caching for smart pointer accessors, building on top
of the CachedConstAccessorsLattice, which caches "normal" accessors.
Smart pointer accessors are a bit different in that they may:
- have aliases to access the same underlying data (but potentially
returning slightly different types like `&` vs `*`). Within a
"checked" sequence users may mix uses of the different aliases and the
check should apply to any of the spellings.
- may have non-const overloads in addition to the const version, where
the non-const doesn't actually modify the container
Part 2 will follow and add transfer functions utilities. It will also
add a user UncheckedOptionalAccessModel. We'd seen false positives when
nesting StatusOr<optional<T>> and optional<StatusOr<T>>, etc. which this
can help address.
Commit: 54665f5252695922dd000f311f82af717f1df0c6
https://github.com/llvm/llvm-project/commit/54665f5252695922dd000f311f82af717f1df0c6
Author: LLVM GN Syncbot <llvmgnsyncbot at gmail.com>
Date: 2024-12-20 (Fri, 20 Dec 2024)
Changed paths:
M llvm/utils/gn/secondary/clang/lib/Analysis/FlowSensitive/BUILD.gn
M llvm/utils/gn/secondary/clang/unittests/Analysis/FlowSensitive/BUILD.gn
Log Message:
-----------
[gn build] Port 54309b1c2f7a
Commit: fa9cef50b1afc203b6b653396f9e775862c26e68
https://github.com/llvm/llvm-project/commit/fa9cef50b1afc203b6b653396f9e775862c26e68
Author: Dominik Steenken <dost at de.ibm.com>
Date: 2024-12-20 (Fri, 20 Dec 2024)
Changed paths:
M llvm/include/llvm/IR/Instruction.h
M llvm/lib/IR/Instruction.cpp
M llvm/lib/Transforms/Utils/Local.cpp
M llvm/test/Transforms/SimplifyCFG/preserve-llvm-loop-metadata.ll
Log Message:
-----------
Only guard loop metadata that has non-debug info in it (#118825)
This PR is motivated by a mismatch we discovered between compilation
results with vs. without `-g3`. We noticed this when compiling SPEC2017
testcases. The specific instance we saw is fixed in this PR by modifying
a guard (see below), but it is likely similar instances exist elsewhere
in the codebase.
The specific case fixed in this PR manifests itself in the `SimplifyCFG`
pass doing different things depending on whether DebugInfo is generated
or not. At the end of this comment, there is reduced example code that
shows the behavior in question.
The differing behavior has two root causes:
1. Commit https://github.com/llvm/llvm-project/commit/c07e19b adds loop
metadata including debug locations to loops that otherwise would not
have loop metadata
2. Commit https://github.com/llvm/llvm-project/commit/ac28efa6c100 adds
a guard to a simplification action in `SImplifyCFG` that prevents it
from simplifying away loop metadata
So, the change in 2. does not consider that when compiling with debug
symbols, loops that otherwise would not have metadata that needs
preserving, now have debug locations in their loop metadata. Thus, with
`-g3`, `SimplifyCFG` behaves differently than without it.
The larger issue is that while debug info is not supposed to influence
the final compilation result, commits like 1. blur the line between what
is and is not debug info, and not all optimization passes account for
this.
This PR does not address that and rather just modifies this particular
guard in order to restore equivalent behavior between debug and
non-debug builds in this one instance.
---
Here is a reduced version of a file from `f526.blender_r` that showcases
the behavior in question:
```C
struct LinkNode;
typedef struct LinkNode {
struct LinkNode *next;
void *link;
} LinkNode;
void do_projectpaint_thread_ph_v_state() {
int *ps = do_projectpaint_thread_ph_v_state;
LinkNode *node;
while (do_projectpaint_thread_ph_v_state)
for (node = ps; node; node = node->next)
;
}
```
Compiling this with and without DebugInfo, and then disassembling the
results, leads to different outcomes (tested on SystemZ and X86). The
reason for this is that the `SimplifyCFG` pass does different things in
either case.
Commit: 9e333872199b1e3bf488d71e222ff4b6f0370347
https://github.com/llvm/llvm-project/commit/9e333872199b1e3bf488d71e222ff4b6f0370347
Author: Congcong Cai <congcongcai0907 at 163.com>
Date: 2024-12-20 (Fri, 20 Dec 2024)
Changed paths:
M clang/lib/StaticAnalyzer/Core/TextDiagnostics.cpp
Log Message:
-----------
[clang analyzer]consume `llvm::Error` (#120597)
`llvm::Error` must be consumed, otherwise it will cause trap during destructor
Commit: acfd26a93be3fb70013560f3fb894eb9086e7e32
https://github.com/llvm/llvm-project/commit/acfd26a93be3fb70013560f3fb894eb9086e7e32
Author: Julian Nagele <j.nagele at apple.com>
Date: 2024-12-20 (Fri, 20 Dec 2024)
Changed paths:
M llvm/lib/Analysis/ScalarEvolution.cpp
M llvm/test/Analysis/ScalarEvolution/backedge-taken-count-guard-info-with-multiple-predecessors.ll
Log Message:
-----------
[SCEV] Fix exit condition for recursive loop guard collection (#120442)
When assumptions are present `Terms.size()` does not actually count the
number of conditions collected from dominating branches; introduce a
separate counter.
Fixes https://github.com/llvm/llvm-project/issues/120237
Commit: 2d5dc5c208532833e2ce55d7e1ce29063d91bbe3
https://github.com/llvm/llvm-project/commit/2d5dc5c208532833e2ce55d7e1ce29063d91bbe3
Author: Jan Voung <jvoung at google.com>
Date: 2024-12-20 (Fri, 20 Dec 2024)
Changed paths:
M clang/lib/Analysis/FlowSensitive/SmartPointerAccessorCaching.cpp
Log Message:
-----------
[clang][dataflow] Fix a missing break from a switch case -Wimplicit-fallthrough (#120739)
Missed when changing code in
https://github.com/llvm/llvm-project/pull/120102
Commit: b87a5fb9fd8d50c911ac95f6854389d287542010
https://github.com/llvm/llvm-project/commit/b87a5fb9fd8d50c911ac95f6854389d287542010
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-12-20 (Fri, 20 Dec 2024)
Changed paths:
M llvm/lib/Transforms/Vectorize/VectorCombine.cpp
Log Message:
-----------
[VectorCombine] Add "VC: Visiting" debug message to help the log show the instruction folding order.
Commit: 70eac255b8c09244c7a9af7599fbe27d886010e9
https://github.com/llvm/llvm-project/commit/70eac255b8c09244c7a9af7599fbe27d886010e9
Author: David Green <david.green at arm.com>
Date: 2024-12-20 (Fri, 20 Dec 2024)
Changed paths:
M llvm/lib/Transforms/Vectorize/VectorCombine.cpp
M llvm/test/Transforms/VectorCombine/AArch64/shuffletoidentity.ll
Log Message:
-----------
[VectorCombine] Add fp cast handling for shuffletoidentity (#120641)
This fixes some regressions from recent changes to vector combine in
#120216. It allows shuffleToIdentity to look through fp casts as other
casts, and makes sure mismatching vector types in splats and casts do
not block the transform, as only the lanes should matter.
Commit: 5845298f9439796a3a2f15dfce8250e322ddce4a
https://github.com/llvm/llvm-project/commit/5845298f9439796a3a2f15dfce8250e322ddce4a
Author: David Sherwood <david.sherwood at arm.com>
Date: 2024-12-20 (Fri, 20 Dec 2024)
Changed paths:
M llvm/test/Transforms/LoopVectorize/X86/CostModel/gather-i16-with-i8-index.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/gather-i32-with-i8-index.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/gather-i64-with-i8-index.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/gather-i8-with-i8-index.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-f32-stride-2.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-f32-stride-3.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-f32-stride-4.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i16-stride-2.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i16-stride-3.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i16-stride-4.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i16-stride-6.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i32-stride-2-indices-0u.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i32-stride-2.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i32-stride-3-indices-01u.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i32-stride-3-indices-0uu.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i32-stride-3.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i32-stride-4-indices-012u.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i32-stride-4-indices-0uuu.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i32-stride-4.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i32-stride-6.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i8-stride-2.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i8-stride-3.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i8-stride-4.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-f32-stride-2.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-f32-stride-3.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-f32-stride-4.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-f32-stride-5.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-f32-stride-6.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-f32-stride-7.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-f64-stride-2.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-f64-stride-3.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-f64-stride-4.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-f64-stride-5.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-f64-stride-6.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-f64-stride-7.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i16-stride-2.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i16-stride-3.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i16-stride-4.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i16-stride-5.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i16-stride-6.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i16-stride-7.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i32-stride-2.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i32-stride-3.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i32-stride-4.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i32-stride-5.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i32-stride-6.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i32-stride-7.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i64-stride-2.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i64-stride-3.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i64-stride-4.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i64-stride-5.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i64-stride-6.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i64-stride-7.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i8-stride-2.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i8-stride-3.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i8-stride-4.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i8-stride-5.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i8-stride-6.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i8-stride-7.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/masked-gather-i32-with-i8-index.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/masked-gather-i64-with-i8-index.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/masked-load-i16.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/masked-load-i32.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/masked-load-i64.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/masked-load-i8.ll
Log Message:
-----------
[LoopVectorize] Teach some X86 cost model tests to use new vplan costs (#120738)
I've only fixed up the tests where I was able to use a simple sed script
to replace the text. Even after this patch lands, there are still over
50 tests that need updating in X86/CostModel!
Commit: 953b07febca46036b2311b5998244fe07b61544f
https://github.com/llvm/llvm-project/commit/953b07febca46036b2311b5998244fe07b61544f
Author: Ivan Butygin <ivan.butygin at gmail.com>
Date: 2024-12-20 (Fri, 20 Dec 2024)
Changed paths:
M mlir/lib/Conversion/AMDGPUToROCDL/AMDGPUToROCDL.cpp
M mlir/test/Conversion/AMDGPUToROCDL/amdgpu-to-rocdl.mlir
Log Message:
-----------
[mlir] AMDGPUToROCDL: RawBufferOpLowering fixes (#120642)
1. We can use `getNumElements()` only for memrefs with trivial layout.
2. Buffer ops expecting sizes in i32 but descriptor values can be either
i32 or i64, add appropriate casts. This implementation is not ideal as
it can overflow, but it's still better than generating broken IR.
Commit: 22b76d079c584fb03df166ecd757f3df5cf92eba
https://github.com/llvm/llvm-project/commit/22b76d079c584fb03df166ecd757f3df5cf92eba
Author: Florian Mayer <fmayer at google.com>
Date: 2024-12-20 (Fri, 20 Dec 2024)
Changed paths:
M bolt/lib/Core/Relocation.cpp
M bolt/lib/Target/AArch64/AArch64MCPlusBuilder.cpp
M clang-tools-extra/docs/clang-tidy/checks/cppcoreguidelines/narrowing-conversions.rst
A clang/include/clang/Analysis/FlowSensitive/SmartPointerAccessorCaching.h
M clang/include/clang/Basic/DiagnosticSemaKinds.td
M clang/lib/Analysis/FlowSensitive/CMakeLists.txt
A clang/lib/Analysis/FlowSensitive/SmartPointerAccessorCaching.cpp
M clang/lib/Sema/SemaExprMember.cpp
M clang/lib/StaticAnalyzer/Core/TextDiagnostics.cpp
M clang/test/SemaCXX/vector-bool.cpp
M clang/unittests/Analysis/FlowSensitive/CMakeLists.txt
A clang/unittests/Analysis/FlowSensitive/SmartPointerAccessorCachingTest.cpp
M compiler-rt/lib/interception/interception_win.cpp
M compiler-rt/lib/sanitizer_common/CMakeLists.txt
M compiler-rt/lib/sanitizer_common/sanitizer_common_interface.inc
R compiler-rt/lib/sanitizer_common/sanitizer_contiguous_container.cpp
M flang/lib/Lower/OpenMP/OpenMP.cpp
M flang/lib/Optimizer/CodeGen/CodeGen.cpp
R flang/test/Lower/OpenMP/Todo/task_untied.f90
M flang/test/Lower/OpenMP/task.f90
M lldb/include/lldb/Host/linux/HostInfoLinux.h
M lldb/include/lldb/Host/posix/HostInfoPosix.h
M lldb/source/Host/linux/HostInfoLinux.cpp
M lldb/source/Host/posix/HostInfoPosix.cpp
M lldb/source/Host/posix/ProcessLauncherPosixFork.cpp
M lldb/source/Plugins/SymbolFile/DWARF/DWARFASTParserClang.cpp
M lldb/source/Plugins/SymbolFile/DWARF/DWARFASTParserClang.h
A lldb/test/Shell/Expr/TestObjCHiddenIvars.test
M lldb/tools/driver/CMakeLists.txt
M llvm/Maintainers.md
M llvm/docs/MemTagSanitizer.rst
M llvm/docs/TestSuiteGuide.md
M llvm/include/llvm/BinaryFormat/ELF.h
M llvm/include/llvm/IR/Instruction.h
M llvm/include/llvm/Passes/DroppedVariableStats.h
A llvm/include/llvm/Passes/DroppedVariableStatsIR.h
M llvm/include/llvm/Passes/StandardInstrumentations.h
M llvm/lib/Analysis/ConstraintSystem.cpp
M llvm/lib/Analysis/MemoryBuiltins.cpp
M llvm/lib/Analysis/ScalarEvolution.cpp
M llvm/lib/CodeGen/MachinePipeliner.cpp
M llvm/lib/IR/Instruction.cpp
M llvm/lib/Passes/CMakeLists.txt
R llvm/lib/Passes/DroppedVariableStats.cpp
A llvm/lib/Passes/DroppedVariableStatsIR.cpp
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
M llvm/lib/Target/AArch64/AArch64InstrInfo.td
M llvm/lib/Target/Mips/MCTargetDesc/CMakeLists.txt
M llvm/lib/Target/Mips/MCTargetDesc/MipsAsmBackend.cpp
M llvm/lib/Target/Mips/MCTargetDesc/MipsMCAsmInfo.cpp
M llvm/lib/Target/Mips/MCTargetDesc/MipsMCAsmInfo.h
M llvm/lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.cpp
M llvm/lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.h
A llvm/lib/Target/Mips/MCTargetDesc/MipsWinCOFFObjectWriter.cpp
A llvm/lib/Target/Mips/MCTargetDesc/MipsWinCOFFStreamer.cpp
M llvm/lib/Target/Mips/MipsTargetMachine.cpp
M llvm/lib/Target/X86/X86TargetTransformInfo.cpp
M llvm/lib/Transforms/Utils/Local.cpp
M llvm/lib/Transforms/Vectorize/VectorCombine.cpp
M llvm/test/Analysis/CostModel/X86/shuffle-concat_subvector-codesize.ll
M llvm/test/Analysis/CostModel/X86/shuffle-concat_subvector-latency.ll
M llvm/test/Analysis/CostModel/X86/shuffle-concat_subvector-sizelatency.ll
M llvm/test/Analysis/CostModel/X86/shuffle-concat_subvector.ll
M llvm/test/Analysis/CostModel/X86/shuffle-insert_subvector-codesize.ll
M llvm/test/Analysis/CostModel/X86/shuffle-insert_subvector-latency.ll
M llvm/test/Analysis/CostModel/X86/shuffle-insert_subvector-sizelatency.ll
M llvm/test/Analysis/CostModel/X86/shuffle-insert_subvector.ll
M llvm/test/Analysis/CostModel/X86/shuffle-two-src-codesize.ll
M llvm/test/Analysis/CostModel/X86/shuffle-two-src-fp16-codesize.ll
M llvm/test/Analysis/CostModel/X86/shuffle-two-src-fp16-latency.ll
M llvm/test/Analysis/CostModel/X86/shuffle-two-src-fp16-sizelatency.ll
M llvm/test/Analysis/CostModel/X86/shuffle-two-src-fp16.ll
M llvm/test/Analysis/CostModel/X86/shuffle-two-src-latency.ll
M llvm/test/Analysis/CostModel/X86/shuffle-two-src-sizelatency.ll
M llvm/test/Analysis/CostModel/X86/shuffle-two-src.ll
M llvm/test/Analysis/ScalarEvolution/backedge-taken-count-guard-info-with-multiple-predecessors.ll
M llvm/test/CodeGen/AArch64/aarch64-neon-vector-insert-uaddlv.ll
A llvm/test/CodeGen/AArch64/neon-ins-trunc-elt.ll
M llvm/test/CodeGen/AArch64/sve-doublereduct.ll
M llvm/test/CodeGen/AArch64/sve-extract-element.ll
M llvm/test/CodeGen/AArch64/sve-extract-fixed-vector.ll
M llvm/test/CodeGen/AArch64/sve-fixed-length-int-reduce.ll
M llvm/test/CodeGen/AArch64/sve-int-reduce.ll
M llvm/test/CodeGen/AArch64/sve-split-int-reduce.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-reduce.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-reductions.ll
M llvm/test/CodeGen/AArch64/sve-vecreduce-dot.ll
M llvm/test/CodeGen/AArch64/uaddlv-vaddlp-combine.ll
M llvm/test/CodeGen/AArch64/vec-combine-compare-to-bitmask.ll
M llvm/test/CodeGen/AArch64/vecreduce-bool.ll
M llvm/test/CodeGen/Mips/Fast-ISel/br1.ll
M llvm/test/CodeGen/Mips/Fast-ISel/icmpbr1.ll
M llvm/test/CodeGen/Mips/addressing-mode.ll
M llvm/test/CodeGen/Mips/atomic-min-max-64.ll
M llvm/test/CodeGen/Mips/atomic-min-max.ll
M llvm/test/CodeGen/Mips/brconeq.ll
M llvm/test/CodeGen/Mips/brconeqk.ll
M llvm/test/CodeGen/Mips/brconeqz.ll
M llvm/test/CodeGen/Mips/brconge.ll
M llvm/test/CodeGen/Mips/brcongt.ll
M llvm/test/CodeGen/Mips/brconle.ll
M llvm/test/CodeGen/Mips/brconlt.ll
M llvm/test/CodeGen/Mips/brconne.ll
M llvm/test/CodeGen/Mips/brconnek.ll
M llvm/test/CodeGen/Mips/brconnez.ll
M llvm/test/CodeGen/Mips/cconv/memory-layout.ll
M llvm/test/CodeGen/Mips/cfi_offset.ll
M llvm/test/CodeGen/Mips/dins.ll
M llvm/test/CodeGen/Mips/dsp-r1.ll
M llvm/test/CodeGen/Mips/eh-return32.ll
M llvm/test/CodeGen/Mips/eh-return64.ll
M llvm/test/CodeGen/Mips/emit-big-cst.ll
M llvm/test/CodeGen/Mips/ex2.ll
M llvm/test/CodeGen/Mips/fpbr.ll
M llvm/test/CodeGen/Mips/frame-address.ll
M llvm/test/CodeGen/Mips/jumptable_labels.ll
M llvm/test/CodeGen/Mips/llvm-ir/add.ll
M llvm/test/CodeGen/Mips/llvm-ir/indirectbr.ll
M llvm/test/CodeGen/Mips/llvm-ir/select-int.ll
M llvm/test/CodeGen/Mips/load-store-left-right.ll
M llvm/test/CodeGen/Mips/mcount.ll
M llvm/test/CodeGen/Mips/micromips-sizereduction/micromips-lbu16-lhu16-sb16-sh16.ll
M llvm/test/CodeGen/Mips/mips64directive.ll
M llvm/test/CodeGen/Mips/msa/2r.ll
M llvm/test/CodeGen/Mips/msa/2r_vector_scalar.ll
M llvm/test/CodeGen/Mips/msa/2rf.ll
M llvm/test/CodeGen/Mips/msa/2rf_exup.ll
M llvm/test/CodeGen/Mips/msa/2rf_float_int.ll
M llvm/test/CodeGen/Mips/msa/2rf_fq.ll
M llvm/test/CodeGen/Mips/msa/2rf_int_float.ll
M llvm/test/CodeGen/Mips/msa/2rf_tq.ll
M llvm/test/CodeGen/Mips/msa/3r-a.ll
M llvm/test/CodeGen/Mips/msa/3r-b.ll
M llvm/test/CodeGen/Mips/msa/3r-c.ll
M llvm/test/CodeGen/Mips/msa/3r-d.ll
M llvm/test/CodeGen/Mips/msa/3r-i.ll
M llvm/test/CodeGen/Mips/msa/3r-m.ll
M llvm/test/CodeGen/Mips/msa/3r-p.ll
M llvm/test/CodeGen/Mips/msa/3r-s.ll
M llvm/test/CodeGen/Mips/msa/3r-v.ll
M llvm/test/CodeGen/Mips/msa/3r_4r.ll
M llvm/test/CodeGen/Mips/msa/3r_4r_widen.ll
M llvm/test/CodeGen/Mips/msa/3r_splat.ll
M llvm/test/CodeGen/Mips/msa/3rf.ll
M llvm/test/CodeGen/Mips/msa/3rf_4rf.ll
M llvm/test/CodeGen/Mips/msa/3rf_4rf_q.ll
M llvm/test/CodeGen/Mips/msa/3rf_exdo.ll
M llvm/test/CodeGen/Mips/msa/3rf_float_int.ll
M llvm/test/CodeGen/Mips/msa/3rf_int_float.ll
M llvm/test/CodeGen/Mips/msa/3rf_q.ll
M llvm/test/CodeGen/Mips/msa/arithmetic_float.ll
M llvm/test/CodeGen/Mips/msa/bit.ll
M llvm/test/CodeGen/Mips/msa/bitcast.ll
M llvm/test/CodeGen/Mips/msa/compare.ll
M llvm/test/CodeGen/Mips/msa/compare_float.ll
M llvm/test/CodeGen/Mips/msa/elm_copy.ll
M llvm/test/CodeGen/Mips/msa/elm_cxcmsa.ll
M llvm/test/CodeGen/Mips/msa/elm_insv.ll
M llvm/test/CodeGen/Mips/msa/elm_move.ll
M llvm/test/CodeGen/Mips/msa/elm_shift_slide.ll
M llvm/test/CodeGen/Mips/msa/endian.ll
M llvm/test/CodeGen/Mips/msa/frameindex.ll
M llvm/test/CodeGen/Mips/msa/i10.ll
M llvm/test/CodeGen/Mips/msa/i5-a.ll
M llvm/test/CodeGen/Mips/msa/i5-c.ll
M llvm/test/CodeGen/Mips/msa/i5-m.ll
M llvm/test/CodeGen/Mips/msa/i5_ld_st.ll
M llvm/test/CodeGen/Mips/msa/i8.ll
M llvm/test/CodeGen/Mips/msa/remat-ldi.ll
M llvm/test/CodeGen/Mips/msa/shift-dagcombine.ll
M llvm/test/CodeGen/Mips/msa/shift_constant_pool.ll
M llvm/test/CodeGen/Mips/msa/special.ll
M llvm/test/CodeGen/Mips/msa/spill.ll
M llvm/test/CodeGen/Mips/msa/vec.ll
M llvm/test/CodeGen/Mips/msa/vecs10.ll
M llvm/test/CodeGen/Mips/octeon.ll
M llvm/test/CodeGen/Mips/prevent-hoisting.ll
M llvm/test/CodeGen/Mips/selTBteqzCmpi.ll
M llvm/test/CodeGen/Mips/selTBtnezCmpi.ll
M llvm/test/CodeGen/Mips/selTBtnezSlti.ll
M llvm/test/CodeGen/Mips/seleq.ll
M llvm/test/CodeGen/Mips/seleqk.ll
M llvm/test/CodeGen/Mips/selgek.ll
M llvm/test/CodeGen/Mips/selgt.ll
M llvm/test/CodeGen/Mips/selle.ll
M llvm/test/CodeGen/Mips/selltk.ll
M llvm/test/CodeGen/Mips/selne.ll
M llvm/test/CodeGen/Mips/selnek.ll
M llvm/test/CodeGen/Mips/selpat.ll
M llvm/test/CodeGen/Mips/unalignedload.ll
M llvm/test/DebugInfo/Mips/tls.ll
A llvm/test/MC/Mips/coff-basic.ll
A llvm/test/MC/Mips/coff-relocs.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/gather-i16-with-i8-index.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/gather-i32-with-i8-index.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/gather-i64-with-i8-index.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/gather-i8-with-i8-index.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-f32-stride-2.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-f32-stride-3.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-f32-stride-4.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i16-stride-2.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i16-stride-3.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i16-stride-4.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i16-stride-6.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i32-stride-2-indices-0u.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i32-stride-2.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i32-stride-3-indices-01u.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i32-stride-3-indices-0uu.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i32-stride-3.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i32-stride-4-indices-012u.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i32-stride-4-indices-0uuu.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i32-stride-4.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i32-stride-6.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i8-stride-2.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i8-stride-3.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i8-stride-4.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-f32-stride-2.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-f32-stride-3.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-f32-stride-4.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-f32-stride-5.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-f32-stride-6.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-f32-stride-7.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-f64-stride-2.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-f64-stride-3.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-f64-stride-4.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-f64-stride-5.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-f64-stride-6.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-f64-stride-7.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i16-stride-2.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i16-stride-3.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i16-stride-4.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i16-stride-5.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i16-stride-6.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i16-stride-7.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i32-stride-2.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i32-stride-3.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i32-stride-4.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i32-stride-5.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i32-stride-6.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i32-stride-7.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i64-stride-2.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i64-stride-3.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i64-stride-4.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i64-stride-5.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i64-stride-6.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i64-stride-7.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i8-stride-2.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i8-stride-3.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i8-stride-4.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i8-stride-5.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i8-stride-6.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i8-stride-7.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/masked-gather-i32-with-i8-index.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/masked-gather-i64-with-i8-index.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/masked-load-i16.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/masked-load-i32.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/masked-load-i64.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/masked-load-i8.ll
M llvm/test/Transforms/LowerConstantIntrinsics/builtin-object-size-phi.ll
M llvm/test/Transforms/LowerConstantIntrinsics/builtin-object-size-range.ll
M llvm/test/Transforms/LowerConstantIntrinsics/objectsize_basic.ll
M llvm/test/Transforms/PhaseOrdering/X86/hadd.ll
M llvm/test/Transforms/PhaseOrdering/X86/pr94546.ll
M llvm/test/Transforms/SLPVectorizer/X86/horizontal-minmax.ll
M llvm/test/Transforms/SLPVectorizer/X86/minbitwidth-transformed-operand.ll
M llvm/test/Transforms/SimplifyCFG/preserve-llvm-loop-metadata.ll
M llvm/test/Transforms/VectorCombine/AArch64/shuffletoidentity.ll
M llvm/test/Transforms/VectorCombine/X86/extract-fneg-insert.ll
M llvm/test/Transforms/VectorCombine/X86/shuffle-of-casts.ll
M llvm/test/Transforms/VectorCombine/X86/shuffle-of-shuffles.ll
M llvm/unittests/IR/CMakeLists.txt
M llvm/utils/gn/secondary/clang/lib/Analysis/FlowSensitive/BUILD.gn
M llvm/utils/gn/secondary/clang/unittests/Analysis/FlowSensitive/BUILD.gn
M llvm/utils/gn/secondary/llvm/lib/Passes/BUILD.gn
M llvm/utils/gn/secondary/llvm/lib/Target/Mips/MCTargetDesc/BUILD.gn
M mlir/docs/DefiningDialects/AttributesAndTypes.md
M mlir/docs/PatternRewriter.md
M mlir/docs/SymbolsAndSymbolTables.md
M mlir/include/mlir/Conversion/Passes.td
M mlir/include/mlir/IR/DialectImplementation.h
M mlir/include/mlir/IR/OpBase.td
M mlir/include/mlir/Tools/mlir-opt/MlirOptMain.h
M mlir/lib/Conversion/AMDGPUToROCDL/AMDGPUToROCDL.cpp
M mlir/lib/Conversion/ControlFlowToLLVM/ControlFlowToLLVM.cpp
M mlir/lib/Conversion/FuncToLLVM/FuncToLLVM.cpp
M mlir/lib/Dialect/Shape/IR/Shape.cpp
M mlir/lib/Dialect/SparseTensor/Pipelines/SparseTensorPipelines.cpp
M mlir/lib/Target/LLVMIR/Dialect/OpenMP/OpenMPToLLVMIRTranslation.cpp
M mlir/test/Conversion/AMDGPUToROCDL/amdgpu-to-rocdl.mlir
A mlir/test/Conversion/ControlFlowToLLVM/branch.mlir
R mlir/test/Conversion/ControlFlowToLLVM/invalid.mlir
A mlir/test/Conversion/ControlFlowToLLVM/switch.mlir
M mlir/test/Conversion/FuncToLLVM/convert-funcs.mlir
M mlir/test/Conversion/FuncToLLVM/func-memref.mlir
M mlir/test/Conversion/FuncToLLVM/func-to-llvm.mlir
M mlir/test/Dialect/ArmSVE/legalize-for-llvm.mlir
M mlir/test/Dialect/Shape/canonicalize.mlir
M mlir/test/Integration/Dialect/Async/CPU/microbench-linalg-async-parallel-for.mlir
M mlir/test/Integration/Dialect/Async/CPU/microbench-scf-async-parallel-for.mlir
M mlir/test/Integration/Dialect/Async/CPU/test-async-parallel-for-1d.mlir
M mlir/test/Integration/Dialect/Async/CPU/test-async-parallel-for-2d.mlir
M mlir/test/Integration/Dialect/Complex/CPU/correctness.mlir
M mlir/test/Integration/Dialect/ControlFlow/assert.mlir
M mlir/test/Integration/Dialect/LLVMIR/CPU/X86/test-inline-asm-vector.mlir
M mlir/test/Integration/Dialect/LLVMIR/CPU/test-vp-intrinsic.mlir
M mlir/test/Integration/Dialect/Linalg/CPU/matmul-vs-matvec.mlir
M mlir/test/Integration/Dialect/Linalg/CPU/runtime-verification.mlir
M mlir/test/Integration/Dialect/Linalg/CPU/test-conv-1d-call.mlir
M mlir/test/Integration/Dialect/Linalg/CPU/test-conv-1d-nwc-wcf-call.mlir
M mlir/test/Integration/Dialect/Linalg/CPU/test-conv-2d-call.mlir
M mlir/test/Integration/Dialect/Linalg/CPU/test-conv-2d-nhwc-hwcf-call.mlir
M mlir/test/Integration/Dialect/Linalg/CPU/test-conv-3d-call.mlir
M mlir/test/Integration/Dialect/Linalg/CPU/test-conv-3d-ndhwc-dhwcf-call.mlir
M mlir/test/Integration/Dialect/Linalg/CPU/test-one-shot-bufferize.mlir
M mlir/test/Integration/Dialect/Linalg/CPU/test-padtensor.mlir
M mlir/test/Integration/Dialect/Linalg/CPU/test-tensor-matmul.mlir
M mlir/test/Integration/Dialect/MemRef/cast-runtime-verification.mlir
M mlir/test/Integration/Dialect/MemRef/load-runtime-verification.mlir
M mlir/test/Integration/Dialect/MemRef/memref_abi.c
M mlir/test/Integration/Dialect/MemRef/reinterpret-cast-runtime-verification.mlir
M mlir/test/Integration/Dialect/MemRef/subview-runtime-verification.mlir
M mlir/test/Integration/Dialect/Standard/CPU/test-ceil-floor-pos-neg.mlir
M mlir/test/Integration/Dialect/Vector/CPU/0-d-vectors.mlir
M mlir/test/Integration/Dialect/Vector/CPU/broadcast.mlir
M mlir/test/Integration/Dialect/Vector/CPU/compress.mlir
M mlir/test/Integration/Dialect/Vector/CPU/constant-mask.mlir
M mlir/test/Integration/Dialect/Vector/CPU/contraction.mlir
M mlir/test/Integration/Dialect/Vector/CPU/create-mask-v4i1.mlir
M mlir/test/Integration/Dialect/Vector/CPU/create-mask.mlir
M mlir/test/Integration/Dialect/Vector/CPU/expand.mlir
M mlir/test/Integration/Dialect/Vector/CPU/extract-strided-slice.mlir
M mlir/test/Integration/Dialect/Vector/CPU/flat-transpose-col.mlir
M mlir/test/Integration/Dialect/Vector/CPU/flat-transpose-row.mlir
M mlir/test/Integration/Dialect/Vector/CPU/fma.mlir
M mlir/test/Integration/Dialect/Vector/CPU/gather.mlir
M mlir/test/Integration/Dialect/Vector/CPU/index-vectors.mlir
M mlir/test/Integration/Dialect/Vector/CPU/insert-strided-slice.mlir
M mlir/test/Integration/Dialect/Vector/CPU/maskedload.mlir
M mlir/test/Integration/Dialect/Vector/CPU/maskedstore.mlir
M mlir/test/Integration/Dialect/Vector/CPU/matrix-multiply-col.mlir
M mlir/test/Integration/Dialect/Vector/CPU/matrix-multiply-row.mlir
M mlir/test/Integration/Dialect/Vector/CPU/outerproduct-f32.mlir
M mlir/test/Integration/Dialect/Vector/CPU/outerproduct-i64.mlir
M mlir/test/Integration/Dialect/Vector/CPU/print-fp.mlir
M mlir/test/Integration/Dialect/Vector/CPU/print-int.mlir
M mlir/test/Integration/Dialect/Vector/CPU/realloc.mlir
M mlir/test/Integration/Dialect/Vector/CPU/reductions-f32-reassoc.mlir
M mlir/test/Integration/Dialect/Vector/CPU/reductions-f32.mlir
M mlir/test/Integration/Dialect/Vector/CPU/reductions-f64-reassoc.mlir
M mlir/test/Integration/Dialect/Vector/CPU/reductions-f64.mlir
M mlir/test/Integration/Dialect/Vector/CPU/reductions-i32.mlir
M mlir/test/Integration/Dialect/Vector/CPU/reductions-i4.mlir
M mlir/test/Integration/Dialect/Vector/CPU/reductions-i64.mlir
M mlir/test/Integration/Dialect/Vector/CPU/reductions-si4.mlir
M mlir/test/Integration/Dialect/Vector/CPU/reductions-ui4.mlir
M mlir/test/Integration/Dialect/Vector/CPU/scan.mlir
M mlir/test/Integration/Dialect/Vector/CPU/scatter.mlir
M mlir/test/Integration/Dialect/Vector/CPU/shape-cast.mlir
M mlir/test/Integration/Dialect/Vector/CPU/shuffle.mlir
M mlir/test/Integration/Dialect/Vector/CPU/shuffle16x16.mlir
M mlir/test/Integration/Dialect/Vector/CPU/sparse-dot-matvec.mlir
M mlir/test/Integration/Dialect/Vector/CPU/sparse-saxpy-jagged-matvec.mlir
M mlir/test/Integration/Dialect/Vector/CPU/transfer-read-1d.mlir
M mlir/test/Integration/Dialect/Vector/CPU/transfer-read-2d.mlir
M mlir/test/Integration/Dialect/Vector/CPU/transfer-read-3d.mlir
M mlir/test/Integration/Dialect/Vector/CPU/transfer-read.mlir
M mlir/test/Integration/Dialect/Vector/CPU/transfer-to-loops.mlir
M mlir/test/Integration/Dialect/Vector/CPU/transfer-write.mlir
M mlir/test/Integration/Dialect/Vector/CPU/transpose.mlir
M mlir/test/Integration/GPU/CUDA/async.mlir
M mlir/test/Target/LLVMIR/openmp-llvm.mlir
M mlir/test/Target/LLVMIR/openmp-todo.mlir
M mlir/test/lib/Dialect/LLVM/TestLowerToLLVM.cpp
M mlir/test/mlir-cpu-runner/async-error.mlir
M mlir/test/mlir-cpu-runner/async-group.mlir
M mlir/test/mlir-cpu-runner/async-value.mlir
M mlir/test/mlir-cpu-runner/async.mlir
M mlir/test/mlir-cpu-runner/bare-ptr-call-conv.mlir
M mlir/test/mlir-cpu-runner/copy.mlir
M mlir/test/mlir-cpu-runner/math-polynomial-approx.mlir
M mlir/test/mlir-cpu-runner/memref-reinterpret-cast.mlir
M mlir/test/mlir-cpu-runner/memref-reshape.mlir
M mlir/test/mlir-cpu-runner/sgemm-naive-codegen.mlir
M mlir/test/mlir-cpu-runner/test-expand-math-approx.mlir
M mlir/test/mlir-cpu-runner/unranked-memref.mlir
M mlir/test/mlir-cpu-runner/utils.mlir
M mlir/test/python/execution_engine.py
M mlir/test/python/integration/dialects/linalg/opsrun.py
M mlir/tools/mlir-vulkan-runner/mlir-vulkan-runner.cpp
M utils/bazel/llvm-project-overlay/mlir/BUILD.bazel
M utils/bazel/llvm-project-overlay/mlir/test/BUILD.bazel
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