[all-commits] [llvm/llvm-project] c2bd5c: [AArch64] Avoid GPR trip when moving truncated i32...

[SpencerAbson via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: c2bd5c25b3634e55089d34afe922aa38eee743e2
      https://github.com/llvm/llvm-project/commit/c2bd5c25b3634e55089d34afe922aa38eee743e2
  Author: SpencerAbson <Spencer.Abson at arm.com>
  Date:   2024-12-20 (Fri, 20 Dec 2024)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
    M llvm/lib/Target/AArch64/AArch64InstrInfo.td
    M llvm/test/CodeGen/AArch64/aarch64-neon-vector-insert-uaddlv.ll
    A llvm/test/CodeGen/AArch64/neon-ins-trunc-elt.ll
    M llvm/test/CodeGen/AArch64/sve-doublereduct.ll
    M llvm/test/CodeGen/AArch64/sve-extract-element.ll
    M llvm/test/CodeGen/AArch64/sve-extract-fixed-vector.ll
    M llvm/test/CodeGen/AArch64/sve-fixed-length-int-reduce.ll
    M llvm/test/CodeGen/AArch64/sve-int-reduce.ll
    M llvm/test/CodeGen/AArch64/sve-split-int-reduce.ll
    M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-reduce.ll
    M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-reductions.ll
    M llvm/test/CodeGen/AArch64/sve-vecreduce-dot.ll
    M llvm/test/CodeGen/AArch64/uaddlv-vaddlp-combine.ll
    M llvm/test/CodeGen/AArch64/vec-combine-compare-to-bitmask.ll
    M llvm/test/CodeGen/AArch64/vecreduce-bool.ll

  Log Message:
  -----------
  [AArch64] Avoid GPR trip when moving truncated i32 vector elements (#114541)

This patch implements a DAG combine whereby
```
        a: v2i64 = ...
      b: i64 = extract_vector_elt a, Constant:i64<n>
    c: i32 = truncate b
```
Becomes
```
        a: v2i64 = ...
      b: v4i32 = AArch64ISD::NVCAST a
    c: i32 = extract_vector_elt c, Constant:i64<2n>
```

The primary goal of this work is to enable the use of [INS
(element)](https://developer.arm.com/documentation/ddi0602/2024-09/SIMD-FP-Instructions/INS--element---Insert-vector-element-from-another-vector-element-?lang=en)
when moving a truncated i32 element between vectors. This combine
canonicalises the structure of the DAG for all legal instances of the
pattern above (by removing the explicit `trunc` operator in this
specific case), allowing us to take advantage of existing ISEL patterns
for this behavior.



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