[all-commits] [llvm/llvm-project] 322206: Reland "[RISCV] Add scheduling model for mips p870...

[Djordje Todorovic via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 32220601247896f508ccfde614f5ba6afc85b27d
      https://github.com/llvm/llvm-project/commit/32220601247896f508ccfde614f5ba6afc85b27d
  Author: Djordje Todorovic <djordje.todorovic at htecgroup.com>
  Date:   2024-12-19 (Thu, 19 Dec 2024)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCV.td
    M llvm/lib/Target/RISCV/RISCVProcessors.td
    A llvm/lib/Target/RISCV/RISCVSchedMIPSP8700.td
    A llvm/test/tools/llvm-mca/RISCV/MIPS/p8700.s

  Log Message:
  -----------
  Reland "[RISCV] Add scheduling model for mips p8700 CPU" (#120550)

This patch introduces a scheduling model for the MIPS p8700, an
out-of-order
RISC-V processor. The model includes pipelines for the following units:

- 2 Integer Arithmetic/Logical Units (ALU and AL2)
- Multiply/Divide Unit (MDU)
- Branch Unit (CTI)
- Load/Store Unit (LSU)
- Short Floating-Point Pipe (FPUS)
- Long Floating-Point Pipe (FPUL)

For additional details, refer to the official product page:
https://mips.com/products/hardware/p8700/.

Also adds `UnsupportedSchedZfhmin` to handle cases like
`WriteFCvtF16ToF32` that
previously caused build failures.



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