[all-commits] [llvm/llvm-project] 6b9fb8: Add a few more opcodes found by asserting on frame...

[Matt Arsenault via All-commits]

  Branch: refs/heads/users/arsenm/riscv-is-load-store-stackslot-rvv
  Home:   https://github.com/llvm/llvm-project
  Commit: 6b9fb88955e08f5b975c8eb46a0386b5c2a99813
      https://github.com/llvm/llvm-project/commit/6b9fb88955e08f5b975c8eb46a0386b5c2a99813
  Author: Matt Arsenault <Matthew.Arsenault at amd.com>
  Date:   2024-12-19 (Thu, 19 Dec 2024)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-interleaved-access.ll

  Log Message:
  -----------
  Add a few more opcodes found by asserting on frame indexes with mayLoad/mayStore.

One test looks like a regression, which is probably rematerialization not
being handled for something.



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