[all-commits] [llvm/llvm-project] 84d6f1: RISCV: Implement isLoadFromStackSlot/isStoreToStac...

[Matt Arsenault via All-commits]

  Branch: refs/heads/users/arsenm/riscv-is-load-store-stackslot-rvv
  Home:   https://github.com/llvm/llvm-project
  Commit: 84d6f1212d65cac7fc81e3b07e6952809072b44e
      https://github.com/llvm/llvm-project/commit/84d6f1212d65cac7fc81e3b07e6952809072b44e
  Author: Matt Arsenault <Matthew.Arsenault at amd.com>
  Date:   2024-12-19 (Thu, 19 Dec 2024)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
    M llvm/test/CodeGen/RISCV/rvv/cttz-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ctlz-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-interleaved-access.ll
    M llvm/test/CodeGen/RISCV/rvv/fshr-fshl-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vfma-vp.ll

  Log Message:
  -----------
  RISCV: Implement isLoadFromStackSlot/isStoreToStackSlot for rvv

This partially helps avoid regressions in a future regalloc patch.
It isn't sufficient, and I think there are more missing implementations
of the copy and spill hooks.



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