[all-commits] [llvm/llvm-project] 1941f3: [TableGen][GISel] Import more "multi-level" patter...

[Sergei Barannikov via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 1941f341722178390f71e07502e08a2250a704c7
      https://github.com/llvm/llvm-project/commit/1941f341722178390f71e07502e08a2250a704c7
  Author: Sergei Barannikov <barannikov88 at gmail.com>
  Date:   2024-12-18 (Wed, 18 Dec 2024)

  Changed paths:
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-ashr.s16.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-ctpop.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-lshr.s16.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-shl.s16.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/xnor.ll
    M llvm/test/CodeGen/AMDGPU/constrained-shift.ll
    M llvm/test/CodeGen/AMDGPU/integer-mad-patterns.ll
    M llvm/utils/TableGen/GlobalISelEmitter.cpp

  Log Message:
  -----------
  [TableGen][GISel] Import more "multi-level" patterns (#120332)

Previously, if the destination DAG has an untyped leaf, we would import
the pattern only if that leaf is defined by the *top-level* source DAG.
This is an unnecessary restriction.

Here is an example of such pattern:
```
def : Pat<(add (mul v8i16:$vA, v8i16:$vB), v8i16:$vC),
          (VMLADDUHM $vA, $vB, $vC)>;
```

Previously, it failed to import because `add` doesn't define neither
`$vA` nor `$vB`.

This change reduces the number of skipped patterns as follows:

```
AArch64: 8695 ->  8548 (-147)
AMDGPU: 11333 -> 11240 (-93)
ARM:     4297 ->  4278 (-1)
PowerPC: 3955 ->  3010 (-945)
```

Other GISel-enabled targets are unaffected.



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