[all-commits] [llvm/llvm-project] a61eea: [RISCV][VLOPT] Add vector indexed loads and stores...

[Michael Maitland via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: a61eeaa7486178a6887e0efc843559d8a35bf4af
      https://github.com/llvm/llvm-project/commit/a61eeaa7486178a6887e0efc843559d8a35bf4af
  Author: Michael Maitland <michaeltmaitland at gmail.com>
  Date:   2024-12-17 (Tue, 17 Dec 2024)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp
    M llvm/test/CodeGen/RISCV/rvv/narrow-shift-extend.ll
    M llvm/test/CodeGen/RISCV/rvv/pr63459.ll
    M llvm/test/CodeGen/RISCV/rvv/vl-opt-op-info.mir
    M llvm/test/CodeGen/RISCV/rvv/vpgather-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vpscatter-sdnode.ll

  Log Message:
  -----------
  [RISCV][VLOPT] Add vector indexed loads and stores to getOperandInfo (#119748)

Use `MO.getOperandNo() == 0` instead of `IsMODef` so naming is clear for the store, since the store should treat its operand 0 like that even though it is not a def.The load should treat its operand 0 def in the same way.



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