[all-commits] [llvm/llvm-project] edbde4: RegAllocGreedy: Fix subrange based instruction spl...

[Matt Arsenault via All-commits]

  Branch: refs/heads/users/arsenm/greedy-fix-subrange-instruction-split-logic
  Home:   https://github.com/llvm/llvm-project
  Commit: edbde4acfa7320611f4053076eb33fd0f7844d8e
      https://github.com/llvm/llvm-project/commit/edbde4acfa7320611f4053076eb33fd0f7844d8e
  Author: Matt Arsenault <Matthew.Arsenault at amd.com>
  Date:   2024-12-18 (Wed, 18 Dec 2024)

  Changed paths:
    M llvm/lib/CodeGen/RegAllocGreedy.cpp
    M llvm/test/CodeGen/AMDGPU/gfx-callable-return-types.ll
    A llvm/test/CodeGen/AMDGPU/inflated-reg-class-snippet-copy-inst-reads-lane-subset-use-after-free.mir
    A llvm/test/CodeGen/AMDGPU/inflated-reg-class-snippet-copy-use-after-free.mir
    M llvm/test/CodeGen/AMDGPU/remat-smrd.mir
    M llvm/test/CodeGen/AMDGPU/splitkit-copy-live-lanes.mir
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-interleaved-access.ll

  Log Message:
  -----------
  RegAllocGreedy: Fix subrange based instruction split logic

Fix the logic for readsLaneSubset. Check at the correct point
for the use operands of the instruction, instead of the result.
Only consider the use register operands, and stop considering
whether the subranges are actually live at this point.

This avoids some unproductive splits. This also happens to avoid
a use after free due to a split of an unspillable register. That
issue still exists if the instruction does not reference the full
set of register lanes.


  Commit: 3cc60cacdeb0efda00e242b0f7f3b1b4336ca10f
      https://github.com/llvm/llvm-project/commit/3cc60cacdeb0efda00e242b0f7f3b1b4336ca10f
  Author: Matt Arsenault <Matthew.Arsenault at amd.com>
  Date:   2024-12-18 (Wed, 18 Dec 2024)

  Changed paths:
    M llvm/lib/CodeGen/RegAllocGreedy.cpp

  Log Message:
  -----------
  Remove unused parameter and rename


  Commit: 05e8c2ef367b017160246e039cd7ddc1bc7c66f6
      https://github.com/llvm/llvm-project/commit/05e8c2ef367b017160246e039cd7ddc1bc7c66f6
  Author: Matt Arsenault <Matthew.Arsenault at amd.com>
  Date:   2024-12-18 (Wed, 18 Dec 2024)

  Changed paths:
    M llvm/test/CodeGen/RISCV/rvv/vector-deinterleave-load.ll
    M llvm/test/CodeGen/RISCV/rvv/vector-deinterleave.ll

  Log Message:
  -----------
  Test merge


Compare: https://github.com/llvm/llvm-project/compare/6fc9c1d35a10...05e8c2ef367b

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