[all-commits] [llvm/llvm-project] 668d96: [RISCV] Add Qualcomm uC Xqcilsm (Load Store Multip...
Paul Kirth via All-commits
all-commits at lists.llvm.org
Tue Dec 17 16:01:30 PST 2024
Branch: refs/heads/users/ilovepi/spr/clang-doc-use-langopts-when-printing-types
Home: https://github.com/llvm/llvm-project
Commit: 668d9688ac8aa97d9156cecabd25bf2a8e82bc9d
https://github.com/llvm/llvm-project/commit/668d9688ac8aa97d9156cecabd25bf2a8e82bc9d
Author: Sudharsan Veeravalli <quic_svs at quicinc.com>
Date: 2024-12-14 (Sat, 14 Dec 2024)
Changed paths:
M clang/test/Driver/print-supported-extensions-riscv.c
M llvm/docs/RISCVUsage.rst
M llvm/docs/ReleaseNotes.md
M llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
M llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
M llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
M llvm/lib/Target/RISCV/RISCVFeatures.td
M llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
M llvm/lib/TargetParser/RISCVISAInfo.cpp
M llvm/test/CodeGen/RISCV/attributes.ll
A llvm/test/MC/RISCV/xqcilsm-aliases-valid.s
A llvm/test/MC/RISCV/xqcilsm-invalid.s
A llvm/test/MC/RISCV/xqcilsm-valid.s
M llvm/unittests/TargetParser/RISCVISAInfoTest.cpp
Log Message:
-----------
[RISCV] Add Qualcomm uC Xqcilsm (Load Store Multiple) extension (#119823)
This extension adds 6 instructions that can do multi-word load/store.
The current spec can be found at:
https://github.com/quic/riscv-unified-db/releases/latest
This patch adds assembler only support.
Commit: 003eb5e80d8c970c2ae7fcbaaebd52b32a61648d
https://github.com/llvm/llvm-project/commit/003eb5e80d8c970c2ae7fcbaaebd52b32a61648d
Author: erichkeane <ekeane at nvidia.com>
Date: 2024-12-13 (Fri, 13 Dec 2024)
Changed paths:
M clang/include/clang/AST/OpenACCClause.h
M clang/include/clang/Basic/OpenACCClauses.def
M clang/lib/AST/OpenACCClause.cpp
M clang/lib/AST/StmtProfile.cpp
M clang/lib/AST/TextNodeDumper.cpp
M clang/lib/Sema/SemaOpenACC.cpp
M clang/lib/Sema/TreeTransform.h
M clang/lib/Serialization/ASTReader.cpp
M clang/lib/Serialization/ASTWriter.cpp
M clang/test/AST/ast-print-openacc-data-construct.cpp
M clang/test/ParserOpenACC/parse-clauses.c
M clang/test/SemaOpenACC/combined-construct-auto_seq_independent-clauses.c
M clang/test/SemaOpenACC/combined-construct-device_type-clause.c
M clang/test/SemaOpenACC/compute-construct-device_type-clause.c
A clang/test/SemaOpenACC/data-construct-finalize-ast.cpp
A clang/test/SemaOpenACC/data-construct-finalize-clause.c
M clang/test/SemaOpenACC/data-construct.cpp
M clang/test/SemaOpenACC/loop-construct-auto_seq_independent-clauses.c
M clang/test/SemaOpenACC/loop-construct-device_type-clause.c
M clang/tools/libclang/CIndex.cpp
Log Message:
-----------
[OpenACC] Implement 'finalize' clause sema
This is a very simple clause as far as sema is concerned. It is only
valid on 'exit data', and doesn't have any rules involving it, so it is
simply applied and passed onto the MLIR.
Commit: 5cac0eb4b4156ed7e2dae2a73af04484cf330ddb
https://github.com/llvm/llvm-project/commit/5cac0eb4b4156ed7e2dae2a73af04484cf330ddb
Author: Ian Wood <ianwood2024 at u.northwestern.edu>
Date: 2024-12-13 (Fri, 13 Dec 2024)
Changed paths:
M llvm/include/llvm/Support/TypeName.h
Log Message:
-----------
[Support] Fix getTypeNameImpl on msvc (#119910)
Updates `Key` to reflect the new name of the function enclosing
`__FUNCSIG__`.
Commit: 3b3394baec18d77e8d5b984882c82f7b3a59f981
https://github.com/llvm/llvm-project/commit/3b3394baec18d77e8d5b984882c82f7b3a59f981
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-12-13 (Fri, 13 Dec 2024)
Changed paths:
M llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
M llvm/test/CodeGen/RISCV/rvv/vmsgeu.ll
Log Message:
-----------
[RISCV] Use Log2SEW=0 for VMNAND/VMSET created for riscv_vmsge(u) intrinsics. (#119767)
These instructions should always be created with Log2SEW=0 and an LMUL
based on SEW=8. This is used by the vsetvli pass to know these
instructions only care about the ratio and not the specific value.
Looks like I fixed riscv_vmsge(u)_mask intrinsics years ago, but forgot
the unmasked intrinsics.
I'm working on an enhancement to our MachineVerifier checks that will
require VMNAND and VMSET to have Log2SEW=0.
Commit: d1f51c67fde6f77b78f78901fb78e3589430a299
https://github.com/llvm/llvm-project/commit/d1f51c67fde6f77b78f78901fb78e3589430a299
Author: Sergei Barannikov <barannikov88 at gmail.com>
Date: 2024-12-13 (Fri, 13 Dec 2024)
Changed paths:
M llvm/utils/TableGen/Common/CodeGenDAGPatterns.cpp
M llvm/utils/TableGen/Common/CodeGenDAGPatterns.h
M llvm/utils/TableGen/DAGISelEmitter.cpp
M llvm/utils/TableGen/DAGISelMatcherGen.cpp
M llvm/utils/TableGen/FastISelEmitter.cpp
M llvm/utils/TableGen/GlobalISelEmitter.cpp
Log Message:
-----------
[TableGen] Add TreePatternNode::children and use it in for loops (NFC) (#119877)
Commit: 9474e09459189fbed30f329a669f9c14979c5367
https://github.com/llvm/llvm-project/commit/9474e09459189fbed30f329a669f9c14979c5367
Author: Louis Dionne <ldionne.2 at gmail.com>
Date: 2024-12-13 (Fri, 13 Dec 2024)
Changed paths:
M libcxx/include/CMakeLists.txt
M libcxx/include/__hash_table
M libcxx/include/__memory/allocator.h
M libcxx/include/__memory/builtin_new_allocator.h
M libcxx/include/__memory/construct_at.h
M libcxx/include/__memory/shared_ptr.h
M libcxx/include/__memory/uninitialized_algorithms.h
A libcxx/include/__new/align_val_t.h
A libcxx/include/__new/allocate.h
A libcxx/include/__new/destroying_delete_t.h
A libcxx/include/__new/exceptions.h
A libcxx/include/__new/global_new_delete.h
A libcxx/include/__new/interference_size.h
A libcxx/include/__new/launder.h
A libcxx/include/__new/new_handler.h
A libcxx/include/__new/nothrow_t.h
A libcxx/include/__new/placement_new_delete.h
M libcxx/include/__utility/small_buffer.h
M libcxx/include/array
M libcxx/include/charconv
M libcxx/include/forward_list
M libcxx/include/future
M libcxx/include/list
M libcxx/include/module.modulemap
M libcxx/include/new
M libcxx/test/libcxx/transitive_includes/cxx03.csv
M libcxx/test/libcxx/transitive_includes/cxx11.csv
M libcxx/test/libcxx/transitive_includes/cxx14.csv
M libcxx/test/libcxx/transitive_includes/cxx23.csv
M libcxx/test/libcxx/transitive_includes/cxx26.csv
M libcxx/test/std/language.support/support.dynamic/alloc.errors/bad.alloc/bad_alloc.pass.cpp
M libcxx/test/std/language.support/support.dynamic/new.delete/new.delete.placement/new_array.pass.cpp
M libcxx/test/std/language.support/support.dynamic/ptr.launder/launder.types.verify.cpp
M libcxx/test/std/utilities/memory/default.allocator/allocator.members/allocate.size.pass.cpp
M libcxxabi/test/cxa_vec_new_overflow_PR41395.pass.cpp
Log Message:
-----------
[libc++] Granularize the <new> header (#119270)
This disentangles the code which previously had a mix of many #ifdefs, a
non-versioned namespace and a versioned namespace. It also makes it
clearer which parts of <new> are implemented on Windows by including <new.h>.
Commit: 2135babe28b038c99d77f15c39b3f7e498fc6694
https://github.com/llvm/llvm-project/commit/2135babe28b038c99d77f15c39b3f7e498fc6694
Author: Louis Dionne <ldionne.2 at gmail.com>
Date: 2024-12-13 (Fri, 13 Dec 2024)
Changed paths:
M libcxx/utils/libcxx/test/format.py
Log Message:
-----------
[libc++] Save benchmark results in a json file (#119761)
When running a benchmark, also save the benchmark results in a JSON
file. That is cheap to do and useful to compare benchmark results
between different runs.
Commit: 64da33a58923e60a5c7854c1a13e14f16d01b1f0
https://github.com/llvm/llvm-project/commit/64da33a58923e60a5c7854c1a13e14f16d01b1f0
Author: Peter Collingbourne <peter at pcc.me.uk>
Date: 2024-12-13 (Fri, 13 Dec 2024)
Changed paths:
M lld/ELF/Config.h
M lld/ELF/Driver.cpp
M lld/ELF/Options.td
M lld/ELF/OutputSections.h
M lld/ELF/SyntheticSections.cpp
M lld/ELF/SyntheticSections.h
M lld/ELF/Writer.cpp
M lld/docs/ld.lld.1
A lld/test/ELF/randomize-section-padding.test
Log Message:
-----------
ELF: Introduce --randomize-section-padding option.
The --randomize-section-padding option randomly inserts padding between
input sections using the given seed. It is intended to be used in A/B
experiments to determine the average effect of a change on program
performance, while controlling for effects such as false sharing in
the cache which may introduce measurement bias. For more details,
see the RFC:
https://discourse.llvm.org/t/rfc-lld-feature-for-controlling-for-code-size-dependent-measurement-bias/83334
Reviewers: smithp35, MaskRay
Reviewed By: MaskRay, smithp35
Pull Request: https://github.com/llvm/llvm-project/pull/117653
Commit: 52e9f2c52cd1d0ffa922761458abc35cd90057ea
https://github.com/llvm/llvm-project/commit/52e9f2c52cd1d0ffa922761458abc35cd90057ea
Author: Djordje Todorovic <56676939+djtodoro at users.noreply.github.com>
Date: 2024-12-13 (Fri, 13 Dec 2024)
Changed paths:
M clang/test/Driver/riscv-cpus.c
M clang/test/Misc/target-invalid-cpu-note/riscv.c
M llvm/docs/ReleaseNotes.md
M llvm/lib/Target/RISCV/RISCVFeatures.td
M llvm/lib/Target/RISCV/RISCVProcessors.td
Log Message:
-----------
[RISCV] Add MIPS P8700 processor (#119882)
The P8700 is a high-performance processor from MIPS designed to meet the
demands of modern workloads, offering exceptional scalability and
efficiency. It builds on MIPS's established architectural strengths
while introducing enhancements that set it apart. For more details, you
can check out the official product page here:
https://mips.com/products/hardware/p8700/.
Scheduling model will be added in a separate commit/PR.
Commit: 8ab6912831277d87838518c5f775f79d14616860
https://github.com/llvm/llvm-project/commit/8ab6912831277d87838518c5f775f79d14616860
Author: Yuxuan Chen <ych at fb.com>
Date: 2024-12-13 (Fri, 13 Dec 2024)
Changed paths:
A clang/test/Interpreter/Inputs/vector
M clang/test/Interpreter/crash.cpp
Log Message:
-----------
[Clang] Interpreter test should not depend on system header (#119903)
https://github.com/llvm/llvm-project/commit/30ad53b92cec0cff9679d559edcc5b933312ba0c
introduced a new test that includes `<vector>` from the system include
path without honoring environment variables that may provide the path to
C++ standard library. This is not supported in some CI systems because
we don't always have the C++ library in the standard location.
The conventional way of doing includes in the test is through `Inputs`
directory and pass it as an include path.
The `vector` file included in this patch has been shortened, but I have
verified that it works with this test. i.e. the clang repl crashes on
this test in the same way if the fix in
https://github.com/llvm/llvm-project/pull/117475 is reverted.
Commit: 9f2dd085ae981740e2986a1b200ca2a7df44953d
https://github.com/llvm/llvm-project/commit/9f2dd085ae981740e2986a1b200ca2a7df44953d
Author: klensy <klensy at users.noreply.github.com>
Date: 2024-12-13 (Fri, 13 Dec 2024)
Changed paths:
M mlir/lib/Interfaces/ValueBoundsOpInterface.cpp
Log Message:
-----------
[mlir] fix copypaste typos in asserts (#119878)
This fixes few copypaste typos
I've also spotted weird `getNumRows() == getNumRows()`: looks like
leftover after refactoring
https://github.com/llvm/llvm-project/blob/ea8e328ae2bea9d9a7d556ef4d791fa116f7de18/mlir/lib/Analysis/Presburger/Simplex.cpp#L107-L111
Co-authored-by: klensy <nightouser at gmail.com>
Commit: e5ab6e960745bfda9204e696a0a99746075f3021
https://github.com/llvm/llvm-project/commit/e5ab6e960745bfda9204e696a0a99746075f3021
Author: lntue <lntue at google.com>
Date: 2024-12-13 (Fri, 13 Dec 2024)
Changed paths:
M libc/docs/talks.rst
Log Message:
-----------
[libc][doc] Add links to LLVM dev meeting talks related to LLVM libc. (#119918)
Commit: 0f776f1df9ec6345f298cc19c33dfea7f98289ec
https://github.com/llvm/llvm-project/commit/0f776f1df9ec6345f298cc19c33dfea7f98289ec
Author: Chris Apple <cja-private at pm.me>
Date: 2024-12-13 (Fri, 13 Dec 2024)
Changed paths:
M clang/lib/CodeGen/BackendUtil.cpp
Log Message:
-----------
[rtsan][clang] NFC: Move rtsan init to addSanitizers (#119904)
Commit: 2244d2e75c50cdd4657ed6c488423790367e1347
https://github.com/llvm/llvm-project/commit/2244d2e75c50cdd4657ed6c488423790367e1347
Author: erichkeane <ekeane at nvidia.com>
Date: 2024-12-13 (Fri, 13 Dec 2024)
Changed paths:
M clang/include/clang/AST/OpenACCClause.h
M clang/include/clang/Basic/OpenACCClauses.def
M clang/lib/AST/OpenACCClause.cpp
M clang/lib/AST/StmtProfile.cpp
M clang/lib/AST/TextNodeDumper.cpp
M clang/lib/Sema/SemaOpenACC.cpp
M clang/lib/Sema/TreeTransform.h
M clang/lib/Serialization/ASTReader.cpp
M clang/lib/Serialization/ASTWriter.cpp
M clang/test/AST/ast-print-openacc-data-construct.cpp
M clang/test/ParserOpenACC/parse-clauses.c
M clang/test/SemaOpenACC/combined-construct-auto_seq_independent-clauses.c
M clang/test/SemaOpenACC/combined-construct-device_type-clause.c
M clang/test/SemaOpenACC/compute-construct-device_type-clause.c
A clang/test/SemaOpenACC/data-construct-if_present-ast.cpp
A clang/test/SemaOpenACC/data-construct-if_present-clause.c
M clang/test/SemaOpenACC/data-construct.cpp
M clang/test/SemaOpenACC/loop-construct-auto_seq_independent-clauses.c
M clang/test/SemaOpenACC/loop-construct-device_type-clause.c
M clang/tools/libclang/CIndex.cpp
Log Message:
-----------
[OpenACC] Implement 'if_present' clause sema
The 'if_present' clause controls the replacement of addresses in the
var-list in current device memory. This clause can only go on
'host_device'. From a Sema perspective, there isn't anything to do
beyond add this to AST and pass it on.
Commit: 2eed88da6a100216bf542e0c16762d336791876b
https://github.com/llvm/llvm-project/commit/2eed88da6a100216bf542e0c16762d336791876b
Author: Momchil Velikov <momchil.velikov at arm.com>
Date: 2024-12-13 (Fri, 13 Dec 2024)
Changed paths:
M clang/include/clang/Basic/arm_sve.td
A clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_fmla.c
M clang/test/Sema/aarch64-sve2-intrinsics/acle_sve2_fp8.c
M llvm/include/llvm/IR/IntrinsicsAArch64.td
M llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
M llvm/lib/Target/AArch64/SVEInstrFormats.td
A llvm/test/CodeGen/AArch64/fp8-sve-fmla.ll
Log Message:
-----------
[AArch64] Implement FP8 SVE intrinsics for fused multiply-add (#118126)
This patch adds the following intrinsics:
* 8-bit floating-point multiply-add long to half-precision (bottom).
// Only if (__ARM_FEATURE_SVE2 && __ARM_FEATURE_FP8FMA) ||
__ARM_FEATURE_SSVE_FP8FMA
svfloat16_t svmlalb[_f16_mf8]_fpm(svfloat16_t zda, svmfloat8_t zn,
svmfloat8_t zm, fpm_t fpm);
svfloat16_t svmlalb[_n_f16_mf8]_fpm(svfloat16_t zda, svmfloat8_t zn,
mfloat8_t zm, fpm_t fpm);
* 8-bit floating-point multiply-add long to half-precision (bottom,
indexed).
// Only if (__ARM_FEATURE_SVE2 && __ARM_FEATURE_FP8FMA) ||
__ARM_FEATURE_SSVE_FP8FMA
svfloat16_t svmlalb_lane[_f16_mf8]_fpm(svfloat16_t zda, svmfloat8_t zn,
svmfloat8_t zm,
uint64_t imm0_15, fpm_t fpm);
* 8-bit floating-point multiply-add long to half-precision (top).
// Only if (__ARM_FEATURE_SVE2 && __ARM_FEATURE_FP8FMA) ||
__ARM_FEATURE_SSVE_FP8FMA
svfloat16_t svmlalt[_f16_mf8]_fpm(svfloat16_t zda, svmfloat8_t zn,
svmfloat8_t zm, fpm_t fpm);
svfloat16_t svmlalt[_n_f16_mf8]_fpm(svfloat16_t zda, svmfloat8_t zn,
mfloat8_t zm, fpm_t fpm);
* 8-bit floating-point multiply-add long to half-precision (top,
indexed).
// Only if (__ARM_FEATURE_SVE2 && __ARM_FEATURE_FP8FMA) ||
__ARM_FEATURE_SSVE_FP8FMA
svfloat16_t svmlalt_lane[_f16_mf8]_fpm(svfloat16_t zda, svmfloat8_t zn,
svmfloat8_t zm,
uint64_t imm0_15, fpm_t fpm);
* 8-bit floating-point multiply-add long long to single-precision
(bottom bottom).
// Only if (__ARM_FEATURE_SVE2 && __ARM_FEATURE_FP8FMA) ||
__ARM_FEATURE_SSVE_FP8FMA
svfloat32_t svmlallbb[_f32_mf8]_fpm(svfloat32_t zda, svmfloat8_t zn,
svmfloat8_t zm, fpm_t fpm);
svfloat32_t svmlallbb[_n_f32_mf8]_fpm(svfloat32_t zda, svmfloat8_t zn,
mfloat8_t zm, fpm_t fpm);
* 8-bit floating-point multiply-add long long to single-precision
(bottom bottom, indexed).
// Only if (__ARM_FEATURE_SVE2 && __ARM_FEATURE_FP8FMA) ||
__ARM_FEATURE_SSVE_FP8FMA
svfloat32_t svmlallbb_lane[_f32_mf8]_fpm(svfloat32_t zda, svmfloat8_t
zn, svmfloat8_t zm,
uint64_t imm0_15, fpm_t fpm);
* 8-bit floating-point multiply-add long long to single-precision
(bottom top).
// Only if (__ARM_FEATURE_SVE2 && __ARM_FEATURE_FP8FMA) ||
__ARM_FEATURE_SSVE_FP8FMA
svfloat32_t svmlallbt[_f32_mf8]_fpm(svfloat32_t zda, svmfloat8_t zn,
svmfloat8_t zm, fpm_t fpm);
svfloat32_t svmlallbt[_n_f32_mf8]_fpm(svfloat32_t zda, svmfloat8_t zn,
mfloat8_t zm, fpm_t fpm);
* 8-bit floating-point multiply-add long long to single-precision
(bottom top, indexed).
// Only if (__ARM_FEATURE_SVE2 && __ARM_FEATURE_FP8FMA) ||
__ARM_FEATURE_SSVE_FP8FMA
svfloat32_t svmlallbt_lane[_f32_mf8]_fpm(svfloat32_t zda, svmfloat8_t
zn, svmfloat8_t zm,
uint64_t imm0_15, fpm_t fpm);
* 8-bit floating-point multiply-add long long to single-precision (top
bottom).
// Only if (__ARM_FEATURE_SVE2 && __ARM_FEATURE_FP8FMA) ||
__ARM_FEATURE_SSVE_FP8FMA
svfloat32_t svmlalltb[_f32_mf8]_fpm(svfloat32_t zda, svmfloat8_t zn,
svmfloat8_t zm, fpm_t fpm);
svfloat32_t svmlalltb[_n_f32_mf8]_fpm(svfloat32_t zda, svmfloat8_t zn,
mfloat8_t zm, fpm_t fpm);
* 8-bit floating-point multiply-add long long to single-precision (top
bottom, indexed).
// Only if (__ARM_FEATURE_SVE2 && __ARM_FEATURE_FP8FMA) ||
__ARM_FEATURE_SSVE_FP8FMA
svfloat32_t svmlalltb_lane[_f32_mf8]_fpm(svfloat32_t zda, svmfloat8_t
zn, svmfloat8_t zm,
uint64_t imm0_15, fpm_t fpm);
* 8-bit floating-point multiply-add long long to single-precision (top
top).
// Only if (__ARM_FEATURE_SVE2 && __ARM_FEATURE_FP8FMA) ||
__ARM_FEATURE_SSVE_FP8FMA
svfloat32_t svmlalltt[_f32_mf8]_fpm(svfloat32_t zda, svmfloat8_t zn,
svmfloat8_t zm, fpm_t fpm);
svfloat32_t svmlalltt[_n_f32_mf8]_fpm(svfloat32_t zda, svmfloat8_t zn,
mfloat8_t zm, fpm_t fpm);
* 8-bit floating-point multiply-add long long to single-precision (top
top, indexed).
// Only if (__ARM_FEATURE_SVE2 && __ARM_FEATURE_FP8FMA) ||
__ARM_FEATURE_SSVE_FP8FMA
svfloat32_t svmlalltt_lane[_f32_mf8]_fpm(svfloat32_t zda, svmfloat8_t
zn, svmfloat8_t zm,
uint64_t imm0_15, fpm_t fpm);
Commit: af5d3afff54e5af61f384a1e95020f0a0374caec
https://github.com/llvm/llvm-project/commit/af5d3afff54e5af61f384a1e95020f0a0374caec
Author: Slava Zakharin <szakharin at nvidia.com>
Date: 2024-12-13 (Fri, 13 Dec 2024)
Changed paths:
M flang/lib/Optimizer/HLFIR/Transforms/OptimizedBufferization.cpp
M flang/test/HLFIR/opt-array-slice-assign.fir
Log Message:
-----------
[flang] Improve disjoint/identical slices recognition in opt-bufferization. (#119780)
The changes are needed to be able to optimize
'x(9,:)=SUM(x(1:8,:),DIM=1)'
without a temporary array. This pattern exists in exchange2.
The patch also fixes an existing problem in Flang with this test:
```
program main
integer :: a(10) = (/1,2,3,4,5,6,7,8,9,10/)
integer :: expected(10) = (/1,10,9,8,7,6,5,4,3,2/)
print *, 'INPUT: ', a
print *, 'EXPECTED: ', expected
call test(a, 10, 2, 10, 9)
print *, 'RESULT: ', a
contains
subroutine test(a, size, x, y, z)
integer :: x, y, z, size
integer :: a(:)
a(x:y:1) = a(z:x-1:-1) + 1
end subroutine test
end program main
```
Commit: a00946fc947d42e67394934bc78b84a37ecc2908
https://github.com/llvm/llvm-project/commit/a00946fc947d42e67394934bc78b84a37ecc2908
Author: Slava Zakharin <szakharin at nvidia.com>
Date: 2024-12-13 (Fri, 13 Dec 2024)
Changed paths:
M flang/include/flang/Optimizer/Builder/HLFIRTools.h
M flang/lib/Optimizer/Builder/HLFIRTools.cpp
M flang/lib/Optimizer/HLFIR/Transforms/SimplifyHLFIRIntrinsics.cpp
M flang/test/HLFIR/simplify-hlfir-intrinsics-sum.fir
Log Message:
-----------
[flang] Simplify hlfir.sum total reductions. (#119482)
I am trying to switch to keeping the reduction value in a temporary
scalar location so that I can use hlfir::genLoopNest easily.
This also allows using omp.loop_nest with worksharing for OpenMP.
Commit: 2daadbdc5e3a6029092963a1c699675320745d70
https://github.com/llvm/llvm-project/commit/2daadbdc5e3a6029092963a1c699675320745d70
Author: Brox Chen <guochen2 at amd.com>
Date: 2024-12-13 (Fri, 13 Dec 2024)
Changed paths:
M llvm/test/MC/AMDGPU/gfx11_asm_vop1.s
M llvm/test/MC/AMDGPU/gfx11_asm_vop1_dpp16.s
M llvm/test/MC/AMDGPU/gfx11_asm_vop1_dpp8.s
M llvm/test/MC/AMDGPU/gfx11_asm_vop3_dpp16_from_vop1.s
M llvm/test/MC/AMDGPU/gfx11_asm_vop3_dpp8_from_vop1.s
M llvm/test/MC/AMDGPU/gfx11_asm_vop3_from_vop1.s
M llvm/test/MC/AMDGPU/gfx12_asm_vop1.s
M llvm/test/MC/AMDGPU/gfx12_asm_vop1_dpp16.s
M llvm/test/MC/AMDGPU/gfx12_asm_vop1_dpp8.s
M llvm/test/MC/AMDGPU/gfx12_asm_vop3_from_vop1.s
M llvm/test/MC/AMDGPU/gfx12_asm_vop3_from_vop1_dpp16.s
M llvm/test/MC/AMDGPU/gfx12_asm_vop3_from_vop1_dpp8.s
Log Message:
-----------
[AMDGPU][true16] [MC] Remove duplication in VOP1 test (#119905)
This is a NFC change. Remove duplicated test line in gfx11/gfx12 vop1
test file with the latest update_mc_test_script.py --unique option
This is also preparing for the up-coming true16 change
Commit: b560b87ba1d85a4262d24386eb7e9a8f7b8086f5
https://github.com/llvm/llvm-project/commit/b560b87ba1d85a4262d24386eb7e9a8f7b8086f5
Author: Maksim Panchenko <maks at fb.com>
Date: 2024-12-13 (Fri, 13 Dec 2024)
Changed paths:
M bolt/lib/Core/BinaryEmitter.cpp
M bolt/lib/Rewrite/RewriteInstance.cpp
Log Message:
-----------
[BOLT] Clean up jump table handling in non-reloc mode. NFCI (#119614)
This change affects non-relocation mode only. Prior to having
CheckLargeFunctions pass, we could have emitted code for functions that
was discarded at the end due to size limitations. Since we didn't know
at the time of emission if the code would be discarded or not, we had to
emit jump tables in separate sections and handle them separately.
However, now we always run CheckLargeFunctions and make sure all emitted
code is used. Thus, we can get rid of the special jump table handling.
Commit: 82459ecf3ebbc697bdde265320d126773111ae0f
https://github.com/llvm/llvm-project/commit/82459ecf3ebbc697bdde265320d126773111ae0f
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-12-13 (Fri, 13 Dec 2024)
Changed paths:
M llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
M llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
M llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
M llvm/test/CodeGen/RISCV/rvv/rvv-peephole-vmerge-to-vmv.mir
Log Message:
-----------
[RISCV] Split OPERAND_SEW operand type for mask only instructions. (#119776)
Mask only instructions like vmand and vmsbf should always have 0 for
their Log2SEW operand. Non-mask instructions should only have
3, 4, 5, or 6 for their Log2SEW operand.
Split the operand type so we can verify these cases separately.
I had to fix the SEW for whole register move to vmv.v.v copy
optimization and update an mir test. The vmv.v.v change isn't
functional since we have already done vsetvli insertion before and
nothing else uses the field after copy expansion. I can split these
changes off if desired.
Commit: 5f72f2c8fd6cf59c9f2066c58559a9a9d2888a9a
https://github.com/llvm/llvm-project/commit/5f72f2c8fd6cf59c9f2066c58559a9a9d2888a9a
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2024-12-14 (Sat, 14 Dec 2024)
Changed paths:
M llvm/lib/Target/AMDGPU/SOPInstructions.td
M llvm/lib/Target/AMDGPU/VOP3Instructions.td
Log Message:
-----------
AMDGPU: Remove large, negative AddedComplexity from minimum/maximum patterns (#119795)
Commit: c4a78b6fe32d72d5c9f3b4a4fa2be206675ccd05
https://github.com/llvm/llvm-project/commit/c4a78b6fe32d72d5c9f3b4a4fa2be206675ccd05
Author: Florian Hahn <flo at fhahn.com>
Date: 2024-12-13 (Fri, 13 Dec 2024)
Changed paths:
M llvm/lib/Transforms/Utils/SimplifyCFG.cpp
M llvm/test/Transforms/SimplifyCFG/hoist-dbgvalue.ll
M llvm/test/Transforms/SimplifyCFG/hoisting-metadata.ll
Log Message:
-----------
[SimplifyCFG] Always allow hoisting if all instructions match. (#97158)
Generalize hoistCommonCodeFromSuccessors's `EqTermsOnly` to
`AllInstsEqOnly` and always allow hoisting if all instructions match.
In that case, all instructions can be hoisted and the
original branch will be replaced and selects for PHIs are added. This
allows preserving metadata in more cases, using the existing hoisting
logic, whereas previously FoldTwoEntryPHINode would drop the metadata.
https://llvm-compile-time-tracker.com/compare.php?from=716360367fbdabac2c374c19b8746f4de49a5599&to=986b2c47df516b31d998c055400e4f62aa76edc6&stat=instructions:u
PR: https://github.com/llvm/llvm-project/pull/97158
Commit: e5e0f23ae8e97eb910cb8ae42373f354eee496c7
https://github.com/llvm/llvm-project/commit/e5e0f23ae8e97eb910cb8ae42373f354eee496c7
Author: Kirill Stoimenov <87100199+kstoimenov at users.noreply.github.com>
Date: 2024-12-13 (Fri, 13 Dec 2024)
Changed paths:
M compiler-rt/lib/ubsan_minimal/ubsan_minimal_handlers.cpp
Log Message:
-----------
[nfc][ubsan-minimal] Refactor error reporting to use a single function (#119920)
This refactoring will allow to make this function weak later on so that
it could be overloaded by a client. See #119242.
Commit: 3273d0bb148795ead4d6e29177bd63346bb6362a
https://github.com/llvm/llvm-project/commit/3273d0bb148795ead4d6e29177bd63346bb6362a
Author: Valentin Clement (バレンタイン クレメン) <clementval at gmail.com>
Date: 2024-12-13 (Fri, 13 Dec 2024)
Changed paths:
M flang/lib/Semantics/resolve-names.cpp
M flang/test/Semantics/modfile55.cuf
Log Message:
-----------
[flang][cuda] Apply implicit data attribute only in device context (#119919)
Fix the condition so the implicit device data attribute is not applied
when the routine has `attribute(host)`
Commit: 3351b3bf8dcb9aebfa6f491fcbe5a00acbcc3291
https://github.com/llvm/llvm-project/commit/3351b3bf8dcb9aebfa6f491fcbe5a00acbcc3291
Author: erichkeane <ekeane at nvidia.com>
Date: 2024-12-13 (Fri, 13 Dec 2024)
Changed paths:
M clang/include/clang/AST/OpenACCClause.h
M clang/include/clang/Basic/OpenACCClauses.def
M clang/include/clang/Sema/SemaOpenACC.h
M clang/lib/AST/OpenACCClause.cpp
M clang/lib/AST/StmtProfile.cpp
M clang/lib/AST/TextNodeDumper.cpp
M clang/lib/Parse/ParseOpenACC.cpp
M clang/lib/Sema/SemaOpenACC.cpp
M clang/lib/Sema/TreeTransform.h
M clang/lib/Serialization/ASTReader.cpp
M clang/lib/Serialization/ASTWriter.cpp
M clang/test/AST/ast-print-openacc-data-construct.cpp
M clang/test/ParserOpenACC/parse-clauses.c
M clang/test/SemaOpenACC/combined-construct-auto_seq_independent-clauses.c
M clang/test/SemaOpenACC/combined-construct-device_type-clause.c
M clang/test/SemaOpenACC/compute-construct-device_type-clause.c
A clang/test/SemaOpenACC/data-construct-detach-ast.cpp
A clang/test/SemaOpenACC/data-construct-detach-clause.c
M clang/test/SemaOpenACC/data-construct.cpp
M clang/test/SemaOpenACC/loop-construct-auto_seq_independent-clauses.c
M clang/test/SemaOpenACC/loop-construct-device_type-clause.c
M clang/tools/libclang/CIndex.cpp
Log Message:
-----------
[OpenACC] implement 'detach' clause sema
This is another new clause specific to 'exit data' that takes a pointer
argument. This patch implements this the same way we do a few other
clauses (like attach) that have the same restrictions.
Commit: ab07c51534b904bab55bcaaf950823fc72719b11
https://github.com/llvm/llvm-project/commit/ab07c51534b904bab55bcaaf950823fc72719b11
Author: Kazu Hirata <kazu at google.com>
Date: 2024-12-13 (Fri, 13 Dec 2024)
Changed paths:
M llvm/unittests/ProfileData/MemProfTest.cpp
Log Message:
-----------
[memprof] Don't use Frame::hash() (NFC) (#119828)
In these tests, we just want to add one instance of
IndexedMemProfRecord to MemProfData.Records and retrieve it from
MemProfReader. There is no particular reason to associate F1.hash()
with the IndexedMemProfRecord instance. A fake value suffices.
While I am at it, I'm switching to try_emplace so that I can move
FakeRecord.
Commit: cd093c2e1bac35dd2c6b914d0b64ce56683cb50a
https://github.com/llvm/llvm-project/commit/cd093c2e1bac35dd2c6b914d0b64ce56683cb50a
Author: Kazu Hirata <kazu at google.com>
Date: 2024-12-13 (Fri, 13 Dec 2024)
Changed paths:
M llvm/include/llvm/ProfileData/InstrProfWriter.h
Log Message:
-----------
[memprof] Make InstrProfwriter::addMemProfRecord and its friends private (NFC) (#119831)
This patch makes the following functions private:
- InstrProfWriter::addMemProfRecord
- InstrProfWriter::addMemProfFrame
- InstrProfWriter::addMemProfCallStack
These days, we add MemProf profile to the writer context via
addMemProfData. We no longer add individual items.
Commit: 5528388e3664c6d7d292f20a739f1bf1c8ef768d
https://github.com/llvm/llvm-project/commit/5528388e3664c6d7d292f20a739f1bf1c8ef768d
Author: Ramkumar Ramachandra <ramkumar.ramachandra at codasip.com>
Date: 2024-12-13 (Fri, 13 Dec 2024)
Changed paths:
M llvm/include/llvm/IR/CmpPredicate.h
M llvm/lib/IR/Instructions.cpp
M llvm/lib/Transforms/Scalar/EarlyCSE.cpp
A llvm/test/Transforms/EarlyCSE/pr119893.ll
Log Message:
-----------
EarlyCSE: fix CmpPredicate duplicate-hashing (#119902)
Strip hash_value() for CmpPredicate, as different callers have different
hashing use-cases. In this case, there is just one caller, namely
EarlyCSE, which calls hash_combine() on a CmpPredicate, which used to
call hash_combine() on a CmpInst::Predicate prior to 4a0d53a
(PatternMatch: migrate to CmpPredicate). This has uncovered a bug where
two icmp instructions differing in just the fact that one of them has
the samesign flag on it are hashed differently, leading to divergent
hashing, and a crash. Fix this crash by dropping samesign information on
icmp instructions before hashing them, preserving the former behavior.
Fixes #119893.
Commit: 537e0e1ff639ed4f8fa4dadbc84f4a6a12e1d20a
https://github.com/llvm/llvm-project/commit/537e0e1ff639ed4f8fa4dadbc84f4a6a12e1d20a
Author: Luke Quinn <quic_lquinn at quicinc.com>
Date: 2024-12-13 (Fri, 13 Dec 2024)
Changed paths:
M llvm/lib/Target/RISCV/RISCVInstrInfo.td
M llvm/test/CodeGen/RISCV/GlobalISel/double-arith.ll
M llvm/test/CodeGen/RISCV/GlobalISel/double-intrinsics.ll
M llvm/test/CodeGen/RISCV/GlobalISel/fp128.ll
M llvm/test/CodeGen/RISCV/GlobalISel/rv64zba.ll
Log Message:
-----------
[RISCV][GISel] Added GISelPredicateCodes to LeadingOnes*Mask (#119886)
Commit: 1345ee4232c90205f152154cfd557c54feb3853d
https://github.com/llvm/llvm-project/commit/1345ee4232c90205f152154cfd557c54feb3853d
Author: Valentin Clement (バレンタイン クレメン) <clementval at gmail.com>
Date: 2024-12-13 (Fri, 13 Dec 2024)
Changed paths:
M flang/lib/Semantics/resolve-names.cpp
M flang/test/Semantics/modfile55.cuf
Log Message:
-----------
[flang][cuda] Do not apply implicit data attribute on dummy arg with VALUE (#119927)
Dummy arguments with the VALUE attribute do not need the implicit data
attribute.
Commit: 71d2fa7988f4ce4647b6ed387cf5b51dafa11e4c
https://github.com/llvm/llvm-project/commit/71d2fa7988f4ce4647b6ed387cf5b51dafa11e4c
Author: Kirill Stoimenov <87100199+kstoimenov at users.noreply.github.com>
Date: 2024-12-13 (Fri, 13 Dec 2024)
Changed paths:
M compiler-rt/lib/ubsan_minimal/ubsan_minimal_handlers.cpp
A compiler-rt/test/ubsan_minimal/TestCases/override-callback.c
Log Message:
-----------
[ubsan-minimal] Switch to weak symbols for callbacks to allow overriding in client code (#119242)
Commit: ecdf0dac565f750376f65f93b5bfd8b08d143116
https://github.com/llvm/llvm-project/commit/ecdf0dac565f750376f65f93b5bfd8b08d143116
Author: Chris White <chriswhiteiodev at gmail.com>
Date: 2024-12-13 (Fri, 13 Dec 2024)
Changed paths:
M llvm/include/llvm/CodeGen/SDPatternMatch.h
M llvm/unittests/CodeGen/SelectionDAGPatternMatchTest.cpp
Log Message:
-----------
[DAG] SDPatternMatch - Add m_ExtractElt and m_InsertElt matchers (#119430)
Resolves #118844
Commit: 9bf79308b893e8998e7efd752835636038c2db4f
https://github.com/llvm/llvm-project/commit/9bf79308b893e8998e7efd752835636038c2db4f
Author: Krzysztof Drewniak <Krzysztof.Drewniak at amd.com>
Date: 2024-12-13 (Fri, 13 Dec 2024)
Changed paths:
M mlir/lib/Dialect/Arith/Transforms/IntRangeOptimizations.cpp
M mlir/test/Dialect/Arith/int-range-narrowing.mlir
Log Message:
-----------
[mlir][Arith] Let integer range narrowing handle negative values (#119642)
Update integer range narrowing to handle negative values.
The previous restriction to only narrowing known-non-negative values
wasn't needed, as both the signed and unsigned ranges represent bounds
on the values of each variable in the program ... except that one might
be more accurate than the other. So, if either the signed or unsigned
interpretetation of the inputs and outputs allows for integer narrowing,
the narrowing is permitted.
This commit also updates the integer optimization rewrites to preserve
the stae of constant-like operations and those that are narrowed so that
rewrites of other operations don't lose that range information.
Commit: d0155789615c2272fbb304e34dc1df4d8d72f7cc
https://github.com/llvm/llvm-project/commit/d0155789615c2272fbb304e34dc1df4d8d72f7cc
Author: alx32 <103613512+alx32 at users.noreply.github.com>
Date: 2024-12-13 (Fri, 13 Dec 2024)
Changed paths:
M llvm/include/llvm/DebugInfo/GSYM/GsymReader.h
M llvm/lib/DebugInfo/GSYM/CallSiteInfo.cpp
M llvm/lib/DebugInfo/GSYM/GsymReader.cpp
A llvm/test/tools/llvm-gsymutil/ARM_AArch64/macho-gsym-merged-callsites-dsym.yaml
Log Message:
-----------
[llvm-gsymutil] Fix dumping of call sites for merged functions (#119759)
Currently, when dumping the contents of a GSYM there are three issues:
- Callsite information is not displayed for merged functions - this is
because of a bug in `CallSiteInfoLoader::buildFunctionMap` where when
enumerating through `Func.MergedFunctions` - we enumerate by value
instead of by reference.
- There is no variable indent for printing callsite info - meaning that
when printing callsites for merged functions, the indent will be
different than the other info of the merged function. To address this we
add configurable indent for printing callsite info
- Callsite info is printed right after merged function info. Meaning
that if the merged function also has call site information, the parent's
callsite info will appear right after the merged function's callsite
info - leading to confusion. To address this we print the callsite info
first, then the merged functions info.
This change addresses all the above 3 issues.
Example of old vs new:
<img width="1074" alt="image"
src="https://github.com/user-attachments/assets/d039ad69-fa79-4abb-9816-eda9cc2eda53"
/>
Commit: f22cff7675f7f64aa52204f4426f5047cc75fbb9
https://github.com/llvm/llvm-project/commit/f22cff7675f7f64aa52204f4426f5047cc75fbb9
Author: Adrian Prantl <aprantl at apple.com>
Date: 2024-12-13 (Fri, 13 Dec 2024)
Changed paths:
M lldb/source/DataFormatters/FormatterSection.cpp
M lldb/test/API/functionalities/data-formatter/embedded-summary/TestEmbeddedTypeSummary.py
M lldb/test/API/functionalities/data-formatter/embedded-summary/main.c
Log Message:
-----------
[lldb] Support zero-padding in formatter sections (#119934)
Commit: d73ef9749e72e59d1d34275e89d4d2fffddd3e8c
https://github.com/llvm/llvm-project/commit/d73ef9749e72e59d1d34275e89d4d2fffddd3e8c
Author: Nico Weber <thakis at chromium.org>
Date: 2024-12-13 (Fri, 13 Dec 2024)
Changed paths:
M lld/COFF/Chunks.cpp
M lld/COFF/Symbols.cpp
M lld/COFF/Symbols.h
M lld/test/COFF/reloc-discarded.s
Log Message:
-----------
[lld/COFF] Demangle symbol name in discarded section relocation error message (#119726)
Commit: 22266bc958abdb1414832fa09a7a3b31166427a6
https://github.com/llvm/llvm-project/commit/22266bc958abdb1414832fa09a7a3b31166427a6
Author: Tom Stellard <tstellar at redhat.com>
Date: 2024-12-13 (Fri, 13 Dec 2024)
Changed paths:
M .github/workflows/build-ci-container.yml
Log Message:
-----------
workflows/build-ci-container: Fix typos in variables (#119943)
This was preventing the containers from being pushed to the registry.
Commit: af20aff35ec37ead88903bc3e44f6a81c5c9ca4e
https://github.com/llvm/llvm-project/commit/af20aff35ec37ead88903bc3e44f6a81c5c9ca4e
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2024-12-13 (Fri, 13 Dec 2024)
Changed paths:
M .github/workflows/build-ci-container-windows.yml
Log Message:
-----------
[Github] Fix windows container push (#119916)
The windows container push was not tested in the pull request and had a
couple of typos that prevented it from functioning. This patch fixes
that so we can actually push the container to GHCR.
Commit: a222d00c667f5582194ba7e50b870312e4b4427b
https://github.com/llvm/llvm-project/commit/a222d00c667f5582194ba7e50b870312e4b4427b
Author: Fangrui Song <i at maskray.me>
Date: 2024-12-13 (Fri, 13 Dec 2024)
Changed paths:
M lld/wasm/Config.h
M lld/wasm/Driver.cpp
Log Message:
-----------
[lld][WebAssembly] Introduce Ctx::arg
and forward it to LinkerDriver's ctor so that some uses of the global
`config` can be dropped. This is similar to how the ELF port
migrates away from the global `config`.
Pull Request: https://github.com/llvm/llvm-project/pull/119829
Commit: e821f642fdc75922b1a020447485acccf3e7fa92
https://github.com/llvm/llvm-project/commit/e821f642fdc75922b1a020447485acccf3e7fa92
Author: Kirill Stoimenov <kstoimenov at google.com>
Date: 2024-12-14 (Sat, 14 Dec 2024)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
M llvm/test/CodeGen/AMDGPU/sgpr-regalloc-flags.ll
Log Message:
-----------
Revert "[AMDGPU][CodeGen] Do not backtrace invalid -regalloc param (#119687)"
Causes bot failure: https://lab.llvm.org/buildbot/#/builders/55/builds/4246/steps/11/logs/stdio
This reverts commit 7a648554f886fbc043c4f3f58ca88f6c4535f2cf.
Commit: 49c2207f21c0922aedb6c70471f8ea068977eb30
https://github.com/llvm/llvm-project/commit/49c2207f21c0922aedb6c70471f8ea068977eb30
Author: Timm Baeder <tbaeder at redhat.com>
Date: 2024-12-14 (Sat, 14 Dec 2024)
Changed paths:
M clang/lib/AST/ByteCode/Integral.h
M clang/lib/AST/ByteCode/Interp.h
M clang/test/AST/ByteCode/shifts.cpp
Log Message:
-----------
[clang][bytecode] Fix some shift edge cases (#119895)
Around shifting negative values.
Commit: a6636ce4d124176856c3913d4bf6c3ceff1f5a1f
https://github.com/llvm/llvm-project/commit/a6636ce4d124176856c3913d4bf6c3ceff1f5a1f
Author: Timm Bäder <tbaeder at redhat.com>
Date: 2024-12-14 (Sat, 14 Dec 2024)
Changed paths:
M clang/lib/AST/ByteCode/Integral.h
M clang/lib/AST/ByteCode/Interp.h
M clang/test/AST/ByteCode/shifts.cpp
Log Message:
-----------
Revert "[clang][bytecode] Fix some shift edge cases (#119895)"
This reverts commit 49c2207f21c0922aedb6c70471f8ea068977eb30.
This breaks on big-endian, again:
https://lab.llvm.org/buildbot/#/builders/154/builds/9018
Commit: 2291e5aa45dc135a5f908032eb31d19ef3570114
https://github.com/llvm/llvm-project/commit/2291e5aa45dc135a5f908032eb31d19ef3570114
Author: Congcong Cai <congcongcai0907 at 163.com>
Date: 2024-12-14 (Sat, 14 Dec 2024)
Changed paths:
M clang-tools-extra/docs/clang-tidy/index.rst
Log Message:
-----------
[clang-tidy][doc] align the title style in clang-tidy/index.rst (#119938)
Uppercase each word in title and toctree
_Originally posted by @nicovank in
https://github.com/llvm/llvm-project/pull/119842#discussion_r1884559775_.
---------
Co-authored-by: Nicolas van Kempen <nvankemp at gmail.com>
Commit: ca79ff07d8ae7a0c2531bfdb1cb623e25e5bd486
https://github.com/llvm/llvm-project/commit/ca79ff07d8ae7a0c2531bfdb1cb623e25e5bd486
Author: Chandler Carruth <chandlerc at gmail.com>
Date: 2024-12-13 (Fri, 13 Dec 2024)
Changed paths:
M clang/include/clang/Basic/Builtins.h
M clang/include/clang/Basic/BuiltinsPPC.def
M clang/include/clang/Basic/TargetInfo.h
M clang/lib/Basic/Builtins.cpp
M clang/lib/Basic/Targets/AArch64.cpp
M clang/lib/Basic/Targets/AArch64.h
M clang/lib/Basic/Targets/AMDGPU.cpp
M clang/lib/Basic/Targets/AMDGPU.h
M clang/lib/Basic/Targets/ARC.h
M clang/lib/Basic/Targets/ARM.cpp
M clang/lib/Basic/Targets/ARM.h
M clang/lib/Basic/Targets/AVR.h
M clang/lib/Basic/Targets/BPF.cpp
M clang/lib/Basic/Targets/BPF.h
M clang/lib/Basic/Targets/CSKY.cpp
M clang/lib/Basic/Targets/CSKY.h
M clang/lib/Basic/Targets/DirectX.h
M clang/lib/Basic/Targets/Hexagon.cpp
M clang/lib/Basic/Targets/Hexagon.h
M clang/lib/Basic/Targets/Lanai.h
M clang/lib/Basic/Targets/LoongArch.cpp
M clang/lib/Basic/Targets/LoongArch.h
M clang/lib/Basic/Targets/M68k.cpp
M clang/lib/Basic/Targets/M68k.h
M clang/lib/Basic/Targets/MSP430.h
M clang/lib/Basic/Targets/Mips.cpp
M clang/lib/Basic/Targets/Mips.h
M clang/lib/Basic/Targets/NVPTX.cpp
M clang/lib/Basic/Targets/NVPTX.h
M clang/lib/Basic/Targets/PNaCl.h
M clang/lib/Basic/Targets/PPC.cpp
M clang/lib/Basic/Targets/PPC.h
M clang/lib/Basic/Targets/RISCV.cpp
M clang/lib/Basic/Targets/RISCV.h
M clang/lib/Basic/Targets/SPIR.cpp
M clang/lib/Basic/Targets/SPIR.h
M clang/lib/Basic/Targets/Sparc.h
M clang/lib/Basic/Targets/SystemZ.cpp
M clang/lib/Basic/Targets/SystemZ.h
M clang/lib/Basic/Targets/TCE.h
M clang/lib/Basic/Targets/VE.cpp
M clang/lib/Basic/Targets/VE.h
M clang/lib/Basic/Targets/WebAssembly.cpp
M clang/lib/Basic/Targets/WebAssembly.h
M clang/lib/Basic/Targets/X86.cpp
M clang/lib/Basic/Targets/X86.h
M clang/lib/Basic/Targets/XCore.cpp
M clang/lib/Basic/Targets/XCore.h
Log Message:
-----------
Revert "Switch builtin strings to use string tables" (#119638)
Reverts llvm/llvm-project#118734
There are currently some specific versions of MSVC that are miscompiling
this code (we think). We don't know why as all the other build bots and
at least some folks' local Windows builds work fine.
This is a candidate revert to help the relevant folks catch their
builders up and have time to debug the issue. However, the expectation
is to roll forward at some point with a workaround if at all possible.
Commit: 7c294eb78009ef252aafa269963f5496d1dedf6f
https://github.com/llvm/llvm-project/commit/7c294eb78009ef252aafa269963f5496d1dedf6f
Author: Kazu Hirata <kazu at google.com>
Date: 2024-12-14 (Sat, 14 Dec 2024)
Changed paths:
M llvm/lib/Transforms/Instrumentation/MemProfiler.cpp
Log Message:
-----------
[memprof] Simplify readMemprof (NFC) (#119930)
This patch essentially replaces:
std::pair<const std::vector<Frame> *, unsigned>
with:
ArrayRef<Frame>
This way, we can store and pass ArrayRef<Frame>, conceptually one
item, instead of the pointer and index.
The only problem is that we don't have an existing hash function for
ArrayRef<Frame>>, so we provide a custom one, namely
CallStackHash.
Commit: 74fb9928443ce3d176911615e6a0297f074736fe
https://github.com/llvm/llvm-project/commit/74fb9928443ce3d176911615e6a0297f074736fe
Author: alx32 <103613512+alx32 at users.noreply.github.com>
Date: 2024-12-14 (Sat, 14 Dec 2024)
Changed paths:
M llvm/test/tools/llvm-gsymutil/ARM_AArch64/macho-gsym-merged-callsites-dsym.yaml
Log Message:
-----------
[llvm-gsymutil] Disable test macho-gsym-merged-callsites-dsym (#119957)
The macho-gsym-merged-callsites-dsym is failing on some hosts.
Disabling for now while we come up with a fix.
Commit: 97c3c32372bb8478c53ab9469585c7c6e531cbd2
https://github.com/llvm/llvm-project/commit/97c3c32372bb8478c53ab9469585c7c6e531cbd2
Author: Sergei Barannikov <barannikov88 at gmail.com>
Date: 2024-12-14 (Sat, 14 Dec 2024)
Changed paths:
M llvm/lib/Target/SystemZ/SystemZInstrInfo.td
M llvm/lib/Target/SystemZ/SystemZOperators.td
M llvm/utils/TableGen/Common/CodeGenDAGPatterns.cpp
Log Message:
-----------
[TableGen][SystemZ] Correctly check the range of a leaf immediate (#119931)
The "Size >= 32" check probably dates back to when TableGen integers
were 32-bit. Delete it and simplify code by using `isInt`/`isUInt`.
Commit: 1911919682c863643787b30286bb67359c7932f4
https://github.com/llvm/llvm-project/commit/1911919682c863643787b30286bb67359c7932f4
Author: Pavel Kosov <kpdev42 at gmail.com>
Date: 2024-12-14 (Sat, 14 Dec 2024)
Changed paths:
M clang/lib/Driver/ToolChains/OHOS.cpp
Log Message:
-----------
Revert "[Driver][OHOS] Fix lld link issue for OHOS (#118192)"
This reverts commit bc28be0a428020ea803c94adb4df48ee4972e9f1.
Some issues were discovered with GN buildbot http://45.33.8.238/linux/155432/step_6.txt
Need to investigate it
Commit: cc54a0ce5674b740c2136d7bd2416ffeb4a230cf
https://github.com/llvm/llvm-project/commit/cc54a0ce5674b740c2136d7bd2416ffeb4a230cf
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-12-14 (Sat, 14 Dec 2024)
Changed paths:
M llvm/lib/Transforms/Vectorize/VectorCombine.cpp
M llvm/test/Transforms/VectorCombine/AMDGPU/as-transition.ll
M llvm/test/Transforms/VectorCombine/X86/load.ll
Log Message:
-----------
[VectorCombine] vectorizeLoadInsert - only fold when inserting into a poison vector (#119906)
We have corresponding poison tests in the "-inseltpoison.ll" sibling test files.
Fixes #119900
Commit: d6b133e5a7f143757736455a2acc7a06266e2c7d
https://github.com/llvm/llvm-project/commit/d6b133e5a7f143757736455a2acc7a06266e2c7d
Author: LLVM GN Syncbot <llvmgnsyncbot at gmail.com>
Date: 2024-12-14 (Sat, 14 Dec 2024)
Changed paths:
M llvm/utils/gn/secondary/lldb/source/Plugins/Process/Utility/BUILD.gn
Log Message:
-----------
[gn build] Port 6c4e70fcbbb6
Commit: b7e75a76449e80d8b6caa1f447d536ffa231783a
https://github.com/llvm/llvm-project/commit/b7e75a76449e80d8b6caa1f447d536ffa231783a
Author: LLVM GN Syncbot <llvmgnsyncbot at gmail.com>
Date: 2024-12-14 (Sat, 14 Dec 2024)
Changed paths:
M llvm/utils/gn/secondary/libcxx/include/BUILD.gn
Log Message:
-----------
[gn build] Port 9474e0945918
Commit: 0ae75eba678a9ab459a382818148ef06afe817b5
https://github.com/llvm/llvm-project/commit/0ae75eba678a9ab459a382818148ef06afe817b5
Author: Aaditya <115080342+easyonaadit at users.noreply.github.com>
Date: 2024-12-14 (Sat, 14 Dec 2024)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
Log Message:
-----------
[AMDGPU] Assert if stack grows downwards. (#119888)
Commit: 10f23d116baa221707d8831d3c34f38f511c408e
https://github.com/llvm/llvm-project/commit/10f23d116baa221707d8831d3c34f38f511c408e
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-12-14 (Sat, 14 Dec 2024)
Changed paths:
M llvm/lib/Target/X86/X86ISelLowering.cpp
Log Message:
-----------
[X86] matchPMADDWD/matchPMADDWD_2 - update to use m_ExtractElt matchers. NFC.
Commit: 6157dbe48c21d900da1c7df11a8072a235f82001
https://github.com/llvm/llvm-project/commit/6157dbe48c21d900da1c7df11a8072a235f82001
Author: Nikolas Klauser <nikolasklauser at berlin.de>
Date: 2024-12-14 (Sat, 14 Dec 2024)
Changed paths:
M libcxx/include/__utility/forward_like.h
M libcxx/include/variant
Log Message:
-----------
[libc++] Introduce __forward_as (#118168)
This allows forwarding an object as a specific type. This is usually
useful when using `deducing this` to avoid calling any functions in a
deriving class.
Commit: 1901da32a4c9318d860a8aa071912da700bfb923
https://github.com/llvm/llvm-project/commit/1901da32a4c9318d860a8aa071912da700bfb923
Author: Nikolas Klauser <nikolasklauser at berlin.de>
Date: 2024-12-14 (Sat, 14 Dec 2024)
Changed paths:
A libcxx/test/std/utilities/meta/derived_from_integral_constant.compile.pass.cpp
Log Message:
-----------
[libc++] Add a test to make sure all the type traits derived from bool_constant
Commit: bca11777bebaf3b61d25fd5874584066e80d57fa
https://github.com/llvm/llvm-project/commit/bca11777bebaf3b61d25fd5874584066e80d57fa
Author: Aviad Cohen <aviadcohen7 at gmail.com>
Date: 2024-12-14 (Sat, 14 Dec 2024)
Changed paths:
M mlir/include/mlir/Dialect/SCF/IR/SCFOps.td
Log Message:
-----------
[nfc][mlir][scf]: Define scf.for lower/upper bounds can be also negative or zero (#117534)
Per the discussion here:
https://github.com/llvm/llvm-project/pull/116748#discussion_r1848680070 , this commit properly declare that lower and upper bounds can be also negative or zero.
Commit: c3276a96d909233b836e839a23a7ad510fae407a
https://github.com/llvm/llvm-project/commit/c3276a96d909233b836e839a23a7ad510fae407a
Author: Nikolas Klauser <nikolasklauser at berlin.de>
Date: 2024-12-14 (Sat, 14 Dec 2024)
Changed paths:
M libcxx/test/std/utilities/meta/derived_from_integral_constant.compile.pass.cpp
Log Message:
-----------
[libc++] Disable deprecation warnings in derived_from_integral_constant.compile.pass.cpp
Commit: a999ab44be8994d39d2469c1b4d025c4e1131197
https://github.com/llvm/llvm-project/commit/a999ab44be8994d39d2469c1b4d025c4e1131197
Author: Aaron Puchert <aaron.puchert at sap.com>
Date: 2024-12-14 (Sat, 14 Dec 2024)
Changed paths:
M clang/lib/Analysis/ThreadSafetyCommon.cpp
M clang/test/SemaCXX/warn-thread-safety-analysis.cpp
Log Message:
-----------
Thread safety analysis: Fix substitution for operator calls (#116487)
For operator calls that go to methods we need to substitute the first
parameter for "this" and the following parameters into the function
parameters, instead of substituting all of them into the parameters.
This revealed an issue about lambdas. An existing test accidentally
worked because the substitution bug was covered by a speciality of
lambdas: a CXXThisExpr in a lambda CXXMethodDecl does not refer to the
implicit this argument of the method, but to a captured "this" from the
context the lambda was created in. This can happen for operator calls,
where it worked due to the substitution bug (we treated the implicit
this argument incorrectly as parameter), and for regular calls (i.e.
obj.operator()(args) instead of obj(args)), where it didn't work.
The correct fix seems to be to clear the self-argument on a lambda call.
Lambdas can only capture "this" inside methods, and calls to the lambda
in that scope cannot substitute anything for "this".
Commit: 9ef73d6017584a5ea425f898754bb5d1e03536bb
https://github.com/llvm/llvm-project/commit/9ef73d6017584a5ea425f898754bb5d1e03536bb
Author: David Green <david.green at arm.com>
Date: 2024-12-14 (Sat, 14 Dec 2024)
Changed paths:
M llvm/lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp
Log Message:
-----------
[AArch64] Fix brackets warning in assert. NFC
Commit: c35108e24488af1db1914ec083439189e6a7fce6
https://github.com/llvm/llvm-project/commit/c35108e24488af1db1914ec083439189e6a7fce6
Author: Kazu Hirata <kazu at google.com>
Date: 2024-12-14 (Sat, 14 Dec 2024)
Changed paths:
M clang/unittests/AST/ASTImporterTest.cpp
Log Message:
-----------
[AST] Migrate away from PointerUnion::get (NFC) (#119949)
Note that PointerUnion::get has been soft deprecated in
PointerUnion.h:
// FIXME: Replace the uses of is(), get() and dyn_cast() with
// isa<T>, cast<T> and the llvm::dyn_cast<T>
Commit: c0849218c43db152259a349aee130eda51057e4e
https://github.com/llvm/llvm-project/commit/c0849218c43db152259a349aee130eda51057e4e
Author: Sergei Barannikov <barannikov88 at gmail.com>
Date: 2024-12-14 (Sat, 14 Dec 2024)
Changed paths:
M llvm/lib/Target/SystemZ/SystemZOperators.td
Log Message:
-----------
[SystemZ] Use the same PatFrag for all "insert imm" fragments (NFC) (#119962)
Commit: 331c2dd8b482e441d8ccddc09f21a02cc9454786
https://github.com/llvm/llvm-project/commit/331c2dd8b482e441d8ccddc09f21a02cc9454786
Author: Alexander Yermolovich <43973793+ayermolo at users.noreply.github.com>
Date: 2024-12-14 (Sat, 14 Dec 2024)
Changed paths:
M bolt/lib/Core/DebugNames.cpp
A bolt/test/X86/dwarf5-debug-names-gnu-push-tls-address.s
Log Message:
-----------
[BOLT][DWARF] Add support for DW_OP_GNU_push_tls_address to .debug_names (#119939)
Added support to BOLT for DW_OP_GNU_push_tls_address. So now
DW_TAG_variable with this OP in DW_AT_location will appear in debug
names acceleration table. Although not in the DWARF 5 spec it is similar
to DW_OP_form_tls_address. Without this support llvm-dwarfdump --verify
--debug-names will report errors.
Commit: 0032c151dcbdbf9cdd8982870c7611e6f08c504b
https://github.com/llvm/llvm-project/commit/0032c151dcbdbf9cdd8982870c7611e6f08c504b
Author: David Green <david.green at arm.com>
Date: 2024-12-14 (Sat, 14 Dec 2024)
Changed paths:
M llvm/include/llvm/Analysis/PtrUseVisitor.h
M llvm/include/llvm/Transforms/Utils/SSAUpdater.h
M llvm/lib/Transforms/Scalar/SROA.cpp
M llvm/lib/Transforms/Utils/SSAUpdater.cpp
M llvm/test/Transforms/SROA/non-capturing-call-readonly.ll
M llvm/test/Transforms/SROA/readonlynocapture.ll
Log Message:
-----------
[SROA] Optimize reloaded values in allocas that escape into readonly nocapture calls. (#116645)
Given an alloca that potentially has many uses in big complex code and
escapes into a call that is readonly+nocapture, we cannot easily split
up the alloca. There are several optimizations that will attempt to take
a value that is stored and a reload, and replace the load with the
original stored value. Instcombine has some simple heuristics, GVN can
sometimes do it, as can CSE in limited situations. They all suffer from
the same issue with complex code - they start from a load/store and need
to prove no-alias for all code between, which in complex cases might be
a lot to look through. Especially if the ptr is an alloca with many uses
that is over the normal escape capture limits.
The pass that does do well with allocas is SROA, as it has a complete
view of all of the uses. This patch adds a case to SROA where it can
detect allocas that are passed into calls that are no-capture readonly.
It can then optimize the reloaded values inside the alloca slice with
the stored value knowing that it is valid no matter the location of the
loads/stores from the no-escaping nature of the alloca.
Commit: e48916f615e0ad2b994b2b785d4fe1b8a98bc322
https://github.com/llvm/llvm-project/commit/e48916f615e0ad2b994b2b785d4fe1b8a98bc322
Author: pzhengqc <55604844+pzhengqc at users.noreply.github.com>
Date: 2024-12-14 (Sat, 14 Dec 2024)
Changed paths:
M llvm/lib/Target/ARM/ARMConstantIslandPass.cpp
A llvm/test/CodeGen/Thumb2/constant-islands-no-split.mir
Log Message:
-----------
[ARM][ConstantIslands] Correct MinNoSplitDisp calculation (#114590)
MinNoSplitDisp was first introduced in D16890 to handle cases where the
ConstantIslands pass fails to converge in the presence of big basic
blocks. However, the computation of the variable seems to be wrong as it
currently computes the offset immediately following UserBB. In other
words, it represents the distance from the beginning of the function to
the end of UserBB. The distance from the beginning of the function does
not seem to be a good indicator of how big the basic block is unless the
basic block is close to the beginning of the function. I think
MinNoSplitDisp should compute the distance between UserOffset and the
end of UserBB instead.
Commit: 9ddcaed3a64c2a187a0cfff4ba8f989c665ae1e5
https://github.com/llvm/llvm-project/commit/9ddcaed3a64c2a187a0cfff4ba8f989c665ae1e5
Author: Davide Italiano <davidino at meta.com>
Date: 2024-12-14 (Sat, 14 Dec 2024)
Changed paths:
R clang/test/Interpreter/Inputs/vector
M clang/test/Interpreter/crash.cpp
Log Message:
-----------
Revert "[Clang] Interpreter test should not depend on system header (#119903)"
This reverts commit 8ab6912831277d87838518c5f775f79d14616860.
Commit: 61ab36a3e226df32855286dd31a2c3859800475d
https://github.com/llvm/llvm-project/commit/61ab36a3e226df32855286dd31a2c3859800475d
Author: Davide Italiano <davidino at meta.com>
Date: 2024-12-14 (Sat, 14 Dec 2024)
Changed paths:
M clang/lib/Interpreter/Interpreter.cpp
R clang/test/Interpreter/crash.cpp
Log Message:
-----------
Revert "[Clang-REPL] Fix crash during `__run_exit_handlers` with dynamic libraries. (#117475)"
This reverts commit 30ad53b92cec0cff9679d559edcc5b933312ba0c as it breaks
systems that don't have a systemwide libc++ or libstdc++ installed. It should
be rewritten to not invoke the system linker. In the meanwhile, reverting
to unblock the bots.
Commit: b5c5c2b26fd4bd0d0d237aaf77a01ca528810707
https://github.com/llvm/llvm-project/commit/b5c5c2b26fd4bd0d0d237aaf77a01ca528810707
Author: Kazu Hirata <kazu at google.com>
Date: 2024-12-14 (Sat, 14 Dec 2024)
Changed paths:
M mlir/include/mlir/Analysis/DataFlow/SparseAnalysis.h
M mlir/lib/Analysis/DataFlow/ConstantPropagationAnalysis.cpp
M mlir/lib/Analysis/DataFlow/IntegerRangeAnalysis.cpp
M mlir/lib/Analysis/DataFlow/SparseAnalysis.cpp
Log Message:
-----------
[DataFlow] Migrate away from PointerUnion::{is,get} (NFC) (#119950)
Note that PointerUnion::{is,get} have been soft deprecated in
PointerUnion.h:
// FIXME: Replace the uses of is(), get() and dyn_cast() with
// isa<T>, cast<T> and the llvm::dyn_cast<T>
I'm not touching PointerUnion::dyn_cast for now because it's a bit
complicated; we could blindly migrate it to dyn_cast_if_present, but
we should probably use dyn_cast when the operand is known to be
non-null.
Commit: 2564f1e1991425cbbfcada52ebaa6191d36fdf53
https://github.com/llvm/llvm-project/commit/2564f1e1991425cbbfcada52ebaa6191d36fdf53
Author: Florian Hahn <flo at fhahn.com>
Date: 2024-12-14 (Sat, 14 Dec 2024)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
M llvm/test/Transforms/LoopVectorize/single_early_exit.ll
M llvm/test/Transforms/LoopVectorize/uncountable-early-exit-vplan.ll
Log Message:
-----------
[VPlan] Simplify Not(Not(A)) -> A.
Follow-up simplification to 5fae408d3a4c073ee4.
Commit: aaadaee7b228d7010ff7076f5002ebb96b5e03dc
https://github.com/llvm/llvm-project/commit/aaadaee7b228d7010ff7076f5002ebb96b5e03dc
Author: Congcong Cai <congcongcai0907 at 163.com>
Date: 2024-12-15 (Sun, 15 Dec 2024)
Changed paths:
M clang-tools-extra/clang-tidy/bugprone/UncheckedOptionalAccessCheck.h
M clang-tools-extra/clang-tidy/cppcoreguidelines/ProTypeMemberInitCheck.cpp
M clang-tools-extra/clang-tidy/cppcoreguidelines/RvalueReferenceParamNotMovedCheck.cpp
M clang-tools-extra/clang-tidy/performance/InefficientVectorOperationCheck.cpp
M clang-tools-extra/clang-tidy/readability/RedundantAccessSpecifiersCheck.h
M clang-tools-extra/clang-tidy/readability/RedundantCastingCheck.cpp
M clang-tools-extra/clang-tidy/utils/RenamerClangTidyCheck.cpp
Log Message:
-----------
[clang-tidy] remove misuse of `getLocalOrGlobal` for non common used options (#119948)
[RFC](https://discourse.llvm.org/t/rfc-global-option-rules-for-clang-tidy/83647)
Commit: 99354f968f64659cbad5c82b0301d851ae54f057
https://github.com/llvm/llvm-project/commit/99354f968f64659cbad5c82b0301d851ae54f057
Author: Richard Dzenis <richard at dzenis.dev>
Date: 2024-12-15 (Sun, 15 Dec 2024)
Changed paths:
M clang/test/SemaCXX/msvc-pragma-function-no-builtin-attr.cpp
Log Message:
-----------
[clang][test] Fix SemaCXX/msvc-pragma-function-no-builtin-attr.cpp for x86 (#119986)
Fix test failure from #119719
84b0f0145887bbfe49fd4dc85490b14108a72cee
Closes #119979
Commit: d33bf2e9df578ff7e44fd22504d6ad5a122b7ee6
https://github.com/llvm/llvm-project/commit/d33bf2e9df578ff7e44fd22504d6ad5a122b7ee6
Author: Hubert Tong <hubert.reinterpretcast at gmail.com>
Date: 2024-12-14 (Sat, 14 Dec 2024)
Changed paths:
M libcxxabi/test/test_demangle.pass.cpp
Log Message:
-----------
NFC: clang-format test_demangle.pass.cpp but keep test "lines"
Add clang-format on/off around test "lines"
Run clang-format without breaking string literals:
clang-format --style='{BasedOnStyle: llvm, BreakStringLiterals: false}'
-i test_demangle.pass.cpp
Add clang-format on/off on fp_literal_cases
Fixups: Split UNSUPPORTED to next line; xfail_cases trailing comma
Replace physical tab
Commit: e2dc0b9b1ec09de2b20387846cd2487362a58322
https://github.com/llvm/llvm-project/commit/e2dc0b9b1ec09de2b20387846cd2487362a58322
Author: Hubert Tong <hubert.reinterpretcast at gmail.com>
Date: 2024-12-14 (Sat, 14 Dec 2024)
Changed paths:
M .git-blame-ignore-revs
Log Message:
-----------
[libc++] Add test_demangle.pass.cpp clang-format to .git-blame-ignore-revs
Commit: 8b02d809d284c8e10b38087431def52c86e3e9e6
https://github.com/llvm/llvm-project/commit/8b02d809d284c8e10b38087431def52c86e3e9e6
Author: Fangrui Song <i at maskray.me>
Date: 2024-12-14 (Sat, 14 Dec 2024)
Changed paths:
M llvm/test/CodeGen/Mips/2008-07-16-SignExtInReg.ll
M llvm/test/CodeGen/Mips/beqzc.ll
M llvm/test/CodeGen/Mips/beqzc1.ll
M llvm/test/CodeGen/Mips/blockaddr.ll
M llvm/test/CodeGen/Mips/brsize3.ll
M llvm/test/CodeGen/Mips/brsize3a.ll
M llvm/test/CodeGen/Mips/ci2.ll
M llvm/test/CodeGen/Mips/const1.ll
M llvm/test/CodeGen/Mips/const4a.ll
M llvm/test/CodeGen/Mips/const6.ll
M llvm/test/CodeGen/Mips/const6a.ll
M llvm/test/CodeGen/Mips/ctlz.ll
M llvm/test/CodeGen/Mips/f16abs.ll
M llvm/test/CodeGen/Mips/fixdfsf.ll
M llvm/test/CodeGen/Mips/fp16instrinsmc.ll
M llvm/test/CodeGen/Mips/fp16mix.ll
M llvm/test/CodeGen/Mips/fpnotneeded.ll
M llvm/test/CodeGen/Mips/funnel-shift-rot.ll
M llvm/test/CodeGen/Mips/funnel-shift.ll
M llvm/test/CodeGen/Mips/helloworld.ll
M llvm/test/CodeGen/Mips/hf16call32.ll
M llvm/test/CodeGen/Mips/hf16call32_body.ll
M llvm/test/CodeGen/Mips/hf1_body.ll
M llvm/test/CodeGen/Mips/hfptrcall.ll
M llvm/test/CodeGen/Mips/i32k.ll
M llvm/test/CodeGen/Mips/l3mc.ll
M llvm/test/CodeGen/Mips/lcb2.ll
M llvm/test/CodeGen/Mips/lcb3c.ll
M llvm/test/CodeGen/Mips/lcb4a.ll
M llvm/test/CodeGen/Mips/lcb5.ll
M llvm/test/CodeGen/Mips/mbrsize4a.ll
M llvm/test/CodeGen/Mips/mips16-hf-attr-2.ll
M llvm/test/CodeGen/Mips/mips16-hf-attr.ll
M llvm/test/CodeGen/Mips/mips16_fpret.ll
M llvm/test/CodeGen/Mips/nomips16.ll
M llvm/test/CodeGen/Mips/powif64_16.ll
M llvm/test/CodeGen/Mips/rotate.ll
M llvm/test/CodeGen/Mips/s2rem.ll
M llvm/test/CodeGen/Mips/sel1c.ll
M llvm/test/CodeGen/Mips/sel2c.ll
M llvm/test/CodeGen/Mips/simplebr.ll
M llvm/test/CodeGen/Mips/small-section-reserve-gp.ll
M llvm/test/CodeGen/Mips/sr1.ll
M llvm/test/CodeGen/Mips/tail16.ll
M llvm/test/CodeGen/Mips/trap1.ll
Log Message:
-----------
[test] Remove redundant -march= in llc -mtriple=
Commit: 8c681a929b8684f5a4ad2ebd4e3e4f20036a9595
https://github.com/llvm/llvm-project/commit/8c681a929b8684f5a4ad2ebd4e3e4f20036a9595
Author: Owen Pan <owenpiano at gmail.com>
Date: 2024-12-14 (Sat, 14 Dec 2024)
Changed paths:
M clang/unittests/Format/FormatTestJS.cpp
Log Message:
-----------
[clang-format][NFC] Add a TypeScript test case
See #108530.
Commit: e04fde193bc2acbaf3ece851479fbd9928c1e280
https://github.com/llvm/llvm-project/commit/e04fde193bc2acbaf3ece851479fbd9928c1e280
Author: Kazu Hirata <kazu at google.com>
Date: 2024-12-14 (Sat, 14 Dec 2024)
Changed paths:
M lld/MachO/Arch/ARM64.cpp
M lld/MachO/ConcatOutputSection.cpp
M lld/MachO/EhFrame.cpp
M lld/MachO/ICF.cpp
M lld/MachO/InputFiles.cpp
M lld/MachO/InputSection.cpp
M lld/MachO/MarkLive.cpp
M lld/MachO/ObjC.cpp
M lld/MachO/Relocations.cpp
M lld/MachO/SyntheticSections.cpp
M lld/MachO/UnwindInfoSection.cpp
Log Message:
-----------
[lld] Migrate away from PointerUnion::{is,get} (NFC) (#119993)
Note that PointerUnion::{is,get} have been soft deprecated in
PointerUnion.h:
// FIXME: Replace the uses of is(), get() and dyn_cast() with
// isa<T>, cast<T> and the llvm::dyn_cast<T>
I'm not touching PointerUnion::dyn_cast for now because it's a bit
complicated; we could blindly migrate it to dyn_cast_if_present, but
we should probably use dyn_cast when the operand is known to be
non-null.
Commit: fe9f2ac8e763d35bf7dea34063b18865ca26a781
https://github.com/llvm/llvm-project/commit/fe9f2ac8e763d35bf7dea34063b18865ca26a781
Author: Fangrui Song <i at maskray.me>
Date: 2024-12-14 (Sat, 14 Dec 2024)
Changed paths:
M llvm/test/MC/ELF/relocation.s
A llvm/test/MC/X86/elf-reloc-got.s
A llvm/test/MC/X86/elf-reloc-size.s
A llvm/test/MC/X86/elf-reloc-tls.s
Log Message:
-----------
[test] Reorganize some R_X86_64_ tests
Commit: 97f43364cc8599bfc64f4f83fb81c7cd0242a1a4
https://github.com/llvm/llvm-project/commit/97f43364cc8599bfc64f4f83fb81c7cd0242a1a4
Author: Amir Ayupov <aaupov at fb.com>
Date: 2024-12-14 (Sat, 14 Dec 2024)
Changed paths:
M bolt/test/merge-fdata-mixed-bat-no-lbr.test
M bolt/test/merge-fdata-mixed-mode.test
M bolt/tools/merge-fdata/merge-fdata.cpp
Log Message:
-----------
[BOLT][NFC] Speedup merge-fdata (#119942)
Eliminate splitting the buffer into lines, and use `std::getline`
directly. Simplify no_lbr and boltedcollection handling as well.
Test Plan: For a large fdata file (200MB), fstream version is ~10%
faster.
Commit: 86526084044167b3c753d32ef8dbf79d57cba0c4
https://github.com/llvm/llvm-project/commit/86526084044167b3c753d32ef8dbf79d57cba0c4
Author: Amir Ayupov <aaupov at fb.com>
Date: 2024-12-14 (Sat, 14 Dec 2024)
Changed paths:
M bolt/test/merge-fdata-lbr-mode.test
M bolt/tools/merge-fdata/merge-fdata.cpp
Log Message:
-----------
[BOLT] Fix counts aggregation in merge-fdata (#119652)
merge-fdata used to consider misprediction count as part of "signature",
or the aggregation key. This prevented it from collapsing profile lines
with different misprediction counts, which resulted in duplicate
`(from, to)` pairs with different misprediction and execution counts.
Fix that by splitting out misprediction count and accumulating it
separately.
Test Plan: updated bolt/test/merge-fdata-lbr-mode.test
Commit: 4c8c1308479166d00b4e1d74ceee7cf0abfe6e72
https://github.com/llvm/llvm-project/commit/4c8c1308479166d00b4e1d74ceee7cf0abfe6e72
Author: David Green <david.green at arm.com>
Date: 2024-12-15 (Sun, 15 Dec 2024)
Changed paths:
M llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
M llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
M llvm/test/CodeGen/AArch64/dup.ll
Log Message:
-----------
[AArch64][GlobalISel] Scalarize i128 shufflevector instructions. (#119980)
This, like other operations, scalarizes shuffle vector operations with
types larger than 64bits. ImplicitDef and Freeze are also handled the
same way, to allow them to legalize. The legalization of
fewerElementsVectorShuffle is adjusted to handled scalarization.
Commit: eb1f9cced9e878362aeac18e120895995f759ee3
https://github.com/llvm/llvm-project/commit/eb1f9cced9e878362aeac18e120895995f759ee3
Author: Alex Rønne Petersen <alex at alexrp.com>
Date: 2024-12-15 (Sun, 15 Dec 2024)
Changed paths:
M libunwind/include/__libunwind_config.h
Log Message:
-----------
[libunwind] Fix compilation for the x32 ABI. (#116608)
This would previously fail the static assertions in `UnwindCursor.hpp`
due to `UnwindCursor`'s size not matching `unw_cursor_t`'s size. As is
done for MIPS N32, this just declares the appropriate size in
`__libunwind_config.h`.
Commit: 6b493baec1ada4ef714197803926c37cd9c56e03
https://github.com/llvm/llvm-project/commit/6b493baec1ada4ef714197803926c37cd9c56e03
Author: Jacek Caban <jacek at codeweavers.com>
Date: 2024-12-15 (Sun, 15 Dec 2024)
Changed paths:
M lld/COFF/Chunks.cpp
M lld/COFF/DLL.cpp
M lld/COFF/Driver.cpp
M lld/COFF/InputFiles.cpp
M lld/COFF/InputFiles.h
M lld/COFF/PDB.cpp
M lld/COFF/SymbolTable.cpp
M lld/COFF/SymbolTable.h
M lld/COFF/Symbols.cpp
Log Message:
-----------
[LLD][COFF] Store reference to SymbolTable instead of COFFLinkerContext in InputFile (NFC) (#119296)
This change prepares for the introduction of separate hybrid namespaces.
Hybrid images will require two `SymbolTable` instances, making it
necessary to associate `InputFile` objects with the relevant one.
Commit: 916bae2d921705c8ce78a4ddec4503c61bc8220c
https://github.com/llvm/llvm-project/commit/916bae2d921705c8ce78a4ddec4503c61bc8220c
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-12-15 (Sun, 15 Dec 2024)
Changed paths:
M llvm/lib/Transforms/Vectorize/VectorCombine.cpp
Log Message:
-----------
[VectorCombine] foldShuffleOfBinops - refactor to make it easier to match icmp/fcmp patterns
NFC refactor to make it easier to also use the fold for icmp/fcmp patterns in a future patch - match the Shuffle with general Instruction operands and avoid explicit use of the BinaryOperator matches as much as possible for the general costing / fold.
Commit: 734a204fbd4b790048c57f79351ad8beeb1000ce
https://github.com/llvm/llvm-project/commit/734a204fbd4b790048c57f79351ad8beeb1000ce
Author: Florian Hahn <flo at fhahn.com>
Date: 2024-12-15 (Sun, 15 Dec 2024)
Changed paths:
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
M llvm/lib/Transforms/Vectorize/VPlan.h
M llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
M llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
Log Message:
-----------
[VPlan] Manage VPWidenIntOrFPInduction debug location via recipe (NFC).
Properly set VPWidenIntOrFpInductionRecipe's debug location in the
recipe and use it, instead of using the debug location of the underlying
IR instruction.
Commit: e1271dd5a7ecf5cee59c8e2684b93501a1aab82d
https://github.com/llvm/llvm-project/commit/e1271dd5a7ecf5cee59c8e2684b93501a1aab82d
Author: Joseph Huber <huberjn at outlook.com>
Date: 2024-12-15 (Sun, 15 Dec 2024)
Changed paths:
M clang-tools-extra/clangd/index/SymbolCollector.cpp
M clang-tools-extra/clangd/unittests/SymbolCollectorTests.cpp
Log Message:
-----------
[clangd] Index reserved symbols from `*intrin.h` system headers (#119735)
Summary:
`clangd` intentionally suppresses indexing symbols from system headers
as these are likely implementation details the user does not want.
Howver, there are plenty of system headers that provide extensions that
we want to index, such as vector intrinsic headers. This patch adds an
extra check for these commonly-named '*intrin.h' headers. This is not
fully inclusive for all symbols the user might want, but it's a good
start.
Fixes: https://github.com/llvm/llvm-project/issues/118684
---------
Co-authored-by: Nathan Ridge <zeratul976 at hotmail.com>
Commit: e85a9f5540f5399b20a32c8d87474e6fc906ad33
https://github.com/llvm/llvm-project/commit/e85a9f5540f5399b20a32c8d87474e6fc906ad33
Author: Jinsong Ji <jinsong.ji at intel.com>
Date: 2024-12-15 (Sun, 15 Dec 2024)
Changed paths:
M libc/shared/rpc.h
M libc/utils/gpu/loader/Loader.h
M libc/utils/gpu/server/rpc_server.cpp
M offload/plugins-nextgen/common/src/RPC.cpp
Log Message:
-----------
libc: Prefix RPC Status code to avoid conflict in windows build (#119991)
Somehow conflict with define in wingdi.h.
Fix build failures:
[ 52%] Building CXX object
projects/offload/plugins-nextgen/common/CMakeFiles/PluginCommon.dir/src/RPC.cpp.obj
In file included from
...llvm\offload\plugins-nextgen\common\src\RPC.cpp:16:
...\llvm\libc\shared\rpc.h(48,3): error: expected identifier
48 | ERROR = 0x1000,
| ^
c:\Program files (x86)\Windows
Kits\10\include\10.0.22000.0\um\wingdi.h(118,29): note: expanded from
macro 'ERROR'
118 | #define ERROR 0
| ^
...\llvm\offload\plugins-nextgen\common\src\RPC.cpp(75,17): error:
expected unqualified-id
75 | return rpc::ERROR;
| ^
c:\Program files (x86)\Windows
Kits\10\include\10.0.22000.0\um\wingdi.h(118,29): note: expanded from
macro 'ERROR'
118 | #define ERROR 0
| ^
2 errors generated.
Commit: 6c98f70b30408916de6ad5cb82081ca7d9b1c39e
https://github.com/llvm/llvm-project/commit/6c98f70b30408916de6ad5cb82081ca7d9b1c39e
Author: Florian Hahn <flo at fhahn.com>
Date: 2024-12-15 (Sun, 15 Dec 2024)
Changed paths:
M llvm/test/Transforms/LoopVectorize/preserve-dbg-loc-and-loop-metadata.ll
Log Message:
-----------
[LV] Add test with missing debug location for pointer IV in vector loop.
Commit: 2067e604a49d49ce054d61a0109ec12a724e3db2
https://github.com/llvm/llvm-project/commit/2067e604a49d49ce054d61a0109ec12a724e3db2
Author: Florian Hahn <flo at fhahn.com>
Date: 2024-12-15 (Sun, 15 Dec 2024)
Changed paths:
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
M llvm/lib/Transforms/Vectorize/VPlan.h
M llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
M llvm/test/Transforms/LoopVectorize/preserve-dbg-loc-and-loop-metadata.ll
Log Message:
-----------
[VPlan] Manage VPWidenPointerInduction debug location via recipe.
Update VPWidenPointerInduction to manage its debug location via recipe.
This makes sure we emit a proper debug location for
VPWidenPointerInductionRecipes.
Commit: 49a5ad8e5714fd404210279303acc97b495d66d0
https://github.com/llvm/llvm-project/commit/49a5ad8e5714fd404210279303acc97b495d66d0
Author: Malte Dehling <mdehling at gmail.com>
Date: 2024-12-15 (Sun, 15 Dec 2024)
Changed paths:
M mlir/docs/Dialects/Transform.md
Log Message:
-----------
[mlir] Add DLTI transform ops section (#118153)
Adds missing _DLTI Transform Operations_ section to the transform
dialect documentation.
Co-authored-by: Malte Dehling <m.dehling at samsung.com>
Commit: b0746c68629c26567cd123d8f9b28e796ef26f47
https://github.com/llvm/llvm-project/commit/b0746c68629c26567cd123d8f9b28e796ef26f47
Author: Kazu Hirata <kazu at google.com>
Date: 2024-12-15 (Sun, 15 Dec 2024)
Changed paths:
M mlir/tools/mlir-tblgen/OpDefinitionsGen.cpp
M mlir/tools/mlir-tblgen/OpPythonBindingGen.cpp
M mlir/tools/mlir-tblgen/RewriterGen.cpp
M mlir/tools/mlir-tblgen/SPIRVUtilsGen.cpp
Log Message:
-----------
[mlir-tblgen] Migrate away from PointerUnion::{is,get} (NFC) (#119994)
Note that PointerUnion::{is,get} have been soft deprecated in
PointerUnion.h:
// FIXME: Replace the uses of is(), get() and dyn_cast() with
// isa<T>, cast<T> and the llvm::dyn_cast<T>
I'm not touching PointerUnion::dyn_cast for now because it's a bit
complicated; we could blindly migrate it to dyn_cast_if_present, but
we should probably use dyn_cast when the operand is known to be
non-null.
Commit: a22578d38c773b3969fc02f80ffd7042dc4ad3e3
https://github.com/llvm/llvm-project/commit/a22578d38c773b3969fc02f80ffd7042dc4ad3e3
Author: Ramkumar Ramachandra <ramkumar.ramachandra at codasip.com>
Date: 2024-12-15 (Sun, 15 Dec 2024)
Changed paths:
M llvm/lib/Transforms/Scalar/ConstraintElimination.cpp
A llvm/test/Transforms/ConstraintElimination/transfer-samesign-facts.ll
Log Message:
-----------
ConstraintElim: teach fact-transfer about samesign (#115893)
When the samesign flag is present on an icmp, we can transfer all the
facts on the unsigned system to the signed system, and vice-versa: we do
this by specializing transferToOtherSystem when samesign is present.
Commit: 0a9810d32599e515236940ce15631cfa8586d403
https://github.com/llvm/llvm-project/commit/0a9810d32599e515236940ce15631cfa8586d403
Author: Jacek Caban <jacek at codeweavers.com>
Date: 2024-12-15 (Sun, 15 Dec 2024)
Changed paths:
M lld/COFF/Driver.cpp
M lld/COFF/Driver.h
M lld/COFF/SymbolTable.cpp
Log Message:
-----------
[LLD][COFF] Factor out LinkerDriver::setMachine (NFC) (#119297)
Commit: d3c485717979add739b90c82b7bc79a1e57f3cd2
https://github.com/llvm/llvm-project/commit/d3c485717979add739b90c82b7bc79a1e57f3cd2
Author: Jacek Caban <jacek at codeweavers.com>
Date: 2024-12-15 (Sun, 15 Dec 2024)
Changed paths:
M lld/COFF/DLL.cpp
M lld/COFF/Driver.cpp
M lld/COFF/InputFiles.cpp
M lld/COFF/SymbolTable.cpp
M lld/COFF/SymbolTable.h
Log Message:
-----------
[LLD][COFF] Store machine type in SymbolTable (NFC) (#119298)
This change prepares for hybrid ARM64X support, which requires two
`SymbolTable` instances: one for native symbols and one for EC symbols.
In such cases, `config.machine` will remain ARM64X, while the
`SymbolTable` instances will store ARM64 and ARM64EC machine types.
Commit: a8206e7b37929f4754806667680ffba0206eef95
https://github.com/llvm/llvm-project/commit/a8206e7b37929f4754806667680ffba0206eef95
Author: Jacek Caban <jacek at codeweavers.com>
Date: 2024-12-15 (Sun, 15 Dec 2024)
Changed paths:
M lld/COFF/COFFLinkerContext.h
M lld/COFF/Driver.cpp
M lld/COFF/InputFiles.cpp
M lld/COFF/InputFiles.h
M lld/COFF/SymbolTable.h
M lld/test/COFF/arm64ec-codemap.test
M lld/test/COFF/arm64ec-entry-thunk.s
M lld/test/COFF/arm64ec-lib.test
M lld/test/COFF/arm64ec-range-thunks.s
A lld/test/COFF/arm64x-symtab.s
Log Message:
-----------
[LLD][COFF] Introduce hybrid symbol table for EC input files on ARM64X (#119294)
On hybrid ARM64X targets, ARM64 and ARM64EC input files operate in
separate namespaces and cannot reference each other. This change
introduces separate `SymbolTable` instances and associates each
`InputFile` with the appropriate table to reflect this behavior.
Commit: 6a865b6d3d44e53adc9342fb2d80a604f5459707
https://github.com/llvm/llvm-project/commit/6a865b6d3d44e53adc9342fb2d80a604f5459707
Author: wldfngrs <wldfngrs at gmail.com>
Date: 2024-12-15 (Sun, 15 Dec 2024)
Changed paths:
M libc/config/linux/x86_64/entrypoints.txt
M libc/docs/headers/math/index.rst
M libc/hdrgen/yaml/math.yaml
M libc/src/math/CMakeLists.txt
A libc/src/math/cosf16.h
M libc/src/math/generic/CMakeLists.txt
A libc/src/math/generic/cosf16.cpp
M libc/src/math/generic/cospif16.cpp
M libc/src/math/generic/sinf16.cpp
M libc/test/src/math/CMakeLists.txt
A libc/test/src/math/cosf16_test.cpp
M libc/test/src/math/smoke/CMakeLists.txt
A libc/test/src/math/smoke/cosf16_test.cpp
Log Message:
-----------
[libc][math][c23] Add cosf16 function (#118785)
Commit: 171056ff5778c40df916c5a4cea84ea6320b965f
https://github.com/llvm/llvm-project/commit/171056ff5778c40df916c5a4cea84ea6320b965f
Author: Fangrui Song <i at maskray.me>
Date: 2024-12-15 (Sun, 15 Dec 2024)
Changed paths:
M llvm/test/CodeGen/M68k/GlobalISel/legalize-add.mir
M llvm/test/CodeGen/M68k/GlobalISel/legalize-and.mir
M llvm/test/CodeGen/M68k/GlobalISel/legalize-load-store.mir
M llvm/test/CodeGen/M68k/GlobalISel/legalize-mul.mir
M llvm/test/CodeGen/M68k/GlobalISel/legalize-sub.mir
M llvm/test/CodeGen/M68k/GlobalISel/legalize-udiv.mir
M llvm/test/CodeGen/MSP430/2009-05-17-Rot.ll
M llvm/test/CodeGen/MSP430/2009-05-17-Shift.ll
M llvm/test/CodeGen/MSP430/2009-05-19-DoubleSplit.ll
M llvm/test/CodeGen/MSP430/2009-10-10-OrImpDef.ll
M llvm/test/CodeGen/MSP430/2009-11-20-NewNode.ll
M llvm/test/CodeGen/MSP430/AddrMode-bis-rx.ll
M llvm/test/CodeGen/MSP430/AddrMode-bis-xr.ll
M llvm/test/CodeGen/MSP430/AddrMode-mov-rx.ll
M llvm/test/CodeGen/MSP430/AddrMode-mov-xr.ll
M llvm/test/CodeGen/MSP430/BranchSelector.ll
M llvm/test/CodeGen/MSP430/DbgValueOtherTargets.test
M llvm/test/CodeGen/MSP430/Inst16mi.ll
M llvm/test/CodeGen/MSP430/Inst16mm.ll
M llvm/test/CodeGen/MSP430/Inst16mr.ll
M llvm/test/CodeGen/MSP430/Inst16ri.ll
M llvm/test/CodeGen/MSP430/Inst16rm.ll
M llvm/test/CodeGen/MSP430/Inst16rr.ll
M llvm/test/CodeGen/MSP430/Inst8mi.ll
M llvm/test/CodeGen/MSP430/Inst8mm.ll
M llvm/test/CodeGen/MSP430/Inst8mr.ll
M llvm/test/CodeGen/MSP430/Inst8ri.ll
M llvm/test/CodeGen/MSP430/Inst8rm.ll
M llvm/test/CodeGen/MSP430/Inst8rr.ll
M llvm/test/CodeGen/MSP430/InstII.ll
M llvm/test/CodeGen/MSP430/bit.ll
M llvm/test/CodeGen/MSP430/flt_rounds.ll
M llvm/test/CodeGen/MSP430/indirectbr.ll
M llvm/test/CodeGen/MSP430/indirectbr2.ll
M llvm/test/CodeGen/MSP430/mult-alt-generic-msp430.ll
M llvm/test/CodeGen/MSP430/select-use-sr.ll
M llvm/test/CodeGen/MSP430/setcc.ll
M llvm/test/CodeGen/MSP430/spill-to-stack.ll
M llvm/test/CodeGen/MSP430/stacksave_restore.ll
M llvm/test/CodeGen/MSP430/umulo-16.ll
Log Message:
-----------
[M68k,MSP430,test] Change llc -march= to -mtriple=
Similar to 806761a7629df268c8aed49657aeccffa6bca449
Commit: 2208c97c1bec2512d4e47b6223db6d95a7037956
https://github.com/llvm/llvm-project/commit/2208c97c1bec2512d4e47b6223db6d95a7037956
Author: Fangrui Song <i at maskray.me>
Date: 2024-12-15 (Sun, 15 Dec 2024)
Changed paths:
M llvm/test/CodeGen/Hexagon/64bit_tstbit.ll
M llvm/test/CodeGen/Hexagon/Atomics.ll
M llvm/test/CodeGen/Hexagon/BranchPredict.ll
M llvm/test/CodeGen/Hexagon/Halide_vec_cast_trunc1.ll
M llvm/test/CodeGen/Hexagon/Halide_vec_cast_trunc2.ll
M llvm/test/CodeGen/Hexagon/M4_mpyri_addi_global.ll
M llvm/test/CodeGen/Hexagon/M4_mpyrr_addi_global.ll
M llvm/test/CodeGen/Hexagon/NVJumpCmp.ll
M llvm/test/CodeGen/Hexagon/P08214.ll
M llvm/test/CodeGen/Hexagon/PR33749.ll
M llvm/test/CodeGen/Hexagon/SUnit-boundary-prob.ll
M llvm/test/CodeGen/Hexagon/V60-VDblNew.ll
M llvm/test/CodeGen/Hexagon/abi-padding-2.ll
M llvm/test/CodeGen/Hexagon/abi-padding.ll
M llvm/test/CodeGen/Hexagon/abs.ll
M llvm/test/CodeGen/Hexagon/absaddr-store.ll
M llvm/test/CodeGen/Hexagon/absimm.ll
M llvm/test/CodeGen/Hexagon/add-use.ll
M llvm/test/CodeGen/Hexagon/add_int_double.ll
M llvm/test/CodeGen/Hexagon/add_mpi_RRR.ll
M llvm/test/CodeGen/Hexagon/addaddi.ll
M llvm/test/CodeGen/Hexagon/addasl-address.ll
M llvm/test/CodeGen/Hexagon/addh-sext-trunc.ll
M llvm/test/CodeGen/Hexagon/addh-shifted.ll
M llvm/test/CodeGen/Hexagon/addh.ll
M llvm/test/CodeGen/Hexagon/addr-calc-opt.ll
M llvm/test/CodeGen/Hexagon/addr-mode-opt.ll
M llvm/test/CodeGen/Hexagon/addrmode-align.ll
M llvm/test/CodeGen/Hexagon/addrmode-globoff.mir
M llvm/test/CodeGen/Hexagon/addrmode-immop.mir
M llvm/test/CodeGen/Hexagon/addrmode-indoff.ll
M llvm/test/CodeGen/Hexagon/addrmode-keepdeadphis.ll
M llvm/test/CodeGen/Hexagon/addrmode-keepdeadphis.mir
M llvm/test/CodeGen/Hexagon/addrmode-no-rdef.mir
M llvm/test/CodeGen/Hexagon/addrmode-offset.ll
M llvm/test/CodeGen/Hexagon/addrmode-opt-assert.mir
M llvm/test/CodeGen/Hexagon/addrmode-rr-to-io.mir
M llvm/test/CodeGen/Hexagon/addsubcarry.ll
M llvm/test/CodeGen/Hexagon/adjust-latency-stackST.ll
M llvm/test/CodeGen/Hexagon/aggr-antidep-tied.ll
M llvm/test/CodeGen/Hexagon/aggr-copy-order.ll
M llvm/test/CodeGen/Hexagon/aggr-licm.ll
M llvm/test/CodeGen/Hexagon/aggressive_licm.ll
M llvm/test/CodeGen/Hexagon/align_Os.ll
M llvm/test/CodeGen/Hexagon/align_test.ll
M llvm/test/CodeGen/Hexagon/alu64.ll
M llvm/test/CodeGen/Hexagon/always-ext.ll
M llvm/test/CodeGen/Hexagon/anti-dep-partial.mir
M llvm/test/CodeGen/Hexagon/args.ll
M llvm/test/CodeGen/Hexagon/ashift-left-right.ll
M llvm/test/CodeGen/Hexagon/asr-rnd.ll
M llvm/test/CodeGen/Hexagon/asr-rnd64.ll
M llvm/test/CodeGen/Hexagon/assert-postinc-ptr-not-value.ll
M llvm/test/CodeGen/Hexagon/atomic-opaque-basic.ll
M llvm/test/CodeGen/Hexagon/atomic-rmw-add.ll
M llvm/test/CodeGen/Hexagon/atomicrmw-cond-sub-clamp.ll
M llvm/test/CodeGen/Hexagon/atomicrmw-uinc-udec-wrap.ll
M llvm/test/CodeGen/Hexagon/autohvx/abs.ll
M llvm/test/CodeGen/Hexagon/autohvx/addi-offset-opt-addr-mode.ll
M llvm/test/CodeGen/Hexagon/autohvx/addi-opt-predicated-def-bug.ll
M llvm/test/CodeGen/Hexagon/autohvx/align-128b.ll
M llvm/test/CodeGen/Hexagon/autohvx/align-64b.ll
M llvm/test/CodeGen/Hexagon/autohvx/align2-128b.ll
M llvm/test/CodeGen/Hexagon/autohvx/align2-64b.ll
M llvm/test/CodeGen/Hexagon/autohvx/arith-float.ll
M llvm/test/CodeGen/Hexagon/autohvx/arith.ll
M llvm/test/CodeGen/Hexagon/autohvx/bitcount-128b.ll
M llvm/test/CodeGen/Hexagon/autohvx/bitcount-64b.ll
M llvm/test/CodeGen/Hexagon/autohvx/bitwise-pred-128b.ll
M llvm/test/CodeGen/Hexagon/autohvx/bitwise-pred-64b.ll
M llvm/test/CodeGen/Hexagon/autohvx/bswap.ll
M llvm/test/CodeGen/Hexagon/autohvx/build-vector-float-type.ll
M llvm/test/CodeGen/Hexagon/autohvx/build-vector-i32-128b.ll
M llvm/test/CodeGen/Hexagon/autohvx/build-vector-i32-64b.ll
M llvm/test/CodeGen/Hexagon/autohvx/build-vector-i32-type.ll
M llvm/test/CodeGen/Hexagon/autohvx/calling-conv.ll
M llvm/test/CodeGen/Hexagon/autohvx/concat-vectors-128b.ll
M llvm/test/CodeGen/Hexagon/autohvx/concat-vectors-64b.ll
M llvm/test/CodeGen/Hexagon/autohvx/contract-128b.ll
M llvm/test/CodeGen/Hexagon/autohvx/contract-64b.ll
M llvm/test/CodeGen/Hexagon/autohvx/conv-fp-fp.ll
M llvm/test/CodeGen/Hexagon/autohvx/conv-fp-int-ieee.ll
M llvm/test/CodeGen/Hexagon/autohvx/ctpop-split.ll
M llvm/test/CodeGen/Hexagon/autohvx/deal-128b.ll
M llvm/test/CodeGen/Hexagon/autohvx/deal-64b.ll
M llvm/test/CodeGen/Hexagon/autohvx/delta-128b.ll
M llvm/test/CodeGen/Hexagon/autohvx/delta-64b.ll
M llvm/test/CodeGen/Hexagon/autohvx/delta2-64b.ll
M llvm/test/CodeGen/Hexagon/autohvx/extract-element.ll
M llvm/test/CodeGen/Hexagon/autohvx/fp-to-int.ll
M llvm/test/CodeGen/Hexagon/autohvx/funnel-128b.ll
M llvm/test/CodeGen/Hexagon/autohvx/hfinsert.ll
M llvm/test/CodeGen/Hexagon/autohvx/hvx-idiom-empty-results.ll
M llvm/test/CodeGen/Hexagon/autohvx/int-to-fp.ll
M llvm/test/CodeGen/Hexagon/autohvx/isel-anyext-inreg.ll
M llvm/test/CodeGen/Hexagon/autohvx/isel-anyext-pair.ll
M llvm/test/CodeGen/Hexagon/autohvx/isel-bitcast-vsplat.ll
M llvm/test/CodeGen/Hexagon/autohvx/isel-bitcast-vsplat2.ll
M llvm/test/CodeGen/Hexagon/autohvx/isel-bool-vector.ll
M llvm/test/CodeGen/Hexagon/autohvx/isel-build-undef.ll
M llvm/test/CodeGen/Hexagon/autohvx/isel-build-vector.ll
M llvm/test/CodeGen/Hexagon/autohvx/isel-concat-multiple.ll
M llvm/test/CodeGen/Hexagon/autohvx/isel-concat-vectors-bool.ll
M llvm/test/CodeGen/Hexagon/autohvx/isel-concat-vectors.ll
M llvm/test/CodeGen/Hexagon/autohvx/isel-const-splat-bitcast.ll
M llvm/test/CodeGen/Hexagon/autohvx/isel-const-splat-imm.ll
M llvm/test/CodeGen/Hexagon/autohvx/isel-const-splat.ll
M llvm/test/CodeGen/Hexagon/autohvx/isel-const-vector.ll
M llvm/test/CodeGen/Hexagon/autohvx/isel-expand-unaligned-loads-noindexed.ll
M llvm/test/CodeGen/Hexagon/autohvx/isel-expand-unaligned-loads.ll
M llvm/test/CodeGen/Hexagon/autohvx/isel-extractelt-illegal-type.ll
M llvm/test/CodeGen/Hexagon/autohvx/isel-hvx-concat-truncate.ll
M llvm/test/CodeGen/Hexagon/autohvx/isel-hvx-pred-bitcast.ll
M llvm/test/CodeGen/Hexagon/autohvx/isel-insert-subvector-v4i8.ll
M llvm/test/CodeGen/Hexagon/autohvx/isel-intrinsics.ll
M llvm/test/CodeGen/Hexagon/autohvx/isel-mstore-fp16.ll
M llvm/test/CodeGen/Hexagon/autohvx/isel-q-legalization-loop.ll
M llvm/test/CodeGen/Hexagon/autohvx/isel-q2v-pair.ll
M llvm/test/CodeGen/Hexagon/autohvx/isel-qfalse.ll
M llvm/test/CodeGen/Hexagon/autohvx/isel-select-const.ll
M llvm/test/CodeGen/Hexagon/autohvx/isel-select-q.ll
M llvm/test/CodeGen/Hexagon/autohvx/isel-setcc-pair-fp.ll
M llvm/test/CodeGen/Hexagon/autohvx/isel-setcc-pair.ll
M llvm/test/CodeGen/Hexagon/autohvx/isel-setcc-v256i1.ll
M llvm/test/CodeGen/Hexagon/autohvx/isel-sext-inreg.ll
M llvm/test/CodeGen/Hexagon/autohvx/isel-shift-byte.ll
M llvm/test/CodeGen/Hexagon/autohvx/isel-shuff-single.ll
M llvm/test/CodeGen/Hexagon/autohvx/isel-shuffle-gather.ll
M llvm/test/CodeGen/Hexagon/autohvx/isel-shuffle-isdisel.ll
M llvm/test/CodeGen/Hexagon/autohvx/isel-shuffle-no-perfect-completion.ll
M llvm/test/CodeGen/Hexagon/autohvx/isel-shuffle-pack.ll
M llvm/test/CodeGen/Hexagon/autohvx/isel-split-masked.ll
M llvm/test/CodeGen/Hexagon/autohvx/isel-store-bitcast-v128i1.ll
M llvm/test/CodeGen/Hexagon/autohvx/isel-truncate-legal.ll
M llvm/test/CodeGen/Hexagon/autohvx/isel-truncate.ll
M llvm/test/CodeGen/Hexagon/autohvx/isel-undef-not-zero.ll
M llvm/test/CodeGen/Hexagon/autohvx/isel-vec-ext.ll
M llvm/test/CodeGen/Hexagon/autohvx/isel-vpackew.ll
M llvm/test/CodeGen/Hexagon/autohvx/isel-vsplat-pair.ll
M llvm/test/CodeGen/Hexagon/autohvx/isel-widen-memop.ll
M llvm/test/CodeGen/Hexagon/autohvx/isel-widen-store.ll
M llvm/test/CodeGen/Hexagon/autohvx/isel-widen-truncate-illegal-elem.ll
M llvm/test/CodeGen/Hexagon/autohvx/isel-widen-truncate-op.ll
M llvm/test/CodeGen/Hexagon/autohvx/isel-widen-truncate-pair.ll
M llvm/test/CodeGen/Hexagon/autohvx/isel-widen-truncate.ll
M llvm/test/CodeGen/Hexagon/autohvx/logical-128b.ll
M llvm/test/CodeGen/Hexagon/autohvx/logical-64b.ll
M llvm/test/CodeGen/Hexagon/autohvx/lower-insert-elt.ll
M llvm/test/CodeGen/Hexagon/autohvx/masked-vmem-basic.ll
M llvm/test/CodeGen/Hexagon/autohvx/minmax-128b.ll
M llvm/test/CodeGen/Hexagon/autohvx/minmax-64b.ll
M llvm/test/CodeGen/Hexagon/autohvx/minmax-float.ll
M llvm/test/CodeGen/Hexagon/autohvx/mulh.ll
M llvm/test/CodeGen/Hexagon/autohvx/non-simple-hvx-type.ll
M llvm/test/CodeGen/Hexagon/autohvx/perfect-single.ll
M llvm/test/CodeGen/Hexagon/autohvx/pred-vmem-128b.ll
M llvm/test/CodeGen/Hexagon/autohvx/pred-vmem-64b.ll
M llvm/test/CodeGen/Hexagon/autohvx/qmul-add-over-32-bit.ll
M llvm/test/CodeGen/Hexagon/autohvx/qmul-chop.ll
M llvm/test/CodeGen/Hexagon/autohvx/qmul.ll
M llvm/test/CodeGen/Hexagon/autohvx/reg-sequence.ll
M llvm/test/CodeGen/Hexagon/autohvx/shift-128b.ll
M llvm/test/CodeGen/Hexagon/autohvx/shift-64b.ll
M llvm/test/CodeGen/Hexagon/autohvx/shuff-128b.ll
M llvm/test/CodeGen/Hexagon/autohvx/shuff-64b.ll
M llvm/test/CodeGen/Hexagon/autohvx/shuff-combos-128b.ll
M llvm/test/CodeGen/Hexagon/autohvx/shuff-combos-64b.ll
M llvm/test/CodeGen/Hexagon/autohvx/shuff-perfect-inverted-pair.ll
M llvm/test/CodeGen/Hexagon/autohvx/shuff-single.ll
M llvm/test/CodeGen/Hexagon/autohvx/shuffle-expanding-128b.ll
M llvm/test/CodeGen/Hexagon/autohvx/shuffle-expanding-64b.ll
M llvm/test/CodeGen/Hexagon/autohvx/shuffle-half-128b.ll
M llvm/test/CodeGen/Hexagon/autohvx/shuffle-half-64b.ll
M llvm/test/CodeGen/Hexagon/autohvx/splat.ll
M llvm/test/CodeGen/Hexagon/autohvx/vdd0.ll
M llvm/test/CodeGen/Hexagon/autohvx/vector-align-addr.ll
M llvm/test/CodeGen/Hexagon/autohvx/vector-align-bad-move.ll
M llvm/test/CodeGen/Hexagon/autohvx/vector-align-bad-move3.ll
M llvm/test/CodeGen/Hexagon/autohvx/vector-align-base-type-mismatch.ll
M llvm/test/CodeGen/Hexagon/autohvx/vector-align-basic.ll
M llvm/test/CodeGen/Hexagon/autohvx/vector-align-interleaved.ll
M llvm/test/CodeGen/Hexagon/autohvx/vector-align-only-phi-use.ll
M llvm/test/CodeGen/Hexagon/autohvx/vector-align-order.ll
M llvm/test/CodeGen/Hexagon/autohvx/vector-align-rescale-nonint.ll
M llvm/test/CodeGen/Hexagon/autohvx/vector-align-scalar-mask.ll
M llvm/test/CodeGen/Hexagon/autohvx/vector-align-store-mask.ll
M llvm/test/CodeGen/Hexagon/autohvx/vector-align-store.ll
M llvm/test/CodeGen/Hexagon/autohvx/vector-align-terminator.ll
M llvm/test/CodeGen/Hexagon/autohvx/vector-align-use-in-different-block.ll
M llvm/test/CodeGen/Hexagon/autohvx/vector-compare-128b.ll
M llvm/test/CodeGen/Hexagon/autohvx/vector-compare-64b.ll
M llvm/test/CodeGen/Hexagon/autohvx/vector-compare-float.ll
M llvm/test/CodeGen/Hexagon/autohvx/vector-load-store-basic.ll
M llvm/test/CodeGen/Hexagon/autohvx/vector-predicate-typecast.ll
M llvm/test/CodeGen/Hexagon/autohvx/vext-128b.ll
M llvm/test/CodeGen/Hexagon/autohvx/vext-64b.ll
M llvm/test/CodeGen/Hexagon/autohvx/vmpy-parts.ll
M llvm/test/CodeGen/Hexagon/autohvx/vmux-order.ll
M llvm/test/CodeGen/Hexagon/autohvx/widen-ext.ll
M llvm/test/CodeGen/Hexagon/autohvx/widen-setcc.ll
M llvm/test/CodeGen/Hexagon/autohvx/widen-trunc.ll
M llvm/test/CodeGen/Hexagon/avoid-predspill-calleesaved.ll
M llvm/test/CodeGen/Hexagon/avoid-predspill.ll
M llvm/test/CodeGen/Hexagon/avoidVectorLowering.ll
M llvm/test/CodeGen/Hexagon/bank-conflict-load.mir
M llvm/test/CodeGen/Hexagon/bank-conflict.mir
M llvm/test/CodeGen/Hexagon/barrier-flag.ll
M llvm/test/CodeGen/Hexagon/base-offset-addr.ll
M llvm/test/CodeGen/Hexagon/base-offset-post.ll
M llvm/test/CodeGen/Hexagon/base-offset-stv4.ll
M llvm/test/CodeGen/Hexagon/bit-addr-align.mir
M llvm/test/CodeGen/Hexagon/bit-bitsplit-at.ll
M llvm/test/CodeGen/Hexagon/bit-bitsplit-regclass.ll
M llvm/test/CodeGen/Hexagon/bit-bitsplit-src.ll
M llvm/test/CodeGen/Hexagon/bit-bitsplit.ll
M llvm/test/CodeGen/Hexagon/bit-cmp0.mir
M llvm/test/CodeGen/Hexagon/bit-eval.ll
M llvm/test/CodeGen/Hexagon/bit-ext-sat.ll
M llvm/test/CodeGen/Hexagon/bit-extract-off.ll
M llvm/test/CodeGen/Hexagon/bit-extract.ll
M llvm/test/CodeGen/Hexagon/bit-extractu-half.ll
M llvm/test/CodeGen/Hexagon/bit-gen-rseq.ll
M llvm/test/CodeGen/Hexagon/bit-has.ll
M llvm/test/CodeGen/Hexagon/bit-loop-rc-mismatch.ll
M llvm/test/CodeGen/Hexagon/bit-loop.ll
M llvm/test/CodeGen/Hexagon/bit-phi.ll
M llvm/test/CodeGen/Hexagon/bit-rie.ll
M llvm/test/CodeGen/Hexagon/bit-skip-byval.ll
M llvm/test/CodeGen/Hexagon/bit-store-upper-sub-hi.mir
M llvm/test/CodeGen/Hexagon/bit-validate-reg.ll
M llvm/test/CodeGen/Hexagon/bit-visit-flowq.ll
M llvm/test/CodeGen/Hexagon/bitcast-i128-to-v128i1.ll
M llvm/test/CodeGen/Hexagon/bitconvert-vector.ll
M llvm/test/CodeGen/Hexagon/bitmanip.ll
M llvm/test/CodeGen/Hexagon/bkfir.ll
M llvm/test/CodeGen/Hexagon/block-addr.ll
M llvm/test/CodeGen/Hexagon/block-address.ll
M llvm/test/CodeGen/Hexagon/block-ranges-nodef.ll
M llvm/test/CodeGen/Hexagon/blockaddr-fpic.ll
M llvm/test/CodeGen/Hexagon/branch-folder-hoist-kills.mir
M llvm/test/CodeGen/Hexagon/branch-non-mbb.ll
M llvm/test/CodeGen/Hexagon/branchfolder-insert-impdef.mir
M llvm/test/CodeGen/Hexagon/branchfolder-keep-impdef.ll
M llvm/test/CodeGen/Hexagon/brcond-setne.ll
M llvm/test/CodeGen/Hexagon/brev_ld.ll
M llvm/test/CodeGen/Hexagon/brev_st.ll
M llvm/test/CodeGen/Hexagon/bss-local.ll
M llvm/test/CodeGen/Hexagon/bug-aa4463-ifconv-vecpred.ll
M llvm/test/CodeGen/Hexagon/bug-allocframe-size.ll
M llvm/test/CodeGen/Hexagon/bug-hcp-tied-kill.ll
M llvm/test/CodeGen/Hexagon/bug14859-iv-cleanup-lpad.ll
M llvm/test/CodeGen/Hexagon/bug14859-split-const-block-addr.ll
M llvm/test/CodeGen/Hexagon/bug17276.ll
M llvm/test/CodeGen/Hexagon/bug17386.ll
M llvm/test/CodeGen/Hexagon/bug18008.ll
M llvm/test/CodeGen/Hexagon/bug18491-optsize.ll
M llvm/test/CodeGen/Hexagon/bug19076.ll
M llvm/test/CodeGen/Hexagon/bug19119.ll
M llvm/test/CodeGen/Hexagon/bug19254-ifconv-vec.ll
M llvm/test/CodeGen/Hexagon/bug27085.ll
M llvm/test/CodeGen/Hexagon/bug31839.ll
M llvm/test/CodeGen/Hexagon/bug6757-endloop.ll
M llvm/test/CodeGen/Hexagon/bug9049.ll
M llvm/test/CodeGen/Hexagon/bug9963.ll
M llvm/test/CodeGen/Hexagon/bugAsmHWloop.ll
M llvm/test/CodeGen/Hexagon/build-vector-shuffle.ll
M llvm/test/CodeGen/Hexagon/build-vector-v4i8-zext.ll
M llvm/test/CodeGen/Hexagon/builtin-expect.ll
M llvm/test/CodeGen/Hexagon/builtin-prefetch-offset.ll
M llvm/test/CodeGen/Hexagon/builtin-prefetch.ll
M llvm/test/CodeGen/Hexagon/call-long1.ll
M llvm/test/CodeGen/Hexagon/call-ret-i1.ll
M llvm/test/CodeGen/Hexagon/call-v4.ll
M llvm/test/CodeGen/Hexagon/callR_noreturn.ll
M llvm/test/CodeGen/Hexagon/calling-conv-2.ll
M llvm/test/CodeGen/Hexagon/calling-conv.ll
M llvm/test/CodeGen/Hexagon/callr-dep-edge.ll
M llvm/test/CodeGen/Hexagon/cext-check.ll
M llvm/test/CodeGen/Hexagon/cext-ice.ll
M llvm/test/CodeGen/Hexagon/cext-opt-basic.mir
M llvm/test/CodeGen/Hexagon/cext-opt-block-addr.mir
M llvm/test/CodeGen/Hexagon/cext-opt-negative-fi.mir
M llvm/test/CodeGen/Hexagon/cext-opt-numops.mir
M llvm/test/CodeGen/Hexagon/cext-opt-range-assert.mir
M llvm/test/CodeGen/Hexagon/cext-opt-range-offset.mir
M llvm/test/CodeGen/Hexagon/cext-opt-shifted-range.mir
M llvm/test/CodeGen/Hexagon/cext-opt-stack-no-rr.mir
M llvm/test/CodeGen/Hexagon/cext-unnamed-global.mir
M llvm/test/CodeGen/Hexagon/cext-valid-packet1.ll
M llvm/test/CodeGen/Hexagon/cext-valid-packet2.ll
M llvm/test/CodeGen/Hexagon/cext.ll
M llvm/test/CodeGen/Hexagon/cexti16.ll
M llvm/test/CodeGen/Hexagon/cfgopt-fall-through.ll
M llvm/test/CodeGen/Hexagon/cfi-late-and-regpressure-init.ll
M llvm/test/CodeGen/Hexagon/cfi-late.ll
M llvm/test/CodeGen/Hexagon/cfi-offset.ll
M llvm/test/CodeGen/Hexagon/cfi_offset.ll
M llvm/test/CodeGen/Hexagon/cfi_offset2.ll
M llvm/test/CodeGen/Hexagon/check-dot-new.ll
M llvm/test/CodeGen/Hexagon/check-subregister-for-latency.ll
M llvm/test/CodeGen/Hexagon/checktabs.ll
M llvm/test/CodeGen/Hexagon/circ-load-isel.ll
M llvm/test/CodeGen/Hexagon/circ_ld.ll
M llvm/test/CodeGen/Hexagon/circ_ldd_bug.ll
M llvm/test/CodeGen/Hexagon/circ_ldw.ll
M llvm/test/CodeGen/Hexagon/circ_new.ll
M llvm/test/CodeGen/Hexagon/circ_pcr_assert.ll
M llvm/test/CodeGen/Hexagon/circ_st.ll
M llvm/test/CodeGen/Hexagon/clr_set_toggle.ll
M llvm/test/CodeGen/Hexagon/cmp-extend.ll
M llvm/test/CodeGen/Hexagon/cmp-promote.ll
M llvm/test/CodeGen/Hexagon/cmp-to-genreg.ll
M llvm/test/CodeGen/Hexagon/cmp-to-predreg.ll
M llvm/test/CodeGen/Hexagon/cmp_pred.ll
M llvm/test/CodeGen/Hexagon/cmp_pred2.ll
M llvm/test/CodeGen/Hexagon/cmp_pred_reg.ll
M llvm/test/CodeGen/Hexagon/cmpb-dec-imm.ll
M llvm/test/CodeGen/Hexagon/cmpb-eq.ll
M llvm/test/CodeGen/Hexagon/cmpb_gtu.ll
M llvm/test/CodeGen/Hexagon/cmpb_pred.ll
M llvm/test/CodeGen/Hexagon/cmpbeq.ll
M llvm/test/CodeGen/Hexagon/cmph-gtu.ll
M llvm/test/CodeGen/Hexagon/cmpy-round.ll
M llvm/test/CodeGen/Hexagon/coalesce_tfri.ll
M llvm/test/CodeGen/Hexagon/coalescing-hvx-across-calls.ll
M llvm/test/CodeGen/Hexagon/combine-imm-ext.ll
M llvm/test/CodeGen/Hexagon/combine-imm-ext2.ll
M llvm/test/CodeGen/Hexagon/combine.ll
M llvm/test/CodeGen/Hexagon/combine_ir.ll
M llvm/test/CodeGen/Hexagon/combine_lh.ll
M llvm/test/CodeGen/Hexagon/combiner-lts.ll
M llvm/test/CodeGen/Hexagon/common-gep-basic.ll
M llvm/test/CodeGen/Hexagon/common-gep-icm.ll
M llvm/test/CodeGen/Hexagon/common-gep-inbounds.ll
M llvm/test/CodeGen/Hexagon/common-global-addr.ll
M llvm/test/CodeGen/Hexagon/concat-vectors-legalize.ll
M llvm/test/CodeGen/Hexagon/const-combine.ll
M llvm/test/CodeGen/Hexagon/const-pool-tf.ll
M llvm/test/CodeGen/Hexagon/constant_compound.ll
M llvm/test/CodeGen/Hexagon/constext-call.ll
M llvm/test/CodeGen/Hexagon/constext-immstore.ll
M llvm/test/CodeGen/Hexagon/constext-replace.ll
M llvm/test/CodeGen/Hexagon/constp-andir-global.mir
M llvm/test/CodeGen/Hexagon/constp-clb.ll
M llvm/test/CodeGen/Hexagon/constp-combine-neg.ll
M llvm/test/CodeGen/Hexagon/constp-ctb.ll
M llvm/test/CodeGen/Hexagon/constp-extract.ll
M llvm/test/CodeGen/Hexagon/constp-rewrite-branches.ll
M llvm/test/CodeGen/Hexagon/constp-rseq.ll
M llvm/test/CodeGen/Hexagon/constp-vsplat.ll
M llvm/test/CodeGen/Hexagon/convert_const_i1_to_i8.ll
M llvm/test/CodeGen/Hexagon/convertdptoint.ll
M llvm/test/CodeGen/Hexagon/convertdptoll.ll
M llvm/test/CodeGen/Hexagon/convertsptoint.ll
M llvm/test/CodeGen/Hexagon/convertsptoll.ll
M llvm/test/CodeGen/Hexagon/copy-to-combine-const64.mir
M llvm/test/CodeGen/Hexagon/copy-to-combine-dbg.ll
M llvm/test/CodeGen/Hexagon/count_0s.ll
M llvm/test/CodeGen/Hexagon/countbits-basic.ll
M llvm/test/CodeGen/Hexagon/csr-func-usedef.ll
M llvm/test/CodeGen/Hexagon/csr_stub_calls_dwarf_frame_info.ll
M llvm/test/CodeGen/Hexagon/ctor.ll
M llvm/test/CodeGen/Hexagon/dadd.ll
M llvm/test/CodeGen/Hexagon/dag-combine-select-or0.ll
M llvm/test/CodeGen/Hexagon/dag-indexed.ll
M llvm/test/CodeGen/Hexagon/dccleana.ll
M llvm/test/CodeGen/Hexagon/dead-store-stack.ll
M llvm/test/CodeGen/Hexagon/dealloc-store.ll
M llvm/test/CodeGen/Hexagon/dealloc_return.ll
M llvm/test/CodeGen/Hexagon/debug-line_table_start.ll
M llvm/test/CodeGen/Hexagon/debug-prologue-loc.ll
M llvm/test/CodeGen/Hexagon/debug-prologue.ll
M llvm/test/CodeGen/Hexagon/def-undef-deps.ll
M llvm/test/CodeGen/Hexagon/default-align.ll
M llvm/test/CodeGen/Hexagon/deflate.ll
M llvm/test/CodeGen/Hexagon/df-min-max.ll
M llvm/test/CodeGen/Hexagon/dfp.ll
M llvm/test/CodeGen/Hexagon/dhry.ll
M llvm/test/CodeGen/Hexagon/dhry_proc8.ll
M llvm/test/CodeGen/Hexagon/dhry_stall.ll
M llvm/test/CodeGen/Hexagon/disable-const64.ll
M llvm/test/CodeGen/Hexagon/dmul.ll
M llvm/test/CodeGen/Hexagon/dont_rotate_pregs_at_O2.ll
M llvm/test/CodeGen/Hexagon/double.ll
M llvm/test/CodeGen/Hexagon/dsub.ll
M llvm/test/CodeGen/Hexagon/duplex-addi-global-imm.mir
M llvm/test/CodeGen/Hexagon/dwarf-discriminator.ll
M llvm/test/CodeGen/Hexagon/early-if-conv-lifetime.mir
M llvm/test/CodeGen/Hexagon/early-if-conversion-bug1.ll
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M llvm/test/CodeGen/Hexagon/entryBB-isLoopHdr.ll
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M llvm/test/CodeGen/Hexagon/i16_VarArg.ll
M llvm/test/CodeGen/Hexagon/i1_VarArg.ll
M llvm/test/CodeGen/Hexagon/i8_VarArg.ll
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M llvm/test/CodeGen/Hexagon/inline-asm-i1.ll
M llvm/test/CodeGen/Hexagon/inline-asm-qv.ll
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M llvm/test/CodeGen/Hexagon/intrinsics-v66.ll
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M llvm/test/CodeGen/Hexagon/intrinsics/atomic_load.ll
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M llvm/test/CodeGen/Hexagon/intrinsics/atomicrmw_addsub_native.ll
M llvm/test/CodeGen/Hexagon/intrinsics/atomicrmw_bitwise_native.ll
M llvm/test/CodeGen/Hexagon/intrinsics/atomicrmw_nand.ll
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M llvm/test/CodeGen/Hexagon/intrinsics/cr.ll
M llvm/test/CodeGen/Hexagon/intrinsics/fence.ll
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M llvm/test/CodeGen/Hexagon/intrinsics/xtype_pred.ll
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M llvm/test/CodeGen/Hexagon/isel-extload-i1.ll
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M llvm/test/CodeGen/Hexagon/isel-hvx-pred-bitcast-order.ll
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M llvm/test/CodeGen/Hexagon/isel-insert-pred.ll
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M llvm/test/CodeGen/Hexagon/isel-prefer.ll
M llvm/test/CodeGen/Hexagon/isel-select-v4i8.ll
M llvm/test/CodeGen/Hexagon/isel-setcc-i1.ll
M llvm/test/CodeGen/Hexagon/isel-setcc-legalize-loop.ll
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M llvm/test/CodeGen/Hexagon/isel-splat-vector-crash.ll
M llvm/test/CodeGen/Hexagon/isel-splat-vector-dag-crash.ll
M llvm/test/CodeGen/Hexagon/isel-splat-vector-neg-i8.ll
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M llvm/test/CodeGen/Hexagon/isel-uaddo-1-i64.ll
M llvm/test/CodeGen/Hexagon/isel-uaddo-1.ll
M llvm/test/CodeGen/Hexagon/isel-v3i16.ll
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M llvm/test/CodeGen/Hexagon/isel-vlsr-v2i16.ll
M llvm/test/CodeGen/Hexagon/isel-vselect-v4i8.ll
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M llvm/test/CodeGen/Hexagon/isel/cmp-i1.ll
M llvm/test/CodeGen/Hexagon/isel/cmp-v2i1.ll
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M llvm/test/CodeGen/Hexagon/isel/logical.ll
M llvm/test/CodeGen/Hexagon/isel/mulh-scalar.ll
M llvm/test/CodeGen/Hexagon/isel/select-i1.ll
M llvm/test/CodeGen/Hexagon/isel/select-vec.ll
M llvm/test/CodeGen/Hexagon/isel/trunc-vNi1.ll
M llvm/test/CodeGen/Hexagon/jump-prob.ll
M llvm/test/CodeGen/Hexagon/jump-table-g0.ll
M llvm/test/CodeGen/Hexagon/jump-table-isel.ll
M llvm/test/CodeGen/Hexagon/large-number-of-preds.ll
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M llvm/test/CodeGen/Hexagon/ldst_vector_offset.ll
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M llvm/test/CodeGen/Hexagon/load-const-extend-opt.ll
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M llvm/test/CodeGen/Hexagon/loadi1-G0.ll
M llvm/test/CodeGen/Hexagon/loadi1-v4-G0.ll
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M llvm/test/CodeGen/Hexagon/loop-rotate-bug.ll
M llvm/test/CodeGen/Hexagon/loop-rotate-liveins.ll
M llvm/test/CodeGen/Hexagon/loop_align_count.ll
M llvm/test/CodeGen/Hexagon/loop_align_count.mir
M llvm/test/CodeGen/Hexagon/loop_correctness.ll
M llvm/test/CodeGen/Hexagon/lower-extract-subvector.ll
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M llvm/test/CodeGen/Hexagon/lsr-post-inc-cross-use-offsets.ll
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M llvm/test/CodeGen/Hexagon/maddsubu.ll
M llvm/test/CodeGen/Hexagon/mapped_intrinsics.ll
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M llvm/test/CodeGen/Hexagon/mem-ops-sub.ll
M llvm/test/CodeGen/Hexagon/mem-ops-sub_01.ll
M llvm/test/CodeGen/Hexagon/mem-ops-sub_i16.ll
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M llvm/test/CodeGen/Hexagon/memcpy-likely-aligned.ll
M llvm/test/CodeGen/Hexagon/memcpy-memmove-inline.ll
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M llvm/test/CodeGen/Hexagon/newify-crash.ll
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M llvm/test/CodeGen/Hexagon/noFalignAfterCallAtO2.ll
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M llvm/test/CodeGen/Hexagon/v6vec-vmemcur-prob.mir
M llvm/test/CodeGen/Hexagon/v6vec-vmemu1.ll
M llvm/test/CodeGen/Hexagon/v6vec-vmemu2.ll
M llvm/test/CodeGen/Hexagon/v6vec-vprint.ll
M llvm/test/CodeGen/Hexagon/v6vec-vshuff.ll
M llvm/test/CodeGen/Hexagon/v6vec_inc1.ll
M llvm/test/CodeGen/Hexagon/v6vec_zero.ll
M llvm/test/CodeGen/Hexagon/v6vect-dbl-fail1.ll
M llvm/test/CodeGen/Hexagon/v6vect-dbl-spill.ll
M llvm/test/CodeGen/Hexagon/v6vect-dbl.ll
M llvm/test/CodeGen/Hexagon/v6vect-dh1.ll
M llvm/test/CodeGen/Hexagon/v6vect-locals1.ll
M llvm/test/CodeGen/Hexagon/v6vect-no-sideeffects.ll
M llvm/test/CodeGen/Hexagon/v6vect-pred2.ll
M llvm/test/CodeGen/Hexagon/v6vect-spill-kill.ll
M llvm/test/CodeGen/Hexagon/v6vect-vmem1.ll
M llvm/test/CodeGen/Hexagon/v6vect-vsplat.ll
M llvm/test/CodeGen/Hexagon/vacopy.ll
M llvm/test/CodeGen/Hexagon/vadd1.ll
M llvm/test/CodeGen/Hexagon/vaddh.ll
M llvm/test/CodeGen/Hexagon/validate-offset.ll
M llvm/test/CodeGen/Hexagon/vararg-deallocate-sp.ll
M llvm/test/CodeGen/Hexagon/vararg-formal.ll
M llvm/test/CodeGen/Hexagon/vararg-linux-abi.ll
M llvm/test/CodeGen/Hexagon/vararg.ll
M llvm/test/CodeGen/Hexagon/vararg_align_check.ll
M llvm/test/CodeGen/Hexagon/vararg_double_onstack.ll
M llvm/test/CodeGen/Hexagon/vararg_named.ll
M llvm/test/CodeGen/Hexagon/varargs-memv.ll
M llvm/test/CodeGen/Hexagon/vassign-to-combine.ll
M llvm/test/CodeGen/Hexagon/vcombine128_to_req_seq.ll
M llvm/test/CodeGen/Hexagon/vcombine_subreg.ll
M llvm/test/CodeGen/Hexagon/vcombine_to_req_seq.ll
M llvm/test/CodeGen/Hexagon/vdmpy-halide-test.ll
M llvm/test/CodeGen/Hexagon/vdotprod.ll
M llvm/test/CodeGen/Hexagon/vec-align.ll
M llvm/test/CodeGen/Hexagon/vec-call-full1.ll
M llvm/test/CodeGen/Hexagon/vec-pred-spill1.ll
M llvm/test/CodeGen/Hexagon/vec-vararg-align.ll
M llvm/test/CodeGen/Hexagon/vecPred2Vec.ll
M llvm/test/CodeGen/Hexagon/vect-any_extend.ll
M llvm/test/CodeGen/Hexagon/vect-dbl-post-inc.ll
M llvm/test/CodeGen/Hexagon/vect-downscale.ll
M llvm/test/CodeGen/Hexagon/vect-set_cc_v2i32.ll
M llvm/test/CodeGen/Hexagon/vect-vd0.ll
M llvm/test/CodeGen/Hexagon/vect-zero_extend.ll
M llvm/test/CodeGen/Hexagon/vect/bit4x8.ll
M llvm/test/CodeGen/Hexagon/vect/build-vect64.ll
M llvm/test/CodeGen/Hexagon/vect/extract-elt-vNi1.ll
M llvm/test/CodeGen/Hexagon/vect/extract-v4i1.ll
M llvm/test/CodeGen/Hexagon/vect/setcc-not.ll
M llvm/test/CodeGen/Hexagon/vect/setcc-v2i32.ll
M llvm/test/CodeGen/Hexagon/vect/setcc-v32.ll
M llvm/test/CodeGen/Hexagon/vect/shuff-32.ll
M llvm/test/CodeGen/Hexagon/vect/shuff-64.ll
M llvm/test/CodeGen/Hexagon/vect/vect-anyextend.ll
M llvm/test/CodeGen/Hexagon/vect/vect-apint-truncate.ll
M llvm/test/CodeGen/Hexagon/vect/vect-bad-bitcast.ll
M llvm/test/CodeGen/Hexagon/vect/vect-bitcast-1.ll
M llvm/test/CodeGen/Hexagon/vect/vect-bitcast.ll
M llvm/test/CodeGen/Hexagon/vect/vect-bool-basic-compile.ll
M llvm/test/CodeGen/Hexagon/vect/vect-bool-isel-crash.ll
M llvm/test/CodeGen/Hexagon/vect/vect-cst-v4i32.ll
M llvm/test/CodeGen/Hexagon/vect/vect-cst-v4i8.ll
M llvm/test/CodeGen/Hexagon/vect/vect-cst.ll
M llvm/test/CodeGen/Hexagon/vect/vect-extract-i1-debug.ll
M llvm/test/CodeGen/Hexagon/vect/vect-extract-i1.ll
M llvm/test/CodeGen/Hexagon/vect/vect-extract.ll
M llvm/test/CodeGen/Hexagon/vect/vect-fma.ll
M llvm/test/CodeGen/Hexagon/vect/vect-illegal-type.ll
M llvm/test/CodeGen/Hexagon/vect/vect-infloop.ll
M llvm/test/CodeGen/Hexagon/vect/vect-insert-extract-elt.ll
M llvm/test/CodeGen/Hexagon/vect/vect-load-1.ll
M llvm/test/CodeGen/Hexagon/vect/vect-load-v4i16.ll
M llvm/test/CodeGen/Hexagon/vect/vect-load.ll
M llvm/test/CodeGen/Hexagon/vect/vect-mul-v2i16.ll
M llvm/test/CodeGen/Hexagon/vect/vect-mul-v2i32.ll
M llvm/test/CodeGen/Hexagon/vect/vect-mul-v4i16.ll
M llvm/test/CodeGen/Hexagon/vect/vect-mul-v4i8.ll
M llvm/test/CodeGen/Hexagon/vect/vect-mul-v8i8.ll
M llvm/test/CodeGen/Hexagon/vect/vect-no-tfrs-1.ll
M llvm/test/CodeGen/Hexagon/vect/vect-no-tfrs.ll
M llvm/test/CodeGen/Hexagon/vect/vect-shift-imm.ll
M llvm/test/CodeGen/Hexagon/vect/vect-shifts.ll
M llvm/test/CodeGen/Hexagon/vect/vect-shuffle.ll
M llvm/test/CodeGen/Hexagon/vect/vect-splat.ll
M llvm/test/CodeGen/Hexagon/vect/vect-store-v2i16.ll
M llvm/test/CodeGen/Hexagon/vect/vect-truncate.ll
M llvm/test/CodeGen/Hexagon/vect/vect-v4i16.ll
M llvm/test/CodeGen/Hexagon/vect/vect-vaddb-1.ll
M llvm/test/CodeGen/Hexagon/vect/vect-vaddb.ll
M llvm/test/CodeGen/Hexagon/vect/vect-vaddh-1.ll
M llvm/test/CodeGen/Hexagon/vect/vect-vaddh.ll
M llvm/test/CodeGen/Hexagon/vect/vect-vaddw.ll
M llvm/test/CodeGen/Hexagon/vect/vect-vaslw.ll
M llvm/test/CodeGen/Hexagon/vect/vect-vshifts.ll
M llvm/test/CodeGen/Hexagon/vect/vect-vsplatb.ll
M llvm/test/CodeGen/Hexagon/vect/vect-vsplath.ll
M llvm/test/CodeGen/Hexagon/vect/vect-vsubb-1.ll
M llvm/test/CodeGen/Hexagon/vect/vect-vsubb.ll
M llvm/test/CodeGen/Hexagon/vect/vect-vsubh-1.ll
M llvm/test/CodeGen/Hexagon/vect/vect-vsubh.ll
M llvm/test/CodeGen/Hexagon/vect/vect-vsubw.ll
M llvm/test/CodeGen/Hexagon/vect/vect-xor.ll
M llvm/test/CodeGen/Hexagon/vect/vect-zeroextend.ll
M llvm/test/CodeGen/Hexagon/vect/vsplat-v8i8.ll
M llvm/test/CodeGen/Hexagon/vect/zext-v4i1.ll
M llvm/test/CodeGen/Hexagon/vect_setcc.ll
M llvm/test/CodeGen/Hexagon/vect_setcc_v2i16.ll
M llvm/test/CodeGen/Hexagon/vector-align.ll
M llvm/test/CodeGen/Hexagon/vector-ext-load.ll
M llvm/test/CodeGen/Hexagon/vector-sint-to-fp.ll
M llvm/test/CodeGen/Hexagon/vector-zext-v4i8.ll
M llvm/test/CodeGen/Hexagon/verify-liveness-at-def.mir
M llvm/test/CodeGen/Hexagon/verify-sink-code.ll
M llvm/test/CodeGen/Hexagon/verify-undef.ll
M llvm/test/CodeGen/Hexagon/vextract-basic.mir
M llvm/test/CodeGen/Hexagon/vgather-opt-addr.ll
M llvm/test/CodeGen/Hexagon/vgather-packetize.mir
M llvm/test/CodeGen/Hexagon/vload-postinc-sel.ll
M llvm/test/CodeGen/Hexagon/vmemu-128.ll
M llvm/test/CodeGen/Hexagon/vmpa-halide-test.ll
M llvm/test/CodeGen/Hexagon/vpack_eo.ll
M llvm/test/CodeGen/Hexagon/vselect-pseudo.ll
M llvm/test/CodeGen/Hexagon/vsplat-ext.ll
M llvm/test/CodeGen/Hexagon/vsplat-isel.ll
M llvm/test/CodeGen/Hexagon/wcsrtomb.ll
M llvm/test/CodeGen/Hexagon/widen-alias.ll
M llvm/test/CodeGen/Hexagon/widen-not-load.ll
M llvm/test/CodeGen/Hexagon/widen-volatile.ll
M llvm/test/CodeGen/Hexagon/zextloadi1.ll
M llvm/test/CodeGen/MIR/Hexagon/addrmode-opt-nonreaching.mir
M llvm/test/CodeGen/MIR/Hexagon/parse-lane-masks.mir
M llvm/test/CodeGen/MIR/Hexagon/target-flags.mir
M llvm/test/MC/Hexagon/extended_relocations.ll
Log Message:
-----------
[Hexagon,test] Change llc -march= to -mtriple=
Similar to 806761a7629df268c8aed49657aeccffa6bca449
-mtriple= specifies the full target triple while -march= merely sets the
architecture part of the default target triple, leaving a target triple which
may not make sense.
Therefore, -march= is error-prone and not recommended for tests without a target
triple. The issue has been benign as we recognize $unknown-apple-darwin as ELF instead
of rejecting it outrightly.
Commit: 5240e0b891fc4bf69d362199f70c94c28a7b9465
https://github.com/llvm/llvm-project/commit/5240e0b891fc4bf69d362199f70c94c28a7b9465
Author: Fangrui Song <i at maskray.me>
Date: 2024-12-15 (Sun, 15 Dec 2024)
Changed paths:
M llvm/test/CodeGen/VE/Packed/vec_fneg.ll
M llvm/test/CodeGen/VE/Packed/vp_add.ll
M llvm/test/CodeGen/VE/Packed/vp_and.ll
M llvm/test/CodeGen/VE/Packed/vp_fadd.ll
M llvm/test/CodeGen/VE/Packed/vp_fdiv.ll
M llvm/test/CodeGen/VE/Packed/vp_fmul.ll
M llvm/test/CodeGen/VE/Packed/vp_fsub.ll
M llvm/test/CodeGen/VE/Packed/vp_mul.ll
M llvm/test/CodeGen/VE/Packed/vp_or.ll
M llvm/test/CodeGen/VE/Packed/vp_sdiv.ll
M llvm/test/CodeGen/VE/Packed/vp_shl.ll
M llvm/test/CodeGen/VE/Packed/vp_sra.ll
M llvm/test/CodeGen/VE/Packed/vp_srl.ll
M llvm/test/CodeGen/VE/Packed/vp_sub.ll
M llvm/test/CodeGen/VE/Packed/vp_udiv.ll
M llvm/test/CodeGen/VE/Packed/vp_xor.ll
M llvm/test/CodeGen/VE/Vector/expand_single_elem_build_vec.ll
M llvm/test/CodeGen/VE/Vector/feature_vpu.ll
M llvm/test/CodeGen/VE/Vector/vec_fma.ll
M llvm/test/CodeGen/VE/Vector/vec_fneg.ll
M llvm/test/CodeGen/VE/Vector/vec_reduce_add.ll
M llvm/test/CodeGen/VE/Vector/vec_reduce_and.ll
M llvm/test/CodeGen/VE/Vector/vec_reduce_or.ll
M llvm/test/CodeGen/VE/Vector/vec_reduce_smax.ll
M llvm/test/CodeGen/VE/Vector/vec_reduce_xor.ll
M llvm/test/CodeGen/VE/Vector/vec_select.ll
M llvm/test/CodeGen/VE/Vector/vp_add.ll
M llvm/test/CodeGen/VE/Vector/vp_and.ll
M llvm/test/CodeGen/VE/Vector/vp_ashr.ll
M llvm/test/CodeGen/VE/Vector/vp_fadd.ll
M llvm/test/CodeGen/VE/Vector/vp_fadd_merge.ll
M llvm/test/CodeGen/VE/Vector/vp_fdiv.ll
M llvm/test/CodeGen/VE/Vector/vp_fdiv_merge.ll
M llvm/test/CodeGen/VE/Vector/vp_fma.ll
M llvm/test/CodeGen/VE/Vector/vp_fma_merge.ll
M llvm/test/CodeGen/VE/Vector/vp_fmul.ll
M llvm/test/CodeGen/VE/Vector/vp_fmul_merge.ll
M llvm/test/CodeGen/VE/Vector/vp_fsub.ll
M llvm/test/CodeGen/VE/Vector/vp_fsub_merge.ll
M llvm/test/CodeGen/VE/Vector/vp_lshr.ll
M llvm/test/CodeGen/VE/Vector/vp_merge.ll
M llvm/test/CodeGen/VE/Vector/vp_mul.ll
M llvm/test/CodeGen/VE/Vector/vp_or.ll
M llvm/test/CodeGen/VE/Vector/vp_reduce_add.ll
M llvm/test/CodeGen/VE/Vector/vp_reduce_and.ll
M llvm/test/CodeGen/VE/Vector/vp_reduce_or.ll
M llvm/test/CodeGen/VE/Vector/vp_reduce_smax.ll
M llvm/test/CodeGen/VE/Vector/vp_reduce_xor.ll
M llvm/test/CodeGen/VE/Vector/vp_sdiv.ll
M llvm/test/CodeGen/VE/Vector/vp_select.ll
M llvm/test/CodeGen/VE/Vector/vp_shl.ll
M llvm/test/CodeGen/VE/Vector/vp_sra.ll
M llvm/test/CodeGen/VE/Vector/vp_srem.ll
M llvm/test/CodeGen/VE/Vector/vp_srl.ll
M llvm/test/CodeGen/VE/Vector/vp_sub.ll
M llvm/test/CodeGen/VE/Vector/vp_udiv.ll
M llvm/test/CodeGen/VE/Vector/vp_urem.ll
M llvm/test/CodeGen/VE/Vector/vp_xor.ll
M llvm/test/CodeGen/VE/null-mctargetstreamer.ll
Log Message:
-----------
[VE,test] Change llc -march= to -mtriple=
Similar to 806761a7629df268c8aed49657aeccffa6bca449
-mtriple= specifies the full target triple while -march= merely sets the
architecture part of the default target triple, leaving a target triple which
may not make sense.
Therefore, -march= is error-prone and not recommended for tests without a target
triple. The issue has been benign as we recognize $ve-apple-darwin as ELF instead
of rejecting it outrightly.
Commit: 9ef1d37ffb5f56a9b949a6307bbb16c2ea0130e3
https://github.com/llvm/llvm-project/commit/9ef1d37ffb5f56a9b949a6307bbb16c2ea0130e3
Author: Fangrui Song <i at maskray.me>
Date: 2024-12-15 (Sun, 15 Dec 2024)
Changed paths:
M llvm/test/CodeGen/AVR/PR31344.ll
M llvm/test/CodeGen/AVR/PR31345.ll
M llvm/test/CodeGen/AVR/PR37143.ll
M llvm/test/CodeGen/AVR/add.ll
M llvm/test/CodeGen/AVR/alloca.ll
M llvm/test/CodeGen/AVR/and.ll
M llvm/test/CodeGen/AVR/atomics/fence.ll
M llvm/test/CodeGen/AVR/atomics/load-store-16-unexpected-register-bug.ll
M llvm/test/CodeGen/AVR/atomics/load16.ll
M llvm/test/CodeGen/AVR/atomics/load32.ll
M llvm/test/CodeGen/AVR/atomics/load64.ll
M llvm/test/CodeGen/AVR/atomics/load8.ll
M llvm/test/CodeGen/AVR/atomics/store.ll
M llvm/test/CodeGen/AVR/atomics/store16.ll
M llvm/test/CodeGen/AVR/atomics/swap.ll
M llvm/test/CodeGen/AVR/avr-rust-issue-123.ll
M llvm/test/CodeGen/AVR/block-address-is-in-progmem-space.ll
M llvm/test/CodeGen/AVR/branch-relaxation-long.ll
M llvm/test/CodeGen/AVR/branch-relaxation.ll
M llvm/test/CodeGen/AVR/brind.ll
M llvm/test/CodeGen/AVR/calling-conv/c/call.ll
M llvm/test/CodeGen/AVR/calling-conv/c/call_aggr.ll
M llvm/test/CodeGen/AVR/calling-conv/c/return.ll
M llvm/test/CodeGen/AVR/calling-conv/c/return_aggr.ll
M llvm/test/CodeGen/AVR/clear-bss.ll
M llvm/test/CodeGen/AVR/cmp.ll
M llvm/test/CodeGen/AVR/copy-data-to-ram.ll
M llvm/test/CodeGen/AVR/ctlz.ll
M llvm/test/CodeGen/AVR/ctpop.ll
M llvm/test/CodeGen/AVR/cttz.ll
M llvm/test/CodeGen/AVR/directmem.ll
M llvm/test/CodeGen/AVR/div.ll
M llvm/test/CodeGen/AVR/dynalloca.ll
M llvm/test/CodeGen/AVR/eor.ll
M llvm/test/CodeGen/AVR/expand-integer-failure.ll
M llvm/test/CodeGen/AVR/features/avr25.ll
M llvm/test/CodeGen/AVR/features/xmega_io.ll
M llvm/test/CodeGen/AVR/frame.ll
M llvm/test/CodeGen/AVR/frmidx-iterator-bug.ll
M llvm/test/CodeGen/AVR/high-pressure-on-ptrregs.ll
M llvm/test/CodeGen/AVR/icall-func-pointer-correct-addr-space.ll
M llvm/test/CodeGen/AVR/impossible-reg-to-reg-copy.ll
M llvm/test/CodeGen/AVR/inline-asm/inline-asm.ll
M llvm/test/CodeGen/AVR/inline-asm/inline-asm2.ll
M llvm/test/CodeGen/AVR/integration/blink.ll
M llvm/test/CodeGen/AVR/interrupts.ll
M llvm/test/CodeGen/AVR/intrinsics/named-reg-alloc.ll
M llvm/test/CodeGen/AVR/intrinsics/named-reg-special.ll
M llvm/test/CodeGen/AVR/intrinsics/stacksave-restore.ll
M llvm/test/CodeGen/AVR/io.ll
M llvm/test/CodeGen/AVR/issue-cannot-select-bswap.ll
M llvm/test/CodeGen/AVR/issue-regalloc-stackframe-folding-earlyclobber.ll
M llvm/test/CodeGen/AVR/large-return-size.ll
M llvm/test/CodeGen/AVR/ldd-immediate-overflow.ll
M llvm/test/CodeGen/AVR/load.ll
M llvm/test/CodeGen/AVR/lower-formal-args-struct-return.ll
M llvm/test/CodeGen/AVR/lower-formal-arguments-assertion.ll
M llvm/test/CodeGen/AVR/no-clear-bss.ll
M llvm/test/CodeGen/AVR/no-copy-data.ll
M llvm/test/CodeGen/AVR/no-print-operand-twice.ll
M llvm/test/CodeGen/AVR/or.ll
M llvm/test/CodeGen/AVR/pre-schedule.ll
M llvm/test/CodeGen/AVR/progmem-extended.ll
M llvm/test/CodeGen/AVR/progmem.ll
M llvm/test/CodeGen/AVR/pseudo/LDDWRdYQ.mir
M llvm/test/CodeGen/AVR/rem.ll
M llvm/test/CodeGen/AVR/runtime-trig.ll
M llvm/test/CodeGen/AVR/rust-avr-bug-112.ll
M llvm/test/CodeGen/AVR/rust-avr-bug-37.ll
M llvm/test/CodeGen/AVR/rust-avr-bug-95.ll
M llvm/test/CodeGen/AVR/rust-avr-bug-99.ll
M llvm/test/CodeGen/AVR/rust-bug-98167.ll
M llvm/test/CodeGen/AVR/select-must-add-unconditional-jump.ll
M llvm/test/CodeGen/AVR/sext.ll
M llvm/test/CodeGen/AVR/shift.ll
M llvm/test/CodeGen/AVR/sign-extension.ll
M llvm/test/CodeGen/AVR/smul-with-overflow.ll
M llvm/test/CodeGen/AVR/software-mul.ll
M llvm/test/CodeGen/AVR/std-immediate-overflow.ll
M llvm/test/CodeGen/AVR/std-ldd-immediate-overflow.ll
M llvm/test/CodeGen/AVR/stdwstk.ll
M llvm/test/CodeGen/AVR/store-undef.ll
M llvm/test/CodeGen/AVR/store.ll
M llvm/test/CodeGen/AVR/sub.ll
M llvm/test/CodeGen/AVR/trunc.ll
M llvm/test/CodeGen/AVR/umul-with-overflow.ll
M llvm/test/CodeGen/AVR/umul.with.overflow.i16-bug.ll
M llvm/test/CodeGen/AVR/unaligned-atomic-ops.ll
M llvm/test/CodeGen/AVR/varargs.ll
M llvm/test/CodeGen/AVR/xor.ll
M llvm/test/CodeGen/AVR/zeroreg.ll
M llvm/test/CodeGen/AVR/zext.ll
Log Message:
-----------
[AVR,test] Change llc -march= to -mtriple=
Similar to 806761a7629df268c8aed49657aeccffa6bca449
-mtriple= specifies the full target triple while -march= merely sets the
architecture part of the default target triple, leaving a target triple which
may not make sense.
Therefore, -march= is error-prone and not recommended for tests without a target
triple. The issue has been benign as we recognize avr-apple-darwin as ELF instead
of rejecting it outrightly.
Commit: 728490257ecc09ada707a0390303bd3c61027a53
https://github.com/llvm/llvm-project/commit/728490257ecc09ada707a0390303bd3c61027a53
Author: Fangrui Song <i at maskray.me>
Date: 2024-12-15 (Sun, 15 Dec 2024)
Changed paths:
M llvm/test/CodeGen/SPARC/2006-01-22-BitConvertLegalize.ll
M llvm/test/CodeGen/SPARC/2007-05-09-JumpTables.ll
M llvm/test/CodeGen/SPARC/2007-07-05-LiveIntervalAssert.ll
M llvm/test/CodeGen/SPARC/2008-10-10-InlineAsmMemoryOperand.ll
M llvm/test/CodeGen/SPARC/2008-10-10-InlineAsmRegOperand.ll
M llvm/test/CodeGen/SPARC/2009-08-28-PIC.ll
M llvm/test/CodeGen/SPARC/2009-08-28-WeakLinkage.ll
M llvm/test/CodeGen/SPARC/2011-01-11-CC.ll
M llvm/test/CodeGen/SPARC/2011-01-11-Call.ll
M llvm/test/CodeGen/SPARC/2011-01-11-FrameAddr.ll
M llvm/test/CodeGen/SPARC/2011-01-19-DelaySlot.ll
M llvm/test/CodeGen/SPARC/2011-01-21-ByValArgs.ll
M llvm/test/CodeGen/SPARC/2011-01-22-SRet.ll
M llvm/test/CodeGen/SPARC/2011-12-03-TailDuplication.ll
M llvm/test/CodeGen/SPARC/2013-05-17-CallFrame.ll
M llvm/test/CodeGen/SPARC/32abi.ll
M llvm/test/CodeGen/SPARC/64abi.ll
M llvm/test/CodeGen/SPARC/64atomics.ll
M llvm/test/CodeGen/SPARC/64bit.ll
M llvm/test/CodeGen/SPARC/64spill.ll
M llvm/test/CodeGen/SPARC/DbgValueOtherTargets.test
M llvm/test/CodeGen/SPARC/LeonCASAInstructionUT.ll
M llvm/test/CodeGen/SPARC/LeonDetectRoundChangePassUT.ll
M llvm/test/CodeGen/SPARC/LeonFixAllFDIVSQRTPassUT.ll
M llvm/test/CodeGen/SPARC/LeonInsertNOPLoadPassUT.ll
M llvm/test/CodeGen/SPARC/LeonItinerariesUT.ll
M llvm/test/CodeGen/SPARC/LeonSMACUMACInstructionUT.ll
M llvm/test/CodeGen/SPARC/alloca-align.ll
M llvm/test/CodeGen/SPARC/atomicrmw-uinc-udec-wrap.ll
M llvm/test/CodeGen/SPARC/atomics.ll
M llvm/test/CodeGen/SPARC/basictest.ll
M llvm/test/CodeGen/SPARC/cast-sret-func.ll
M llvm/test/CodeGen/SPARC/ctpop.ll
M llvm/test/CodeGen/SPARC/cttz.ll
M llvm/test/CodeGen/SPARC/data-align.ll
M llvm/test/CodeGen/SPARC/disable-fsmuld-fmuls.ll
M llvm/test/CodeGen/SPARC/float-constants.ll
M llvm/test/CodeGen/SPARC/float.ll
M llvm/test/CodeGen/SPARC/fp128.ll
M llvm/test/CodeGen/SPARC/inlineasm-bad.ll
M llvm/test/CodeGen/SPARC/inlineasm-v9.ll
M llvm/test/CodeGen/SPARC/inlineasm.ll
M llvm/test/CodeGen/SPARC/leafproc.ll
M llvm/test/CodeGen/SPARC/mult-alt-generic-sparc.ll
M llvm/test/CodeGen/SPARC/multiple-div.ll
M llvm/test/CodeGen/SPARC/parts.ll
M llvm/test/CodeGen/SPARC/private.ll
M llvm/test/CodeGen/SPARC/readcycle.ll
M llvm/test/CodeGen/SPARC/reg64.ll
M llvm/test/CodeGen/SPARC/register-clobber.ll
M llvm/test/CodeGen/SPARC/reserved-regs.ll
M llvm/test/CodeGen/SPARC/salvage-debug-isel.ll
M llvm/test/CodeGen/SPARC/select-mask.ll
M llvm/test/CodeGen/SPARC/setjmp.ll
M llvm/test/CodeGen/SPARC/soft-float.ll
M llvm/test/CodeGen/SPARC/soft-mul-div.ll
M llvm/test/CodeGen/SPARC/spill.ll
M llvm/test/CodeGen/SPARC/sret-secondary.ll
M llvm/test/CodeGen/SPARC/stack-align.ll
M llvm/test/CodeGen/SPARC/tn0009.mir
M llvm/test/CodeGen/SPARC/tn0010.mir
M llvm/test/CodeGen/SPARC/tn0012.mir
M llvm/test/CodeGen/SPARC/tn0013.mir
M llvm/test/CodeGen/SPARC/vector-call.ll
M llvm/test/CodeGen/SPARC/vector-extract-elt.ll
M llvm/test/CodeGen/SPARC/zerostructcall.ll
Log Message:
-----------
[Sparc,test] Change llc -march= to -mtriple=
Similar to 806761a7629df268c8aed49657aeccffa6bca449
-mtriple= specifies the full target triple while -march= merely sets the
architecture part of the default target triple (e.g. Windows, macOS),
leaving a target triple which may not make sense.
Therefore, -march= is error-prone and not recommended for tests without a target
triple. The issue has been benign as we recognize sparc*-apple-darwin as ELF instead
of rejecting it outrightly.
Commit: f1987c74ee5637ec248675a9a7070654167a5260
https://github.com/llvm/llvm-project/commit/f1987c74ee5637ec248675a9a7070654167a5260
Author: Fangrui Song <i at maskray.me>
Date: 2024-12-15 (Sun, 15 Dec 2024)
Changed paths:
M llvm/test/CodeGen/XCore/2008-11-17-Shl64.ll
M llvm/test/CodeGen/XCore/2009-01-08-Crash.ll
M llvm/test/CodeGen/XCore/2009-01-14-Remat-Crash.ll
M llvm/test/CodeGen/XCore/2009-03-27-v2f64-param.ll
M llvm/test/CodeGen/XCore/2009-07-15-store192.ll
M llvm/test/CodeGen/XCore/2010-02-25-LSR-Crash.ll
M llvm/test/CodeGen/XCore/2011-01-31-DAGCombineBug.ll
M llvm/test/CodeGen/XCore/2011-08-01-DynamicAllocBug.ll
M llvm/test/CodeGen/XCore/DbgValueOtherTargets.test
M llvm/test/CodeGen/XCore/addsub64.ll
M llvm/test/CodeGen/XCore/aliases.ll
M llvm/test/CodeGen/XCore/align.ll
M llvm/test/CodeGen/XCore/alignment.ll
M llvm/test/CodeGen/XCore/ashr.ll
M llvm/test/CodeGen/XCore/atomic.ll
M llvm/test/CodeGen/XCore/basictest.ll
M llvm/test/CodeGen/XCore/bigstructret.ll
M llvm/test/CodeGen/XCore/bitrev.ll
M llvm/test/CodeGen/XCore/byVal.ll
M llvm/test/CodeGen/XCore/call.ll
M llvm/test/CodeGen/XCore/constants.ll
M llvm/test/CodeGen/XCore/events.ll
M llvm/test/CodeGen/XCore/exception.ll
M llvm/test/CodeGen/XCore/fneg.ll
M llvm/test/CodeGen/XCore/getid.ll
M llvm/test/CodeGen/XCore/globals.ll
M llvm/test/CodeGen/XCore/indirectbr.ll
M llvm/test/CodeGen/XCore/inline-asm.ll
M llvm/test/CodeGen/XCore/inlineasm-output-template.ll
M llvm/test/CodeGen/XCore/ladd_lsub_combine.ll
M llvm/test/CodeGen/XCore/licm-ldwcp.ll
M llvm/test/CodeGen/XCore/linkage.ll
M llvm/test/CodeGen/XCore/llvm-intrinsics.ll
M llvm/test/CodeGen/XCore/load.ll
M llvm/test/CodeGen/XCore/memcpy.ll
M llvm/test/CodeGen/XCore/misc-intrinsics.ll
M llvm/test/CodeGen/XCore/mkmsk.ll
M llvm/test/CodeGen/XCore/mul64.ll
M llvm/test/CodeGen/XCore/offset_folding.ll
M llvm/test/CodeGen/XCore/private.ll
M llvm/test/CodeGen/XCore/ps-intrinsics.ll
M llvm/test/CodeGen/XCore/resources.ll
M llvm/test/CodeGen/XCore/resources_combine.ll
M llvm/test/CodeGen/XCore/section-name.ll
M llvm/test/CodeGen/XCore/sext.ll
M llvm/test/CodeGen/XCore/shedulingPreference.ll
M llvm/test/CodeGen/XCore/sr-intrinsics.ll
M llvm/test/CodeGen/XCore/store.ll
M llvm/test/CodeGen/XCore/switch.ll
M llvm/test/CodeGen/XCore/switch_long.ll
M llvm/test/CodeGen/XCore/tls.ll
M llvm/test/CodeGen/XCore/trampoline.ll
M llvm/test/CodeGen/XCore/trap.ll
M llvm/test/CodeGen/XCore/unaligned_load.ll
M llvm/test/CodeGen/XCore/unaligned_store.ll
M llvm/test/CodeGen/XCore/unaligned_store_combine.ll
M llvm/test/CodeGen/XCore/varargs.ll
M llvm/test/CodeGen/XCore/zext.ll
M llvm/test/CodeGen/XCore/zextfree.ll
Log Message:
-----------
[XCore,test] Change llc -march= to -mtriple=
Similar to 806761a7629df268c8aed49657aeccffa6bca449
-mtriple= specifies the full target triple while -march= merely sets the
architecture part of the default target triple (e.g. Windows, macOS),
leaving a target triple which may not make sense.
Therefore, -march= is error-prone and not recommended for tests without a target
triple. The issue has been benign as we recognize xcore-apple-darwin as ELF instead
of rejecting it outrightly.
Commit: b279f6b098d3849f7f1c1f539b108307d5f8ae2d
https://github.com/llvm/llvm-project/commit/b279f6b098d3849f7f1c1f539b108307d5f8ae2d
Author: Fangrui Song <i at maskray.me>
Date: 2024-12-15 (Sun, 15 Dec 2024)
Changed paths:
M llvm/test/CodeGen/MIR/NVPTX/expected-floating-point-literal.mir
M llvm/test/CodeGen/MIR/NVPTX/floating-point-immediate-operands.mir
M llvm/test/CodeGen/MIR/NVPTX/floating-point-invalid-type-error.mir
M llvm/test/CodeGen/NVPTX/APIntLoadStore.ll
M llvm/test/CodeGen/NVPTX/APIntParam.ll
M llvm/test/CodeGen/NVPTX/APIntSextParam.ll
M llvm/test/CodeGen/NVPTX/APIntZextParam.ll
M llvm/test/CodeGen/NVPTX/access-non-generic.ll
M llvm/test/CodeGen/NVPTX/activemask.ll
M llvm/test/CodeGen/NVPTX/add-sub-128bit.ll
M llvm/test/CodeGen/NVPTX/addr-mode.ll
M llvm/test/CodeGen/NVPTX/addrspacecast-gvar.ll
M llvm/test/CodeGen/NVPTX/addrspacecast.ll
M llvm/test/CodeGen/NVPTX/aggr-param.ll
M llvm/test/CodeGen/NVPTX/aggregate-return.ll
M llvm/test/CodeGen/NVPTX/alias-errors.ll
M llvm/test/CodeGen/NVPTX/alias.ll
M llvm/test/CodeGen/NVPTX/annotations.ll
M llvm/test/CodeGen/NVPTX/anonymous-fn-param.ll
M llvm/test/CodeGen/NVPTX/arg-lowering.ll
M llvm/test/CodeGen/NVPTX/arithmetic-fp-sm20.ll
M llvm/test/CodeGen/NVPTX/arithmetic-int.ll
M llvm/test/CodeGen/NVPTX/async-copy.ll
M llvm/test/CodeGen/NVPTX/atomicrmw-expand.ll
M llvm/test/CodeGen/NVPTX/atomics-sm60.ll
M llvm/test/CodeGen/NVPTX/atomics-sm70.ll
M llvm/test/CodeGen/NVPTX/atomics-sm90.ll
M llvm/test/CodeGen/NVPTX/atomics-with-scope.ll
M llvm/test/CodeGen/NVPTX/atomics.ll
M llvm/test/CodeGen/NVPTX/barrier.ll
M llvm/test/CodeGen/NVPTX/bf16-instructions.ll
M llvm/test/CodeGen/NVPTX/bf16.ll
M llvm/test/CodeGen/NVPTX/bf16x2-instructions-approx.ll
M llvm/test/CodeGen/NVPTX/bf16x2-instructions.ll
M llvm/test/CodeGen/NVPTX/bfe.ll
M llvm/test/CodeGen/NVPTX/boolean-patterns.ll
M llvm/test/CodeGen/NVPTX/branch-fold.ll
M llvm/test/CodeGen/NVPTX/branch-fold.mir
M llvm/test/CodeGen/NVPTX/brkpt.ll
M llvm/test/CodeGen/NVPTX/bswap.ll
M llvm/test/CodeGen/NVPTX/bug17709.ll
M llvm/test/CodeGen/NVPTX/bug21465.ll
M llvm/test/CodeGen/NVPTX/bug22246.ll
M llvm/test/CodeGen/NVPTX/bug22322.ll
M llvm/test/CodeGen/NVPTX/bug26185-2.ll
M llvm/test/CodeGen/NVPTX/bug26185.ll
M llvm/test/CodeGen/NVPTX/bug52623.ll
M llvm/test/CodeGen/NVPTX/bypass-div.ll
M llvm/test/CodeGen/NVPTX/call-with-alloca-buffer.ll
M llvm/test/CodeGen/NVPTX/call_bitcast_byval.ll
M llvm/test/CodeGen/NVPTX/callchain.ll
M llvm/test/CodeGen/NVPTX/calling-conv.ll
M llvm/test/CodeGen/NVPTX/calls-with-phi.ll
M llvm/test/CodeGen/NVPTX/cluster-dim.ll
M llvm/test/CodeGen/NVPTX/cmpxchg.ll
M llvm/test/CodeGen/NVPTX/combine-min-max.ll
M llvm/test/CodeGen/NVPTX/common-linkage.ll
M llvm/test/CodeGen/NVPTX/compare-int.ll
M llvm/test/CodeGen/NVPTX/compute-ptx-value-vts.ll
M llvm/test/CodeGen/NVPTX/constant-vectors.ll
M llvm/test/CodeGen/NVPTX/convert-fp.ll
M llvm/test/CodeGen/NVPTX/convert-int-sm20.ll
M llvm/test/CodeGen/NVPTX/convert-sm80.ll
M llvm/test/CodeGen/NVPTX/convert-sm89.ll
M llvm/test/CodeGen/NVPTX/copysign.ll
M llvm/test/CodeGen/NVPTX/cp-async-bulk-tensor-g2s.ll
M llvm/test/CodeGen/NVPTX/cp-async-bulk-tensor-prefetch.ll
M llvm/test/CodeGen/NVPTX/cp-async-bulk-tensor-reduce.ll
M llvm/test/CodeGen/NVPTX/cp-async-bulk-tensor-s2g.ll
M llvm/test/CodeGen/NVPTX/ctlz.ll
M llvm/test/CodeGen/NVPTX/ctpop.ll
M llvm/test/CodeGen/NVPTX/cttz.ll
M llvm/test/CodeGen/NVPTX/dag-cse.ll
M llvm/test/CodeGen/NVPTX/demote-vars.ll
M llvm/test/CodeGen/NVPTX/disable-opt.ll
M llvm/test/CodeGen/NVPTX/div-ri.ll
M llvm/test/CodeGen/NVPTX/div.ll
M llvm/test/CodeGen/NVPTX/divrem-combine.ll
M llvm/test/CodeGen/NVPTX/dot-product.ll
M llvm/test/CodeGen/NVPTX/dynamic-stackalloc-regression.ll
M llvm/test/CodeGen/NVPTX/dynamic_stackalloc.ll
M llvm/test/CodeGen/NVPTX/elect.ll
M llvm/test/CodeGen/NVPTX/empty-type.ll
M llvm/test/CodeGen/NVPTX/envreg.ll
M llvm/test/CodeGen/NVPTX/extloadv.ll
M llvm/test/CodeGen/NVPTX/extractelement.ll
M llvm/test/CodeGen/NVPTX/f16-ex2.ll
M llvm/test/CodeGen/NVPTX/fast-math.ll
M llvm/test/CodeGen/NVPTX/fcos-no-fast-math.ll
M llvm/test/CodeGen/NVPTX/fence-proxy-tensormap.ll
M llvm/test/CodeGen/NVPTX/fence-sm-90.ll
M llvm/test/CodeGen/NVPTX/fence.ll
M llvm/test/CodeGen/NVPTX/filetype-null.ll
M llvm/test/CodeGen/NVPTX/fma-assoc.ll
M llvm/test/CodeGen/NVPTX/fma-disable.ll
M llvm/test/CodeGen/NVPTX/fma-relu-contract.ll
M llvm/test/CodeGen/NVPTX/fma-relu-fma-intrinsic.ll
M llvm/test/CodeGen/NVPTX/fma-relu-instruction-flag.ll
M llvm/test/CodeGen/NVPTX/fma.ll
M llvm/test/CodeGen/NVPTX/fminimum-fmaximum.ll
M llvm/test/CodeGen/NVPTX/fns.ll
M llvm/test/CodeGen/NVPTX/fp-contract.ll
M llvm/test/CodeGen/NVPTX/fp-literals.ll
M llvm/test/CodeGen/NVPTX/fp16.ll
M llvm/test/CodeGen/NVPTX/fsin-no-fast-math.ll
M llvm/test/CodeGen/NVPTX/function-align.ll
M llvm/test/CodeGen/NVPTX/funnel-shift-clamp.ll
M llvm/test/CodeGen/NVPTX/generic-to-nvvm.ll
M llvm/test/CodeGen/NVPTX/global-addrspace.ll
M llvm/test/CodeGen/NVPTX/global-ctor-empty.ll
M llvm/test/CodeGen/NVPTX/global-ctor.ll
M llvm/test/CodeGen/NVPTX/global-dtor.ll
M llvm/test/CodeGen/NVPTX/global-incomplete-init.ll
M llvm/test/CodeGen/NVPTX/global-ordering.ll
M llvm/test/CodeGen/NVPTX/global-visibility.ll
M llvm/test/CodeGen/NVPTX/globals_init.ll
M llvm/test/CodeGen/NVPTX/gvar-init.ll
M llvm/test/CodeGen/NVPTX/half.ll
M llvm/test/CodeGen/NVPTX/i1-array-global.ll
M llvm/test/CodeGen/NVPTX/i1-ext-load.ll
M llvm/test/CodeGen/NVPTX/i1-global.ll
M llvm/test/CodeGen/NVPTX/i1-icmp.ll
M llvm/test/CodeGen/NVPTX/i1-int-to-fp.ll
M llvm/test/CodeGen/NVPTX/i1-load-lower.ll
M llvm/test/CodeGen/NVPTX/i1-param.ll
M llvm/test/CodeGen/NVPTX/i128-global.ll
M llvm/test/CodeGen/NVPTX/i128-param.ll
M llvm/test/CodeGen/NVPTX/i128-retval.ll
M llvm/test/CodeGen/NVPTX/i128-struct.ll
M llvm/test/CodeGen/NVPTX/i8-param.ll
M llvm/test/CodeGen/NVPTX/idioms.ll
M llvm/test/CodeGen/NVPTX/imad.ll
M llvm/test/CodeGen/NVPTX/indirect_byval.ll
M llvm/test/CodeGen/NVPTX/inline-asm-b128-test1.ll
M llvm/test/CodeGen/NVPTX/inline-asm-b128-test2.ll
M llvm/test/CodeGen/NVPTX/inline-asm-b128-test3.ll
M llvm/test/CodeGen/NVPTX/inline-asm.ll
M llvm/test/CodeGen/NVPTX/inlineasm-output-template.ll
M llvm/test/CodeGen/NVPTX/intrinsic-old.ll
M llvm/test/CodeGen/NVPTX/intrinsics-sm90.ll
M llvm/test/CodeGen/NVPTX/intrinsics.ll
M llvm/test/CodeGen/NVPTX/isspacep.ll
M llvm/test/CodeGen/NVPTX/kernel-param-align.ll
M llvm/test/CodeGen/NVPTX/ld-addrspace.ll
M llvm/test/CodeGen/NVPTX/ld-generic.ll
M llvm/test/CodeGen/NVPTX/ld-st-addrrspace.py
M llvm/test/CodeGen/NVPTX/ldg-invariant.ll
M llvm/test/CodeGen/NVPTX/ldparam-v4.ll
M llvm/test/CodeGen/NVPTX/ldu-i8.ll
M llvm/test/CodeGen/NVPTX/ldu-ldg.ll
M llvm/test/CodeGen/NVPTX/ldu-reg-plus-offset.ll
M llvm/test/CodeGen/NVPTX/load-sext-i1.ll
M llvm/test/CodeGen/NVPTX/load-store-sm-70.ll
M llvm/test/CodeGen/NVPTX/load-store-sm-90.ll
M llvm/test/CodeGen/NVPTX/load-store.ll
M llvm/test/CodeGen/NVPTX/load-with-non-coherent-cache.ll
M llvm/test/CodeGen/NVPTX/local-stack-frame.ll
M llvm/test/CodeGen/NVPTX/lower-aggr-copies.ll
M llvm/test/CodeGen/NVPTX/lower-alloca.ll
M llvm/test/CodeGen/NVPTX/lower-kernel-ptr-arg.ll
M llvm/test/CodeGen/NVPTX/machine-sink.ll
M llvm/test/CodeGen/NVPTX/managed.ll
M llvm/test/CodeGen/NVPTX/match.ll
M llvm/test/CodeGen/NVPTX/math-intrins-sm53-ptx42.ll
M llvm/test/CodeGen/NVPTX/math-intrins-sm80-ptx70-autoupgrade.ll
M llvm/test/CodeGen/NVPTX/math-intrins-sm80-ptx70.ll
M llvm/test/CodeGen/NVPTX/math-intrins-sm86-ptx72-autoupgrade.ll
M llvm/test/CodeGen/NVPTX/math-intrins-sm86-ptx72.ll
M llvm/test/CodeGen/NVPTX/max-align.ll
M llvm/test/CodeGen/NVPTX/maxclusterrank.ll
M llvm/test/CodeGen/NVPTX/mbarrier.ll
M llvm/test/CodeGen/NVPTX/minmax-negative.ll
M llvm/test/CodeGen/NVPTX/misaligned-vector-ldst.ll
M llvm/test/CodeGen/NVPTX/misched_func_call.ll
M llvm/test/CodeGen/NVPTX/mma-no-sink-after-laneid-check.ll
M llvm/test/CodeGen/NVPTX/module-inline-asm.ll
M llvm/test/CodeGen/NVPTX/mulwide.ll
M llvm/test/CodeGen/NVPTX/named-barriers.ll
M llvm/test/CodeGen/NVPTX/nanosleep.ll
M llvm/test/CodeGen/NVPTX/no-extra-parens.ll
M llvm/test/CodeGen/NVPTX/nofunc.ll
M llvm/test/CodeGen/NVPTX/noreturn.ll
M llvm/test/CodeGen/NVPTX/nounroll.ll
M llvm/test/CodeGen/NVPTX/nvcl-param-align.ll
M llvm/test/CodeGen/NVPTX/nvvm-reflect-arch-O0.ll
M llvm/test/CodeGen/NVPTX/packed-aggr.ll
M llvm/test/CodeGen/NVPTX/param-align.ll
M llvm/test/CodeGen/NVPTX/param-load-store.ll
M llvm/test/CodeGen/NVPTX/param-overalign.ll
M llvm/test/CodeGen/NVPTX/pass-name.ll
M llvm/test/CodeGen/NVPTX/pow2_mask_cmp.ll
M llvm/test/CodeGen/NVPTX/pr13291-i1-store.ll
M llvm/test/CodeGen/NVPTX/pr16278.ll
M llvm/test/CodeGen/NVPTX/pr17529.ll
M llvm/test/CodeGen/NVPTX/proxy-reg-erasure-ptx.ll
M llvm/test/CodeGen/NVPTX/proxy-reg-erasure.mir
M llvm/test/CodeGen/NVPTX/rcp-opt.ll
M llvm/test/CodeGen/NVPTX/read-global-variable-constant.ll
M llvm/test/CodeGen/NVPTX/redux-sync.ll
M llvm/test/CodeGen/NVPTX/refl1.ll
M llvm/test/CodeGen/NVPTX/reg-copy.ll
M llvm/test/CodeGen/NVPTX/reg-types.ll
M llvm/test/CodeGen/NVPTX/rotate_64.ll
M llvm/test/CodeGen/NVPTX/rsqrt-opt.ll
M llvm/test/CodeGen/NVPTX/rsqrt.ll
M llvm/test/CodeGen/NVPTX/sched1.ll
M llvm/test/CodeGen/NVPTX/sched2.ll
M llvm/test/CodeGen/NVPTX/setmaxnreg.ll
M llvm/test/CodeGen/NVPTX/sext-in-reg.ll
M llvm/test/CodeGen/NVPTX/sext-params.ll
M llvm/test/CodeGen/NVPTX/sext-setcc.ll
M llvm/test/CodeGen/NVPTX/shfl-p.ll
M llvm/test/CodeGen/NVPTX/shfl-sync-p.ll
M llvm/test/CodeGen/NVPTX/shfl-sync.ll
M llvm/test/CodeGen/NVPTX/shfl.ll
M llvm/test/CodeGen/NVPTX/shift-parts.ll
M llvm/test/CodeGen/NVPTX/short-ptr.ll
M llvm/test/CodeGen/NVPTX/shuffle-vec-undef-init.ll
M llvm/test/CodeGen/NVPTX/simple-call.ll
M llvm/test/CodeGen/NVPTX/sm-version.ll
M llvm/test/CodeGen/NVPTX/sqrt-approx.ll
M llvm/test/CodeGen/NVPTX/st-addrspace.ll
M llvm/test/CodeGen/NVPTX/st-generic.ll
M llvm/test/CodeGen/NVPTX/st-param-imm.ll
M llvm/test/CodeGen/NVPTX/stacksaverestore.ll
M llvm/test/CodeGen/NVPTX/store-undef.ll
M llvm/test/CodeGen/NVPTX/surf-read-cuda.ll
M llvm/test/CodeGen/NVPTX/surf-write-cuda.ll
M llvm/test/CodeGen/NVPTX/symbol-naming.ll
M llvm/test/CodeGen/NVPTX/tex-read-cuda.ll
M llvm/test/CodeGen/NVPTX/texsurf-queries.ll
M llvm/test/CodeGen/NVPTX/tid-range.ll
M llvm/test/CodeGen/NVPTX/unaligned-param-load-store.ll
M llvm/test/CodeGen/NVPTX/unreachable.ll
M llvm/test/CodeGen/NVPTX/variadics-backend.ll
M llvm/test/CodeGen/NVPTX/vec-param-load.ll
M llvm/test/CodeGen/NVPTX/vec8.ll
M llvm/test/CodeGen/NVPTX/vector-args.ll
M llvm/test/CodeGen/NVPTX/vector-call.ll
M llvm/test/CodeGen/NVPTX/vector-compare.ll
M llvm/test/CodeGen/NVPTX/vector-global.ll
M llvm/test/CodeGen/NVPTX/vector-loads.ll
M llvm/test/CodeGen/NVPTX/vector-returns.ll
M llvm/test/CodeGen/NVPTX/vector-select.ll
M llvm/test/CodeGen/NVPTX/vector-stores.ll
M llvm/test/CodeGen/NVPTX/vote.ll
M llvm/test/CodeGen/NVPTX/weak-global.ll
M llvm/test/CodeGen/NVPTX/weak-linkage.ll
M llvm/test/CodeGen/NVPTX/wmma-ptx60-sm70.py
M llvm/test/CodeGen/NVPTX/wmma-ptx61-sm70.py
M llvm/test/CodeGen/NVPTX/wmma-ptx63-sm72.py
M llvm/test/CodeGen/NVPTX/wmma-ptx63-sm75.py
M llvm/test/CodeGen/NVPTX/wmma-ptx64-sm70.py
M llvm/test/CodeGen/NVPTX/wmma-ptx65-sm75.py
M llvm/test/CodeGen/NVPTX/wmma-ptx71-sm80.py
M llvm/test/CodeGen/NVPTX/zeroext-32bit.ll
Log Message:
-----------
[NVPTX,test] Change llc -march= to -mtriple=
Similar to 806761a7629df268c8aed49657aeccffa6bca449
-mtriple= specifies the full target triple while -march= merely sets the
architecture part of the default target triple (e.g. Windows, macOS),
leaving a target triple which may not make sense.
Therefore, -march= is error-prone and not recommended for tests without
a target triple. The issue has been benign as we recognize
nvptx{,64}-apple-darwin as ELF instead of rejecting it outrightly.
Commit: e64650d702f23674f5a7995a0bb6bd56a604b291
https://github.com/llvm/llvm-project/commit/e64650d702f23674f5a7995a0bb6bd56a604b291
Author: Florian Hahn <flo at fhahn.com>
Date: 2024-12-15 (Sun, 15 Dec 2024)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
M llvm/test/Transforms/LoopVectorize/AArch64/sve-widen-gep.ll
Log Message:
-----------
[VPlan] Get types and step from VPWidenPointerInductionRecipe (NFC).
Use information directly from operands instead of going through
IVDescriptor.
Commit: 9afaf9c6c89efb22bccab39677e8dff47da91a00
https://github.com/llvm/llvm-project/commit/9afaf9c6c89efb22bccab39677e8dff47da91a00
Author: Fangrui Song <i at maskray.me>
Date: 2024-12-15 (Sun, 15 Dec 2024)
Changed paths:
M llvm/test/CodeGen/AMDGPU/GlobalISel/mmra.ll
M llvm/test/CodeGen/AMDGPU/bf16-conversions.ll
M llvm/test/CodeGen/AMDGPU/bitreverse-inline-immediates.ll
M llvm/test/CodeGen/AMDGPU/invalid-inline-asm-constraint-crash.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.bitop3.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.read.tr.gfx950.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.gfx950.bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.gfx950.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.prng.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.atomic.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.atomic.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.buffer.prefetch.data.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.prefetch.data.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.smfmac.gfx950.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.atomic.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.atomic.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.update.dpp.gfx90a.ll
M llvm/test/CodeGen/AMDGPU/llvm.set.rounding.ll
M llvm/test/CodeGen/AMDGPU/load-store-opt-addc0.mir
M llvm/test/CodeGen/AMDGPU/mai-hazards-mfma-scale.gfx950.mir
M llvm/test/CodeGen/AMDGPU/mmra.ll
M llvm/test/CodeGen/AMDGPU/v_swap_b16.ll
M llvm/test/MachineVerifier/AMDGPU/fix-illegal-vector-copies.mir
Log Message:
-----------
[AMDGPU,test] Change llc -march= to -mtriple=
Follow-up to 806761a7629df268c8aed49657aeccffa6bca449
Commit: c5037db4acd95790a0ca5061c8fa79c5c291607e
https://github.com/llvm/llvm-project/commit/c5037db4acd95790a0ca5061c8fa79c5c291607e
Author: Fangrui Song <i at maskray.me>
Date: 2024-12-15 (Sun, 15 Dec 2024)
Changed paths:
M llvm/test/CodeGen/BPF/32-bit-subreg-alu.ll
M llvm/test/CodeGen/BPF/32-bit-subreg-cond-select.ll
M llvm/test/CodeGen/BPF/32-bit-subreg-load-store.ll
M llvm/test/CodeGen/BPF/32-bit-subreg-peephole-phi-1.ll
M llvm/test/CodeGen/BPF/32-bit-subreg-peephole-phi-2.ll
M llvm/test/CodeGen/BPF/32-bit-subreg-peephole-phi-3.ll
M llvm/test/CodeGen/BPF/32-bit-subreg-peephole.ll
M llvm/test/CodeGen/BPF/32-bit-subreg-zext.ll
M llvm/test/CodeGen/BPF/BTF/array-1d-char.ll
M llvm/test/CodeGen/BPF/BTF/array-1d-int.ll
M llvm/test/CodeGen/BPF/BTF/array-2d-int.ll
M llvm/test/CodeGen/BPF/BTF/array-size-0.ll
M llvm/test/CodeGen/BPF/BTF/array-typedef.ll
M llvm/test/CodeGen/BPF/BTF/atomics.ll
M llvm/test/CodeGen/BPF/BTF/char-no-debuginfo.ll
M llvm/test/CodeGen/BPF/BTF/char.ll
M llvm/test/CodeGen/BPF/BTF/double.ll
M llvm/test/CodeGen/BPF/BTF/empty-btf.ll
M llvm/test/CodeGen/BPF/BTF/enum-basic.ll
M llvm/test/CodeGen/BPF/BTF/extern-builtin.ll
M llvm/test/CodeGen/BPF/BTF/extern-func-arg.ll
M llvm/test/CodeGen/BPF/BTF/extern-func-ptr.ll
M llvm/test/CodeGen/BPF/BTF/extern-global-var.ll
M llvm/test/CodeGen/BPF/BTF/extern-var-func-weak-section.ll
M llvm/test/CodeGen/BPF/BTF/extern-var-func-weak.ll
M llvm/test/CodeGen/BPF/BTF/extern-var-func.ll
M llvm/test/CodeGen/BPF/BTF/extern-var-func2.ll
M llvm/test/CodeGen/BPF/BTF/extern-var-section.ll
M llvm/test/CodeGen/BPF/BTF/extern-var-struct-weak.ll
M llvm/test/CodeGen/BPF/BTF/extern-var-struct.ll
M llvm/test/CodeGen/BPF/BTF/extern-var-weak-section.ll
M llvm/test/CodeGen/BPF/BTF/filename.ll
M llvm/test/CodeGen/BPF/BTF/float.ll
M llvm/test/CodeGen/BPF/BTF/func-func-ptr.ll
M llvm/test/CodeGen/BPF/BTF/func-non-void.ll
M llvm/test/CodeGen/BPF/BTF/func-source.ll
M llvm/test/CodeGen/BPF/BTF/func-typedef.ll
M llvm/test/CodeGen/BPF/BTF/func-unused-arg.ll
M llvm/test/CodeGen/BPF/BTF/func-void.ll
M llvm/test/CodeGen/BPF/BTF/fwd-no-define.ll
M llvm/test/CodeGen/BPF/BTF/fwd-with-define.ll
M llvm/test/CodeGen/BPF/BTF/global-var-bss-and-data.ll
M llvm/test/CodeGen/BPF/BTF/global-var-inited.ll
M llvm/test/CodeGen/BPF/BTF/global-var-sec-readonly.ll
M llvm/test/CodeGen/BPF/BTF/global-var-sec.ll
M llvm/test/CodeGen/BPF/BTF/incomplete-debuginfo.ll
M llvm/test/CodeGen/BPF/BTF/int.ll
M llvm/test/CodeGen/BPF/BTF/local-var-readonly-1.ll
M llvm/test/CodeGen/BPF/BTF/local-var-readonly-2.ll
M llvm/test/CodeGen/BPF/BTF/local-var.ll
M llvm/test/CodeGen/BPF/BTF/longlong.ll
M llvm/test/CodeGen/BPF/BTF/map-def-2.ll
M llvm/test/CodeGen/BPF/BTF/map-def-3.ll
M llvm/test/CodeGen/BPF/BTF/map-def.ll
M llvm/test/CodeGen/BPF/BTF/pruning-const.ll
M llvm/test/CodeGen/BPF/BTF/pruning-dup-ptr-struct.ll
M llvm/test/CodeGen/BPF/BTF/pruning-multi-derived-type.ll
M llvm/test/CodeGen/BPF/BTF/pruning-typedef.ll
M llvm/test/CodeGen/BPF/BTF/ptr-const-void.ll
M llvm/test/CodeGen/BPF/BTF/ptr-func-1.ll
M llvm/test/CodeGen/BPF/BTF/ptr-func-2.ll
M llvm/test/CodeGen/BPF/BTF/ptr-func-3.ll
M llvm/test/CodeGen/BPF/BTF/ptr-int.ll
M llvm/test/CodeGen/BPF/BTF/ptr-prune-type.ll
M llvm/test/CodeGen/BPF/BTF/ptr-void.ll
M llvm/test/CodeGen/BPF/BTF/ptr-volatile-const-void.ll
M llvm/test/CodeGen/BPF/BTF/ptr-volatile-void.ll
M llvm/test/CodeGen/BPF/BTF/restrict-ptr.ll
M llvm/test/CodeGen/BPF/BTF/short.ll
M llvm/test/CodeGen/BPF/BTF/static-func.ll
M llvm/test/CodeGen/BPF/BTF/static-var-derived-type.ll
M llvm/test/CodeGen/BPF/BTF/static-var-inited-sec.ll
M llvm/test/CodeGen/BPF/BTF/static-var-inited.ll
M llvm/test/CodeGen/BPF/BTF/static-var-readonly-sec.ll
M llvm/test/CodeGen/BPF/BTF/static-var-readonly.ll
M llvm/test/CodeGen/BPF/BTF/static-var-sec.ll
M llvm/test/CodeGen/BPF/BTF/static-var-zerolen-array.ll
M llvm/test/CodeGen/BPF/BTF/static-var.ll
M llvm/test/CodeGen/BPF/BTF/struct-anon-2.ll
M llvm/test/CodeGen/BPF/BTF/struct-anon.ll
M llvm/test/CodeGen/BPF/BTF/struct-basic.ll
M llvm/test/CodeGen/BPF/BTF/struct-bitfield-typedef.ll
M llvm/test/CodeGen/BPF/BTF/struct-enum.ll
M llvm/test/CodeGen/BPF/BTF/tag-1.ll
M llvm/test/CodeGen/BPF/BTF/tag-2.ll
M llvm/test/CodeGen/BPF/BTF/tag-extern-func.ll
M llvm/test/CodeGen/BPF/BTF/tag-typedef.ll
M llvm/test/CodeGen/BPF/BTF/type-tag-fixup-fwd.ll
M llvm/test/CodeGen/BPF/BTF/type-tag-fixup-resolved.ll
M llvm/test/CodeGen/BPF/BTF/type-tag-var.ll
M llvm/test/CodeGen/BPF/BTF/uchar.ll
M llvm/test/CodeGen/BPF/BTF/uint.ll
M llvm/test/CodeGen/BPF/BTF/ulonglong.ll
M llvm/test/CodeGen/BPF/BTF/union-array-typedef.ll
M llvm/test/CodeGen/BPF/BTF/ushort.ll
M llvm/test/CodeGen/BPF/BTF/weak-global-2.ll
M llvm/test/CodeGen/BPF/BTF/weak-global-3.ll
M llvm/test/CodeGen/BPF/BTF/weak-global.ll
M llvm/test/CodeGen/BPF/CORE/field-reloc-st-imm.ll
M llvm/test/CodeGen/BPF/CORE/simplifypatable-nullptr.ll
M llvm/test/CodeGen/BPF/addr-space-cast.ll
M llvm/test/CodeGen/BPF/addr-space-globals.ll
M llvm/test/CodeGen/BPF/addr-space-globals2.ll
M llvm/test/CodeGen/BPF/alu8.ll
M llvm/test/CodeGen/BPF/atomics.ll
M llvm/test/CodeGen/BPF/atomics_2.ll
M llvm/test/CodeGen/BPF/atomics_mem_order_v1.ll
M llvm/test/CodeGen/BPF/atomics_mem_order_v3.ll
M llvm/test/CodeGen/BPF/atomics_sub64_relaxed_v1.ll
M llvm/test/CodeGen/BPF/basictest.ll
M llvm/test/CodeGen/BPF/bpf-fastcall-1.ll
M llvm/test/CodeGen/BPF/bpf-fastcall-2.ll
M llvm/test/CodeGen/BPF/bpf-fastcall-3.ll
M llvm/test/CodeGen/BPF/bpf-fastcall-4.ll
M llvm/test/CodeGen/BPF/bpf-fastcall-5.ll
M llvm/test/CodeGen/BPF/bpf-fastcall-regmask-1.ll
M llvm/test/CodeGen/BPF/bswap.ll
M llvm/test/CodeGen/BPF/byval.ll
M llvm/test/CodeGen/BPF/callx.ll
M llvm/test/CodeGen/BPF/cc_args.ll
M llvm/test/CodeGen/BPF/cc_args_be.ll
M llvm/test/CodeGen/BPF/cc_ret.ll
M llvm/test/CodeGen/BPF/cmp.ll
M llvm/test/CodeGen/BPF/cttz-ctlz.ll
M llvm/test/CodeGen/BPF/dwarfdump.ll
M llvm/test/CodeGen/BPF/ex1.ll
M llvm/test/CodeGen/BPF/fi_ri.ll
M llvm/test/CodeGen/BPF/gotol.ll
M llvm/test/CodeGen/BPF/i128.ll
M llvm/test/CodeGen/BPF/inline_asm.ll
M llvm/test/CodeGen/BPF/inlineasm-wreg.ll
M llvm/test/CodeGen/BPF/intrinsics.ll
M llvm/test/CodeGen/BPF/is_trunc_free.ll
M llvm/test/CodeGen/BPF/is_zext_free.ll
M llvm/test/CodeGen/BPF/ldsx.ll
M llvm/test/CodeGen/BPF/load.ll
M llvm/test/CodeGen/BPF/loops.ll
M llvm/test/CodeGen/BPF/many_args1.ll
M llvm/test/CodeGen/BPF/many_args2.ll
M llvm/test/CodeGen/BPF/mem_offset.ll
M llvm/test/CodeGen/BPF/mem_offset_be.ll
M llvm/test/CodeGen/BPF/memcmp.ll
M llvm/test/CodeGen/BPF/memcpy-expand-in-order.ll
M llvm/test/CodeGen/BPF/movsx.ll
M llvm/test/CodeGen/BPF/no-merge-attr.ll
M llvm/test/CodeGen/BPF/optnone-1.ll
M llvm/test/CodeGen/BPF/optnone-2.ll
M llvm/test/CodeGen/BPF/remove_truncate_1.ll
M llvm/test/CodeGen/BPF/remove_truncate_2.ll
M llvm/test/CodeGen/BPF/remove_truncate_3.ll
M llvm/test/CodeGen/BPF/remove_truncate_4.ll
M llvm/test/CodeGen/BPF/remove_truncate_5.ll
M llvm/test/CodeGen/BPF/remove_truncate_6.ll
M llvm/test/CodeGen/BPF/remove_truncate_7.ll
M llvm/test/CodeGen/BPF/remove_truncate_8.ll
M llvm/test/CodeGen/BPF/remove_truncate_9.ll
M llvm/test/CodeGen/BPF/rodata_1.ll
M llvm/test/CodeGen/BPF/rodata_2.ll
M llvm/test/CodeGen/BPF/rodata_3.ll
M llvm/test/CodeGen/BPF/rodata_4.ll
M llvm/test/CodeGen/BPF/rodata_5.ll
M llvm/test/CodeGen/BPF/rodata_6.ll
M llvm/test/CodeGen/BPF/rodata_7.ll
M llvm/test/CodeGen/BPF/sdiv_smod.ll
M llvm/test/CodeGen/BPF/sdiv_to_mul.ll
M llvm/test/CodeGen/BPF/select_ri.ll
M llvm/test/CodeGen/BPF/selectiondag-bug.ll
M llvm/test/CodeGen/BPF/setcc.ll
M llvm/test/CodeGen/BPF/shifts.ll
M llvm/test/CodeGen/BPF/sockex2.ll
M llvm/test/CodeGen/BPF/spill-alu32.ll
M llvm/test/CodeGen/BPF/store_imm.ll
M llvm/test/CodeGen/BPF/struct-arg.ll
M llvm/test/CodeGen/BPF/struct_ret1.ll
M llvm/test/CodeGen/BPF/struct_ret2.ll
M llvm/test/CodeGen/BPF/undef.ll
M llvm/test/CodeGen/BPF/vararg1.ll
M llvm/test/CodeGen/BPF/warn-call.ll
M llvm/test/CodeGen/BPF/warn-stack.ll
M llvm/test/CodeGen/BPF/xadd.ll
M llvm/test/CodeGen/BPF/xadd_legal.ll
M llvm/test/CodeGen/BPF/xaddd_v1.ll
Log Message:
-----------
[BPF,test] Change llc -march= to -mtriple=
Similar to 806761a7629df268c8aed49657aeccffa6bca449
-mtriple= specifies the full target triple while -march= merely sets the
architecture part of the default target triple (e.g. Windows, macOS),
leaving a target triple which may not make sense.
Therefore, -march= is error-prone and not recommended for tests without
a target triple. The issue has been benign as we recognize
bpf*-apple-darwin as ELF instead of rejecting it outrightly.
Commit: 50046221b8e913ec6506eb96ce4c0cd267a5cc99
https://github.com/llvm/llvm-project/commit/50046221b8e913ec6506eb96ce4c0cd267a5cc99
Author: Nico Weber <thakis at chromium.org>
Date: 2024-12-15 (Sun, 15 Dec 2024)
Changed paths:
M clang/lib/Driver/ToolChains/CommonArgs.cpp
M clang/lib/Driver/ToolChains/CommonArgs.h
M clang/lib/Driver/ToolChains/FreeBSD.cpp
M clang/lib/Driver/ToolChains/Fuchsia.cpp
M clang/lib/Driver/ToolChains/Gnu.cpp
M clang/lib/Driver/ToolChains/Hexagon.cpp
M clang/lib/Driver/ToolChains/NetBSD.cpp
M clang/lib/Driver/ToolChains/OpenBSD.cpp
M clang/lib/Driver/ToolChains/Solaris.cpp
Log Message:
-----------
Revert "[Driver] Cache SanitizerArgs (NFC) (#119442)"
This reverts commit bae383ba6b53b0d8257c83f99ceecdd751d0a378.
Prerequisite to reverting #119071.
Commit: 1464b8ec8a675fd11dc7280db1c56aac03771b0a
https://github.com/llvm/llvm-project/commit/1464b8ec8a675fd11dc7280db1c56aac03771b0a
Author: Nico Weber <thakis at chromium.org>
Date: 2024-12-15 (Sun, 15 Dec 2024)
Changed paths:
M clang/lib/Driver/ToolChains/CommonArgs.cpp
M clang/test/Driver/sanitizer-ld.c
M compiler-rt/lib/msan/msan_interceptors.cpp
M compiler-rt/lib/sanitizer_common/sanitizer_common_interceptors.inc
M compiler-rt/lib/sanitizer_common/sanitizer_platform_interceptors.h
R compiler-rt/test/msan/Linux/dn_expand.cpp
A compiler-rt/test/sanitizer_common/TestCases/Linux/b64.cpp
A compiler-rt/test/sanitizer_common/TestCases/Linux/dn_expand.cpp
Log Message:
-----------
Revert "Move interceptors for libresolv functions to MSan (#119071)"
This reverts commit f5f965058a5f9b835382f96bd4041bc7e608ece0.
Breaks a test on some bots, see
https://github.com/llvm/llvm-project/pull/119071#issuecomment-2544000926
Commit: 40a4cbb0f200e5e0bafbd58d55c2da6daab9515d
https://github.com/llvm/llvm-project/commit/40a4cbb0f200e5e0bafbd58d55c2da6daab9515d
Author: Fangrui Song <i at maskray.me>
Date: 2024-12-15 (Sun, 15 Dec 2024)
Changed paths:
M llvm/test/CodeGen/MIR/X86/basic-block-liveins.mir
M llvm/test/CodeGen/MIR/X86/basic-block-not-at-start-of-line-error.mir
M llvm/test/CodeGen/MIR/X86/block-address-operands.mir
M llvm/test/CodeGen/MIR/X86/callee-saved-info.mir
M llvm/test/CodeGen/MIR/X86/cfi-def-cfa-offset.mir
M llvm/test/CodeGen/MIR/X86/cfi-def-cfa-register.mir
M llvm/test/CodeGen/MIR/X86/cfi-offset.mir
M llvm/test/CodeGen/MIR/X86/constant-pool-item-redefinition-error.mir
M llvm/test/CodeGen/MIR/X86/constant-pool.mir
M llvm/test/CodeGen/MIR/X86/constant-value-error.mir
M llvm/test/CodeGen/MIR/X86/copyIRflags.mir
M llvm/test/CodeGen/MIR/X86/dead-register-flag.mir
M llvm/test/CodeGen/MIR/X86/def-register-already-tied-error.mir
M llvm/test/CodeGen/MIR/X86/duplicate-memory-operand-flag.mir
M llvm/test/CodeGen/MIR/X86/duplicate-register-flag-error.mir
M llvm/test/CodeGen/MIR/X86/early-clobber-register-flag.mir
M llvm/test/CodeGen/MIR/X86/exception-function-state.mir
M llvm/test/CodeGen/MIR/X86/expected-align-in-memory-operand.mir
M llvm/test/CodeGen/MIR/X86/expected-alignment-after-align-in-memory-operand.mir
M llvm/test/CodeGen/MIR/X86/expected-basic-block-at-start-of-body.mir
M llvm/test/CodeGen/MIR/X86/expected-block-reference-in-blockaddress.mir
M llvm/test/CodeGen/MIR/X86/expected-comma-after-cfi-register.mir
M llvm/test/CodeGen/MIR/X86/expected-comma-after-memory-operand.mir
M llvm/test/CodeGen/MIR/X86/expected-different-implicit-operand.mir
M llvm/test/CodeGen/MIR/X86/expected-different-implicit-register-flag.mir
M llvm/test/CodeGen/MIR/X86/expected-function-reference-after-blockaddress.mir
M llvm/test/CodeGen/MIR/X86/expected-global-value-after-blockaddress.mir
M llvm/test/CodeGen/MIR/X86/expected-integer-after-offset-sign.mir
M llvm/test/CodeGen/MIR/X86/expected-integer-after-tied-def.mir
M llvm/test/CodeGen/MIR/X86/expected-integer-in-successor-weight.mir
M llvm/test/CodeGen/MIR/X86/expected-load-or-store-in-memory-operand.mir
M llvm/test/CodeGen/MIR/X86/expected-machine-operand.mir
M llvm/test/CodeGen/MIR/X86/expected-metadata-node-after-debug-location.mir
M llvm/test/CodeGen/MIR/X86/expected-metadata-node-after-exclaim.mir
M llvm/test/CodeGen/MIR/X86/expected-metadata-node-in-stack-object.mir
M llvm/test/CodeGen/MIR/X86/expected-named-register-in-allocation-hint.mir
M llvm/test/CodeGen/MIR/X86/expected-named-register-in-callee-saved-register.mir
M llvm/test/CodeGen/MIR/X86/expected-named-register-in-functions-livein.mir
M llvm/test/CodeGen/MIR/X86/expected-named-register-livein.mir
M llvm/test/CodeGen/MIR/X86/expected-newline-at-end-of-list.mir
M llvm/test/CodeGen/MIR/X86/expected-number-after-bb.mir
M llvm/test/CodeGen/MIR/X86/expected-offset-after-cfi-operand.mir
M llvm/test/CodeGen/MIR/X86/expected-pointer-value-in-memory-operand.mir
M llvm/test/CodeGen/MIR/X86/expected-positive-alignment-after-align.mir
M llvm/test/CodeGen/MIR/X86/expected-power-of-2-after-align.mir
M llvm/test/CodeGen/MIR/X86/expected-register-after-cfi-operand.mir
M llvm/test/CodeGen/MIR/X86/expected-register-after-flags.mir
M llvm/test/CodeGen/MIR/X86/expected-size-integer-after-memory-operation.mir
M llvm/test/CodeGen/MIR/X86/expected-size-integer-after-memory-operation2.mir
M llvm/test/CodeGen/MIR/X86/expected-stack-object-function-context.mir
M llvm/test/CodeGen/MIR/X86/expected-stack-object.mir
M llvm/test/CodeGen/MIR/X86/expected-subregister-after-colon.mir
M llvm/test/CodeGen/MIR/X86/expected-target-flag-name.mir
M llvm/test/CodeGen/MIR/X86/expected-tied-def-after-lparen.mir
M llvm/test/CodeGen/MIR/X86/expected-value-in-memory-operand.mir
M llvm/test/CodeGen/MIR/X86/expected-virtual-register-in-functions-livein.mir
M llvm/test/CodeGen/MIR/X86/external-symbol-operands.mir
M llvm/test/CodeGen/MIR/X86/fastmath.mir
M llvm/test/CodeGen/MIR/X86/frame-info-save-restore-points.mir
M llvm/test/CodeGen/MIR/X86/frame-info-stack-references.mir
M llvm/test/CodeGen/MIR/X86/frame-setup-instruction-flag.mir
M llvm/test/CodeGen/MIR/X86/function-liveins.mir
M llvm/test/CodeGen/MIR/X86/generic-instr-type.mir
M llvm/test/CodeGen/MIR/X86/global-value-operands.mir
M llvm/test/CodeGen/MIR/X86/immediate-operands.mir
M llvm/test/CodeGen/MIR/X86/implicit-register-flag.mir
M llvm/test/CodeGen/MIR/X86/inline-asm-registers.mir
M llvm/test/CodeGen/MIR/X86/instr-cfi-type.mir
M llvm/test/CodeGen/MIR/X86/instr-heap-alloc-operands.mir
M llvm/test/CodeGen/MIR/X86/instr-pcsections.mir
M llvm/test/CodeGen/MIR/X86/instr-symbols-and-mcsymbol-operands.mir
M llvm/test/CodeGen/MIR/X86/instructions-debug-location.mir
M llvm/test/CodeGen/MIR/X86/invalid-constant-pool-item.mir
M llvm/test/CodeGen/MIR/X86/invalid-metadata-node-type.mir
M llvm/test/CodeGen/MIR/X86/invalid-target-flag-name.mir
M llvm/test/CodeGen/MIR/X86/invalid-tied-def-index-error.mir
M llvm/test/CodeGen/MIR/X86/jump-table-info.mir
M llvm/test/CodeGen/MIR/X86/jump-table-redefinition-error.mir
M llvm/test/CodeGen/MIR/X86/killed-register-flag.mir
M llvm/test/CodeGen/MIR/X86/large-cfi-offset-number-error.mir
M llvm/test/CodeGen/MIR/X86/large-immediate-operand-error.mir
M llvm/test/CodeGen/MIR/X86/large-index-number-error.mir
M llvm/test/CodeGen/MIR/X86/large-offset-number-error.mir
M llvm/test/CodeGen/MIR/X86/large-size-in-memory-operand-error.mir
M llvm/test/CodeGen/MIR/X86/liveout-register-mask.mir
M llvm/test/CodeGen/MIR/X86/load-with-max-alignment.mir
M llvm/test/CodeGen/MIR/X86/machine-basic-block-operands.mir
M llvm/test/CodeGen/MIR/X86/machine-instructions.mir
M llvm/test/CodeGen/MIR/X86/machine-verifier-address.mir
M llvm/test/CodeGen/MIR/X86/machine-verifier.mir
M llvm/test/CodeGen/MIR/X86/memory-operands.mir
M llvm/test/CodeGen/MIR/X86/metadata-operands.mir
M llvm/test/CodeGen/MIR/X86/mircanon-flags.mir
M llvm/test/CodeGen/MIR/X86/missing-closing-quote.mir
M llvm/test/CodeGen/MIR/X86/missing-comma.mir
M llvm/test/CodeGen/MIR/X86/missing-implicit-operand.mir
M llvm/test/CodeGen/MIR/X86/named-registers.mir
M llvm/test/CodeGen/MIR/X86/newline-handling.mir
M llvm/test/CodeGen/MIR/X86/null-register-operands.mir
M llvm/test/CodeGen/MIR/X86/register-mask-operands.mir
M llvm/test/CodeGen/MIR/X86/register-operand-class-invalid0.mir
M llvm/test/CodeGen/MIR/X86/register-operand-class-invalid1.mir
M llvm/test/CodeGen/MIR/X86/register-operand-class.mir
M llvm/test/CodeGen/MIR/X86/register-operands-target-flag-error.mir
M llvm/test/CodeGen/MIR/X86/renamable-register-flag.mir
M llvm/test/CodeGen/MIR/X86/simple-register-allocation-hints.mir
M llvm/test/CodeGen/MIR/X86/spill-slot-fixed-stack-object-aliased.mir
M llvm/test/CodeGen/MIR/X86/spill-slot-fixed-stack-object-immutable.mir
M llvm/test/CodeGen/MIR/X86/spill-slot-fixed-stack-objects.mir
M llvm/test/CodeGen/MIR/X86/stack-object-debug-info.mir
M llvm/test/CodeGen/MIR/X86/stack-object-invalid-name.mir
M llvm/test/CodeGen/MIR/X86/stack-object-operand-name-mismatch-error.mir
M llvm/test/CodeGen/MIR/X86/stack-object-redefinition-error.mir
M llvm/test/CodeGen/MIR/X86/stack-objects.mir
M llvm/test/CodeGen/MIR/X86/standalone-register-error.mir
M llvm/test/CodeGen/MIR/X86/subreg-on-physreg.mir
M llvm/test/CodeGen/MIR/X86/subregister-index-operands.mir
M llvm/test/CodeGen/MIR/X86/subregister-operands.mir
M llvm/test/CodeGen/MIR/X86/successor-basic-blocks-weights.mir
M llvm/test/CodeGen/MIR/X86/successor-basic-blocks.mir
M llvm/test/CodeGen/MIR/X86/tied-def-operand-invalid.mir
M llvm/test/CodeGen/MIR/X86/tied-physical-regs-match.mir
M llvm/test/CodeGen/MIR/X86/undef-register-flag.mir
M llvm/test/CodeGen/MIR/X86/undefined-fixed-stack-object.mir
M llvm/test/CodeGen/MIR/X86/undefined-global-value.mir
M llvm/test/CodeGen/MIR/X86/undefined-ir-block-in-blockaddress.mir
M llvm/test/CodeGen/MIR/X86/undefined-ir-block-slot-in-blockaddress.mir
M llvm/test/CodeGen/MIR/X86/undefined-jump-table-id.mir
M llvm/test/CodeGen/MIR/X86/undefined-named-global-value.mir
M llvm/test/CodeGen/MIR/X86/undefined-register-class.mir
M llvm/test/CodeGen/MIR/X86/undefined-stack-object.mir
M llvm/test/CodeGen/MIR/X86/undefined-value-in-memory-operand.mir
M llvm/test/CodeGen/MIR/X86/undefined-virtual-register.mir
M llvm/test/CodeGen/MIR/X86/unexpected-type-phys.mir
M llvm/test/CodeGen/MIR/X86/unknown-instruction.mir
M llvm/test/CodeGen/MIR/X86/unknown-machine-basic-block.mir
M llvm/test/CodeGen/MIR/X86/unknown-metadata-keyword.mir
M llvm/test/CodeGen/MIR/X86/unknown-metadata-node.mir
M llvm/test/CodeGen/MIR/X86/unknown-named-machine-basic-block.mir
M llvm/test/CodeGen/MIR/X86/unknown-register.mir
M llvm/test/CodeGen/MIR/X86/unknown-subregister-index-op.mir
M llvm/test/CodeGen/MIR/X86/unknown-subregister-index.mir
M llvm/test/CodeGen/MIR/X86/unrecognized-character.mir
M llvm/test/CodeGen/MIR/X86/variable-sized-stack-object-size-error.mir
M llvm/test/CodeGen/MIR/X86/variable-sized-stack-objects.mir
M llvm/test/CodeGen/MIR/X86/virtual-register-redefinition-error.mir
M llvm/test/CodeGen/MIR/X86/virtual-registers.mir
M llvm/test/DebugInfo/MIR/InstrRef/instr-ref-roundtrip.mir
M llvm/test/DebugInfo/MIR/InstrRef/livedebugvalues_illegal_locs.mir
M llvm/test/DebugInfo/MIR/InstrRef/livedebugvalues_instrref_tolocs.mir
M llvm/test/DebugInfo/MIR/InstrRef/livedebugvalues_recover_clobbers.mir
M llvm/test/DebugInfo/MIR/InstrRef/livedebugvalues_stackslot_subregs.mir
M llvm/test/DebugInfo/MIR/InstrRef/livedebugvalues_subreg_substitutions.mir
M llvm/test/DebugInfo/MIR/InstrRef/memory-operand-tracking.mir
M llvm/test/DebugInfo/MIR/InstrRef/no-duplicates.mir
M llvm/test/DebugInfo/MIR/InstrRef/no-metainstrs.mir
M llvm/test/DebugInfo/MIR/InstrRef/out-of-scope-blocks.mir
M llvm/test/DebugInfo/MIR/InstrRef/pretty-print.mir
M llvm/test/DebugInfo/MIR/InstrRef/single-assign-propagation.mir
M llvm/test/DebugInfo/MIR/InstrRef/substitusions-roundtrip.mir
M llvm/test/DebugInfo/MIR/X86/dbginfo-entryvals.mir
M llvm/test/DebugInfo/MIR/X86/live-debug-values-restore.mir
M llvm/test/DebugInfo/MIR/X86/livedebugvalues-ignores-metaInstructions.mir
M llvm/test/DebugInfo/MIR/X86/livedebugvalues_basic_diamond.mir
M llvm/test/DebugInfo/MIR/X86/livedebugvalues_basic_diamond_match_clobber.mir
M llvm/test/DebugInfo/MIR/X86/livedebugvalues_basic_diamond_match_move.mir
M llvm/test/DebugInfo/MIR/X86/livedebugvalues_basic_diamond_one_clobber.mir
M llvm/test/DebugInfo/MIR/X86/livedebugvalues_basic_diamond_one_move.mir
M llvm/test/DebugInfo/MIR/X86/livedebugvalues_basic_loop.mir
M llvm/test/DebugInfo/MIR/X86/livedebugvalues_bb_to_bb.mir
M llvm/test/DebugInfo/MIR/X86/livedebugvalues_bb_to_bb_clobbered.mir
M llvm/test/DebugInfo/MIR/X86/livedebugvalues_bb_to_bb_move_to_clobber.mir
M llvm/test/DebugInfo/MIR/X86/livedebugvalues_load_in_loop.mir
M llvm/test/DebugInfo/MIR/X86/livedebugvalues_loop_break.mir
M llvm/test/DebugInfo/MIR/X86/livedebugvalues_loop_break_clobbered.mir
M llvm/test/DebugInfo/MIR/X86/livedebugvalues_loop_clobbered.mir
M llvm/test/DebugInfo/MIR/X86/livedebugvalues_loop_diamond.mir
M llvm/test/DebugInfo/MIR/X86/livedebugvalues_loop_diamond_clobber.mir
M llvm/test/DebugInfo/MIR/X86/livedebugvalues_loop_diamond_move.mir
M llvm/test/DebugInfo/MIR/X86/livedebugvalues_loop_early_clobber.mir
M llvm/test/DebugInfo/MIR/X86/livedebugvalues_loop_terminated.mir
M llvm/test/DebugInfo/MIR/X86/livedebugvalues_loop_two_backedge.mir
M llvm/test/DebugInfo/MIR/X86/livedebugvalues_loop_two_backedge_clobbered.mir
M llvm/test/DebugInfo/MIR/X86/livedebugvalues_loop_within_loop.mir
M llvm/test/DebugInfo/MIR/X86/livedebugvalues_loop_within_loop_clobbered.mir
M llvm/test/DebugInfo/MIR/X86/livedebugvalues_loop_within_loop_moved.mir
M llvm/test/DebugInfo/MIR/X86/livedebugvalues_loop_within_loop_outer_moved.mir
M llvm/test/DebugInfo/MIR/X86/livedebugvalues_many_loop_heads.mir
M llvm/test/DebugInfo/MIR/X86/multiple-param-dbg-value-entry.mir
M llvm/test/DebugInfo/MIR/X86/no-cfi-loc.mir
Log Message:
-----------
[MIR,test] Change llc -march=x86-64 to -mtriple=x86_64
Similar to 806761a7629df268c8aed49657aeccffa6bca449
-mtriple= specifies the full target triple while -march= merely sets the
architecture part of the default target triple (e.g. Windows, macOS).
Therefore, -march= is error-prone and not recommended for tests without
a target triple. The issue has been benign as these MIR tests do not
utilize object file format specific detail, but it's good to change
these tests to neighbor files that use -mtriple=x86_64
Commit: e339f0a9daf2e61bd24414c99e49e0170c9a486e
https://github.com/llvm/llvm-project/commit/e339f0a9daf2e61bd24414c99e49e0170c9a486e
Author: Fangrui Song <i at maskray.me>
Date: 2024-12-15 (Sun, 15 Dec 2024)
Changed paths:
M llvm/test/CodeGen/MIR/X86/dbg-value-list.mir
M llvm/test/DebugInfo/MIR/X86/backup-entry-values-usage.mir
M llvm/test/DebugInfo/MIR/X86/complex-entryvalue.mir
M llvm/test/DebugInfo/MIR/X86/entry-value-of-modified-param.mir
M llvm/test/DebugInfo/MIR/X86/entry-value-of-modified-param2.mir
M llvm/test/DebugInfo/MIR/X86/entry-values-diamond-bbs.mir
M llvm/test/DebugInfo/MIR/X86/kill-entry-value-after-diamond-bbs.mir
M llvm/test/DebugInfo/MIR/X86/kill-entry-value-after-diamond-bbs2.mir
M llvm/test/DebugInfo/MIR/X86/live-debug-values-3preds.mir
M llvm/test/DebugInfo/MIR/X86/live-debug-values-spill.mir
M llvm/test/DebugInfo/MIR/X86/live-debug-values.mir
M llvm/test/DebugInfo/MIR/X86/livedebugvalues-limit.mir
M llvm/test/DebugInfo/MIR/X86/piece-entryval.mir
M llvm/test/DebugInfo/MIR/X86/propagate-entry-value-cross-bbs.mir
M llvm/test/DebugInfo/MIR/X86/remove-entry-value-from-loop.mir
Log Message:
-----------
[test] Remove redundant -march=x86-64 when target triple is specified in IR
Commit: 6e8718c3e32225c579a3a974be003c7f38c32a05
https://github.com/llvm/llvm-project/commit/6e8718c3e32225c579a3a974be003c7f38c32a05
Author: Fangrui Song <i at maskray.me>
Date: 2024-12-15 (Sun, 15 Dec 2024)
Changed paths:
M llvm/test/CodeGen/ARC/addrmode.ll
M llvm/test/CodeGen/ARC/alu.ll
M llvm/test/CodeGen/ARC/brcc.ll
M llvm/test/CodeGen/ARC/call.ll
M llvm/test/CodeGen/ARC/intrinsics.ll
M llvm/test/CodeGen/ARC/ldst.ll
Log Message:
-----------
[ARC,test] Change llc -march= to -mtriple=
Similar to 806761a7629df268c8aed49657aeccffa6bca449
-mtriple= specifies the full target triple while -march= merely sets the
architecture part of the default target triple (e.g. Windows, macOS),
leaving a target triple which may not make sense.
Therefore, -march= is error-prone and not recommended for tests without
a target triple. The issue has been benign as we recognize
arc-apple-darwin as ELF instead of rejecting it outrightly.
Commit: 133352feb30605ec51b15f77826ed3a2fbf8db56
https://github.com/llvm/llvm-project/commit/133352feb30605ec51b15f77826ed3a2fbf8db56
Author: Fangrui Song <i at maskray.me>
Date: 2024-12-15 (Sun, 15 Dec 2024)
Changed paths:
M llvm/test/CodeGen/AArch64/stack-tagging-ex-2.ll
M llvm/test/CodeGen/Hexagon/autohvx/float-cost.ll
M llvm/test/CodeGen/Hexagon/autohvx/interleave.ll
M llvm/test/CodeGen/Hexagon/autohvx/maximize-bandwidth.ll
M llvm/test/CodeGen/Hexagon/bug15515-shuffle.ll
M llvm/test/CodeGen/Hexagon/const-pool-tf.ll
M llvm/test/CodeGen/Hexagon/glob-align-volatile.ll
M llvm/test/CodeGen/Hexagon/loop-idiom/pmpy-infinite-loop.ll
M llvm/test/CodeGen/Hexagon/loop-idiom/pmpy-long-loop.ll
M llvm/test/CodeGen/Hexagon/loop-idiom/pmpy-mod.ll
M llvm/test/CodeGen/Hexagon/loop-idiom/pmpy-shiftconv-fail.ll
M llvm/test/CodeGen/Hexagon/vcombine_zero_diff_ptrs.ll
M llvm/test/CodeGen/Lanai/delay_filler.ll
M llvm/test/CodeGen/Lanai/lowering-128.ll
M llvm/test/CodeGen/NVPTX/surf-read.ll
M llvm/test/CodeGen/NVPTX/surf-write.ll
M llvm/test/CodeGen/NVPTX/tex-read.ll
M llvm/test/CodeGen/PowerPC/ppc64le-aggregates.ll
M llvm/test/CodeGen/Thumb2/bug-subw.ll
M llvm/test/DebugInfo/NVPTX/debug-ptx-symbols.ll
M llvm/test/DebugInfo/X86/instr-ref-flag.ll
M llvm/test/DebugInfo/X86/no-entry-values-with-O0.ll
M llvm/test/DebugInfo/X86/single-dbg_value.ll
M llvm/test/Transforms/LoadStoreVectorizer/NVPTX/propagate-invariance-metadata.ll
M llvm/test/Transforms/StraightLineStrengthReduce/NVPTX/reassociate-geps-and-slsr.ll
M llvm/test/Transforms/StraightLineStrengthReduce/NVPTX/speculative-slsr.ll
Log Message:
-----------
[test] Remove redundant -march= when target triple is specified in IR
Commit: 43045051d4114f2490bf0e6b01a7969d5c27ee04
https://github.com/llvm/llvm-project/commit/43045051d4114f2490bf0e6b01a7969d5c27ee04
Author: Florian Hahn <flo at fhahn.com>
Date: 2024-12-15 (Sun, 15 Dec 2024)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
M llvm/test/Transforms/LoopVectorize/PowerPC/vplan-force-tail-with-evl.ll
M llvm/test/Transforms/LoopVectorize/first-order-recurrence-sink-replicate-region.ll
M llvm/test/Transforms/LoopVectorize/icmp-uniforms.ll
M llvm/test/Transforms/LoopVectorize/vplan-iv-transforms.ll
M llvm/test/Transforms/LoopVectorize/vplan-printing.ll
M llvm/test/Transforms/LoopVectorize/vplan-sink-scalars-and-merge.ll
Log Message:
-----------
[VPlan] Modernize VPWidenIntOrFpInductionRecipe printing (NFC).
Modernize VPWidenIntOrFpInductionRecipe printing by including the result
VPValue and all operand VPValues, similar to VPScalarIVStepsRecipe and
VPDerivedIVRecipe.
Commit: 8d550aa0f027eb2cf32850f3905dc1db22317587
https://github.com/llvm/llvm-project/commit/8d550aa0f027eb2cf32850f3905dc1db22317587
Author: Fangrui Song <i at maskray.me>
Date: 2024-12-15 (Sun, 15 Dec 2024)
Changed paths:
M llvm/test/CodeGen/X86/stack-frame-layout-remarks.ll
Log Message:
-----------
[test] Replace -march=x86 -mcpu=i386 with -mtriple
Commit: cd12922235f14a78eeed25fabf364950d02cb786
https://github.com/llvm/llvm-project/commit/cd12922235f14a78eeed25fabf364950d02cb786
Author: Fangrui Song <i at maskray.me>
Date: 2024-12-15 (Sun, 15 Dec 2024)
Changed paths:
M llvm/test/Analysis/CostModel/X86/scalarize.ll
M llvm/test/CodeGen/MIR/X86/fixed-stack-memory-operands.mir
M llvm/test/CodeGen/MIR/X86/fixed-stack-object-redefinition-error.mir
M llvm/test/CodeGen/MIR/X86/fixed-stack-objects.mir
M llvm/test/CodeGen/MIR/X86/stack-object-operands.mir
M llvm/test/CodeGen/X86/2006-10-02-BoolRetCrash.ll
M llvm/test/MachineVerifier/test_copy_physregs_x86.mir
M llvm/test/MachineVerifier/verify-regops.mir
M llvm/test/Transforms/NaryReassociate/NVPTX/nary-slsr.ll
Log Message:
-----------
[test] Change llc -march= to -mtriple=
Similar to 806761a7629df268c8aed49657aeccffa6bca449
-march= is error-prone when running on a host whose OS is different.
Commit: 7168de5ca7a09b929006bd0fb5c3d9510c0ba058
https://github.com/llvm/llvm-project/commit/7168de5ca7a09b929006bd0fb5c3d9510c0ba058
Author: Jacek Caban <jacek at codeweavers.com>
Date: 2024-12-15 (Sun, 15 Dec 2024)
Changed paths:
M lld/COFF/COFFLinkerContext.h
M lld/COFF/Driver.cpp
M lld/COFF/InputFiles.cpp
M lld/COFF/InputFiles.h
M lld/COFF/SymbolTable.h
M lld/test/COFF/arm64ec-codemap.test
M lld/test/COFF/arm64ec-entry-thunk.s
M lld/test/COFF/arm64ec-lib.test
M lld/test/COFF/arm64ec-range-thunks.s
R lld/test/COFF/arm64x-symtab.s
Log Message:
-----------
Revert "[LLD][COFF] Introduce hybrid symbol table for EC input files on ARM64X (#119294)"
This reverts commit a8206e7b37929f4754806667680ffba0206eef95 due to sanitizer failures.
Commit: e86910337f98e57f5b9253f7d80d5b916eb1d97e
https://github.com/llvm/llvm-project/commit/e86910337f98e57f5b9253f7d80d5b916eb1d97e
Author: Ryosuke Niwa <rniwa at webkit.org>
Date: 2024-12-15 (Sun, 15 Dec 2024)
Changed paths:
M clang/lib/StaticAnalyzer/Checkers/WebKit/UncountedLambdaCapturesChecker.cpp
M clang/test/Analysis/Checkers/WebKit/uncounted-lambda-captures.cpp
Log Message:
-----------
[webkit.UncountedLambdaCapturesChecker] Add a fallback for checking lambda captures (#119800)
Commit: 938cdd60d4938e32a7f4f1620e3d9c11aabc4af5
https://github.com/llvm/llvm-project/commit/938cdd60d4938e32a7f4f1620e3d9c11aabc4af5
Author: Oleksandr "Alex" Zinenko <git at ozinenko.com>
Date: 2024-12-15 (Sun, 15 Dec 2024)
Changed paths:
M mlir/lib/Dialect/Transform/Transforms/CheckUses.cpp
M mlir/test/Dialect/Transform/check-use-after-free.mlir
Log Message:
-----------
correctly check uses of pattern descriptor transform ops (#118791)
In the transform dialect use-after-free chcker pass, account for pattern
descriptor operations that intentionally have no declared side effects.
They are not destroying any handles.
Closes #118761.
Commit: 1c352e66e7bac03a654cbd4c13c3bec6ed346048
https://github.com/llvm/llvm-project/commit/1c352e66e7bac03a654cbd4c13c3bec6ed346048
Author: Oleksandr "Alex" Zinenko <git at ozinenko.com>
Date: 2024-12-15 (Sun, 15 Dec 2024)
Changed paths:
M mlir/include/mlir/Dialect/Transform/IR/TransformOps.td
M mlir/lib/Dialect/Transform/IR/TransformOps.cpp
M mlir/test/Dialect/Transform/test-interpreter.mlir
Log Message:
-----------
make transform.split_handle accept any handle kind (#118752)
It can now split value and parameter handles in addition to operation
handles. This is a generally useful functionality.
Commit: d072ca1a496cc3f4ad0adf6f7d43f76406a704d6
https://github.com/llvm/llvm-project/commit/d072ca1a496cc3f4ad0adf6f7d43f76406a704d6
Author: Oleksandr "Alex" Zinenko <git at ozinenko.com>
Date: 2024-12-15 (Sun, 15 Dec 2024)
Changed paths:
M mlir/include/mlir/Dialect/Func/IR/FuncOps.td
M mlir/lib/Dialect/Func/Extensions/InlinerExtension.cpp
M mlir/test/Transforms/inlining.mlir
Log Message:
-----------
[mlir] add noinline attribute to func.func/call (#119970)
This allows for inlining to be somewhat controlled by the user instead
of always inlining everything. External heuristics may be used to place
`no_inline` attributes on invidiual calls or functions to prevent
inlining.
Commit: 8345a95a404cb490918201274da877b8ca2edf51
https://github.com/llvm/llvm-project/commit/8345a95a404cb490918201274da877b8ca2edf51
Author: William Moses <gh at wsmoses.com>
Date: 2024-12-15 (Sun, 15 Dec 2024)
Changed paths:
M mlir/include/mlir-c/Dialect/LLVM.h
M mlir/lib/CAPI/Dialect/LLVM.cpp
Log Message:
-----------
MLIR-C: Add accessor for LLVM array type (#119998)
Commit: 646ad49eacea19cfd656145cd41ae5ef99029a97
https://github.com/llvm/llvm-project/commit/646ad49eacea19cfd656145cd41ae5ef99029a97
Author: Lang Hames <lhames at gmail.com>
Date: 2024-12-16 (Mon, 16 Dec 2024)
Changed paths:
M llvm/tools/llvm-jitlink/llvm-jitlink.cpp
Log Message:
-----------
[llvm-jitlink] Avoid some SymbolStringPtr copies.
Commit: 8daf4f16fa08b5d876e98108721dd1743a360326
https://github.com/llvm/llvm-project/commit/8daf4f16fa08b5d876e98108721dd1743a360326
Author: Lang Hames <lhames at gmail.com>
Date: 2024-12-15 (Sun, 15 Dec 2024)
Changed paths:
M compiler-rt/lib/orc/CMakeLists.txt
A compiler-rt/lib/orc/sysv_reenter.x86-64.S
M compiler-rt/test/orc/TestCases/Generic/lazy-link.ll
M llvm/include/llvm/ExecutionEngine/JITLink/x86_64.h
M llvm/lib/ExecutionEngine/JITLink/x86_64.cpp
M llvm/lib/ExecutionEngine/Orc/JITLinkReentryTrampolines.cpp
Log Message:
-----------
[ORC][ORC-RT] Add ORC-RT based lazy compilation support for x86-64.
Adds support for the ORC-RT based lazy compilation scheme that was introduced
in 570ecdcf8b4.
Commit: f86f4574bbab9cb8c998f9e6560c68696c45f90f
https://github.com/llvm/llvm-project/commit/f86f4574bbab9cb8c998f9e6560c68696c45f90f
Author: Maksim Panchenko <maks at fb.com>
Date: 2024-12-15 (Sun, 15 Dec 2024)
Changed paths:
M bolt/test/X86/linux-static-keys.s
Log Message:
-----------
[BOLT][Linux] Fix static keys test case (#119771)
The key address in the static keys jump table was incorrectly encoded as
an absolute value instead of PC-relative causing incorrect
interpretation of the "likely" property of the key.
Commit: ca60ee2b8c57034175f590f0aff5978a066569a0
https://github.com/llvm/llvm-project/commit/ca60ee2b8c57034175f590f0aff5978a066569a0
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-12-15 (Sun, 15 Dec 2024)
Changed paths:
M llvm/lib/CodeGen/MachineVerifier.cpp
M llvm/test/MachineVerifier/test_abd_su.mir
Log Message:
-----------
[GISel] Remove unnecessary MachineVerifier checks for G_ABDS/G_ABDU. (#120014)
These are declared to use a single type index for all operands in
GenericOpcodes.td and the verifier knows how to check that all operands
with the same type index match.
Commit: 73eecb70c2abb1c6149647ec213cb9312c398569
https://github.com/llvm/llvm-project/commit/73eecb70c2abb1c6149647ec213cb9312c398569
Author: Sergei Barannikov <barannikov88 at gmail.com>
Date: 2024-12-16 (Mon, 16 Dec 2024)
Changed paths:
M llvm/utils/TableGen/Common/CodeGenTarget.cpp
M llvm/utils/TableGen/Common/CodeGenTarget.h
M llvm/utils/TableGen/GlobalISelEmitter.cpp
Log Message:
-----------
[TableGen][GISel] Don't use std::optional with pointers (NFC) (#120026)
Pointers already have a well-defined null value.
Commit: bb18e49edb2c4bbb7dd70ee0b5946598822a4e2a
https://github.com/llvm/llvm-project/commit/bb18e49edb2c4bbb7dd70ee0b5946598822a4e2a
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2024-12-16 (Mon, 16 Dec 2024)
Changed paths:
M llvm/include/llvm/IR/DiagnosticInfo.h
M llvm/lib/CodeGen/RegAllocBase.cpp
M llvm/lib/CodeGen/RegAllocFast.cpp
M llvm/lib/IR/DiagnosticInfo.cpp
M llvm/test/CodeGen/AArch64/arm64-anyregcc-crash.ll
M llvm/test/CodeGen/AMDGPU/illegal-eviction-assert.mir
M llvm/test/CodeGen/AMDGPU/issue48473.mir
A llvm/test/CodeGen/AMDGPU/ran-out-of-registers-error-all-regs-reserved.ll
A llvm/test/CodeGen/AMDGPU/ran-out-of-registers-errors.ll
M llvm/test/CodeGen/AMDGPU/remaining-virtual-register-operands.ll
M llvm/test/CodeGen/PowerPC/ppc64-anyregcc-crash.ll
M llvm/test/CodeGen/X86/anyregcc-crash.ll
Log Message:
-----------
RegAlloc: Use DiagnosticInfo to report register allocation failures (#119492)
Improve the non-fatal cases to use DiagnosticInfo, which will now
provide a location. The allocators attempt to report different errors
if it happens to see inline assembly is involved (this detection is
quite unreliable) using srcloc instead of dbgloc. For now, leave this
behavior unchanged. I think reporting the full location and context
function would be more useful.
Commit: 61f99a1c75e9dc84b70d6f2a660e99c1ac182e5b
https://github.com/llvm/llvm-project/commit/61f99a1c75e9dc84b70d6f2a660e99c1ac182e5b
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2024-12-16 (Mon, 16 Dec 2024)
Changed paths:
M llvm/include/llvm/CodeGen/MachineFunction.h
M llvm/lib/CodeGen/MachineFunction.cpp
M llvm/lib/CodeGen/RegAllocBase.cpp
M llvm/lib/CodeGen/RegAllocBase.h
M llvm/lib/CodeGen/RegAllocFast.cpp
M llvm/lib/CodeGen/VirtRegMap.cpp
M llvm/test/CodeGen/AMDGPU/alloc-all-regs-reserved-in-class.mir
M llvm/test/CodeGen/AMDGPU/ran-out-of-registers-error-all-regs-reserved.ll
M llvm/test/CodeGen/AMDGPU/ran-out-of-registers-errors.ll
M llvm/test/CodeGen/AMDGPU/regalloc-illegal-eviction-assert.ll
Log Message:
-----------
RegAlloc: Do not fatal error if there are no registers in the alloc order (#119640)
Try to use DiagnosticInfo if every register in the class is reserved
by forcing assignment to a reserved register. Also reduces the number
of redundant errors emitted, particularly with fast.
This is still broken in the case of undef uses. There are additional
complications in greedy and fast, so leave it for a separate fix.
Commit: 818bffcb1c454da8ec778327bde3d974dfe44550
https://github.com/llvm/llvm-project/commit/818bffcb1c454da8ec778327bde3d974dfe44550
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2024-12-16 (Mon, 16 Dec 2024)
Changed paths:
M llvm/lib/CodeGen/RegAllocFast.cpp
M llvm/lib/CodeGen/RegAllocGreedy.cpp
M llvm/test/CodeGen/AMDGPU/ran-out-of-registers-error-all-regs-reserved.ll
Log Message:
-----------
RegAlloc: Fix failure on undef use when all registers are reserved (#119647)
Greedy and fast would hit different assertions on undef uses if all
registers in a class were reserved.
Commit: 58cd17d960462c63c3a964efe539ae15774a6c66
https://github.com/llvm/llvm-project/commit/58cd17d960462c63c3a964efe539ae15774a6c66
Author: Lang Hames <lhames at gmail.com>
Date: 2024-12-16 (Mon, 16 Dec 2024)
Changed paths:
M llvm/include/llvm/ExecutionEngine/Orc/Core.h
Log Message:
-----------
[ORC] Add comments to ResourceManager to clarify locking rules.
Commit: 4914b188998deb50402405567d5a98186bf0a155
https://github.com/llvm/llvm-project/commit/4914b188998deb50402405567d5a98186bf0a155
Author: Lang Hames <lhames at gmail.com>
Date: 2024-12-16 (Mon, 16 Dec 2024)
Changed paths:
M llvm/include/llvm/ExecutionEngine/Orc/LazyObjectLinkingLayer.h
Log Message:
-----------
[ORC] Fix / add comments for LazyObjectLinkingLayer. NFC.
Also remove some redundant namespace qualification.
Commit: f8ad6e0cdae3cbc1618b19c3c7b41021070c0e94
https://github.com/llvm/llvm-project/commit/f8ad6e0cdae3cbc1618b19c3c7b41021070c0e94
Author: Luke Lau <luke at igalia.com>
Date: 2024-12-16 (Mon, 16 Dec 2024)
Changed paths:
M llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp
Log Message:
-----------
[RISCV][VLOPT] Get MachineInstr from MachineOperand in getOperandInfo. NFC (#119838)
IICU MI should be MO's parent, so just use MachineOperand::getParent().
Commit: 4746395bd75bc234dfd026bad672613b99e87e7a
https://github.com/llvm/llvm-project/commit/4746395bd75bc234dfd026bad672613b99e87e7a
Author: Luke Lau <luke at igalia.com>
Date: 2024-12-16 (Mon, 16 Dec 2024)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
M llvm/test/Transforms/LoopVectorize/AArch64/clamped-trip-count.ll
M llvm/test/Transforms/LoopVectorize/AArch64/divs-with-scalable-vfs.ll
M llvm/test/Transforms/LoopVectorize/AArch64/outer_loop_prefer_scalable.ll
M llvm/test/Transforms/LoopVectorize/AArch64/scalable-avoid-scalarization.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve-inductions-unusual-types.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve-tail-folding.ll
M llvm/test/Transforms/LoopVectorize/RISCV/blocks-with-dead-instructions.ll
M llvm/test/Transforms/LoopVectorize/RISCV/dead-ops-cost.ll
M llvm/test/Transforms/LoopVectorize/RISCV/induction-costs.ll
M llvm/test/Transforms/LoopVectorize/RISCV/mask-index-type.ll
M llvm/test/Transforms/LoopVectorize/RISCV/masked_gather_scatter.ll
M llvm/test/Transforms/LoopVectorize/RISCV/pr87378-vpinstruction-or-drop-poison-generating-flags.ll
M llvm/test/Transforms/LoopVectorize/RISCV/strided-accesses.ll
M llvm/test/Transforms/LoopVectorize/RISCV/uniform-load-store.ll
M llvm/test/Transforms/LoopVectorize/RISCV/vectorize-force-tail-with-evl-cond-reduction.ll
M llvm/test/Transforms/LoopVectorize/RISCV/vectorize-force-tail-with-evl-interleave.ll
M llvm/test/Transforms/LoopVectorize/outer_loop_scalable.ll
Log Message:
-----------
[VPlan] Omit zero add in VPWidenIntOrFpInductionRecipe (#119668)
I'm not sure if getStepVector was used for other things in the past
where StartIdx was non-zero, but nowadays VPWidenIntOrFpInductionRecipe
is the only user of it, and just passes zero to it. I presume
InstCombine was already catching this so hopefully removing this won't
affect codegen.
Commit: 9571d2023bee35f7c0e60a931ce5a4074d034635
https://github.com/llvm/llvm-project/commit/9571d2023bee35f7c0e60a931ce5a4074d034635
Author: Pengcheng Wang <wangpengcheng.pp at bytedance.com>
Date: 2024-12-16 (Mon, 16 Dec 2024)
Changed paths:
M llvm/lib/Target/RISCV/RISCVProcessors.td
M llvm/lib/Target/RISCV/RISCVSubtarget.cpp
M llvm/lib/Target/RISCV/RISCVSubtarget.h
Log Message:
-----------
[RISCV] Add tune info for postra scheduling direction (#115864)
The results differ on different platforms so it is really hard to
determine a common default value.
Tune info for postra scheduling direction is added and CPUs can
set their own preferable postra scheduling direction.
Commit: de1a423c2356d2040cab74e657ed024bf9ce8517
https://github.com/llvm/llvm-project/commit/de1a423c2356d2040cab74e657ed024bf9ce8517
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-12-15 (Sun, 15 Dec 2024)
Changed paths:
M llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
M llvm/test/CodeGen/AArch64/GlobalISel/legalize-threeway-cmp.mir
M llvm/test/CodeGen/AArch64/scmp.ll
M llvm/test/CodeGen/AArch64/ucmp.ll
M llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-threeway-cmp-rv32.mir
M llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-threeway-cmp-rv64.mir
M llvm/test/CodeGen/RISCV/GlobalISel/scmp.ll
M llvm/test/CodeGen/RISCV/GlobalISel/ucmp.ll
Log Message:
-----------
[GISel][RISCV][AArch64] Support legalizing G_SCMP/G_UCMP to sub(isgt,islt). (#119265)
Convert the LLT to EVT and call
TargetLowering::shouldExpandCmpUsingSelects to determine if we should do
this.
We don't have a getSetccResultType, so I'm boolean extending the
compares to the result type and using that. If the compares legalize to
the same type, these extends will get removed. Unfortunately, if the
compares legalize to a different type, we end up with truncates or
extends that might not be optimally placed.
Commit: e4fb30205f1df5156328b234ff2a2866b7035fef
https://github.com/llvm/llvm-project/commit/e4fb30205f1df5156328b234ff2a2866b7035fef
Author: hev <wangrui at loongson.cn>
Date: 2024-12-16 (Mon, 16 Dec 2024)
Changed paths:
M llvm/lib/Target/LoongArch/LoongArchOptWInstrs.cpp
M llvm/test/CodeGen/LoongArch/sextw-removal.ll
Log Message:
-----------
[LoongArch] Adds support for vectors in OptWInstrs (#118935)
Commit: f420d26e9dd7ff6aed435f86e7d6768501a29741
https://github.com/llvm/llvm-project/commit/f420d26e9dd7ff6aed435f86e7d6768501a29741
Author: Lang Hames <lhames at gmail.com>
Date: 2024-12-16 (Mon, 16 Dec 2024)
Changed paths:
M llvm/include/llvm/ExecutionEngine/Orc/ObjectLinkingLayer.h
M llvm/lib/ExecutionEngine/Orc/ObjectLinkingLayer.cpp
Log Message:
-----------
[ORC] Make ObjectLinkingLayerJITLinkContext a private nested class.
This class is an implementation detail, so doesn't need a publicly accessible
name.
Commit: 9ba7e2da009d7128c81e16f5a8e60c9abcb0e83d
https://github.com/llvm/llvm-project/commit/9ba7e2da009d7128c81e16f5a8e60c9abcb0e83d
Author: David Green <david.green at arm.com>
Date: 2024-12-16 (Mon, 16 Dec 2024)
Changed paths:
M llvm/include/llvm/CodeGen/GlobalISel/LegalizationArtifactCombiner.h
M llvm/test/CodeGen/AArch64/GlobalISel/legalize-ext.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-and.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-merge-values.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-or.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-phi.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-shuffle-vector.s16.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-xor.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-zext.mir
Log Message:
-----------
[GlobalISel] Use replaceRegOrBuildCopy when legalizer-combining s/zext(undef) (#119850)
Similar to #119721, this helps remove some of the COPYs created by the
CSE builder.
Commit: b446c208a5f0e2ad7193cc23e70642d207db4d13
https://github.com/llvm/llvm-project/commit/b446c208a5f0e2ad7193cc23e70642d207db4d13
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2024-12-16 (Mon, 16 Dec 2024)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPULibCalls.cpp
M llvm/lib/Target/AMDGPU/AMDGPULibFunc.cpp
M llvm/lib/Target/AMDGPU/AMDGPULibFunc.h
A llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-image-function-signatures.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-ldexp.ll
Log Message:
-----------
AMDGPU: Verify function type matches when matching libcalls (#119043)
Previously this would recognize a call to a mangled ldexp(float, float)
as a candidate to replace with the intrinsic. We need to verify the second
parameter is in fact an integer.
Fixes: SWDEV-501389
Commit: 1100d6a995fe392b3885b8d2bd5afed2bd57e80c
https://github.com/llvm/llvm-project/commit/1100d6a995fe392b3885b8d2bd5afed2bd57e80c
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2024-12-16 (Mon, 16 Dec 2024)
Changed paths:
M clang/test/CodeGenOpenCL/opencl_types.cl
M llvm/lib/Target/AMDGPU/AMDGPULibFunc.cpp
M llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-image-function-signatures.ll
Log Message:
-----------
AMDGPU: Fix libcall recognition of image array types (#119832)
Add tests with get_image_width as a sample for all of the non-extension
image types. The transform doesn't do anything, but this runs through
all the mangled libfunc parsing and shows it does not crash. It would
probably be smarter to check for exact match of the types, rather than
checking the prefix.
Commit: 6dc24f6a2fcf0a199e007dc127ca5a4901a3a24e
https://github.com/llvm/llvm-project/commit/6dc24f6a2fcf0a199e007dc127ca5a4901a3a24e
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-12-15 (Sun, 15 Dec 2024)
Changed paths:
M llvm/lib/CodeGen/MachineVerifier.cpp
M llvm/test/MachineVerifier/test_uscmp.mir
Log Message:
-----------
[GISel] Improve MachineVerifier for G_SCMP/UCMP. (#120017)
-Ensure destination type is at least 2 bits.
-Remove unnecessary check that both sources are the same type. The
verifier already handles this generically.
Commit: 8476ba71f20a6c260c8b55822ce02db45f8252be
https://github.com/llvm/llvm-project/commit/8476ba71f20a6c260c8b55822ce02db45f8252be
Author: Kazu Hirata <kazu at google.com>
Date: 2024-12-15 (Sun, 15 Dec 2024)
Changed paths:
M llvm/test/Transforms/PGOProfile/memprof_match_hot_cold_new_calls.ll
Log Message:
-----------
[memprof] YAMLify one test (NFC) (#119955)
This patch replaces the raw binary profile with a YAML profile.
I've trimmed the profile by removing all MemProfRecords except the one
for _Z3foov.
This patch demonstrates that we can see !memprof generated even with a
YAML profile.
Commit: 62cd735db36c1ba41ba627c8336dfa643ff703af
https://github.com/llvm/llvm-project/commit/62cd735db36c1ba41ba627c8336dfa643ff703af
Author: Yuhao Gu <49391101+yhgu2000 at users.noreply.github.com>
Date: 2024-12-16 (Mon, 16 Dec 2024)
Changed paths:
Log Message:
-----------
[docs] remove some out-of-date content in LLVM Programmer's Manual. (#119565)
Remove the part about implicit conversion from an iterator to a pointer.
This part of the manual was written 14 years ago, in:
https://github.com/llvm/llvm-project/commit/37027c30ec526afe3bb571df6f8701bf0d322f22
There do exist a type casting operator in `ilist` then:
https://github.com/llvm/llvm-project/blob/37027c30ec526afe3bb571df6f8701bf0d322f22/llvm/include/llvm/ADT/ilist.h#L192-L194
But it has been remove since 2016:
https://github.com/llvm/llvm-project/commit/f197b1f78f854d8513ef617b8cfc61860f7b4b84
So I think it makes sense to remove this part to avoid mislead new
contributors.
Commit: 115872902b9b056d42e24273f93a2be7c93d2f54
https://github.com/llvm/llvm-project/commit/115872902b9b056d42e24273f93a2be7c93d2f54
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-12-15 (Sun, 15 Dec 2024)
Changed paths:
M llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
M llvm/test/CodeGen/RISCV/GlobalISel/double-arith.ll
M llvm/test/CodeGen/RISCV/GlobalISel/double-convert.ll
M llvm/test/CodeGen/RISCV/GlobalISel/double-fcmp.ll
M llvm/test/CodeGen/RISCV/GlobalISel/float-arith.ll
M llvm/test/CodeGen/RISCV/GlobalISel/float-convert.ll
M llvm/test/CodeGen/RISCV/GlobalISel/float-fcmp.ll
M llvm/test/CodeGen/RISCV/GlobalISel/float-intrinsics.ll
M llvm/test/CodeGen/RISCV/GlobalISel/fp128.ll
M llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-addo-subo-rv64.mir
M llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-icmp-rv64.mir
M llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-sat-rv64.mir
M llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-umax-rv64.mir
M llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-umin-rv64.mir
M llvm/test/CodeGen/RISCV/GlobalISel/rv64zbb.ll
M llvm/test/CodeGen/RISCV/GlobalISel/ucmp.ll
Log Message:
-----------
[GISel][RISCV] Use isSExtCheaperThanZExt when widening G_ICMP. (#120032)
Sign extending i32->i64 is more efficient than zero extend for RV64.
Commit: 54dac27c57d05d3f5c33bd4ec878bcb0a9c7cb71
https://github.com/llvm/llvm-project/commit/54dac27c57d05d3f5c33bd4ec878bcb0a9c7cb71
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-12-15 (Sun, 15 Dec 2024)
Changed paths:
M llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
M llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-umax-rv64.mir
M llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-umin-rv64.mir
M llvm/test/CodeGen/RISCV/GlobalISel/rv64zbb.ll
Log Message:
-----------
[GISel][RISCV] Use isSExtCheaperThanZExt when widening G_UMAX/G_UMIN. (#120041)
Similar to what we do for unsigned comparisons after #120032.
Commit: f65a21a4ecc2e712c700c59842b6b9a1d2a9a060
https://github.com/llvm/llvm-project/commit/f65a21a4ecc2e712c700c59842b6b9a1d2a9a060
Author: Daniil Kovalev <dkovalev at accesssoftek.com>
Date: 2024-12-16 (Mon, 16 Dec 2024)
Changed paths:
M clang/lib/CodeGen/CodeGenModule.cpp
M clang/test/CodeGen/ptrauth-module-flags.c
M llvm/include/llvm/CodeGen/MachineModuleInfoImpls.h
M llvm/include/llvm/CodeGen/TargetLoweringObjectFileImpl.h
M llvm/include/llvm/Target/TargetLoweringObjectFile.h
M llvm/lib/CodeGen/AsmPrinter/DwarfCFIException.cpp
M llvm/lib/CodeGen/MachineModuleInfoImpls.cpp
M llvm/lib/CodeGen/TargetLoweringObjectFileImpl.cpp
M llvm/lib/Target/AArch64/AArch64TargetObjectFile.cpp
M llvm/lib/Target/AArch64/AArch64TargetObjectFile.h
M llvm/lib/Target/AArch64/MCTargetDesc/AArch64TargetStreamer.cpp
M llvm/lib/Target/AArch64/MCTargetDesc/AArch64TargetStreamer.h
M llvm/lib/Target/TargetLoweringObjectFile.cpp
A llvm/test/CodeGen/AArch64/ptrauth-sign-personality.ll
Log Message:
-----------
[PAC][ELF][AArch64] Support signed personality function pointer (#119361)
Re-apply #113148 after revert in #119331
If function pointer signing is enabled, sign personality function
pointer stored in `.DW.ref.__gxx_personality_v0` section with IA key,
0x7EAD = `ptrauth_string_discriminator("personality")` constant
discriminator and address diversity enabled.
Commit: a3db5910b434d746c9c0585a092100ff7abcd1a0
https://github.com/llvm/llvm-project/commit/a3db5910b434d746c9c0585a092100ff7abcd1a0
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2024-12-16 (Mon, 16 Dec 2024)
Changed paths:
M llvm/lib/CodeGen/RegAllocBase.cpp
Log Message:
-----------
RegAllocBase: Avoid using temporary DiagnosticInfo (#120046)
Commit: 003fb2aeb49dc7440cab7e009bd264f8f42fc8dc
https://github.com/llvm/llvm-project/commit/003fb2aeb49dc7440cab7e009bd264f8f42fc8dc
Author: Yingwei Zheng <dtcxzyw2333 at gmail.com>
Date: 2024-12-16 (Mon, 16 Dec 2024)
Changed paths:
M llvm/lib/Transforms/Scalar/ConstraintElimination.cpp
A llvm/test/Transforms/ConstraintElimination/sub-nsw.ll
Log Message:
-----------
[ConstraintElim] Decompose `sub nsw` (#118219)
Closes https://github.com/llvm/llvm-project/issues/118211.
Commit: b4c1f0cc492f1597397dcf0b06b816fa0a2135f1
https://github.com/llvm/llvm-project/commit/b4c1f0cc492f1597397dcf0b06b816fa0a2135f1
Author: David Spickett <david.spickett at linaro.org>
Date: 2024-12-16 (Mon, 16 Dec 2024)
Changed paths:
M lldb/test/API/CMakeLists.txt
Log Message:
-----------
[lldb][test] Prefer gmake to make and warn for potentially non-GNU make (#119573)
System make on FreeBSD is missing some GNU make features so out of the
box you get a lot of:
```
make: "<...>/Makefile.rules" line 569: Invalid line type
```
To solve this, you can install gmake which is a port of GNU make.
However because we prefer 'make', gmake won't be used unless you set
LLDB_TEST_MAKE.
To fix that, prefer 'gmake'. Also check (as best we can) that the make
we found is GNU make. This won't be perfect but it's better than the
cryptic error shown above.
```
-- Found make: /usr/bin/make
CMake Warning at /home/ec2-user/llvm-project/lldb/test/API/CMakeLists.txt:63 (message):
'make' tool /usr/bin/make may not be GNU make compatible. Some tests may
fail to build. Provide a GNU compatible 'make' tool by setting
LLDB_TEST_MAKE.
```
When a make isn't found at all, the warning message will show the names
we tried:
```
-- Did not find one of: gmake make
CMake Warning at /home/ec2-user/llvm-project/lldb/test/API/CMakeLists.txt:69 (message):
Many LLDB API tests require a 'make' tool. Please provide it in Path or
pass via LLDB_TEST_MAKE.
```
Commit: a35db2880a488b62a16f269972ad885fd58033f7
https://github.com/llvm/llvm-project/commit/a35db2880a488b62a16f269972ad885fd58033f7
Author: David Green <david.green at arm.com>
Date: 2024-12-16 (Mon, 16 Dec 2024)
Changed paths:
M llvm/include/llvm/CodeGen/GlobalISel/GIMatchTableExecutorImpl.h
M llvm/include/llvm/CodeGen/GlobalISel/LegalizationArtifactCombiner.h
M llvm/lib/CodeGen/BranchFolding.cpp
M llvm/lib/CodeGen/GlobalISel/CSEInfo.cpp
M llvm/lib/CodeGen/MIRCanonicalizerPass.cpp
M llvm/lib/CodeGen/MachineCombiner.cpp
M llvm/lib/CodeGen/MachineLateInstrsCleanup.cpp
M llvm/lib/CodeGen/MachineOutliner.cpp
M llvm/lib/CodeGen/MachinePipeliner.cpp
M llvm/lib/CodeGen/ModuloSchedule.cpp
M llvm/lib/CodeGen/ScheduleDAGInstrs.cpp
M llvm/lib/CodeGen/SelectionDAG/FastISel.cpp
M llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
M llvm/lib/Target/AArch64/AArch64PBQPRegAlloc.cpp
M llvm/lib/Target/ARM/ARMISelLowering.cpp
M llvm/lib/Target/ARM/Thumb2ITBlockPass.cpp
Log Message:
-----------
[NFC] Remove some unnecessary semicolons
All inside LLVM_DEBUG, some of which have been cleaned up by adding block
scopes to allow them to format more nicely.
Commit: a24645463bd8a758005f4e5fdcd78971f87e3ba1
https://github.com/llvm/llvm-project/commit/a24645463bd8a758005f4e5fdcd78971f87e3ba1
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2024-12-16 (Mon, 16 Dec 2024)
Changed paths:
M .ci/monolithic-linux.sh
M .ci/monolithic-windows.sh
Log Message:
-----------
[CI] Only upload test results if buildkite-agent is present (#119954)
This patch modifies the monolithic shell scrips to only run if the
buildkite-agent application is present. This allows for running the
scripts to completion outside of buildkite (eg inside of a GHA
pipeline).
Commit: 2503a6659621e27e6b4c5946c3acff7a5b9dadca
https://github.com/llvm/llvm-project/commit/2503a6659621e27e6b4c5946c3acff7a5b9dadca
Author: Timm Bäder <tbaeder at redhat.com>
Date: 2024-12-16 (Mon, 16 Dec 2024)
Changed paths:
M clang/lib/AST/ByteCode/Integral.h
M clang/lib/AST/ByteCode/Interp.h
M clang/test/AST/ByteCode/shifts.cpp
Log Message:
-----------
Reapply "[clang][bytecode] Fix some shift edge cases (#119895)"
This reverts commit a6636ce4d124176856c3913d4bf6c3ceff1f5a1f.
This original commit failed on hosts with signed wchar_t. Care for
this in the test.
Commit: 92a4f4dda5796049b6dbeb5ed89384380bff97d9
https://github.com/llvm/llvm-project/commit/92a4f4dda5796049b6dbeb5ed89384380bff97d9
Author: Vadim D. <vvd170501 at gmail.com>
Date: 2024-12-16 (Mon, 16 Dec 2024)
Changed paths:
M clang/lib/Tooling/Inclusions/Stdlib/StdSpecialSymbolMap.inc
M clang/lib/Tooling/Inclusions/Stdlib/StdSymbolMap.inc
Log Message:
-----------
[Tooling/Inclusion] Update std symbol mapping (#118174)
This adds new symbols to the generated mapping and removes special
mappings for missing symbols introduced in #113612, as these symbols are
now included in the generated mapping.
Commit: e0fb3acd8a0b2a9340b9b2ae370c84c98f1a5cc2
https://github.com/llvm/llvm-project/commit/e0fb3acd8a0b2a9340b9b2ae370c84c98f1a5cc2
Author: Sander de Smalen <sander.desmalen at arm.com>
Date: 2024-12-16 (Mon, 16 Dec 2024)
Changed paths:
M compiler-rt/lib/builtins/aarch64/sme-abi.S
M compiler-rt/lib/builtins/aarch64/sme-libc-mem-routines.S
Log Message:
-----------
[compiler-rt][AArch64] Allow platform-specific mangling of SME routines. (#119864)
Support platform-specific mangling to avoid the compiler emitting a call
to a function that is mangled differently than the definition in the
runtime library.
Commit: ace87ec04cd588e5fbe393c3b642bd759a7abadb
https://github.com/llvm/llvm-project/commit/ace87ec04cd588e5fbe393c3b642bd759a7abadb
Author: Juan Manuel Martinez Caamaño <jmartinezcaamao at gmail.com>
Date: 2024-12-16 (Mon, 16 Dec 2024)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
M llvm/test/CodeGen/AMDGPU/gfx12_scalar_subword_loads.ll
Log Message:
-----------
[AMDGPU][AMDGPURegBankInfo] Map S_BUFFER_LOAD_XXX to its corresponding BUFFER_LOAD_XXX (#117574)
In one test code generation diverged between GISEL and DAG
For example, this intrinsic
> %ld = call i8 @llvm.amdgcn.s.buffer.load.u8(<4 x i32> %src, i32
%offset, i32 0)
would be lowered into these two cases:
* `buffer_load_u8 v2, v2, s[0:3], null offen`
* `buffer_load_b32 v2, v2, s[0:3], null offen`
This patch fixes this issue.
Commit: 978de2d6664a74864471d62244700c216fdc6741
https://github.com/llvm/llvm-project/commit/978de2d6664a74864471d62244700c216fdc6741
Author: Vyacheslav Levytskyy <vyacheslav.levytskyy at intel.com>
Date: 2024-12-16 (Mon, 16 Dec 2024)
Changed paths:
M llvm/docs/SPIRVUsage.rst
M llvm/lib/Target/SPIRV/MCTargetDesc/SPIRVMCCodeEmitter.cpp
M llvm/lib/Target/SPIRV/SPIRVBuiltins.cpp
M llvm/lib/Target/SPIRV/SPIRVBuiltins.h
M llvm/lib/Target/SPIRV/SPIRVCommandLine.cpp
M llvm/lib/Target/SPIRV/SPIRVEmitIntrinsics.cpp
M llvm/lib/Target/SPIRV/SPIRVGlobalRegistry.cpp
M llvm/lib/Target/SPIRV/SPIRVInstrInfo.td
M llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
M llvm/lib/Target/SPIRV/SPIRVLegalizerInfo.cpp
M llvm/lib/Target/SPIRV/SPIRVModuleAnalysis.cpp
M llvm/lib/Target/SPIRV/SPIRVPostLegalizer.cpp
M llvm/lib/Target/SPIRV/SPIRVPreLegalizer.cpp
M llvm/lib/Target/SPIRV/SPIRVSymbolicOperands.td
A llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_float_controls2/exec_mode_float_control_empty.ll
A llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_float_controls2/exec_mode_float_control_intel.ll
M llvm/test/CodeGen/SPIRV/instructions/integer-casts.ll
A llvm/test/CodeGen/SPIRV/llvm-intrinsics/constrained-arithmetic.ll
Log Message:
-----------
[SPIR-V] Add saturation and float rounding mode decorations, a subset of arithmetic constrained floating-point intrinsics, and SPV_INTEL_float_controls2 extension (#119862)
This PR adds the following features:
* saturation and float rounding mode decorations,
* arithmetic constrained floating-point intrinsics (strict_fadd,
strict_fsub, strict_fmul, strict_fdiv, strict_frem, strict_fma and
strict_fldexp),
* and SPV_INTEL_float_controls2 extension,
* using recent improvements of emit-intrinsics step, this PR also
simplifies pre- and post-legalizer steps and improves instruction
selection.
Commit: 95e509a98993e84ef987accb2ed7109c3810281e
https://github.com/llvm/llvm-project/commit/95e509a98993e84ef987accb2ed7109c3810281e
Author: Florian Hahn <flo at fhahn.com>
Date: 2024-12-16 (Mon, 16 Dec 2024)
Changed paths:
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
M llvm/lib/Transforms/Vectorize/VPlan.cpp
M llvm/lib/Transforms/Vectorize/VPlan.h
M llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
M llvm/test/Transforms/LoopVectorize/vplan-printing.ll
Log Message:
-----------
[VPlan] Add VPWidenInduction recipe as common base class (NFC). (#120008)
This helps to simplify some existing code and new code
(https://github.com/llvm/llvm-project/pull/112145)
PR: https://github.com/llvm/llvm-project/pull/120008
Commit: aff3e68d6f10dd3087c29a09865683b9d35a362e
https://github.com/llvm/llvm-project/commit/aff3e68d6f10dd3087c29a09865683b9d35a362e
Author: Shao-Ce SUN <sunshaoce at outlook.com>
Date: 2024-12-16 (Mon, 16 Dec 2024)
Changed paths:
M llvm/lib/MC/TargetRegistry.cpp
M llvm/test/tools/llc/invalid-target.ll
M llvm/tools/llc/llc.cpp
Log Message:
-----------
[LLVM][tools] Remove unnecessary newline from error message (#120037)
The previous missing a newline:
```shell
$ llc --mattr=help
llc: error: unable to get target for 'unknown', see --version and --triple.$
```
Commit: 3b17d041dd775e033cca499f2a25548c8c22bb86
https://github.com/llvm/llvm-project/commit/3b17d041dd775e033cca499f2a25548c8c22bb86
Author: Benjamin Maxwell <benjamin.maxwell at arm.com>
Date: 2024-12-16 (Mon, 16 Dec 2024)
Changed paths:
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
A llvm/test/CodeGen/AArch64/sve-load-store-strict-align.ll
A llvm/test/CodeGen/AArch64/sve-unaligned-load-store-strict-align.ll
Log Message:
-----------
[AArch64][SVE] Don't require 16-byte aligned SVE loads/stores with +strict-align (#119732)
Instead, allow any alignment >= the element size (in bytes). This is all
that is needed for (predicated) vector loads even if unaligned accesses
are disabled.
See:
https://developer.arm.com/documentation/ddi0602/2024-09/Shared-Pseudocode/aarch64-functions-memory?lang=en#impl-aarch64.Mem.read.3
Specifically:
```
// Check alignment on size of element accessed, not overall access size.
constant integer alignment = if accdesc.ispair then size DIV 2 else size;
```
The `size` passed to `Mem` by SVE load/store instructions is the element
size.
Commit: 9455ea740d8ef91f73e0c7d4e1fc04a705d37ad8
https://github.com/llvm/llvm-project/commit/9455ea740d8ef91f73e0c7d4e1fc04a705d37ad8
Author: Dmitry Chestnykh <dm.chestnykh at gmail.com>
Date: 2024-12-16 (Mon, 16 Dec 2024)
Changed paths:
M llvm/lib/Target/ARM/ARMInstrInfo.td
M llvm/lib/Target/ARM/ARMInstrThumb2.td
A llvm/test/MC/ARM/idiv-2op.s
M llvm/test/MC/ARM/idiv.s
Log Message:
-----------
[ARM][Thumb2] Allow 2-operand variants of `[us]div` (#119976)
Fixes #119963
Commit: e31c70d9fa9ba4e61ecf0b34fbc6da2785e60eb6
https://github.com/llvm/llvm-project/commit/e31c70d9fa9ba4e61ecf0b34fbc6da2785e60eb6
Author: Oliver Stannard <oliver.stannard at arm.com>
Date: 2024-12-16 (Mon, 16 Dec 2024)
Changed paths:
M llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
Log Message:
-----------
[AArch64] Add immediate range checks for more MTE instructions (#119216)
This would have turned the bug fixed in #117146 from a miscompilation
into an assertion failure.
Commit: 0dbdc23e78ac1f34a5b563f2db73f9ca64714fac
https://github.com/llvm/llvm-project/commit/0dbdc23e78ac1f34a5b563f2db73f9ca64714fac
Author: Pavel Labath <pavel at labath.sk>
Date: 2024-12-16 (Mon, 16 Dec 2024)
Changed paths:
M lldb/include/lldb/Core/Progress.h
M lldb/source/Core/Progress.cpp
M lldb/source/Plugins/SymbolFile/DWARF/ManualDWARFIndex.cpp
M lldb/unittests/Core/ProgressReportTest.cpp
Log Message:
-----------
[lldb] Add ability to rate-limit progress reports (#119377)
For high-frequency multithreaded progress reports, the contention of
taking the progress mutex and the overhead of generating event can
significantly slow down the operation whose progress we are reporting.
This patch adds an (optional) capability to rate-limit them. It's
optional because this approach has one drawback: if the progress
reporting has a pattern where it generates a burst of activity and then
blocks (without reporting anything) for a large amount of time, it can
appear as if less progress was made that it actually was (because we
only reported the first event from the burst and dropped the other
ones).
I've also made a small refactor of the Progress class to better
distinguish between const (don't need protection), atomic (are used on
the hot path) and other (need mutex protection) members.
Commit: 6414d6174198689f00ff325e667fff9eb1c0d9de
https://github.com/llvm/llvm-project/commit/6414d6174198689f00ff325e667fff9eb1c0d9de
Author: Nikita Popov <npopov at redhat.com>
Date: 2024-12-16 (Mon, 16 Dec 2024)
Changed paths:
M mlir/unittests/Analysis/Presburger/CMakeLists.txt
M mlir/unittests/Bytecode/CMakeLists.txt
M mlir/unittests/Conversion/PDLToPDLInterp/CMakeLists.txt
M mlir/unittests/Debug/CMakeLists.txt
M mlir/unittests/Dialect/AMDGPU/CMakeLists.txt
M mlir/unittests/Dialect/ArmSME/CMakeLists.txt
M mlir/unittests/Dialect/CMakeLists.txt
M mlir/unittests/Dialect/Index/CMakeLists.txt
M mlir/unittests/Dialect/LLVMIR/CMakeLists.txt
M mlir/unittests/Dialect/MemRef/CMakeLists.txt
M mlir/unittests/Dialect/OpenACC/CMakeLists.txt
M mlir/unittests/Dialect/Polynomial/CMakeLists.txt
M mlir/unittests/Dialect/SCF/CMakeLists.txt
M mlir/unittests/Dialect/SPIRV/CMakeLists.txt
M mlir/unittests/Dialect/SparseTensor/CMakeLists.txt
M mlir/unittests/Dialect/Transform/CMakeLists.txt
M mlir/unittests/Dialect/Utils/CMakeLists.txt
M mlir/unittests/ExecutionEngine/CMakeLists.txt
M mlir/unittests/IR/CMakeLists.txt
M mlir/unittests/Interfaces/CMakeLists.txt
M mlir/unittests/Parser/CMakeLists.txt
M mlir/unittests/Pass/CMakeLists.txt
M mlir/unittests/Rewrite/CMakeLists.txt
M mlir/unittests/Support/CMakeLists.txt
M mlir/unittests/Target/LLVM/CMakeLists.txt
M mlir/unittests/Tools/lsp-server-support/CMakeLists.txt
M mlir/unittests/Transforms/CMakeLists.txt
Log Message:
-----------
[mlir] Use mlir_target_link_libraries for unit tests (#119858)
This is a followup to https://github.com/llvm/llvm-project/pull/119408,
which switches unit test binaries to also use
mlir_target_link_libraries() where necessary. This allows them to link
against against the MLIR dylib.
Commit: 3ad2399148953837622d78d18ae9fd0db6ad0557
https://github.com/llvm/llvm-project/commit/3ad2399148953837622d78d18ae9fd0db6ad0557
Author: Björn Pettersson <bjorn.a.pettersson at ericsson.com>
Date: 2024-12-16 (Mon, 16 Dec 2024)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
M llvm/test/CodeGen/ARM/dagcombine-ld-op-st.ll
M llvm/test/CodeGen/X86/apx/or.ll
M llvm/test/CodeGen/X86/illegal-bitfield-loadstore.ll
M llvm/test/CodeGen/X86/pr35763.ll
M llvm/test/CodeGen/X86/store_op_load_fold.ll
Log Message:
-----------
[DAGCombiner] Refactor and improve ReduceLoadOpStoreWidth (#119564)
This patch make a couple of improvements to ReduceLoadOpStoreWidth.
When determining the minimum size of "NewBW" we now take byte boundaries
into account. If we for example touch bits 6-10 we shouldn't accept
NewBW=8, because we would fail later when detecting that we can't access
bits from two different bytes in memory using a single load. Instead we
make sure to align LSB/MSB according to byte size boundaries up front
before searching for a viable "NewBW".
In the past we only tried to find a "ShAmt" that was a multiple of
"NewBW", but now we use a sliding window technique to scan for a viable
"ShAmt" that is a multiple of the byte size. This can help out finding
more opportunities for optimization (specially if the original type
isn't byte sized, and for big-endian targets when the original
load/store is aligned on the most significant bit).
Commit: 02328e0465c256293950542f1a85eb55bcbc9d45
https://github.com/llvm/llvm-project/commit/02328e0465c256293950542f1a85eb55bcbc9d45
Author: Paul Walker <paul.walker at arm.com>
Date: 2024-12-16 (Mon, 16 Dec 2024)
Changed paths:
M llvm/lib/IR/ConstantFold.cpp
M llvm/lib/IR/Constants.cpp
M llvm/test/Transforms/InstCombine/clamp-to-minmax.ll
M llvm/test/Transforms/InstCombine/fabs-fneg-fold.ll
M llvm/test/Transforms/InstCombine/fadd.ll
M llvm/test/Transforms/InstCombine/fdiv.ll
M llvm/test/Transforms/InstCombine/fmul.ll
M llvm/test/Transforms/InstCombine/fneg.ll
Log Message:
-----------
[LLVM][ConstantFold] Remove remaining uses of ConstantInt/FP::get(LLVMContext... (#119912)
This extends the constant folds to support vector ConstantInt/FP.
Commit: d280a9c5e22662fd24708245add50b152ab10fc8
https://github.com/llvm/llvm-project/commit/d280a9c5e22662fd24708245add50b152ab10fc8
Author: Shao-Ce SUN <sunshaoce at outlook.com>
Date: 2024-12-16 (Mon, 16 Dec 2024)
Changed paths:
M clang/test/Driver/print-enabled-extensions/riscv-rocket-rv64.c
M clang/test/Driver/print-supported-extensions-riscv.c
M llvm/lib/Target/RISCV/RISCVFeatures.td
A llvm/test/CodeGen/RISCV/features-info.ll
Log Message:
-----------
[NFC] [RISCV] Refactor class RISCVExtension (#120040)
I think typo can be avoided by reducing the number of times we re-enter
the extension name.
Commit: 2df48fa78b496a2d276aa848598634bb2aad6857
https://github.com/llvm/llvm-project/commit/2df48fa78b496a2d276aa848598634bb2aad6857
Author: Paschalis Mpeis <paschalis.mpeis at arm.com>
Date: 2024-12-16 (Mon, 16 Dec 2024)
Changed paths:
M bolt/include/bolt/Passes/ADRRelaxationPass.h
M bolt/lib/Rewrite/BinaryPassManager.cpp
Log Message:
-----------
[BOLT][AArch64] Enable function print after ADRRelaxation (#119869)
Introduce `--print-adr-relaxation` to print after ADR Relaxation pass.
Commit: 03847f19f2e462a339e1afa1093f253ec8a23765
https://github.com/llvm/llvm-project/commit/03847f19f2e462a339e1afa1093f253ec8a23765
Author: Sergei Barannikov <barannikov88 at gmail.com>
Date: 2024-12-16 (Mon, 16 Dec 2024)
Changed paths:
A llvm/lib/Target/AMDGPU/AMDGPUSelectionDAGInfo.cpp
A llvm/lib/Target/AMDGPU/AMDGPUSelectionDAGInfo.h
M llvm/lib/Target/AMDGPU/CMakeLists.txt
M llvm/lib/Target/AMDGPU/GCNSubtarget.cpp
M llvm/lib/Target/AMDGPU/GCNSubtarget.h
M llvm/lib/Target/AMDGPU/R600Subtarget.cpp
M llvm/lib/Target/AMDGPU/R600Subtarget.h
M llvm/lib/Target/Mips/CMakeLists.txt
A llvm/lib/Target/Mips/MipsSelectionDAGInfo.cpp
A llvm/lib/Target/Mips/MipsSelectionDAGInfo.h
M llvm/lib/Target/Mips/MipsSubtarget.cpp
M llvm/lib/Target/Mips/MipsSubtarget.h
M llvm/lib/Target/NVPTX/CMakeLists.txt
A llvm/lib/Target/NVPTX/NVPTXSelectionDAGInfo.cpp
A llvm/lib/Target/NVPTX/NVPTXSelectionDAGInfo.h
M llvm/lib/Target/NVPTX/NVPTXSubtarget.cpp
M llvm/lib/Target/NVPTX/NVPTXSubtarget.h
M llvm/lib/Target/PowerPC/CMakeLists.txt
A llvm/lib/Target/PowerPC/PPCSelectionDAGInfo.cpp
A llvm/lib/Target/PowerPC/PPCSelectionDAGInfo.h
M llvm/lib/Target/PowerPC/PPCSubtarget.cpp
M llvm/lib/Target/PowerPC/PPCSubtarget.h
M llvm/lib/Target/RISCV/CMakeLists.txt
A llvm/lib/Target/RISCV/RISCVSelectionDAGInfo.cpp
A llvm/lib/Target/RISCV/RISCVSelectionDAGInfo.h
M llvm/lib/Target/RISCV/RISCVSubtarget.cpp
M llvm/lib/Target/RISCV/RISCVSubtarget.h
M llvm/lib/Target/RISCV/RISCVTargetMachine.h
Log Message:
-----------
[SelectionDAG] Add empty implementation of SelectionDAGInfo to some targets (#119968)
#119969 adds a couple of new methods to this class, which will need to
be overridden by these targets.
Part of #119709.
Pull Request: https://github.com/llvm/llvm-project/pull/119968
Commit: 671095b452365826b1ccb65483d6ae890a2a81f7
https://github.com/llvm/llvm-project/commit/671095b452365826b1ccb65483d6ae890a2a81f7
Author: Nicholas <45984215+liusy58 at users.noreply.github.com>
Date: 2024-12-16 (Mon, 16 Dec 2024)
Changed paths:
M bolt/lib/Passes/LongJmp.cpp
A bolt/test/AArch64/long-jmp-one-stub.s
Log Message:
-----------
[BOLT][AArch64] Check Last Element Instead of Returning `nullptr` in `lookupStubFromGroup` (#114015)
The current implementation of `lookupStubFromGroup` is incorrect. The
function is intended to find and return the closest stub using
`lower_bound`, which identifies the first element in a sorted range that
is not less than a specified value. However, if such an element is not
found within `Candidates` and the list is not empty, the function
returns `nullptr`. Instead, it should check whether the last element
satisfies the condition.
Commit: 38b3d87bd384a469a6618ec6a971352cb4f813ba
https://github.com/llvm/llvm-project/commit/38b3d87bd384a469a6618ec6a971352cb4f813ba
Author: Dmitry Polukhin <34227995+dmpolukhin at users.noreply.github.com>
Date: 2024-12-16 (Mon, 16 Dec 2024)
Changed paths:
M clang/include/clang/Serialization/ASTBitCodes.h
M clang/include/clang/Serialization/ASTReader.h
M clang/include/clang/Serialization/ASTWriter.h
M clang/lib/Sema/SemaTemplateInstantiateDecl.cpp
M clang/lib/Serialization/ASTReader.cpp
M clang/lib/Serialization/ASTReaderDecl.cpp
M clang/lib/Serialization/ASTWriter.cpp
M clang/lib/Serialization/ASTWriterDecl.cpp
A clang/test/Headers/crash-instantiated-in-scope-cxx-modules4.cpp
A clang/test/Modules/friend-inline-function-body.cpp
Log Message:
-----------
[C++20][Modules] Load function body from the module that gives canonical decl (#111992)
Summary:
Fix crash from reproducer provided in
https://github.com/llvm/llvm-project/pull/109167#issuecomment-2405289565
Also fix issues with merged inline friend functions merged during deserialization.
Test Plan: check-clang
Commit: 90968794e26709957d49dd660e4e453235d393e8
https://github.com/llvm/llvm-project/commit/90968794e26709957d49dd660e4e453235d393e8
Author: Phoebe Wang <phoebe.wang at intel.com>
Date: 2024-12-16 (Mon, 16 Dec 2024)
Changed paths:
M clang/test/Preprocessor/predefined-arch-macros.c
M llvm/lib/Target/X86/X86.td
M llvm/lib/TargetParser/X86TargetParser.cpp
Log Message:
-----------
[X86] Add missing feature USERMSR to DiamondRapids (#120061)
Ref.: https://cdrdv2.intel.com/v1/dl/getContent/671368
Commit: dd6f6a096a59892ce1f9c454461aa5ed4c2aa971
https://github.com/llvm/llvm-project/commit/dd6f6a096a59892ce1f9c454461aa5ed4c2aa971
Author: Timm Baeder <tbaeder at redhat.com>
Date: 2024-12-16 (Mon, 16 Dec 2024)
Changed paths:
M clang/lib/AST/ByteCode/InterpBuiltin.cpp
M clang/test/AST/ByteCode/builtin-functions.cpp
Log Message:
-----------
[clang][bytecode] Handle builtin_wmemcmp (#120070)
Commit: 24238aacd9e67072f2bd7bebe4c41b52c7881e65
https://github.com/llvm/llvm-project/commit/24238aacd9e67072f2bd7bebe4c41b52c7881e65
Author: LLVM GN Syncbot <llvmgnsyncbot at gmail.com>
Date: 2024-12-16 (Mon, 16 Dec 2024)
Changed paths:
M llvm/utils/gn/secondary/llvm/lib/Target/AMDGPU/BUILD.gn
M llvm/utils/gn/secondary/llvm/lib/Target/Mips/BUILD.gn
M llvm/utils/gn/secondary/llvm/lib/Target/NVPTX/BUILD.gn
M llvm/utils/gn/secondary/llvm/lib/Target/PowerPC/BUILD.gn
M llvm/utils/gn/secondary/llvm/lib/Target/RISCV/BUILD.gn
Log Message:
-----------
[gn build] Port 03847f19f2e4
Commit: 8dd27d4569555c181a92f2c3914d3ea16aa1a741
https://github.com/llvm/llvm-project/commit/8dd27d4569555c181a92f2c3914d3ea16aa1a741
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-12-16 (Mon, 16 Dec 2024)
Changed paths:
A llvm/test/Transforms/VectorCombine/X86/shuffle-of-cmps.ll
Log Message:
-----------
[VectorCombine] Add test coverage for shuffle(cmp,cmp) fold patterns
Commit: 7d25bcef0937e454bb2d3cf3b4ed615257951120
https://github.com/llvm/llvm-project/commit/7d25bcef0937e454bb2d3cf3b4ed615257951120
Author: Yingwei Zheng <dtcxzyw2333 at gmail.com>
Date: 2024-12-16 (Mon, 16 Dec 2024)
Changed paths:
M llvm/lib/Transforms/InstCombine/InstCombineSelect.cpp
M llvm/test/Transforms/InstCombine/select.ll
Log Message:
-----------
[InstCombine] Recursively replace condition with constant in select arms (#120011)
This patch is proposed to reduce the number of selects with undefs
introduced by https://github.com/llvm/llvm-project/pull/119884.
Commit: ef4b597015db0e558f3a75f2f75d471a1cabe0b6
https://github.com/llvm/llvm-project/commit/ef4b597015db0e558f3a75f2f75d471a1cabe0b6
Author: Jonathan Thackray <jonathan.thackray at arm.com>
Date: 2024-12-16 (Mon, 16 Dec 2024)
Changed paths:
M clang/include/clang/Basic/arm_sme.td
M clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_fp8_fdot.c
M clang/test/Sema/aarch64-sme2-intrinsics/acle_sme2_fp8_fdot.c
M llvm/include/llvm/IR/IntrinsicsAArch64.td
M llvm/lib/Target/AArch64/AArch64SMEInstrInfo.td
M llvm/lib/Target/AArch64/SMEInstrFormats.td
M llvm/test/CodeGen/AArch64/sme2-intrinsics-fp8-fdot.ll
Log Message:
-----------
[AArch64] Add intrinsics for SME FP8 FDOT single and multi instructions (#119845)
Add support for the following SME 8 bit floating-point dot-product intrinsics:
```
// Only if __ARM_FEATURE_SME_F8F16 != 0
void svdot[_single]_za16[_mf8]_vg1x2_fpm(uint32_t slice, svmfloat8x2_t zn,
svmfloat8_t zm,
fpm_t fpm) __arm_streaming __arm_inout("za");
void svdot[_single]_za16[_mf8]_vg1x4_fpm(uint32_t slice, svmfloat8x4_t zn,
svmfloat8_t zm,
fpm_t fpm) __arm_streaming __arm_inout("za");
void svdot_za16[_mf8]_vg1x2_fpm(uint32_t slice, svmfloat8x2_t zn,
svmfloat8x2_t zm,
fpm_t fpm) __arm_streaming __arm_inout("za");
void svdot_za16[_mf8]_vg1x4_fpm(uint32_t slice, svmfloat8x4_t zn,
svmfloat8x4_t zm,
fpm_t fpm) __arm_streaming __arm_inout("za");
// Only if __ARM_FEATURE_SME_F8F32 != 0
void svdot[_single]_za32[_mf8]_vg1x2_fpm(uint32_t slice, svmfloat8x2_t zn,
svmfloat8_t zm,
fpm_t fpm) __arm_streaming __arm_inout("za");
void svdot[_single]_za32[_mf8]_vg1x4_fpm(uint32_t slice, svmfloat8x4_t zn,
svmfloat8_t zm,
fpm_t fpm) __arm_streaming __arm_inout("za");
void svdot_za32[_mf8]_vg1x2_fpm(uint32_t slice, svmfloat8x2_t zn,
svmfloat8x2_t zm,
fpm_t fpm) __arm_streaming __arm_inout("za");
void svdot_za32[_mf8]_vg1x4_fpm(uint32_t slice, svmfloat8x4_t zn,
svmfloat8x4_t zm,
fpm_t fpm) __arm_streaming __arm_inout("za");
```
These intrinsics are extracted from:
https://github.com/ARM-software/acle/pull/323/
Co-authored-by: Momchil Velikov <momchil.velikov at arm.com>
Co-authored-by: Marian Lukac <marian.lukac at arm.com>
Commit: 93fab6e362a3124af76c6e82f90ca1385aea6d1f
https://github.com/llvm/llvm-project/commit/93fab6e362a3124af76c6e82f90ca1385aea6d1f
Author: Mikhail Goncharov <goncharov.mikhail at gmail.com>
Date: 2024-12-16 (Mon, 16 Dec 2024)
Changed paths:
M llvm/test/CodeGen/NVPTX/nvcl-param-align.ll
Log Message:
-----------
[NVPTX] fix nvcl-param-align test triple
for b279f6b098d3849f7f1c1f539b108307d5f8ae2d
Commit: d866005f6928a2a97e67866bedb26139d8cc27d9
https://github.com/llvm/llvm-project/commit/d866005f6928a2a97e67866bedb26139d8cc27d9
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2024-12-16 (Mon, 16 Dec 2024)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPULibFunc.cpp
A llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-unexpected-types.ll
Log Message:
-----------
AMDGPU: Do not assert on unhandled types when demangling libcalls (#120068)
Commit: 3c3094b60d3587b1db8ef35b3bf54e73ac5894d9
https://github.com/llvm/llvm-project/commit/3c3094b60d3587b1db8ef35b3bf54e73ac5894d9
Author: macurtis-amd <macurtis at amd.com>
Date: 2024-12-16 (Mon, 16 Dec 2024)
Changed paths:
M flang/lib/Parser/parsing.cpp
M flang/test/Preprocessing/pp132.f90
Log Message:
-----------
[flang] Ensure directive sentinels are in cols 1-5 in pp output (#119406)
Preprocessor output is intended to be valid fixed form.
Commit: 8380bafaed84cb5799feef70bf34387d6f15acff
https://github.com/llvm/llvm-project/commit/8380bafaed84cb5799feef70bf34387d6f15acff
Author: Jonathan Thackray <jonathan.thackray at arm.com>
Date: 2024-12-16 (Mon, 16 Dec 2024)
Changed paths:
M clang/include/clang/Basic/arm_sme.td
A clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_fp8_fvdot.c
A clang/test/Sema/aarch64-sme2-intrinsics/acle_sme2_fp8_fvdot.c
M llvm/include/llvm/IR/IntrinsicsAArch64.td
M llvm/lib/Target/AArch64/AArch64SMEInstrInfo.td
M llvm/lib/Target/AArch64/SMEInstrFormats.td
A llvm/test/CodeGen/AArch64/sme2-intrinsics-fp8-fvdot.ll
Log Message:
-----------
[AArch64] Add intrinsics for SME FP8 FVDOT, FVDOTB and FVDOTT intrinsics (#119922)
Add support for the following SME 8 bit floating-point dot-product
intrinsics:
```
// Only if __ARM_FEATURE_SME_F8F16 != 0
void svvdot_lane_za16[_mf8]_vg1x2_fpm(uint32_t slice, svmfloat8x2_t zn,
svmfloat8_t zm, uint64_t imm_idx,
fpm_t fpm) __arm_streaming __arm_inout("za");
// Only if __ARM_FEATURE_SME_F8F32 != 0
void svvdott_lane_za32[_mf8]_vg1x4_fpm(uint32_t slice, svmfloat8x2_t zn,
svmfloat8_t zm, uint64_t imm_idx,
fpm_t fpm) __arm_streaming __arm_inout("za");
void svvdotb_lane_za32[_mf8]_vg1x4_fpm(uint32_t slice, svmfloat8x2_t zn,
svmfloat8_t zm, uint64_t imm_idx,
fpm_t fpm) __arm_streaming __arm_inout("za");
```
---------
Co-authored-by: Momchil Velikov <momchil.velikov at arm.com>
Co-authored-by: Marian Lukac <marian.lukac at arm.com>
Commit: 1ab81f8e7f77110c4a752dd7d2cc39fb5148760c
https://github.com/llvm/llvm-project/commit/1ab81f8e7f77110c4a752dd7d2cc39fb5148760c
Author: erichkeane <ekeane at nvidia.com>
Date: 2024-12-16 (Mon, 16 Dec 2024)
Changed paths:
M clang/include/clang/AST/OpenACCClause.h
M clang/include/clang/Basic/OpenACCClauses.def
M clang/include/clang/Sema/SemaOpenACC.h
M clang/lib/AST/OpenACCClause.cpp
M clang/lib/AST/StmtProfile.cpp
M clang/lib/AST/TextNodeDumper.cpp
M clang/lib/Parse/ParseOpenACC.cpp
M clang/lib/Sema/SemaOpenACC.cpp
M clang/lib/Sema/TreeTransform.h
M clang/lib/Serialization/ASTReader.cpp
M clang/lib/Serialization/ASTWriter.cpp
M clang/test/AST/ast-print-openacc-data-construct.cpp
M clang/test/ParserOpenACC/parse-clauses.c
M clang/test/ParserOpenACC/parse-clauses.cpp
M clang/test/SemaOpenACC/combined-construct-auto_seq_independent-clauses.c
M clang/test/SemaOpenACC/combined-construct-device_type-clause.c
M clang/test/SemaOpenACC/compute-construct-device_type-clause.c
A clang/test/SemaOpenACC/data-construct-delete-ast.cpp
A clang/test/SemaOpenACC/data-construct-delete-clause.c
M clang/test/SemaOpenACC/data-construct.cpp
M clang/test/SemaOpenACC/loop-construct-auto_seq_independent-clauses.c
M clang/test/SemaOpenACC/loop-construct-device_type-clause.c
M clang/tools/libclang/CIndex.cpp
Log Message:
-----------
[OpenACC] Implement 'delete' AST/Sema for 'exit data' construct
'delete' is another clause that has very little compile-time
implication, but needs a full AST that takes a var list. This patch
ipmlements it fully, plus adds sufficient test coverage.
Commit: 65e00315c92f53895c1d88912de8838d7790c3f0
https://github.com/llvm/llvm-project/commit/65e00315c92f53895c1d88912de8838d7790c3f0
Author: Valentin Clement (バレンタイン クレメン) <clementval at gmail.com>
Date: 2024-12-16 (Mon, 16 Dec 2024)
Changed paths:
M flang/lib/Optimizer/CodeGen/TargetRewrite.cpp
M flang/test/Fir/CUDA/cuda-target-rewrite.mlir
Log Message:
-----------
[flang][cuda] Adapt TargetRewrite to support gpu.launch_func (#119933)
Commit: 6a4750d227420cad8406d0ee1ea9d8ce05cca10f
https://github.com/llvm/llvm-project/commit/6a4750d227420cad8406d0ee1ea9d8ce05cca10f
Author: Mehdi Amini <joker.eph at gmail.com>
Date: 2024-12-16 (Mon, 16 Dec 2024)
Changed paths:
M mlir/lib/Dialect/Tensor/IR/TensorOps.cpp
M mlir/test/Dialect/Tensor/canonicalize.mlir
Log Message:
-----------
[mlir] Fix crash when folding tensor.dim(tensor.collapse()) on out-of-bound dim (#119941)
Addresses one of the cases described in #119866
Commit: cedc9bf94a6c40561c4ecb292126352d49c9129b
https://github.com/llvm/llvm-project/commit/cedc9bf94a6c40561c4ecb292126352d49c9129b
Author: Djordje Todorovic <djordje.todorovic at htecgroup.com>
Date: 2024-12-16 (Mon, 16 Dec 2024)
Changed paths:
M llvm/lib/Target/RISCV/RISCVFeatures.td
M llvm/lib/Target/RISCV/RISCVSubtarget.h
Log Message:
-----------
[RISCV] Add MIPSP8700 RISCVProcFamilyEnum (#120073)
Commit: 9cb68b4ddad84f8c1f3a96ca3304d9916f3ee7da
https://github.com/llvm/llvm-project/commit/9cb68b4ddad84f8c1f3a96ca3304d9916f3ee7da
Author: Joseph Huber <huberjn at outlook.com>
Date: 2024-12-16 (Mon, 16 Dec 2024)
Changed paths:
M libc/shared/rpc.h
M libc/shared/rpc_util.h
Log Message:
-----------
[libc] Make the RPC headers work when included from CUDA or HIP (#120016)
Summary:
In order for this to work with CUDA we need to declare functions as
__host__ and __device__ while also making sure we only call the GPU
functions during the CUDA / HIP compile stage.
Commit: 6d1a51303edd33faab34732a77a874f3eb74dbfd
https://github.com/llvm/llvm-project/commit/6d1a51303edd33faab34732a77a874f3eb74dbfd
Author: Joseph Huber <huberjn at outlook.com>
Date: 2024-12-16 (Mon, 16 Dec 2024)
Changed paths:
M libc/docs/gpu/rpc.rst
M libc/docs/gpu/using.rst
Log Message:
-----------
[libc][Docs] Update `libc` documentation for RPC and others (#120018)
Summary:
A few of these were out of date, update them now that the C library
interface into RPC was deleted.
Commit: b3d392af5b2706d46fea086579ffdf1dda5c648b
https://github.com/llvm/llvm-project/commit/b3d392af5b2706d46fea086579ffdf1dda5c648b
Author: Krzysztof Drewniak <Krzysztof.Drewniak at amd.com>
Date: 2024-12-16 (Mon, 16 Dec 2024)
Changed paths:
M mlir/test/lib/Dialect/Test/TestOpsSyntax.td
M mlir/test/mlir-tblgen/op-format.mlir
M mlir/tools/mlir-tblgen/OpFormatGen.cpp
Log Message:
-----------
[mlir][tblgen] Fix bug around parsing optional prop-dict keys (#120045)
The printer for prop-dict would elide properties that had their default
value, such as optional properties that were not present. The parser
would similarly not raise an error if such a key was missing. However,
after not raising an error, the parser would attempt to convert the null
attribute to a property anyway, causing failures.
This commit fixes the issue and adds tests.
Commit: 5c5f66937fa7fbc6721ba2203b0874966640a05f
https://github.com/llvm/llvm-project/commit/5c5f66937fa7fbc6721ba2203b0874966640a05f
Author: Sudharsan Veeravalli <quic_svs at quicinc.com>
Date: 2024-12-16 (Mon, 16 Dec 2024)
Changed paths:
M llvm/unittests/TargetParser/RISCVISAInfoTest.cpp
Log Message:
-----------
[RISCV] Add ISAInfoTest tests for a few XQCI extensions (#120060)
Missed out adding rv32 only support test checks for a few of the
extensions.
Commit: 76f258920d3baf32be297f60bee5b8520f195c25
https://github.com/llvm/llvm-project/commit/76f258920d3baf32be297f60bee5b8520f195c25
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2024-12-16 (Mon, 16 Dec 2024)
Changed paths:
M llvm/lib/CodeGen/MLRegAllocEvictAdvisor.cpp
Log Message:
-----------
[MLGO] Do not include urgent LRs in max cascade calculation (#120052)
A previous PR introduced a threshold where we would mask out a LR that
had been evicted a certain number of times to combat pathological
compile time cases with a somewhat adversarial model. However, this
patch did not take into account urgent LRs which led to compilation
failures when greedy would expect us to provide an eviction and we could
not due to the newly introduced logic.
Commit: 35d4f20098538a0d2ac6b870eeae2b0ead7d2982
https://github.com/llvm/llvm-project/commit/35d4f20098538a0d2ac6b870eeae2b0ead7d2982
Author: Nikita Popov <npopov at redhat.com>
Date: 2024-12-16 (Mon, 16 Dec 2024)
Changed paths:
M llvm/cmake/modules/AddLLVM.cmake
Log Message:
-----------
[CMake] Use correct exports file for MLIR tools (#120079)
llvm_add_tool() currently does not respect the passed project and puts
all tools into LLVMExports.cmake. This means that we end up with
binaries like mlir-opt in LLVMExports.cmake instead of
MLIRTargets.cmake, where they should be.
Adjust llvm_add_tool() to take the project into account.
Commit: 4104906a2336aa03361537d93bb58033c59592da
https://github.com/llvm/llvm-project/commit/4104906a2336aa03361537d93bb58033c59592da
Author: Louis Dionne <ldionne.2 at gmail.com>
Date: 2024-12-16 (Mon, 16 Dec 2024)
Changed paths:
R libcxx/test/std/utilities/meta/derived_from_integral_constant.compile.pass.cpp
Log Message:
-----------
[libc++] Revert new test for integral_constant that breaks CI
This commit reverts c3276a96d9 and 1901da32, which added a test to
ensure that type traits are derived from integral_constant. While that
is a fine test to add, the commit didn't go through a PR and as a result
it looks like some of our CI has been broken by it.
This should be an uncontroversial change, but let's re-land it via a PR
to get our usual CI coverage.
Commit: 39c9dda1aa593bb129c7a2ef7724c212255a58d6
https://github.com/llvm/llvm-project/commit/39c9dda1aa593bb129c7a2ef7724c212255a58d6
Author: David Green <david.green at arm.com>
Date: 2024-12-16 (Mon, 16 Dec 2024)
Changed paths:
M llvm/lib/Target/AArch64/AArch64ISelLowering.h
Log Message:
-----------
[AArch64] Move SME_ZA_LDR and SME_ZA_STR into FIRST_TARGET_MEMORY_OPCODE. NFCI (#120091)
These opcodes are currently in the "strictfp" section. They should
either be in "memory", or moved into the generic ocodes.
Note that isTargetMemoryOpcode/FIRST_TARGET_MEMORY_OPCODE doesn't seem
to be used for anything at the moment.
Commit: 9f63940a65a85b34a947e4947d14a50da9f753c0
https://github.com/llvm/llvm-project/commit/9f63940a65a85b34a947e4947d14a50da9f753c0
Author: Hari Limaye <hari.limaye at arm.com>
Date: 2024-12-16 (Mon, 16 Dec 2024)
Changed paths:
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
M llvm/test/CodeGen/AArch64/aarch64-dup-ext-crash.ll
M llvm/test/CodeGen/AArch64/aarch64-dup-ext.ll
Log Message:
-----------
[AArch64] Handle ANY_EXTEND in BuildShuffleExtendCombine (#118308)
Handle ANY_EXTEND when combining a buildvector/shuffle of extended
operands, as we can safely ignore ANY_EXTENDS when checking if all signs
of the other extends are matching.
Commit: c53901405a309a414cb731c4b22f32eafccbbd2a
https://github.com/llvm/llvm-project/commit/c53901405a309a414cb731c4b22f32eafccbbd2a
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2024-12-16 (Mon, 16 Dec 2024)
Changed paths:
A llvm/test/Transforms/SLPVectorizer/X86/minbw-node-used-twice.ll
Log Message:
-----------
[SLP][NFC]Add a test with incorrect bitwidth for the node, previously identified as non-shrinkable
Commit: 7bfcf93527782f1ebf83880f35e981665308d89c
https://github.com/llvm/llvm-project/commit/7bfcf93527782f1ebf83880f35e981665308d89c
Author: Florian Hahn <flo at fhahn.com>
Date: 2024-12-16 (Mon, 16 Dec 2024)
Changed paths:
M llvm/include/llvm/Analysis/ScalarEvolution.h
M llvm/lib/Analysis/ScalarEvolution.cpp
M llvm/test/Analysis/LoopAccessAnalysis/memcheck-wrapping-pointers.ll
M llvm/test/Analysis/LoopAccessAnalysis/nssw-predicate-implied.ll
Log Message:
-----------
[SCEV] Use Step and Start to check if SCEVWrapPredicate is implied. (#118184)
A SCEVWrapPredicate A implies B, if
* they have the same flag,
* both steps are positive and
* B's start and step are ULE/SLE (for NSUW/NSSW) than A's.
See https://alive2.llvm.org/ce/z/n2T4ss (first pair with known constants
as strides, second pair with variable strides).
Note that this is limited to steps of the same size, due to NSUW having
slightly different semantics than regular NUW. We should be able to
remove this restriction for NSSW (which matches NSW) in the future.
PR: https://github.com/llvm/llvm-project/pull/118184
Commit: d576021853fd64c10fd746389a9b263cf10c5295
https://github.com/llvm/llvm-project/commit/d576021853fd64c10fd746389a9b263cf10c5295
Author: Dmitry Vasilyev <dvassiliev at accesssoftek.com>
Date: 2024-12-16 (Mon, 16 Dec 2024)
Changed paths:
M lldb/test/API/iohandler/resize/TestIOHandlerResizeNoEditline.py
Log Message:
-----------
[lldb] Disable TestIOHandlerResizeNoEditline.py for Windows hosts (#120025)
See #120021 for details.
Commit: f239922cdc15c68266abb94b4b58ed46aa2572b4
https://github.com/llvm/llvm-project/commit/f239922cdc15c68266abb94b4b58ed46aa2572b4
Author: Slava Zakharin <szakharin at nvidia.com>
Date: 2024-12-16 (Mon, 16 Dec 2024)
Changed paths:
M flang/lib/Optimizer/HLFIR/Transforms/SimplifyHLFIRIntrinsics.cpp
Log Message:
-----------
[flang] Enable hlfir.sum inlining by default. (#119937)
There is already a LIT test for hlfir.sum inlining that uses
the engineering option. I would like to keep the option
for short period of time to be able to revert
in case of performance regressions that I was not able to see.
Commit: 2402bccc805614069efb0a47e1ef43349ea7ba1e
https://github.com/llvm/llvm-project/commit/2402bccc805614069efb0a47e1ef43349ea7ba1e
Author: Slava Zakharin <szakharin at nvidia.com>
Date: 2024-12-16 (Mon, 16 Dec 2024)
Changed paths:
M flang/lib/Optimizer/HLFIR/Transforms/SimplifyHLFIRIntrinsics.cpp
M flang/test/HLFIR/simplify-hlfir-intrinsics-cshift.fir
M flang/test/HLFIR/simplify-hlfir-intrinsics-sum.fir
M flang/test/HLFIR/simplify-hlfir-intrinsics.fir
Log Message:
-----------
[flang] Turn SimplifyHLFIRIntrinsics into a greedy rewriter. (#119946)
This is almost an NFC, except that folding changed ordering
of some operations.
Commit: d1a7225076218ce224cd29c74259b715b393dc9d
https://github.com/llvm/llvm-project/commit/d1a7225076218ce224cd29c74259b715b393dc9d
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2024-12-16 (Mon, 16 Dec 2024)
Changed paths:
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
M llvm/test/Transforms/SLPVectorizer/X86/minbw-node-used-twice.ll
Log Message:
-----------
[SLP]Check if the node must keep its original bitwidth
Need to check if during previous analysis the node has requested to keep
its original bitwidth to avoid incorrect codegen.
Fixes #120076
Commit: 3cbc73f71eef599e678197e445e11a98f8f61689
https://github.com/llvm/llvm-project/commit/3cbc73f71eef599e678197e445e11a98f8f61689
Author: Hugo Trachino <hugo.trachino at huawei.com>
Date: 2024-12-16 (Mon, 16 Dec 2024)
Changed paths:
M mlir/lib/Conversion/ArithToLLVM/ArithToLLVM.cpp
M mlir/lib/Conversion/ArithToLLVM/CMakeLists.txt
M mlir/test/Conversion/ArithToLLVM/arith-to-llvm.mlir
Log Message:
-----------
[MLIR][Arith] Add CeilFloorDivExpandOpsPatterns to conversion to LLVM (Reland) (#118839)
When running `convert-to-llvm`, `ceildiv` and `floordiv` ops, which do not
have direct llvm conversion pattern, would not get lowered to llvm
dialect. This patch adds CeilFloorDivExpandOpsPatterns to both
`convert-to-llvm` and `arith-to-llvm` (deprecated) lowering those ops to
lower level arith ops which can be lowered to llvm using LLVM
conversion.
Reland of https://github.com/llvm/llvm-project/pull/117305 after
buildbot failures.
See:
https://lab.llvm.org/buildbot/#/builders/80/builds/7168
https://lab.llvm.org/buildbot/#/builders/130/builds/7036
https://lab.llvm.org/buildbot/#/builders/138/builds/7290
Added dependence to ArithTransforms in ArithToLLVM. In previous
discussion, it has been suggested to move the
CeilFloorDivExpandOpsPatterns to ArithUtils but I think linking
ArithTransforms makes more sense as otherwise :
* ArithToLLVM needs a new dependency to ArithUtils
* ArithUtils needs new dependency to ArithTransforms or move the
patterns as well which will create more dependencies
* It creates lots of code motion which makes it hard to review.
Commit: 290f38cd1a9fa7b1a91ddb25632807ecb5308dc7
https://github.com/llvm/llvm-project/commit/290f38cd1a9fa7b1a91ddb25632807ecb5308dc7
Author: Ramkumar Ramachandra <ramkumar.ramachandra at codasip.com>
Date: 2024-12-16 (Mon, 16 Dec 2024)
Changed paths:
M llvm/include/llvm/IR/Instructions.h
Log Message:
-----------
IR: fix getSwappedCmpPredicate() return type (#120097)
The change 51a895a (IR: introduce struct with CmpInst::Predicate and
samesign) missed a change to ICmpInst::getSwappedCmpPredicate(), which
intends to return a CmpPredicate, but returns a Predicate instead. Fix
this.
Commit: 0954c67d7ae412af9f8da5149565d9af837ac575
https://github.com/llvm/llvm-project/commit/0954c67d7ae412af9f8da5149565d9af837ac575
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-12-16 (Mon, 16 Dec 2024)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
A llvm/test/CodeGen/X86/pr120093.ll
Log Message:
-----------
[DAG] visitFREEZE - only fold integer types to an all ones constant
ISD::isBuildVectorAllOnes can peek through bitcasts, so this can match against FP NAN (ish) data (e.g. double (bitcast i64 -1)) under certain circumstances - bail if the type isn't an integer and let bitcast folding handle it first.
Fixes #120093
Commit: b21fa18b44dd73284bd1c6551b8046c94f84f9f3
https://github.com/llvm/llvm-project/commit/b21fa18b44dd73284bd1c6551b8046c94f84f9f3
Author: Vedant Paranjape <22630228+VedantParanjape at users.noreply.github.com>
Date: 2024-12-16 (Mon, 16 Dec 2024)
Changed paths:
M llvm/lib/Transforms/Utils/LoopVersioning.cpp
A llvm/test/Transforms/LoopVersioning/crash-36998.ll
Log Message:
-----------
[LoopVersioning] Add a check to see if the input loop is in LCSSA form (#116443)
Loop Optimizations expect the input loop to be in LCSSA form. But it
seems that LoopVersioning doesn't have any check to see if the loop is
actually in LCSSA form. As a result, if we give it a loop which is not
in LCSSA form but still correct semantically, the resulting
transformation fails to pass through verifier pass with the following
error.
Instruction does not dominate all uses!
%inc = add nsw i16 undef, 1
store i16 %inc, ptr @c, align 1
As the loop is not in LCSSA form, LoopVersioning's transformations leads
to invalid IR! As some instructions do not dominate all their uses.
This patch checks if a loop is in LCSSA form, if not it will call
formLCSSARecursively on the loop before passing it to LoopVersioning.
Fixes: #36998
Commit: f75c84674cd8ea3b45b6c711d627144efcf582f5
https://github.com/llvm/llvm-project/commit/f75c84674cd8ea3b45b6c711d627144efcf582f5
Author: Schrodinger ZHU Yifan <yifanzhu at rochester.edu>
Date: 2024-12-16 (Mon, 16 Dec 2024)
Changed paths:
M libc/src/__support/CPP/atomic.h
M libc/src/__support/CPP/type_traits.h
A libc/src/__support/CPP/type_traits/has_unique_object_representations.h
M libc/test/src/__support/CPP/type_traits_test.cpp
Log Message:
-----------
[libc] fix atomic and apply an explicit check on unique object representations (#119715)
Commit: 9919295cfd05222159246d7448ec42392e98fbf2
https://github.com/llvm/llvm-project/commit/9919295cfd05222159246d7448ec42392e98fbf2
Author: Renaud Kauffmann <rkauffmann at nvidia.com>
Date: 2024-12-16 (Mon, 16 Dec 2024)
Changed paths:
M mlir/include/mlir/Dialect/GPU/IR/CompilationInterfaces.h
M mlir/include/mlir/Dialect/GPU/Transforms/Passes.td
M mlir/lib/Dialect/GPU/IR/GPUDialect.cpp
M mlir/lib/Dialect/GPU/Transforms/ModuleToBinary.cpp
M mlir/lib/Target/LLVM/NVVM/Target.cpp
M mlir/lib/Target/LLVMIR/Dialect/GPU/SelectObjectAttr.cpp
M mlir/test/Dialect/GPU/module-to-binary-nvvm.mlir
M mlir/unittests/Target/LLVM/SerializeNVVMTarget.cpp
M mlir/unittests/Target/LLVM/SerializeROCDLTarget.cpp
M mlir/unittests/Target/LLVM/SerializeToLLVMBitcode.cpp
Log Message:
-----------
[mlir][gpu] Adding ELF section option to the gpu-module-to-binary pass (#119440)
This is a follow-up of #117246.
I thought then it would be easy to edit a DictionaryAttr but it turns
out that these attributes are immutable and need to be passed during the
construction of the gpu.binary Op.
The first commit was using the NVVMTargetAttr to pass the information.
After feedback from @fabianmcg, this PR now passes the information
through a new option of the gpu-module-to-binary pass.
Please add reviewers, as you see fit.
Commit: 8217c2eaef2f93427735a45c45c7fd91178e2ed8
https://github.com/llvm/llvm-project/commit/8217c2eaef2f93427735a45c45c7fd91178e2ed8
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-12-16 (Mon, 16 Dec 2024)
Changed paths:
M llvm/lib/Transforms/Vectorize/VectorCombine.cpp
M llvm/test/Transforms/VectorCombine/X86/shuffle-of-cmps.ll
Log Message:
-----------
[VectorCombine] foldShuffleOfBinops - extend to handle icmp/fcmp ops as well (#120075)
Extend binary instructions matching to match compare instructions + predicate as well.
Commit: de401599b10f51258260ea7f1f493d52d22a9d24
https://github.com/llvm/llvm-project/commit/de401599b10f51258260ea7f1f493d52d22a9d24
Author: Justin Bogner <mail at justinbogner.com>
Date: 2024-12-16 (Mon, 16 Dec 2024)
Changed paths:
M clang/lib/Sema/HLSLExternalSemaSource.cpp
M clang/test/AST/HLSL/TypedBuffers-AST.hlsl
M clang/test/CodeGenHLSL/builtins/RWBuffer-subscript.hlsl
Log Message:
-----------
[HLSL] Add RWBuffer::Load(Index) (#117018)
This method is the same as `operator[]`, except that it returns a value
instead of a reference.
Commit: 11d2911ef117aef2afb136339f0c24f8eee10c32
https://github.com/llvm/llvm-project/commit/11d2911ef117aef2afb136339f0c24f8eee10c32
Author: Kazu Hirata <kazu at google.com>
Date: 2024-12-16 (Mon, 16 Dec 2024)
Changed paths:
M lldb/unittests/Core/ProgressReportTest.cpp
Log Message:
-----------
[lldb] Fix warnings
This patch fixes:
third-party/unittest/googletest/include/gtest/gtest.h:1379:11:
error: comparison of integers of different signs: 'const unsigned
long' and 'const int' [-Werror,-Wsign-compare]
Commit: fbb14dd97702db242a31e1b36ca8a3554a73c212
https://github.com/llvm/llvm-project/commit/fbb14dd97702db242a31e1b36ca8a3554a73c212
Author: erichkeane <ekeane at nvidia.com>
Date: 2024-12-16 (Mon, 16 Dec 2024)
Changed paths:
M clang/include/clang/AST/OpenACCClause.h
M clang/include/clang/Basic/DiagnosticSemaKinds.td
M clang/include/clang/Basic/OpenACCClauses.def
M clang/include/clang/Sema/SemaOpenACC.h
M clang/lib/AST/OpenACCClause.cpp
M clang/lib/AST/StmtProfile.cpp
M clang/lib/AST/TextNodeDumper.cpp
M clang/lib/Parse/ParseOpenACC.cpp
M clang/lib/Sema/SemaOpenACC.cpp
M clang/lib/Sema/TreeTransform.h
M clang/lib/Serialization/ASTReader.cpp
M clang/lib/Serialization/ASTWriter.cpp
M clang/test/AST/ast-print-openacc-data-construct.cpp
M clang/test/ParserOpenACC/parse-clauses.c
M clang/test/SemaOpenACC/combined-construct-auto_seq_independent-clauses.c
M clang/test/SemaOpenACC/combined-construct-device_type-clause.c
M clang/test/SemaOpenACC/compute-construct-device_type-clause.c
M clang/test/SemaOpenACC/data-construct-ast.cpp
M clang/test/SemaOpenACC/data-construct-async-clause.c
M clang/test/SemaOpenACC/data-construct-attach-clause.c
M clang/test/SemaOpenACC/data-construct-detach-clause.c
M clang/test/SemaOpenACC/data-construct-deviceptr-clause.c
M clang/test/SemaOpenACC/data-construct-finalize-clause.c
M clang/test/SemaOpenACC/data-construct-if-ast.cpp
M clang/test/SemaOpenACC/data-construct-if-clause.c
M clang/test/SemaOpenACC/data-construct-if_present-ast.cpp
M clang/test/SemaOpenACC/data-construct-if_present-clause.c
M clang/test/SemaOpenACC/data-construct-present-clause.c
A clang/test/SemaOpenACC/data-construct-use_device-ast.cpp
A clang/test/SemaOpenACC/data-construct-use_device-clause.c
M clang/test/SemaOpenACC/data-construct-wait-clause.c
M clang/test/SemaOpenACC/data-construct.cpp
M clang/test/SemaOpenACC/loop-construct-auto_seq_independent-clauses.c
M clang/test/SemaOpenACC/loop-construct-device_type-clause.c
M clang/tools/libclang/CIndex.cpp
Log Message:
-----------
[OpenACC] Implement 'use_device' clause AST/Sema
This is a clause that is only valid on 'host_data' constructs, and
identifies variables which it should use the current device address.
>From a Sema perspective, the only thing novel here is mild changes to
how ActOnVar works for this clause, else this is very much like the rest
of the 'var-list' clauses.
Commit: 4032ce3413d0230b0ccba1203536f9cb35e5c3b5
https://github.com/llvm/llvm-project/commit/4032ce3413d0230b0ccba1203536f9cb35e5c3b5
Author: Sander de Smalen <sander.desmalen at arm.com>
Date: 2024-12-16 (Mon, 16 Dec 2024)
Changed paths:
M compiler-rt/lib/builtins/aarch64/sme-abi.S
M compiler-rt/lib/builtins/aarch64/sme-libc-mem-routines.S
Log Message:
-----------
Revert "[compiler-rt][AArch64] Allow platform-specific mangling of SME routines. (#119864)"
This reverts commit e0fb3acd8a0b2a9340b9b2ae370c84c98f1a5cc2.
Commit: 4f279a570110e3d688356a327637c57071f4b13b
https://github.com/llvm/llvm-project/commit/4f279a570110e3d688356a327637c57071f4b13b
Author: Kazu Hirata <kazu at google.com>
Date: 2024-12-16 (Mon, 16 Dec 2024)
Changed paths:
M mlir/lib/Dialect/Linalg/TransformOps/LinalgTransformOps.cpp
M mlir/lib/Dialect/Linalg/Transforms/ConvertToDestinationStyle.cpp
M mlir/lib/Dialect/Linalg/Transforms/ElementwiseOpFusion.cpp
M mlir/lib/Dialect/Linalg/Transforms/Tiling.cpp
M mlir/lib/Dialect/Linalg/Transforms/Transforms.cpp
Log Message:
-----------
[Linalg] Migrate away from PointerUnion::{is,get} (NFC) (#120043)
Note that PointerUnion::{is,get} have been soft deprecated in
PointerUnion.h:
// FIXME: Replace the uses of is(), get() and dyn_cast() with
// isa<T>, cast<T> and the llvm::dyn_cast<T>
I'm not touching PointerUnion::dyn_cast for now because it's a bit
complicated; we could blindly migrate it to dyn_cast_if_present, but
we should probably use dyn_cast when the operand is known to be
non-null.
Commit: 1dac0cd41f1d04ca66d74c49322ddd93332954f8
https://github.com/llvm/llvm-project/commit/1dac0cd41f1d04ca66d74c49322ddd93332954f8
Author: Kazu Hirata <kazu at google.com>
Date: 2024-12-16 (Mon, 16 Dec 2024)
Changed paths:
M llvm/lib/Transforms/IPO/MemProfContextDisambiguation.cpp
Log Message:
-----------
[memprof] Use ListSeparator (NFC) (#120047)
ListSeparator from StringExtras.h is essentially the same as
FieldSeparator being removed in this patch. ListSeparator returns the
empty string on the first use via "operator StringRef()". It returns
", " on subsequent uses.
Commit: 31272e4f83f24fee1bf37ebc8ea7dd4d082edea8
https://github.com/llvm/llvm-project/commit/31272e4f83f24fee1bf37ebc8ea7dd4d082edea8
Author: Vitaly Buka <vitalybuka at google.com>
Date: 2024-12-16 (Mon, 16 Dec 2024)
Changed paths:
M libcxx/test/std/localization/locale.categories/category.monetary/locale.moneypunct.byname/grouping.pass.cpp
M libcxx/test/std/localization/locale.categories/facet.numpunct/locale.numpunct.byname/grouping.pass.cpp
Log Message:
-----------
[libc++] Update locale grouping tests (#119463)
Fixes #119047
Commit: ef31141ebded71eeb32f7714d924d427a4315540
https://github.com/llvm/llvm-project/commit/ef31141ebded71eeb32f7714d924d427a4315540
Author: Mészáros Gergely <gergely.meszaros at intel.com>
Date: 2024-12-16 (Mon, 16 Dec 2024)
Changed paths:
M clang/include/clang/Driver/Options.td
A clang/test/Driver/unknown-arg-drivermodes.test
Log Message:
-----------
[clang-cl][flang][dxc] Fix opts exposed to clang-cl/dxc by mistake (#118640)
When these options were enabled for flang the visibility was also
extended to clang-cl and dxc. This was due to a
misunderstanding of the default value for `Visibility`.
Commit: 0a7e0486673f829406a9bcb4b49be20dbd9c5e45
https://github.com/llvm/llvm-project/commit/0a7e0486673f829406a9bcb4b49be20dbd9c5e45
Author: Alexander Yermolovich <43973793+ayermolo at users.noreply.github.com>
Date: 2024-12-16 (Mon, 16 Dec 2024)
Changed paths:
M bolt/test/X86/dwarf5-debug-names-gnu-push-tls-address.s
Log Message:
-----------
[BOLT][DWARF][NFC] Minimize dwarf5-debug-names-gnu-push-tls-address.s (#120103)
Removed unnecessary parts from the .text section.
Commit: 7bf3137c39a61283ebcb58793e830f8b768b74e7
https://github.com/llvm/llvm-project/commit/7bf3137c39a61283ebcb58793e830f8b768b74e7
Author: Petr Hosek <phosek at google.com>
Date: 2024-12-16 (Mon, 16 Dec 2024)
Changed paths:
M libc/config/baremetal/aarch64/entrypoints.txt
M libc/config/baremetal/arm/entrypoints.txt
M libc/config/baremetal/riscv/entrypoints.txt
M libc/fuzzing/__support/CMakeLists.txt
A libc/fuzzing/__support/fake_heap.s
M libc/src/__support/CMakeLists.txt
A libc/src/__support/freelist_heap.cpp
M libc/src/stdlib/CMakeLists.txt
M libc/src/stdlib/baremetal/CMakeLists.txt
A libc/src/stdlib/baremetal/aligned_alloc.cpp
A libc/src/stdlib/baremetal/calloc.cpp
A libc/src/stdlib/baremetal/free.cpp
A libc/src/stdlib/baremetal/malloc.cpp
A libc/src/stdlib/baremetal/realloc.cpp
R libc/src/stdlib/freelist_malloc.cpp
M libc/test/src/__support/CMakeLists.txt
R libc/test/src/__support/freelist_malloc_test.cpp
M libc/test/src/stdlib/CMakeLists.txt
Log Message:
-----------
[libc] Breakup freelist_malloc into separate files (#119806)
This better matches the structure we use for the rest of libc.
Commit: d7f3775977875a8208e494bab822b9cdef991822
https://github.com/llvm/llvm-project/commit/d7f3775977875a8208e494bab822b9cdef991822
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-12-16 (Mon, 16 Dec 2024)
Changed paths:
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/test/CodeGen/X86/oddshuffles.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i32-stride-7.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i32-stride-8.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i32-stride-6.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i32-stride-8.ll
Log Message:
-----------
[X86] combineEXTRACT_SUBVECTOR - fold extract_subvector(pshufd(v,i)) -> pshufd(extract_subvector(v,i))
Attempt to avoid unnecessary wide PSHUFD or VPERMILIPS/D instructions by pre-extracting the subvector source if thats its only use.
Commit: 89e530a27c04f1c45a8c9b5cb97099b4b9d2b048
https://github.com/llvm/llvm-project/commit/89e530a27c04f1c45a8c9b5cb97099b4b9d2b048
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-12-16 (Mon, 16 Dec 2024)
Changed paths:
M llvm/test/Analysis/CostModel/X86/shuffle-non-pow-2-codesize.ll
M llvm/test/Analysis/CostModel/X86/shuffle-non-pow-2-latency.ll
M llvm/test/Analysis/CostModel/X86/shuffle-non-pow-2-sizelatency.ll
M llvm/test/Analysis/CostModel/X86/shuffle-non-pow-2.ll
Log Message:
-----------
[CostModel[X86] Update shuffle non-pow-2 tests to not analyse shuffle(undef,undef)
Avoid shuffle patterns that can be folded away.
Commit: 9ee454a57c061e47223e079cdc64d315580367ed
https://github.com/llvm/llvm-project/commit/9ee454a57c061e47223e079cdc64d315580367ed
Author: Adrian Prantl <aprantl at apple.com>
Date: 2024-12-16 (Mon, 16 Dec 2024)
Changed paths:
M lldb/docs/resources/formatterbytecode.rst
Log Message:
-----------
[lldb] Fix RST table formatting
Commit: 750cb896caee7132cde69bdb5b5acab6210fad59
https://github.com/llvm/llvm-project/commit/750cb896caee7132cde69bdb5b5acab6210fad59
Author: Nick Desaulniers <nickdesaulniers at users.noreply.github.com>
Date: 2024-12-16 (Mon, 16 Dec 2024)
Changed paths:
M libc/docs/index.rst
Log Message:
-----------
[libc][docs] Refresh landing page (#120122)
- Replace section on ABI Compatibility with a rephrased warning at the
top of
the page.
- Add links to the Note.
- Update C and POSIX standards.
- Inline link to fuzzing.
Commit: 696d120d091f086532165f938000d86ace7c9ea0
https://github.com/llvm/llvm-project/commit/696d120d091f086532165f938000d86ace7c9ea0
Author: Sergei Barannikov <barannikov88 at gmail.com>
Date: 2024-12-16 (Mon, 16 Dec 2024)
Changed paths:
M llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp
M llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.h
M llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp
M llvm/lib/Target/NVPTX/NVPTXISelLowering.h
M llvm/lib/Target/NVPTX/NVPTXIntrinsics.td
Log Message:
-----------
[NVPTX] Pattern match texture/surface intrinsics (NFCI) (#119982)
Pull Request: https://github.com/llvm/llvm-project/pull/119982
Commit: 3dfc1d9b0bc41eaf63e551ca357b44a71636b152
https://github.com/llvm/llvm-project/commit/3dfc1d9b0bc41eaf63e551ca357b44a71636b152
Author: Jonas Devlieghere <jonas at devlieghere.com>
Date: 2024-12-16 (Mon, 16 Dec 2024)
Changed paths:
M lldb/include/lldb/API/SBDebugger.h
M lldb/include/lldb/Core/Debugger.h
M lldb/include/lldb/Host/Editline.h
M lldb/source/API/SBDebugger.cpp
M lldb/source/Core/CoreProperties.td
M lldb/source/Core/Debugger.cpp
M lldb/source/Host/common/Editline.cpp
M lldb/test/API/functionalities/completion/TestCompletion.py
M lldb/test/API/terminal/TestEditlineCompletions.py
M lldb/tools/driver/Driver.cpp
M lldb/tools/driver/Driver.h
Log Message:
-----------
[lldb] Use the terminal height for paging editline completions (#119914)
Currently, we arbitrarily paginate editline completions to 40 elements.
On large terminals, that leaves some real-estate unused. On small
terminals, it's pretty annoying to not see the first completions. We can
address both issues by using the terminal height for pagination.
This builds on the improvements of #116456.
Commit: b95dfa3920f71c42ef2991f42a95903cc1202c55
https://github.com/llvm/llvm-project/commit/b95dfa3920f71c42ef2991f42a95903cc1202c55
Author: fabrizio-indirli <fabrizio.indirli at arm.com>
Date: 2024-12-16 (Mon, 16 Dec 2024)
Changed paths:
M mlir/lib/Dialect/SPIRV/Transforms/LowerABIAttributesPass.cpp
M mlir/test/Dialect/SPIRV/Transforms/abi-interface.mlir
M mlir/test/Dialect/SPIRV/Transforms/abi-load-store.mlir
Log Message:
-----------
[mlir][spirv] Fix LowerABIAttributesPass to generate EntryPoints for SPV1.4 (#118994)
- Extend the SPIRV::LowerABIAttributesPass to detect when the target env
is using SPIR-V ver >= 1.4, and in this case add all the functions'
interface storage variables to the spirv.EntryPoint calls, as required
by the spec of OpEntryPoint:
"_Before version 1.4, the interface’s storage classes are limited to the
Input and Output storage classes. Starting with version 1.4, the
interface’s storage classes are all storage classes used in declaring
all global variables referenced by the entry point’s call tree_."
- Fix: generate the replacement ops (spirv.AddressOf and .AccessChain)
in the order in which the associated variable appears in the function
signature
Signed-off-by: Fabrizio Indirli <Fabrizio.Indirli at arm.com>
Commit: 89d5272841f7825920ccd911f86b4e8aeb95fb49
https://github.com/llvm/llvm-project/commit/89d5272841f7825920ccd911f86b4e8aeb95fb49
Author: Florian Hahn <flo at fhahn.com>
Date: 2024-12-16 (Mon, 16 Dec 2024)
Changed paths:
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
M llvm/lib/Transforms/Vectorize/VPlan.h
Log Message:
-----------
[VPlan] Remove getPreheader(). (NFC)
The preheader is now the entry block, connected to the vector.ph.
Clean up after https://github.com/llvm/llvm-project/pull/114292.
Commit: bfc2dbe02e00f0023c0a2d58b53cdbd1f4139f02
https://github.com/llvm/llvm-project/commit/bfc2dbe02e00f0023c0a2d58b53cdbd1f4139f02
Author: erichkeane <ekeane at nvidia.com>
Date: 2024-12-16 (Mon, 16 Dec 2024)
Changed paths:
M clang/include/clang/Basic/DiagnosticSemaKinds.td
M clang/include/clang/Sema/SemaOpenACC.h
M clang/lib/Parse/ParseOpenACC.cpp
M clang/lib/Sema/SemaOpenACC.cpp
M clang/lib/Sema/TreeTransform.h
M clang/test/AST/ast-print-openacc-data-construct.cpp
M clang/test/ParserOpenACC/parse-clauses.c
M clang/test/ParserOpenACC/parse-constructs.c
M clang/test/SemaOpenACC/combined-construct-collapse-clause.cpp
M clang/test/SemaOpenACC/combined-construct-if-clause.c
M clang/test/SemaOpenACC/compute-construct-device_type-clause.c
M clang/test/SemaOpenACC/compute-construct-if-clause.c
M clang/test/SemaOpenACC/data-construct-async-ast.cpp
M clang/test/SemaOpenACC/data-construct-copy-clause.c
M clang/test/SemaOpenACC/data-construct-copyin-clause.c
M clang/test/SemaOpenACC/data-construct-copyout-clause.c
M clang/test/SemaOpenACC/data-construct-create-clause.c
M clang/test/SemaOpenACC/data-construct-default-clause.c
M clang/test/SemaOpenACC/data-construct-delete-clause.c
M clang/test/SemaOpenACC/data-construct-device_type-ast.cpp
M clang/test/SemaOpenACC/data-construct-device_type-clause.c
M clang/test/SemaOpenACC/data-construct-no_create-clause.c
M clang/test/SemaOpenACC/data-construct-use_device-clause.c
M clang/test/SemaOpenACC/data-construct.cpp
M clang/test/SemaOpenACC/loop-construct-collapse-clause.cpp
Log Message:
-----------
[OpenACC] Implement data construct 'at least 1 of ... clauses' rule
All 4 of the 'data' constructs have a requirement that at least 1 of a
small list of clauses must appear on the construct. This patch
implements that restriction, and updates all of the tests it takes to
do so.
Commit: f9c8c01d38f8fbea81db99ab90b7d0f2bdcc8b4d
https://github.com/llvm/llvm-project/commit/f9c8c01d38f8fbea81db99ab90b7d0f2bdcc8b4d
Author: Alex MacLean <amaclean at nvidia.com>
Date: 2024-12-16 (Mon, 16 Dec 2024)
Changed paths:
M llvm/lib/Target/NVPTX/NVPTXAsmPrinter.cpp
M llvm/lib/Target/NVPTX/NVPTXMachineFunctionInfo.h
M llvm/lib/Target/NVPTX/NVPTXReplaceImageHandles.cpp
M llvm/lib/Target/NVPTX/NVPTXSubtarget.cpp
M llvm/lib/Target/NVPTX/NVPTXSubtarget.h
M llvm/lib/Target/NVPTX/NVPTXTargetMachine.cpp
M llvm/test/CodeGen/NVPTX/surf-read-cuda.ll
M llvm/test/CodeGen/NVPTX/surf-tex.py
M llvm/test/CodeGen/NVPTX/surf-write-cuda.ll
M llvm/test/CodeGen/NVPTX/tex-read-cuda.ll
M llvm/test/CodeGen/NVPTX/texsurf-queries.ll
Log Message:
-----------
[NVPTX] Aggressively try to replace image handles with references (#119730)
Even in cases where handles are supported, references are still
preferable for performance. This is because, a ref uses one
less register and can avoid the handle creating code associated with
taking the address of a tex/surf/sampler.
Commit: 8f151f0f559c4881a0d206124c64226a82d44a79
https://github.com/llvm/llvm-project/commit/8f151f0f559c4881a0d206124c64226a82d44a79
Author: Jonas Devlieghere <jonas at devlieghere.com>
Date: 2024-12-16 (Mon, 16 Dec 2024)
Changed paths:
M lldb/tools/driver/Driver.cpp
M lldb/tools/driver/Driver.h
Log Message:
-----------
[lldb] Unify window resizing logic in command line driver
Unify the logic for window resizing in the command line driver. This was
prompted by the Windows bot not knowing about the ws_col field.
Commit: 1751914a5229104c51fbea7c91e455650c370908
https://github.com/llvm/llvm-project/commit/1751914a5229104c51fbea7c91e455650c370908
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2024-12-16 (Mon, 16 Dec 2024)
Changed paths:
M .github/workflows/containers/github-action-ci/Dockerfile
Log Message:
-----------
[Github] Add some additional system packages (#119988)
This patch adds some additional system packages to the CI container.
These are necessary for use in the new premerge workflows. The size
increase is not super small, but should be manageable with the size
increase being about 100MB.
Commit: f8656204d7ce2fd97c15ffa134212e0e3dc5f662
https://github.com/llvm/llvm-project/commit/f8656204d7ce2fd97c15ffa134212e0e3dc5f662
Author: Valentin Clement (バレンタイン クレメン) <clementval at gmail.com>
Date: 2024-12-16 (Mon, 16 Dec 2024)
Changed paths:
M flang/lib/Evaluate/tools.cpp
M flang/test/Lower/CUDA/cuda-program-global.cuf
Log Message:
-----------
[flang][cuda] Do not lower device target in porgram as global (#120126)
As it was done in #102512, do not create global for arrays declared in
program unit with cuda data attribute.
Commit: 1be4a67454b02dae4df2368af31b5f655736d829
https://github.com/llvm/llvm-project/commit/1be4a67454b02dae4df2368af31b5f655736d829
Author: QuietMisdreavus <QuietMisdreavus at users.noreply.github.com>
Date: 2024-12-16 (Mon, 16 Dec 2024)
Changed paths:
M clang/lib/ExtractAPI/Serialization/SymbolGraphSerializer.cpp
M clang/test/ExtractAPI/objc_external_category.m
Log Message:
-----------
[ExtractAPI] reorder the module names in extension symbol graph file names (#119925)
Resolves rdar://140298287
ExtractAPI's support for printing Objective-C category extensions from
other modules emits symbol graphs with an
`ExtendedModule at HostModule.symbols.json`. However, this is backwards
from existing symbol graph practices, causing issues when these symbol
graphs are consumed alongside symbol graphs generated with other tools
like Swift. This PR flips the naming scheme to be in line with existing
symbol graph tooling.
Commit: 58da789e72c3d26c9dac1b29884f5ce62b8150b1
https://github.com/llvm/llvm-project/commit/58da789e72c3d26c9dac1b29884f5ce62b8150b1
Author: Andrzej Warzyński <andrzej.warzynski at arm.com>
Date: 2024-12-16 (Mon, 16 Dec 2024)
Changed paths:
M mlir/lib/Dialect/Linalg/Transforms/Transforms.cpp
M mlir/test/Dialect/Linalg/decompose-tensor-unpack.mlir
Log Message:
-----------
[mlir][linalg] Fix and Refactor DecomposeOuterUnitDimsUnPackOpPattern (#119379)
Commit: b558c6b288c469959fbb2827bfbaba57a79932cb
https://github.com/llvm/llvm-project/commit/b558c6b288c469959fbb2827bfbaba57a79932cb
Author: Andrzej Warzyński <andrzej.warzynski at arm.com>
Date: 2024-12-16 (Mon, 16 Dec 2024)
Changed paths:
M mlir/test/Dialect/Linalg/vectorize-tensor-extract.mlir
Log Message:
-----------
[mlir][nfc] Update vectorize-tensor-extract.mlir (4/N) (#119697)
Commit: 9f1c8b13f1f81f79ec3beeca4c0b14c7dd3a76ca
https://github.com/llvm/llvm-project/commit/9f1c8b13f1f81f79ec3beeca4c0b14c7dd3a76ca
Author: Andrzej Warzyński <andrzej.warzynski at arm.com>
Date: 2024-12-16 (Mon, 16 Dec 2024)
Changed paths:
A mlir/test/Integration/Dialect/Linalg/CPU/ArmSVE/pack-scalable-inner-tile.mlir
Log Message:
-----------
[mlir][tensor][SVE] Add e2e test for tensor.pack targeting SVE (#119692)
Commit: 1297933f35b4948b4d281259627a72094c407a75
https://github.com/llvm/llvm-project/commit/1297933f35b4948b4d281259627a72094c407a75
Author: Thurston Dang <thurston at google.com>
Date: 2024-12-16 (Mon, 16 Dec 2024)
Changed paths:
M llvm/test/CodeGen/AMDGPU/ran-out-of-registers-error-all-regs-reserved.ll
M llvm/test/CodeGen/AMDGPU/ran-out-of-registers-errors.ll
Log Message:
-----------
[CodeGen] Disable ran-out-of-registers-error* tests (#120142)
Two tests are failing on the buildbot in stage2/asan with a stack
use-after-scope:
https://lab.llvm.org/buildbot/#/builders/52/builds/4533 (first failure
here; contains https://github.com/llvm/llvm-project/pull/119492 and
https://github.com/llvm/llvm-project/pull/119640)
...
https://lab.llvm.org/buildbot/#/builders/52/builds/4550
This patch disables the tests for now, to allow the bots to return to
green (instead of reverting the patch series).
Commit: df0b34cbeb822c81fec43390663659bea97dd2ae
https://github.com/llvm/llvm-project/commit/df0b34cbeb822c81fec43390663659bea97dd2ae
Author: erichkeane <ekeane at nvidia.com>
Date: 2024-12-16 (Mon, 16 Dec 2024)
Changed paths:
M clang/include/clang/AST/StmtOpenACC.h
Log Message:
-----------
[OpenACC/NFC] Fix 'trailing objects' CRTP.
A previous patch mistakenly set the CRTP object for the trailing objects
incorrectly. This patch fixes those. This wasn't noticed in testing,
since these types have the same layout.
Commit: f9120dc2a60aedcab5ce99e40b6a2bd3849f0bb9
https://github.com/llvm/llvm-project/commit/f9120dc2a60aedcab5ce99e40b6a2bd3849f0bb9
Author: Florian Hahn <flo at fhahn.com>
Date: 2024-12-16 (Mon, 16 Dec 2024)
Changed paths:
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
Log Message:
-----------
[VPlan] Make sure vector trip count is ready for prepareToExecute (NFC)
Split off from https://github.com/llvm/llvm-project/pull/112145. This
ensures that getOrCreateVectorTripCount creates the trip count as needed
when induction resume value creation is moved to VPlan and no longer
creates the vector trip count early.
Commit: a9237b1a1083c7c6c4778e8a586d329bc41a6adc
https://github.com/llvm/llvm-project/commit/a9237b1a1083c7c6c4778e8a586d329bc41a6adc
Author: Artem Pianykh <artem.pyanykh at gmail.com>
Date: 2024-12-16 (Mon, 16 Dec 2024)
Changed paths:
M llvm/include/llvm/Transforms/Utils/Cloning.h
M llvm/lib/Transforms/Utils/CloneFunction.cpp
Log Message:
-----------
[NFC][Utils] Extract CloneFunctionMetadataInto from CloneFunctionInto (#118623)
Summary:
The new API expects the caller to populate the VMap. We need it this way
for a subsequent change around coroutine cloning.
Test Plan:
ninja check-llvm-unit check-llvm
Commit: 0b442bc51631552ab8a249485dd81b5c83cf5a5d
https://github.com/llvm/llvm-project/commit/0b442bc51631552ab8a249485dd81b5c83cf5a5d
Author: Slava Zakharin <szakharin at nvidia.com>
Date: 2024-12-16 (Mon, 16 Dec 2024)
Changed paths:
M flang/lib/Optimizer/HLFIR/Transforms/OptimizedBufferization.cpp
Log Message:
-----------
[flang][NFC] Added debug output to opt-bufferization pass. (#119936)
Commit: 3769fcb3e78eba5f3e34d1c2dfa994625edb005a
https://github.com/llvm/llvm-project/commit/3769fcb3e78eba5f3e34d1c2dfa994625edb005a
Author: vporpo <vporpodas at google.com>
Date: 2024-12-16 (Mon, 16 Dec 2024)
Changed paths:
M llvm/include/llvm/Transforms/Vectorize/SandboxVectorizer/Interval.h
M llvm/unittests/Transforms/Vectorize/SandboxVectorizer/IntervalTest.cpp
Log Message:
-----------
[SandboxVec][Interval] Implement Interval::notifyMoveInstr() (#119471)
This patch implements the notifier for Instruction intervals. It updates
the interval's top/bottom.
Commit: b86a22aa3915c5ed7f802ebad7578c0906bdd8a9
https://github.com/llvm/llvm-project/commit/b86a22aa3915c5ed7f802ebad7578c0906bdd8a9
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2024-12-16 (Mon, 16 Dec 2024)
Changed paths:
M .github/workflows/build-ci-container.yml
M .github/workflows/containers/github-action-ci/Dockerfile
Log Message:
-----------
[Github] Default to non-root user in linux CI container (#119987)
This patch sets the default user in the linux CI container to a non-root
user, which enables properly testing a couple of features, particularly
in libcxx.
Commit: 2fe296965930932be9b7b155bf8c10a0f81c58cf
https://github.com/llvm/llvm-project/commit/2fe296965930932be9b7b155bf8c10a0f81c58cf
Author: Jay Foad <jay.foad at amd.com>
Date: 2024-12-16 (Mon, 16 Dec 2024)
Changed paths:
M llvm/include/llvm/CodeGenTypes/LowLevelType.h
M llvm/lib/CodeGenTypes/LowLevelType.cpp
Log Message:
-----------
[CodeGen] Simplify LLT bitfields. NFC. (#120074)
- Put the element size field in the same place for all non-pointer
types.
- Put the element size and address space fields in the same place for
all pointer types.
- Put the number of elements and scalable fields in the same place for
all vector types.
This simplifies initialization and accessor methods isScalable,
getElementCount, getScalarSizeInBits and getAddressSpace.
Commit: 51a0919412cf1868de689e03024c6f761a1b8b0a
https://github.com/llvm/llvm-project/commit/51a0919412cf1868de689e03024c6f761a1b8b0a
Author: Petr Hosek <phosek at google.com>
Date: 2024-12-16 (Mon, 16 Dec 2024)
Changed paths:
M libc/fuzzing/__support/CMakeLists.txt
M libc/test/src/__support/CMakeLists.txt
Log Message:
-----------
[libc] Exclude FreeListHeap test and fuzzer on GPU (#120137)
FreeListHeap uses the _end symbol which conflicts with the _end symbol
defined by GPU start.cpp files so for now we exclude the test and the
fuzzer on GPU.
Commit: 484a2819de1bbee5aec5fabb942c7ebb77d29bc0
https://github.com/llvm/llvm-project/commit/484a2819de1bbee5aec5fabb942c7ebb77d29bc0
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2024-12-16 (Mon, 16 Dec 2024)
Changed paths:
A .github/workflows/premerge.yaml
Log Message:
-----------
[CI][Github] Add linux premerge workflow (#119635)
This patch adds a Github Actions workflow for Linux premerge. This
currently just calls into the existing CI scripts as a starting point.
Commit: 67ae944bfa97db737e2600ca0bcc2f35fc6cef9e
https://github.com/llvm/llvm-project/commit/67ae944bfa97db737e2600ca0bcc2f35fc6cef9e
Author: Valentin Clement (バレンタイン クレメン) <clementval at gmail.com>
Date: 2024-12-16 (Mon, 16 Dec 2024)
Changed paths:
M flang/lib/Semantics/check-cuda.cpp
M flang/test/Semantics/cuf09.cuf
Log Message:
-----------
[flang][cuda] Check for use of host array in device context (#119756)
Now that variables have implicit attribute, we can check for illegal use
of module host variable in device context.
Commit: 38099d0608342ddff0737a048ca5fa325c4b0749
https://github.com/llvm/llvm-project/commit/38099d0608342ddff0737a048ca5fa325c4b0749
Author: SpencerAbson <Spencer.Abson at arm.com>
Date: 2024-12-16 (Mon, 16 Dec 2024)
Changed paths:
M clang/include/clang/Basic/arm_sme.td
A clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_mla.c
M clang/test/Sema/aarch64-fp8-intrinsics/acle_sme2_fp8_imm.c
A clang/test/Sema/aarch64-fp8-intrinsics/acle_sme2_fp8_mla.c
M llvm/include/llvm/IR/IntrinsicsAArch64.td
M llvm/lib/Target/AArch64/AArch64SMEInstrInfo.td
M llvm/lib/Target/AArch64/SMEInstrFormats.td
A llvm/test/CodeGen/AArch64/sme2-fp8-intrinsics-mla.ll
Log Message:
-----------
[AArch64] Implement intrinsics for SME FP8 FMLAL/FMLALL (Indexed) (#118549)
This patch implements the following intrinsics:
Multi-vector 8-bit floating-point multiply-add long.
``` c
// Only if __ARM_FEATURE_SME_F8F16 != 0
void svmla_lane_za16[_mf8]_vg2x1_fpm(uint32_t slice, svmfloat8_t zn,
svmfloat8_t zm, uint64_t imm_idx,
fpm_t fpm) __arm_streaming __arm_inout("za");
void svmla_lane_za16[_mf8]_vg2x2_fpm(uint32_t slice, svmfloat8x2_t zn,
svmfloat8_t zm, uint64_t imm_idx,
fpm_t fpm) __arm_streaming __arm_inout("za");
void svmla_lane_za16[_mf8]_vg2x4_fpm(uint32_t slice, svmfloat8x4_t zn,
svmfloat8_t zm, uint64_t imm_idx
fpm_t fpm) __arm_streaming __arm_inout("za");
// Only if __ARM_FEATURE_SME_F8F32 != 0
void svmla_lane_za32[_mf8]_vg4x1_fpm(uint32_t slice, svmfloat8_t zn,
svmfloat8_t zm, uint64_t imm_idx,
fpm_t fpm)__arm_streaming __arm_inout("za");
void svmla_lane_za32[_mf8]_vg4x2_fpm(uint32_t slice, svmfloat8x2_t zn,
svmfloat8_t zm, uint64_t imm_idx,
fpm_t fpm)__arm_streaming __arm_inout("za");
void svmla_lane_za32[_mf8]_vg4x4_fpm(uint32_t slice, svmfloat8x4_t zn,
svmfloat8_t zm, uint64_t imm_idx,
fpm_t fpm)__arm_streaming __arm_inout("za");
```
In accordance with: https://github.com/ARM-software/acle/pull/323
Commit: 8402a0fab09a2c3a1b5c2e23e2ababcb575709d7
https://github.com/llvm/llvm-project/commit/8402a0fab09a2c3a1b5c2e23e2ababcb575709d7
Author: Artem Pianykh <artem.pyanykh at gmail.com>
Date: 2024-12-16 (Mon, 16 Dec 2024)
Changed paths:
M llvm/include/llvm/Transforms/Utils/Cloning.h
M llvm/lib/Transforms/Utils/CloneFunction.cpp
Log Message:
-----------
[NFC][Utils] Extract CloneFunctionBodyInto from CloneFunctionInto (#118624)
Summary:
This and previously extracted `CloneFunction*Into` functions will be used in later diffs.
Test Plan:
ninja check-llvm-unit check-llvm
Commit: 8c163237573df097a99b65a83280757d1b39062c
https://github.com/llvm/llvm-project/commit/8c163237573df097a99b65a83280757d1b39062c
Author: erichkeane <ekeane at nvidia.com>
Date: 2024-12-16 (Mon, 16 Dec 2024)
Changed paths:
M clang/include/clang/AST/OpenACCClause.h
M clang/include/clang/AST/StmtOpenACC.h
Log Message:
-----------
[OpenACC/NFC] Make 'trailing objects' use private inheritence.
I noticed this while working on something else, these are supposed to be
privately inherited.
Commit: 084309a0ef781b45f5d124732ba20be89b61b6de
https://github.com/llvm/llvm-project/commit/084309a0ef781b45f5d124732ba20be89b61b6de
Author: Louis Dionne <ldionne.2 at gmail.com>
Date: 2024-12-16 (Mon, 16 Dec 2024)
Changed paths:
M libcxx/docs/ReleaseNotes/20.rst
M libcxx/include/CMakeLists.txt
M libcxx/include/__locale_dir/locale_base_api.h
R libcxx/include/__locale_dir/locale_base_api/win32.h
M libcxx/include/__locale_dir/locale_guard.h
A libcxx/include/__locale_dir/support/windows.h
M libcxx/include/module.modulemap
M libcxx/src/support/win32/locale_win32.cpp
M libcxx/src/support/win32/support.cpp
Log Message:
-----------
[libc++] Refactor the Windows and MinGW implementation of the locale base API (#115752)
This patch reimplements the locale base support for Windows flavors in a
way that is more modules-friendly and without defining non-internal
names.
Since this changes the name of some types and entry points in the built
library, this is effectively an ABI break on Windows (which is
acceptable after checking with the Windows/libc++ maintainers).
Commit: 46bbd2c80eb8673ef54decc6d3d55350e3126f50
https://github.com/llvm/llvm-project/commit/46bbd2c80eb8673ef54decc6d3d55350e3126f50
Author: LLVM GN Syncbot <llvmgnsyncbot at gmail.com>
Date: 2024-12-16 (Mon, 16 Dec 2024)
Changed paths:
M llvm/utils/gn/secondary/libcxx/include/BUILD.gn
Log Message:
-----------
[gn build] Port 084309a0ef78
Commit: 482237e884dde4a7887c6ac3609437c7186b5124
https://github.com/llvm/llvm-project/commit/482237e884dde4a7887c6ac3609437c7186b5124
Author: Justin Bogner <mail at justinbogner.com>
Date: 2024-12-16 (Mon, 16 Dec 2024)
Changed paths:
M llvm/include/llvm/Analysis/DXILResource.h
M llvm/lib/Analysis/DXILResource.cpp
M llvm/lib/Target/DirectX/DXILOpLowering.cpp
M llvm/lib/Target/DirectX/DXILPrettyPrinter.cpp
M llvm/lib/Target/DirectX/DXILTranslateMetadata.cpp
M llvm/test/Analysis/DXILResource/buffer-frombinding.ll
M llvm/unittests/Analysis/DXILResourceTest.cpp
Log Message:
-----------
[DirectX] Get resource information via TargetExtType (#119772)
Instead of storing an auxilliary structure with the information from the
DXIL resource target extension types duplicated, access the information
that we can via the type itself.
This also means we need to handle some of the target extension types we
haven't fully defined yet, like Texture and CBuffer. For now we make an
educated guess to what those should look like based on llvm/wg-hlsl#76,
and we can update them fairly easily when we've defined them more
thoroughly.
First part of #118400
Commit: a8456c9a2fb36f7c3a69eaa296c3f5d23ec52fe5
https://github.com/llvm/llvm-project/commit/a8456c9a2fb36f7c3a69eaa296c3f5d23ec52fe5
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2024-12-16 (Mon, 16 Dec 2024)
Changed paths:
M .github/workflows/premerge.yaml
Log Message:
-----------
[Github] Enable new premerge workflow postcommit
This patch enables the new premerge workflow postcommit so that we can start
testing it at a reasonable scale with minimal disruption.
Commit: 13449c3de45111d21a1a7dc4df8be1c29bff6447
https://github.com/llvm/llvm-project/commit/13449c3de45111d21a1a7dc4df8be1c29bff6447
Author: Nick Desaulniers <nickdesaulniers at users.noreply.github.com>
Date: 2024-12-16 (Mon, 16 Dec 2024)
Changed paths:
A libc/docs/arch_support.rst
M libc/docs/index.rst
A libc/docs/platform_support.rst
Log Message:
-----------
[libc][docs] split up platform and arch support (#120125)
Creates a new toctree "Support" under which we have distinct links to arch,
platform, and compiler support.
* Moved "Platform Support" from index landing page to new doc.
* Created explicit "Architecture Support". Requested in https://github.com/llvm/llvm-project/issues/118964#issuecomment-2531503046.
* Moved "Compiler Support" from Status toctree to new Support toctree.
---------
Co-authored-by: Carlo Cabrera <github at carlo.cab>
Commit: 0f6d93f8d5c99f137c05be23fe2cc161154d73df
https://github.com/llvm/llvm-project/commit/0f6d93f8d5c99f137c05be23fe2cc161154d73df
Author: Florian Hahn <flo at fhahn.com>
Date: 2024-12-16 (Mon, 16 Dec 2024)
Changed paths:
A llvm/test/Transforms/LoopVectorize/epilog-iv-select-cmp.ll
Log Message:
-----------
[LV] Add test showing bug in epilogue vectorization of selects.
This is causing mis-compiles when in SPEC2017 on AArch64 after
b3cba9be41bfa8.
Commit: 0e528ac404e13ed2d952a2d83aaf8383293c851e
https://github.com/llvm/llvm-project/commit/0e528ac404e13ed2d952a2d83aaf8383293c851e
Author: Florian Hahn <flo at fhahn.com>
Date: 2024-12-16 (Mon, 16 Dec 2024)
Changed paths:
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
M llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
M llvm/test/Transforms/LoopVectorize/epilog-iv-select-cmp.ll
Log Message:
-----------
[VPlan] Use start value operand for FindLastIV reduction phis.
Update VPReductionPHIRecipe::execute to use the start value from the
start value operand of the recipe. This is needed to make sure we resume
from the correct value during epilogue vectorization.
At the moment, the start value is set to the sentinel value in
adjustRecipesForReductions, as the original start value needs to be used
when creating ResumePhi recipes.
Fixes a mis-compile introduced by b3cba9be41bfa8 in SPEC2017 on AArch64.
Commit: dda1d1674755e0e68789e01ed8698ea91b0b54b0
https://github.com/llvm/llvm-project/commit/dda1d1674755e0e68789e01ed8698ea91b0b54b0
Author: norx1991 <yifei.xu at utexas.edu>
Date: 2024-12-16 (Mon, 16 Dec 2024)
Changed paths:
M utils/bazel/llvm-project-overlay/mlir/BUILD.bazel
Log Message:
-----------
Update BUILD.bazel
Fix issue introduced by https://github.com/llvm/llvm-project/pull/118839.
Commit: 41a6e9cfd693c8570d48e73c5649d83ee6376b6d
https://github.com/llvm/llvm-project/commit/41a6e9cfd693c8570d48e73c5649d83ee6376b6d
Author: Ashley Coleman <ascoleman at microsoft.com>
Date: 2024-12-16 (Mon, 16 Dec 2024)
Changed paths:
M clang/include/clang/Basic/Builtins.td
M clang/lib/CodeGen/CGBuiltin.cpp
M clang/lib/CodeGen/CGHLSLRuntime.h
M clang/lib/Headers/hlsl/hlsl_intrinsics.h
A clang/test/CodeGenHLSL/builtins/WaveActiveAllTrue.hlsl
A clang/test/SemaHLSL/BuiltIns/WaveActiveAllTrue-errors.hlsl
M llvm/include/llvm/IR/IntrinsicsDirectX.td
M llvm/include/llvm/IR/IntrinsicsSPIRV.td
M llvm/lib/Target/DirectX/DXIL.td
M llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
A llvm/test/CodeGen/DirectX/WaveActiveAllTrue.ll
A llvm/test/CodeGen/SPIRV/hlsl-intrinsics/WaveActiveAllTrue.ll
Log Message:
-----------
[HLSL] Implement `WaveActiveAllTrue` Intrinsic (#117245)
Resolves https://github.com/llvm/llvm-project/issues/99161
- [x] Implement `WaveActiveAllTrue` clang builtin,
- [x] Link `WaveActiveAllTrue` clang builtin with `hlsl_intrinsics.h`
- [x] Add sema checks for `WaveActiveAllTrue` to
`CheckHLSLBuiltinFunctionCall` in `SemaChecking.cpp`
- [x] Add codegen for `WaveActiveAllTrue` to `EmitHLSLBuiltinExpr` in
`CGBuiltin.cpp`
- [x] Add codegen tests to
`clang/test/CodeGenHLSL/builtins/WaveActiveAllTrue.hlsl`
- [x] Add sema tests to
`clang/test/SemaHLSL/BuiltIns/WaveActiveAllTrue-errors.hlsl`
- [x] Create the `int_dx_WaveActiveAllTrue` intrinsic in
`IntrinsicsDirectX.td`
- [x] Create the `DXILOpMapping` of `int_dx_WaveActiveAllTrue` to `114`
in `DXIL.td`
- [x] Create the `WaveActiveAllTrue.ll` and
`WaveActiveAllTrue_errors.ll` tests in `llvm/test/CodeGen/DirectX/`
- [x] Create the `int_spv_WaveActiveAllTrue` intrinsic in
`IntrinsicsSPIRV.td`
- [x] In SPIRVInstructionSelector.cpp create the `WaveActiveAllTrue`
lowering and map it to `int_spv_WaveActiveAllTrue` in
`SPIRVInstructionSelector::selectIntrinsic`.
- [x] Create SPIR-V backend test case in
`llvm/test/CodeGen/SPIRV/hlsl-intrinsics/WaveActiveAllTrue.ll`
Commit: 72e8b9aeaa3f584f223bc59924812df69a09a48b
https://github.com/llvm/llvm-project/commit/72e8b9aeaa3f584f223bc59924812df69a09a48b
Author: Mehdi Amini <joker.eph at gmail.com>
Date: 2024-12-17 (Tue, 17 Dec 2024)
Changed paths:
M mlir/include/mlir/Dialect/GPU/IR/CompilationInterfaces.h
M mlir/include/mlir/IR/BuiltinAttributeInterfaces.td
M mlir/include/mlir/IR/BuiltinAttributes.td
M mlir/include/mlir/Target/LLVM/ModuleToObject.h
M mlir/include/mlir/Target/LLVM/NVVM/Utils.h
M mlir/include/mlir/Target/LLVM/ROCDL/Utils.h
M mlir/lib/Dialect/GPU/IR/GPUDialect.cpp
M mlir/lib/Dialect/GPU/Transforms/ModuleToBinary.cpp
M mlir/lib/IR/BuiltinAttributes.cpp
M mlir/lib/Target/LLVM/ModuleToObject.cpp
M mlir/lib/Target/LLVM/NVVM/Target.cpp
M mlir/lib/Target/LLVM/ROCDL/Target.cpp
M mlir/unittests/Target/LLVM/CMakeLists.txt
M mlir/unittests/Target/LLVM/SerializeNVVMTarget.cpp
Log Message:
-----------
[MLIR] Add a BlobAttr interface for attribute to wrap arbitrary content and use it as linkLibs for ModuleToObject (#120116)
This change allows to expose through an interface attributes wrapping
content as external resources, and the usage inside the ModuleToObject
show how we will be able to provide runtime libraries without relying on
the filesystem.
Commit: 6e58e99a07facd73547f7fa1a6f8c0719d8af30d
https://github.com/llvm/llvm-project/commit/6e58e99a07facd73547f7fa1a6f8c0719d8af30d
Author: Sirraide <aeternalmail at gmail.com>
Date: 2024-12-17 (Tue, 17 Dec 2024)
Changed paths:
M clang/docs/MatrixTypes.rst
M clang/docs/ReleaseNotes.rst
M clang/include/clang/Basic/DiagnosticSemaKinds.td
M clang/lib/Sema/SemaType.cpp
A clang/test/CodeGenCXX/matrix-vector-bit-int.cpp
M clang/test/SemaCXX/matrix-type.cpp
Log Message:
-----------
[Clang] [Sema] Reject non-power-of-2 `_BitInt` matrix element types (#117487)
Essentially, this makes this ill-formed:
```c++
using mat4 = _BitInt(12) [[clang::matrix_type(3, 3)]];
```
This matches preexisting behaviour for vector types (e.g.
`ext_vector_type`), and given that LLVM IR intrinsics for matrices also
take vector types, it seems like a sensible thing to do.
This is currently especially problematic since we sometimes lower matrix
types to LLVM array types instead, and while e.g. `[4 x i32]` and `<4 x
i32>` *probably* have the same similar memory layout (though I don’t
think it’s sound to rely on that either, see #117486), `[4 x i12]` and
`<4 x i12>` definitely don’t.
Commit: a1766699c66e7b9f8094256f98de57ba79099e94
https://github.com/llvm/llvm-project/commit/a1766699c66e7b9f8094256f98de57ba79099e94
Author: Jie Fu <jiefu at tencent.com>
Date: 2024-12-17 (Tue, 17 Dec 2024)
Changed paths:
M clang/lib/CodeGen/CGBuiltin.cpp
Log Message:
-----------
[clang] Fix -Wunused-variable in CGBuiltin.cpp (NFC)
/llvm-project/clang/lib/CodeGen/CGBuiltin.cpp:19441:17:
error: unused variable 'Ty' [-Werror,-Wunused-variable]
llvm::Type *Ty = Op->getType();
^
1 error generated.
Commit: f0878995c217d6c6f808532fcfa106a7c680ce5a
https://github.com/llvm/llvm-project/commit/f0878995c217d6c6f808532fcfa106a7c680ce5a
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2024-12-17 (Tue, 17 Dec 2024)
Changed paths:
M .github/workflows/premerge.yaml
Log Message:
-----------
[Github] Fix concurrency groups for premerge
According to https://docs.github.com/en/rest/using-the-rest-api/github-event-types?apiVersion=2022-11-28,
When we look at the push event payload, github.event.push.head is a string
containing the SHA. This is currently causing new commits on main to cancel
the premerge pipeline of older commits.
Commit: bf700c39d1c9f88387bfe2ec4567567397200ea3
https://github.com/llvm/llvm-project/commit/bf700c39d1c9f88387bfe2ec4567567397200ea3
Author: Teresa Johnson <tejohnson at google.com>
Date: 2024-12-16 (Mon, 16 Dec 2024)
Changed paths:
M llvm/lib/Analysis/MemoryProfileInfo.cpp
Log Message:
-----------
[MemProf] Remove dead code (NFC) (#120156)
Remove unused collection of context size information that was likely
leftover from debugging / testing.
Commit: fba3e069b4ed38b16754d5e45837bfec9d5a372a
https://github.com/llvm/llvm-project/commit/fba3e069b4ed38b16754d5e45837bfec9d5a372a
Author: Luke Lau <luke at igalia.com>
Date: 2024-12-17 (Tue, 17 Dec 2024)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlan.h
Log Message:
-----------
[VPlan] Remove overlapping VPInstruction::mayWriteToMemory. NFCI (#120039)
VPInstruction has a definition of mayWriteToMemory, which seems to only
be used by VPlanSLP. However VPInstructions are already handled in
VPRecipeBase::mayWriteToMemory, and everywhere else seems to use this
definition. I think these should be the same for all intents and
purposes. The VPRecipeBase definition is more conservative but returns
true for stores/calls/invokes/SLPStores.
Commit: 5e1f87e849d1f94f3e8baf190be20219edf44584
https://github.com/llvm/llvm-project/commit/5e1f87e849d1f94f3e8baf190be20219edf44584
Author: Valentin Clement (バレンタイン クレメン) <clementval at gmail.com>
Date: 2024-12-16 (Mon, 16 Dec 2024)
Changed paths:
M flang/lib/Optimizer/CodeGen/CodeGen.cpp
A flang/test/Fir/CUDA/cuda-code-gen.mlir
Log Message:
-----------
[flang][cuda] Correctly allocate memory for descriptor load (#120164)
CodeGen will allocate memory for a new descriptor on descriptor loads.
CUDA Fortran local descriptor are allocated in managed memory by the
runtime. The newly allocated storage for cuda descriptor must also be
allocated through the runtime.
Commit: ad64946549e377e5cfdcfe84081149b7aa17c4d6
https://github.com/llvm/llvm-project/commit/ad64946549e377e5cfdcfe84081149b7aa17c4d6
Author: Koakuma <koachan at protonmail.com>
Date: 2024-12-17 (Tue, 17 Dec 2024)
Changed paths:
M llvm/lib/Target/Sparc/AsmParser/SparcAsmParser.cpp
M llvm/lib/Target/Sparc/DelaySlotFiller.cpp
M llvm/lib/Target/Sparc/SparcInstrInfo.td
M llvm/test/MC/Sparc/sparc-ctrl-instructions.s
Log Message:
-----------
[SPARC][IAS] Add support for `call dest, imm` form (#119078)
This follows GCC behavior of allowing a trailing immediate, that is
ignored by the assembler.
Commit: 2806705c4bf69cbb1a8e482104efb9429bb50683
https://github.com/llvm/llvm-project/commit/2806705c4bf69cbb1a8e482104efb9429bb50683
Author: Ivan R. Ivanov <ivanov.i.aa at m.titech.ac.jp>
Date: 2024-12-17 (Tue, 17 Dec 2024)
Changed paths:
M mlir/include/mlir/Dialect/LLVMIR/NVVMOps.td
M mlir/test/Target/LLVMIR/Import/nvvmir.ll
Log Message:
-----------
[MLIR][NVVM] Enable import of nvvm.barrier0 (#119965)
Co-authored-by: Tobias Gysi <tobias.gysi at nextsilicon.com>
Commit: e2a94a97bdf26198ab254d61ee4be23a140dab2d
https://github.com/llvm/llvm-project/commit/e2a94a97bdf26198ab254d61ee4be23a140dab2d
Author: Yifei Xu <yifei.xu at utexas.edu>
Date: 2024-12-16 (Mon, 16 Dec 2024)
Changed paths:
M utils/bazel/llvm-project-overlay/mlir/BUILD.bazel
Log Message:
-----------
Update BUILD.bazel
Fix bazel build after https://github.com/llvm/llvm-project/pull/120116
Commit: c6ff809ae9acbc90455dc8b58b2dae84a13366cf
https://github.com/llvm/llvm-project/commit/c6ff809ae9acbc90455dc8b58b2dae84a13366cf
Author: Fangrui Song <i at maskray.me>
Date: 2024-12-16 (Mon, 16 Dec 2024)
Changed paths:
M llvm/docs/CommandGuide/llvm-mc.rst
A llvm/test/MC/Disassembler/X86/hex-bytes.txt
M llvm/tools/llvm-mc/Disassembler.cpp
M llvm/tools/llvm-mc/Disassembler.h
M llvm/tools/llvm-mc/llvm-mc.cpp
Log Message:
-----------
[llvm-mc] Add --hex to disassemble hex bytes
`--disassemble`/`--cdis` parses input bytes as decimal, 0bbin, 0ooct, or
0xhex. While the hexadecimal digit form is most commonly used, requiring
a 0x prefix for each byte (`0x48 0x29 0xc3`) is cumbersome.
Tools like xxd -p and rz-asm use a plain hex dump form without the 0x
prefix or space separator. This patch adds --hex to disassemble such hex
bytes with optional whitespace.
```
% rz-asm -a x86 -b 64 -d 4829c34829c4
sub rbx, rax
sub rsp, rax
% llvm-mc -triple=x86_64 --cdis --hex --output-asm-variant=1 <<< 4829c34829c4
.text
sub rbx, rax
sub rsp, rax
```
Pull Request: https://github.com/llvm/llvm-project/pull/119992
Commit: 056cd12284f72105a3e2338f901882e43a90c8b2
https://github.com/llvm/llvm-project/commit/056cd12284f72105a3e2338f901882e43a90c8b2
Author: Timm Baeder <tbaeder at redhat.com>
Date: 2024-12-17 (Tue, 17 Dec 2024)
Changed paths:
M clang/lib/AST/ByteCode/Interp.h
M clang/test/AST/ByteCode/functions.cpp
Log Message:
-----------
[clang][bytecode] Don't check returned pointers for liveness (#120107)
We're supposed to let them through and then later diagnose reading from
them, but returning dead pointers is fine.
Commit: e2cabd715bb6e8c81fe7437e74ccf78e4db5edf7
https://github.com/llvm/llvm-project/commit/e2cabd715bb6e8c81fe7437e74ccf78e4db5edf7
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2024-12-17 (Tue, 17 Dec 2024)
Changed paths:
M llvm/lib/CodeGen/RegAllocGreedy.cpp
Log Message:
-----------
RegAllocGreedy: Fix comment typo
Commit: eb5c21108fca4c871987faef581158811954c916
https://github.com/llvm/llvm-project/commit/eb5c21108fca4c871987faef581158811954c916
Author: Sirraide <aeternalmail at gmail.com>
Date: 2024-12-17 (Tue, 17 Dec 2024)
Changed paths:
M clang/docs/ReleaseNotes.rst
M clang/lib/Sema/SemaExprCXX.cpp
M clang/test/CodeGenCXX/matrix-type.cpp
A clang/test/SemaCXX/matrix-types-pseudo-destructor.cpp
Log Message:
-----------
[Clang] [Sema] Support matrix types in pseudo-destructor expressions (#117483)
We already support vector types, and since matrix element types have to
be scalar types, there should be no problem w/ just enabling this.
This now also allows matrix types to be stored in STL containers.
Commit: 3c357a49d61e4c81a1ac016502ee504521bc8dda
https://github.com/llvm/llvm-project/commit/3c357a49d61e4c81a1ac016502ee504521bc8dda
Author: Alexander Yermolovich <43973793+ayermolo at users.noreply.github.com>
Date: 2024-12-16 (Mon, 16 Dec 2024)
Changed paths:
M bolt/docs/CommandLineArgumentReference.md
M bolt/include/bolt/Core/BinaryFunction.h
M bolt/include/bolt/Passes/IdenticalCodeFolding.h
M bolt/lib/Core/BinaryFunction.cpp
M bolt/lib/Passes/IdenticalCodeFolding.cpp
M bolt/lib/Rewrite/BinaryPassManager.cpp
M bolt/lib/Rewrite/BoltDiff.cpp
M bolt/lib/Rewrite/RewriteInstance.cpp
A bolt/test/X86/icf-safe-icp.test
A bolt/test/X86/icf-safe-process-rela-data.test
A bolt/test/X86/icf-safe-test1-no-relocs.test
A bolt/test/X86/icf-safe-test1.test
A bolt/test/X86/icf-safe-test2GlobalConstPtrNoPic.test
Log Message:
-----------
[BOLT] Add support for safe-icf (#116275)
Identical Code Folding (ICF) folds functions that are identical into one
function, and updates symbol addresses to the new address. This reduces
the size of a binary, but can lead to problems. For example when
function pointers are compared. This can be done either explicitly in
the code or generated IR by optimization passes like Indirect Call
Promotion (ICP). After ICF what used to be two different addresses
become the same address. This can lead to a different code path being
taken.
This is where safe ICF comes in. Linker (LLD) does it using address
significant section generated by clang. If symbol is in it, or an object
doesn't have this section symbols are not folded.
BOLT does not have the information regarding which objects do not have
this section, so can't re-use this mechanism.
This implementation scans code section and conservatively marks
functions symbols as unsafe. It treats symbols as unsafe if they are
used in non-control flow instruction. It also scans through the data
relocation sections and does the same for relocations that reference a
function symbol. The latter handles the case when function pointer is
stored in a local or global variable, etc. If a relocation address
points within a vtable these symbols are skipped.
Commit: 5e727e8bed5c57cbc804a2453bba1c2379084f27
https://github.com/llvm/llvm-project/commit/5e727e8bed5c57cbc804a2453bba1c2379084f27
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2024-12-17 (Tue, 17 Dec 2024)
Changed paths:
M llvm/lib/CodeGen/FixupStatepointCallerSaved.cpp
M llvm/lib/CodeGen/StackMaps.cpp
A llvm/test/CodeGen/X86/stackmap-undef-operand-anyregcc.mir
M llvm/test/CodeGen/X86/statepoint-fixup-undef.mir
Log Message:
-----------
[Statepoint] Treat undef operands less specially (#119682)
This reverts commit f7443905af1e06eaacda1e437fff8d54dc89c487.
This is to avoid an assertion if an undef operand appears in a
stackmap. This is important to avoid hitting verifier errors
when register allocation starts adding undefs in error scenarios.
Rather than trying to treat undef operands as special, leave them
alone and avoid producing an invalid spill. It would a bit more
precise to produce a spill of an undef register here, but that's not
exposed through the storeRegToStackSlot API.
https://reviews.llvm.org/D122605
This was an alternative to https://reviews.llvm.org/D122582
Commit: 8387cbd0f9056fdf4e3886652e50fe4d94aaad7c
https://github.com/llvm/llvm-project/commit/8387cbd0f9056fdf4e3886652e50fe4d94aaad7c
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2024-12-17 (Tue, 17 Dec 2024)
Changed paths:
M llvm/lib/Target/AMDGPU/SILowerSGPRSpills.cpp
M llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
M llvm/test/CodeGen/AMDGPU/sgpr-spill-partially-undef.mir
M llvm/test/CodeGen/AMDGPU/spill-agpr-partially-undef.mir
M llvm/test/CodeGen/AMDGPU/vgpr-spill.mir
Log Message:
-----------
AMDGPU: Delete spills of undef values (#119684)
AMDGPU: Delete spills of undef values
It would be a bit more logical to preserve the undef and do the normal
expansion, but this is less work. This avoids verifier errors in a
future patch which starts deleting liveness from registers after
allocation failures which results in spills of undef values.
https://reviews.llvm.org/D122607
Move where undef sgpr spills are deleted
Commit: e83afbe793071727533d822bcc29f547dfab2905
https://github.com/llvm/llvm-project/commit/e83afbe793071727533d822bcc29f547dfab2905
Author: Fangrui Song <i at maskray.me>
Date: 2024-12-16 (Mon, 16 Dec 2024)
Changed paths:
M lld/ELF/LinkerScript.cpp
M lld/ELF/LinkerScript.h
Log Message:
-----------
[ELF] Remove unneeded sec->file check
Commit: b3d2548d5b04ed3b7aaedfd22e62da40875c0f31
https://github.com/llvm/llvm-project/commit/b3d2548d5b04ed3b7aaedfd22e62da40875c0f31
Author: Lang Hames <lhames at gmail.com>
Date: 2024-12-17 (Tue, 17 Dec 2024)
Changed paths:
M llvm/include/llvm/ExecutionEngine/Orc/COFFPlatform.h
A llvm/include/llvm/ExecutionEngine/Orc/LinkGraphLayer.h
A llvm/include/llvm/ExecutionEngine/Orc/LinkGraphLinkingLayer.h
M llvm/include/llvm/ExecutionEngine/Orc/ObjectLinkingLayer.h
M llvm/lib/ExecutionEngine/Orc/CMakeLists.txt
A llvm/lib/ExecutionEngine/Orc/LinkGraphLayer.cpp
A llvm/lib/ExecutionEngine/Orc/LinkGraphLinkingLayer.cpp
M llvm/lib/ExecutionEngine/Orc/ObjectLinkingLayer.cpp
Log Message:
-----------
[ORC] Introduce LinkGraphLayer interface and LinkGraphLinkingLayer. (#120182)
Introduces a new layer interface, LinkGraphLayer, that can be used to
add LinkGraphs to an ExecutionSession.
This patch moves most of ObjectLinkingLayer's functionality into a new
LinkGraphLinkingLayer which should (in the future) be able to be used
without linking libObject. ObjectLinkingLayer now inherits from
LinkGraphLinkingLayer and just handles conversion of object files to
LinkGraphs, which are then handed down to LinkGraphLinkingLayer to be
linked.
Commit: a5d00ae9d18bdc8f7076ae2d44949b4f134e585e
https://github.com/llvm/llvm-project/commit/a5d00ae9d18bdc8f7076ae2d44949b4f134e585e
Author: LLVM GN Syncbot <llvmgnsyncbot at gmail.com>
Date: 2024-12-17 (Tue, 17 Dec 2024)
Changed paths:
M llvm/utils/gn/secondary/llvm/lib/ExecutionEngine/Orc/BUILD.gn
Log Message:
-----------
[gn build] Port b3d2548d5b04
Commit: 4a7673ddf2377784c1c7f11edcfa3ddb54e702a0
https://github.com/llvm/llvm-project/commit/4a7673ddf2377784c1c7f11edcfa3ddb54e702a0
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2024-12-17 (Tue, 17 Dec 2024)
Changed paths:
M .github/workflows/premerge.yaml
Log Message:
-----------
[Github] Fix premerge concurrency cancellation
This should actually fix the problem as I validated that github.sha returns an
actual value by running a workflow in a test repo. I'm not sure why the
existing value doesn't work, but it returns nothing.
Commit: f515d7aa720142dfbb72f52e9d0106ba33e1fe69
https://github.com/llvm/llvm-project/commit/f515d7aa720142dfbb72f52e9d0106ba33e1fe69
Author: Ryosuke Niwa <rniwa at webkit.org>
Date: 2024-12-16 (Mon, 16 Dec 2024)
Changed paths:
M clang/tools/scan-build/bin/scan-build
Log Message:
-----------
[Static analysis] Encodes a filename before inserting it into a URL. (#120123)
This fixes a bug where report links generated from files such as
StylePrimitiveNumericTypes+Conversions.h in WebKit result in an error.
Co-authored-by: Brianna Fan <bfan2 at apple.com>
Commit: 417d2d7ce694acfa09a7d950cf1c5c41796eb313
https://github.com/llvm/llvm-project/commit/417d2d7ce694acfa09a7d950cf1c5c41796eb313
Author: Daniil Kovalev <dkovalev at accesssoftek.com>
Date: 2024-12-17 (Tue, 17 Dec 2024)
Changed paths:
M lld/ELF/Arch/AArch64.cpp
M lld/ELF/InputSection.cpp
M lld/ELF/Relocations.cpp
M lld/ELF/Relocations.h
M lld/ELF/Symbols.h
M lld/ELF/SyntheticSections.cpp
M lld/ELF/SyntheticSections.h
A lld/test/ELF/aarch64-got-relocations-pauth.s
Log Message:
-----------
[PAC][lld][AArch64][ELF] Support signed GOT (#113815)
Depends on #113811
Support `R_AARCH64_AUTH_ADR_GOT_PAGE`, `R_AARCH64_AUTH_GOT_LO12_NC` and
`R_AARCH64_AUTH_GOT_ADD_LO12_NC` GOT-generating relocations. For preemptible
symbols, dynamic relocation `R_AARCH64_AUTH_GLOB_DAT` is emitted. Otherwise,
we unconditionally emit `R_AARCH64_AUTH_RELATIVE` dynamic relocation since
pointers in signed GOT needs to be signed during dynamic link time.
Commit: a56ca3a4e4f9ee8a7ce231cf7b162c4688524fdf
https://github.com/llvm/llvm-project/commit/a56ca3a4e4f9ee8a7ce231cf7b162c4688524fdf
Author: Fangrui Song <i at maskray.me>
Date: 2024-12-16 (Mon, 16 Dec 2024)
Changed paths:
M llvm/test/MC/Disassembler/AArch64/armv8.6a-amvs.s
M llvm/test/MC/Disassembler/AArch64/armv8r-sysreg.txt
M llvm/test/MC/Disassembler/AArch64/armv9.6a-lsui.txt
M llvm/test/MC/Disassembler/AArch64/armv9.6a-occmo.txt
M llvm/test/MC/Disassembler/AArch64/armv9.6a-pcdphint.txt
M llvm/test/MC/Disassembler/AArch64/armv9.6a-rme-gpc3.txt
M llvm/test/MC/Disassembler/AArch64/armv9.6a-srmask.txt
M llvm/test/MC/Disassembler/Mips/eva/valid_R6-eva.txt
M llvm/test/MC/Disassembler/Mips/eva/valid_preR6-eva.txt
M llvm/test/MC/Disassembler/Mips/mips1/valid-mips1-el.txt
M llvm/test/MC/Disassembler/Mips/mips1/valid-mips1.txt
M llvm/test/MC/Disassembler/Mips/mips2/valid-mips2-el.txt
M llvm/test/MC/Disassembler/Mips/mips2/valid-mips2.txt
M llvm/test/MC/Disassembler/Mips/mips3/valid-mips3-el.txt
M llvm/test/MC/Disassembler/Mips/mips3/valid-mips3.txt
M llvm/test/MC/Disassembler/Mips/mips4/valid-mips4-el.txt
M llvm/test/MC/Disassembler/Mips/mips4/valid-mips4.txt
M llvm/test/MC/Disassembler/Mips/mips64r2/valid-mips64r2-el.txt
M llvm/test/MC/Disassembler/Mips/mips64r2/valid-mips64r2.txt
M llvm/test/MC/Disassembler/Mips/mips64r3/valid-mips64r3-el.txt
M llvm/test/MC/Disassembler/Mips/mips64r3/valid-mips64r3.txt
M llvm/test/MC/Disassembler/Mips/mips64r5/valid-mips64r5-el.txt
M llvm/test/MC/Disassembler/Mips/mips64r5/valid-mips64r5.txt
M llvm/test/MC/Disassembler/RISCV/colored.txt
M llvm/test/MC/Disassembler/WebAssembly/wasm-error.txt
M llvm/test/MC/Disassembler/WebAssembly/wasm.txt
Log Message:
-----------
[test] Don't test initial ".text" in llvm-mc --disassemble output
This kludge will go away after #120185.
Commit: 6db1b2035bbef5ec477a1e645e249ebf7b29688c
https://github.com/llvm/llvm-project/commit/6db1b2035bbef5ec477a1e645e249ebf7b29688c
Author: Ryosuke Niwa <rniwa at webkit.org>
Date: 2024-12-16 (Mon, 16 Dec 2024)
Changed paths:
M clang/tools/scan-build/bin/scan-build
Log Message:
-----------
Revert "[Static analysis] Encodes a filename before inserting it into a URL." (#120195)
Reverts llvm/llvm-project#120123
Broke some tests.
Commit: 495bd4c255a0eb0e5b4fef5240eddc5fded1911b
https://github.com/llvm/llvm-project/commit/495bd4c255a0eb0e5b4fef5240eddc5fded1911b
Author: Fangrui Song <i at maskray.me>
Date: 2024-12-16 (Mon, 16 Dec 2024)
Changed paths:
M llvm/lib/MC/MCAsmStreamer.cpp
M llvm/test/MC/Disassembler/AArch64/colored.txt
M llvm/test/MC/Disassembler/ARM/arm-trustzone.txt
M llvm/test/tools/llvm-mc/line_end_with_space.test
M llvm/tools/llvm-mc/Disassembler.cpp
Log Message:
-----------
[llvm-mc] Don't print initial .text for disassembler
```
% echo 90 | llvm-mc -triple=x86_64 --disassemble --hex
.text
nop
```
The initial `.text` kludge is due `initSection`, which is actually only
needed by AIX XCOFF for its `getCurrentSectionOnly()` use in
MCAsmStreamer::emitInstruction (https://reviews.llvm.org/D95518). Adjust
MCAsmStreamer::emitInstruction to not trigger failures on
```
echo 7c4303a6 | llvm-mc --cdis --hex --triple=powerpc-aix-ibm-xcoff
```
Pull Request: https://github.com/llvm/llvm-project/pull/120185
Commit: 43ede4689892a716fc9ec1c9ae4096621f3b0f57
https://github.com/llvm/llvm-project/commit/43ede4689892a716fc9ec1c9ae4096621f3b0f57
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-12-16 (Mon, 16 Dec 2024)
Changed paths:
M llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
M llvm/test/CodeGen/RISCV/GlobalISel/fp128.ll
Log Message:
-----------
[RISCV][GISel] Add legalization for more fp128 libcalls.
Commit: 300deebf41d2da96701fe29c0faa8025b7efa120
https://github.com/llvm/llvm-project/commit/300deebf41d2da96701fe29c0faa8025b7efa120
Author: Lang Hames <lhames at gmail.com>
Date: 2024-12-17 (Tue, 17 Dec 2024)
Changed paths:
M llvm/include/llvm/ExecutionEngine/Orc/Core.h
M llvm/include/llvm/ExecutionEngine/Orc/LazyReexports.h
M llvm/lib/ExecutionEngine/Orc/LazyReexports.cpp
M llvm/unittests/ExecutionEngine/Orc/LazyCallThroughAndReexportsTest.cpp
Log Message:
-----------
[ORC] Make LazyReexportsManager implement ResourceManager.
This ensures that the reexports mappings are cleared when the resource tracker
associated with each mapping is removed.
Commit: bfe8a21bad7e90629fb079217929a79e7377d8b3
https://github.com/llvm/llvm-project/commit/bfe8a21bad7e90629fb079217929a79e7377d8b3
Author: Brendan Sweeney <brs at eecs.berkeley.edu>
Date: 2024-12-17 (Tue, 17 Dec 2024)
Changed paths:
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/lib/Target/RISCV/RISCVISelLowering.h
M llvm/lib/Target/RISCV/RISCVInstrInfoA.td
M llvm/lib/Target/RISCV/RISCVInstrInfoZalasr.td
M llvm/test/CodeGen/RISCV/atomic-load-store.ll
Log Message:
-----------
[RISCV][ISEL] Lowering to load-acquire/store-release for RISCV Zalasr (#82914)
Lowering to load-acquire/store-release for RISCV Zalasr.
Currently uses the psABI lowerings for WMO load-acquire/store-release
(which are identical to A.7). These are incompatable with the A.6
lowerings currently used by LLVM. This should be OK for now since Zalasr
is behind the enable experimental extensions flag, but needs to be fixed
before it is removed from that.
For TSO, it uses the standard Ztso mappings except for lowering seq_cst
loads/store to load-acquire/store-release, I had Andrea review that.
Commit: 58cfa39861bfbb6605df1480a3068ea7fc737d4d
https://github.com/llvm/llvm-project/commit/58cfa39861bfbb6605df1480a3068ea7fc737d4d
Author: Florian Hahn <flo at fhahn.com>
Date: 2024-12-17 (Tue, 17 Dec 2024)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlan.cpp
M llvm/lib/Transforms/Vectorize/VPlan.h
M llvm/unittests/Transforms/Vectorize/VPDomTreeTest.cpp
M llvm/unittests/Transforms/Vectorize/VPlanTest.cpp
M llvm/unittests/Transforms/Vectorize/VPlanVerifierTest.cpp
Log Message:
-----------
[VPlan] Remove legacy VPlan() constructors (NFC).
The constructors were retained to reduce the diff during transition.
Remove them now.
Commit: 514580b43898921cc95659de47b383bd2c9b4b12
https://github.com/llvm/llvm-project/commit/514580b43898921cc95659de47b383bd2c9b4b12
Author: Florian Mayer <fmayer at google.com>
Date: 2024-12-17 (Tue, 17 Dec 2024)
Changed paths:
M clang/lib/CodeGen/SanitizerMetadata.cpp
M clang/test/CodeGen/memtag-globals.cpp
M llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
M llvm/lib/IR/Verifier.cpp
M llvm/lib/Target/AArch64/AArch64.h
R llvm/lib/Target/AArch64/AArch64GlobalsTagging.cpp
M llvm/lib/Target/AArch64/AArch64TargetMachine.cpp
M llvm/lib/Target/AArch64/CMakeLists.txt
M llvm/test/CodeGen/AArch64/O0-pipeline.ll
M llvm/test/CodeGen/AArch64/O3-pipeline.ll
M llvm/unittests/IR/VerifierTest.cpp
M llvm/utils/gn/secondary/llvm/lib/Target/AArch64/BUILD.gn
Log Message:
-----------
[MTE] Apply alignment / size in AsmPrinter rather than IR (#111918)
This makes sure no optimizations are applied that assume the
bigger alignment or size, which could be incorrect if we link
together with non-instrumented code.
Commit: fbdbb13d5ba9e7a2bd6c544d290f913490da858f
https://github.com/llvm/llvm-project/commit/fbdbb13d5ba9e7a2bd6c544d290f913490da858f
Author: Artem Pianykh <artem.pyanykh at gmail.com>
Date: 2024-12-17 (Tue, 17 Dec 2024)
Changed paths:
M llvm/lib/Transforms/Utils/CloneFunction.cpp
Log Message:
-----------
[NFC][Utils] Eliminate DISubprogram set from BuildDebugInfoMDMap (#118625)
Summary:
Previously, we'd add all SPs distinct from the cloned one into a set.
Then when cloning a local scope we'd check if it's from one of those
'distinct' SPs by checking if it's in the set. We don't need to do that.
We can just check against the cloned SP directly and drop the set.
Test Plan:
ninja check-llvm-unit check-llvm
Commit: df2356b47548ad69c2ded12e5ad7657be51aca42
https://github.com/llvm/llvm-project/commit/df2356b47548ad69c2ded12e5ad7657be51aca42
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-12-17 (Tue, 17 Dec 2024)
Changed paths:
M llvm/lib/Target/X86/X86TargetTransformInfo.cpp
M llvm/test/Transforms/VectorCombine/X86/concat-boolmasks.ll
Log Message:
-----------
[X86] getShuffleCost - ensure we treat constant folded shuffles as free
Commit: 3508d8f6ddd65e27486fad70cdce47adebafc364
https://github.com/llvm/llvm-project/commit/3508d8f6ddd65e27486fad70cdce47adebafc364
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2024-12-17 (Tue, 17 Dec 2024)
Changed paths:
M llvm/lib/CodeGen/RegAllocFast.cpp
M llvm/test/CodeGen/AMDGPU/ran-out-of-registers-error-all-regs-reserved.ll
M llvm/test/CodeGen/AMDGPU/ran-out-of-registers-errors.ll
Log Message:
-----------
RegAllocFast: Avoid using temporary DiagnosticInfo (#120184)
This reverts commit 1297933f35b4948b4d281259627a72094c407a75.
Commit: 2a7ed2c1aaf5c84280d947eea56daaf302eb83d1
https://github.com/llvm/llvm-project/commit/2a7ed2c1aaf5c84280d947eea56daaf302eb83d1
Author: David Green <david.green at arm.com>
Date: 2024-12-17 (Tue, 17 Dec 2024)
Changed paths:
M llvm/lib/Transforms/Scalar/SROA.cpp
M llvm/test/Transforms/SROA/readonlynocapture.ll
Log Message:
-----------
[SROA] Protect against calling the alloca ptr
In case we are calling the alloca ptr directly, check that the Use is a normal
operand to the call. Fortran is a funny language.
Commit: 9c89b40f183b6900d364e3496fd955f0c17fe27e
https://github.com/llvm/llvm-project/commit/9c89b40f183b6900d364e3496fd955f0c17fe27e
Author: SpencerAbson <Spencer.Abson at arm.com>
Date: 2024-12-17 (Tue, 17 Dec 2024)
Changed paths:
M clang/include/clang/Basic/arm_sme.td
M clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_mla.c
M clang/test/Sema/aarch64-fp8-intrinsics/acle_sme2_fp8_mla.c
M llvm/include/llvm/IR/IntrinsicsAArch64.td
M llvm/lib/Target/AArch64/AArch64SMEInstrInfo.td
M llvm/lib/Target/AArch64/SMEInstrFormats.td
M llvm/test/CodeGen/AArch64/sme2-fp8-intrinsics-mla.ll
Log Message:
-----------
[AArch64] Implement intrinsics for FMLAL/FMLALL (single) (#119568)
Multi-vector 8-bit floating-point multiply-add long (single)
```c
// Only if __ARM_FEATURE_SME_F8F16 != 0
void svmla[_single]_za16[_mf8]_vg2x1_fpm(uint32_t slice, svmfloat8_t zn,
svmfloat8_t zm, fpm_t fpm)
__arm_streaming __arm_inout("za");
void svmla[_single]_za16[_mf8]_vg2x2_fpm(uint32_t slice, svmfloat8x2_t zn,
svmfloat8_t zm, fpm_t fpm)
__arm_streaming __arm_inout("za");
void svmla[_single]_za16[_mf8]_vg2x4_fpm(uint32_t slice, svmfloat8x4_t zn,
svmfloat8_t zm, fpm_t fpm)
__arm_streaming __arm_inout("za");
// Only if __ARM_FEATURE_SME_F8F32 != 0
void svmla[_single]_za32[_mf8]_vg4x1_fpm(uint32_t slice, svmfloat8_t zn,
svmfloat8_t zm, fpm_t fpm)
__arm_streaming __arm_inout("za");
void svmla[_single]_za32[_mf8]_vg4x2_fpm(uint32_t slice, svmfloat8x2_t zn,
svmfloat8_t zm, fpm_t fpm)
__arm_streaming __arm_inout("za");
void svmla[_single]_za32[_mf8]_vg4x4_fpm(uint32_t slice, svmfloat8x4_t zn,
svmfloat8_t zm, fpm_t fpm)
__arm_streaming __arm_inout("za");
```
In accordance with https://github.com/ARM-software/acle/pull/323.
Co-authored-by: Momchil Velikov momchil.velikov at arm.com
Commit: e5a6f1c7793408adfe299c8fa5f4a53e236076b5
https://github.com/llvm/llvm-project/commit/e5a6f1c7793408adfe299c8fa5f4a53e236076b5
Author: Mariya Podchishchaeva <mariya.podchishchaeva at intel.com>
Date: 2024-12-17 (Tue, 17 Dec 2024)
Changed paths:
M clang/lib/StaticAnalyzer/Checkers/WebKit/UncountedLambdaCapturesChecker.cpp
Log Message:
-----------
[NFC][webkit.UncountedLambdaCapturesChecker] Remove unnecessary check (#120069)
CXXMD is checked for null, but it can't be null inside of a visitor's
method. Found by a static analyzer tool.
Commit: 75b2d786734cd3fc0825fc6e20a3925d16993205
https://github.com/llvm/llvm-project/commit/75b2d786734cd3fc0825fc6e20a3925d16993205
Author: Andrei Safronov <andrei.safronov at espressif.com>
Date: 2024-12-17 (Tue, 17 Dec 2024)
Changed paths:
M .github/new-prs-labeler.yml
Log Message:
-----------
[GitHub] Add Xtensa backend labeler. (#120133)
Add patterns to label Xtensa backend related changes automatically.
Commit: 7c135e17fbb7178466eafce9826c896518907637
https://github.com/llvm/llvm-project/commit/7c135e17fbb7178466eafce9826c896518907637
Author: Nikita Popov <npopov at redhat.com>
Date: 2024-12-17 (Tue, 17 Dec 2024)
Changed paths:
M llvm/lib/Analysis/InstructionSimplify.cpp
M llvm/test/Transforms/InstSimplify/select-equivalence-fp.ll
Log Message:
-----------
[InstSimplify] Treat float binop with identity as refining (#120098)
If x is NaN, then fmul (x, 1) may produce a different NaN value.
Our float semantics explicitly permit folding fmul (x, 1) to x, but we
can't do this when we're replacing a select input, as selects are
supposed to preserve the exact bitwise value.
Fixes
https://github.com/llvm/llvm-project/pull/115152#issuecomment-2545773114.
Commit: a1f5fe8c851ba6a0070e4cab9e7436e962677ac6
https://github.com/llvm/llvm-project/commit/a1f5fe8c851ba6a0070e4cab9e7436e962677ac6
Author: Fraser Cormack <fraser at codeplay.com>
Date: 2024-12-17 (Tue, 17 Dec 2024)
Changed paths:
M llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp
M llvm/test/CodeGen/NVPTX/bf16-instructions.ll
M llvm/test/CodeGen/NVPTX/fma-relu-contract.ll
M llvm/test/CodeGen/NVPTX/fma-relu-fma-intrinsic.ll
M llvm/test/CodeGen/NVPTX/fma-relu-instruction-flag.ll
M llvm/test/CodeGen/NVPTX/i16x2-instructions.ll
Log Message:
-----------
[NVPTX] Optimize v2x16 BUILD_VECTORs to PRMT (#116675)
When two 16-bit values are combined into a v2x16 vector, and those
values are truncated come from 32-bit values, a PRMT instruction can
save registers by selecting bytes directly from the original 32-bit
values. We do this during a post-legalize DAG combine, as these
opportunities are typically only exposed after the BUILD_VECTOR's
operands have been legalized.
Additionally, if the 32-bit values are right-shifted, we can fold in the
shift by selecting higher bytes with PRMT. Only logical right-shifts by
16 are supported (for now) since those are the only situations seen in
practice. Right shifts by 16 often come up during the legalization of
EXTRACT_VECTOR_ELT.
This idea was brought up in a PR comment by @Artem-B.
Commit: 8cd8b5079b3c8debc1fa0b7b2287a00d7d385819
https://github.com/llvm/llvm-project/commit/8cd8b5079b3c8debc1fa0b7b2287a00d7d385819
Author: Matthias Springer <me at m-sp.org>
Date: 2024-12-17 (Tue, 17 Dec 2024)
Changed paths:
M mlir/lib/Conversion/VectorToLLVM/ConvertVectorToLLVMPass.cpp
M mlir/test/Conversion/VectorToLLVM/vector-mask-to-llvm.mlir
M mlir/test/Conversion/VectorToLLVM/vector-to-llvm.mlir
M mlir/test/Conversion/VectorToLLVM/vector-xfer-to-llvm.mlir
Log Message:
-----------
[mlir][Vector] Move mask materialization patterns to greedy rewrite (#119973)
The mask materialization patterns during `VectorToLLVM` are rewrite
patterns. They should run as part of the greedy pattern rewrite and not
the dialect conversion. (Rewrite patterns and conversion patterns are
not generally compatible.)
The current combination of rewrite patterns and conversion patterns
triggered an edge case when merging the 1:1 and 1:N dialect conversions.
Commit: 59890c13343af9e308281b3c76bac425087f4f8a
https://github.com/llvm/llvm-project/commit/59890c13343af9e308281b3c76bac425087f4f8a
Author: Nikolas Klauser <nikolasklauser at berlin.de>
Date: 2024-12-17 (Tue, 17 Dec 2024)
Changed paths:
M libcxx/include/__algorithm/inplace_merge.h
M libcxx/include/__algorithm/stable_partition.h
M libcxx/include/__algorithm/stable_sort.h
M libcxx/include/__exception/exception_ptr.h
M libcxx/include/__functional/function.h
M libcxx/include/__memory/allocator.h
M libcxx/include/__memory/builtin_new_allocator.h
M libcxx/include/__memory/ranges_construct_at.h
M libcxx/include/__memory/ranges_uninitialized_algorithms.h
M libcxx/include/__memory/raw_storage_iterator.h
M libcxx/include/__memory/shared_ptr.h
M libcxx/include/__memory/uninitialized_algorithms.h
M libcxx/include/__memory/unique_temporary_buffer.h
M libcxx/include/__memory_resource/polymorphic_allocator.h
M libcxx/include/__ostream/basic_ostream.h
M libcxx/include/__pstl/backends/libdispatch.h
M libcxx/include/__pstl/cpu_algos/transform_reduce.h
M libcxx/include/__pstl/handle_exception.h
M libcxx/include/__utility/no_destroy.h
M libcxx/include/__utility/small_buffer.h
M libcxx/include/exception
M libcxx/include/future
M libcxx/include/locale
M libcxx/include/map
M libcxx/include/module.modulemap
M libcxx/include/optional
M libcxx/include/stdexcept
M libcxx/include/unordered_map
M libcxx/include/valarray
M libcxx/include/variant
M libcxx/test/libcxx/transitive_includes/cxx23.csv
M libcxx/test/libcxx/transitive_includes/cxx26.csv
M libcxxabi/src/cxa_default_handlers.cpp
Log Message:
-----------
[libc++] Granularize <new> includes (#119964)
Commit: 0693b9e9ccdec5f09a3080b1bec73f5004a8dfa3
https://github.com/llvm/llvm-project/commit/0693b9e9ccdec5f09a3080b1bec73f5004a8dfa3
Author: Matthias Springer <me at m-sp.org>
Date: 2024-12-17 (Tue, 17 Dec 2024)
Changed paths:
M mlir/include/mlir/Dialect/Vector/Transforms/LoweringPatterns.h
M mlir/lib/Conversion/GPUCommon/GPUToLLVMConversion.cpp
M mlir/lib/Conversion/VectorToLLVM/ConvertVectorToLLVM.cpp
M mlir/lib/Conversion/VectorToLLVM/ConvertVectorToLLVMPass.cpp
M mlir/test/Conversion/GPUCommon/lower-vector.mlir
M mlir/test/Conversion/VectorToLLVM/vector-to-llvm.mlir
Log Message:
-----------
[mlir][Vector] Clean up `populateVectorToLLVMConversionPatterns` (#119975)
Clean up `populateVectorToLLVMConversionPatterns` so that it populates
only conversion patterns. All rewrite patterns that do not lower to LLVM
should be populated into a separate greedy pattern rewrite.
The current combination of rewrite patterns and conversion patterns
triggered an edge case when merging the 1:1 and 1:N dialect conversions.
Depends on #119973.
Commit: 10b12e6e07b4a2e6ff558b4a3066431bd704abfe
https://github.com/llvm/llvm-project/commit/10b12e6e07b4a2e6ff558b4a3066431bd704abfe
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2024-12-17 (Tue, 17 Dec 2024)
Changed paths:
M llvm/include/llvm/CodeGen/LiveVariables.h
M llvm/lib/CodeGen/LiveVariables.cpp
Log Message:
-----------
LiveVariables: Use Register (#120204)
Commit: f7988a338ddb53b03e7cb89d839616925bd0ade1
https://github.com/llvm/llvm-project/commit/f7988a338ddb53b03e7cb89d839616925bd0ade1
Author: Mirko Brkušanin <Mirko.Brkusanin at amd.com>
Date: 2024-12-17 (Tue, 17 Dec 2024)
Changed paths:
M llvm/lib/Target/AMDGPU/SIPreEmitPeephole.cpp
A llvm/test/CodeGen/AMDGPU/remove-not-short-exec-branch-on-unconditional-jump.mir
Log Message:
-----------
[AMDGPU][SIPreEmitPeephole] Fix mustRetainExeczBranch (#120121)
Do not remove S_CBRANCH_EXECZ if one of the following blocks contains an
unconditional branch to a block other than the one immediately following
it. This can cause unwanted behavior like infinite loops.
Commit: a7dafea384a519342b2fbe210ed101c1e67f3be7
https://github.com/llvm/llvm-project/commit/a7dafea384a519342b2fbe210ed101c1e67f3be7
Author: Benjamin Maxwell <benjamin.maxwell at arm.com>
Date: 2024-12-17 (Tue, 17 Dec 2024)
Changed paths:
M llvm/include/llvm/CodeGen/SelectionDAG.h
M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
M llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
M llvm/test/CodeGen/AArch64/sincos-stack-slots.ll
M llvm/test/CodeGen/PowerPC/f128-arith.ll
M llvm/test/CodeGen/RISCV/llvm.frexp.ll
M llvm/test/CodeGen/X86/llvm.frexp.ll
A llvm/test/CodeGen/X86/llvm.sincos.ll
M llvm/test/CodeGen/X86/sincos-stack-args.ll
Log Message:
-----------
[SDAG] Allow folding stack slots into sincos/frexp in more cases (#118117)
This adds a new helper `canFoldStoreIntoLibCallOutputPointers()` to
check that it is safe to fold a store into a node that will expand to a
library call that takes output pointers. This requires checking for two
(independent) properties:
1. The store is not within a CALLSEQ_START..CALLSEQ_END pair
* If it is, the expansion would lead to nested call sequences (which is
invalid)
2. The node does not appear as a predecessor to the store
* If it does, attempting to merge the store into the call would result
in a cycle in the DAG
These two properties are checked as part of the same traversal in
`canFoldStoreIntoLibCallOutputPointers()`
Commit: bdf727065b581c45b68a81090272f497f1ce5485
https://github.com/llvm/llvm-project/commit/bdf727065b581c45b68a81090272f497f1ce5485
Author: wanglei <wanglei at loongson.cn>
Date: 2024-12-17 (Tue, 17 Dec 2024)
Changed paths:
M clang/lib/Frontend/CompilerInvocation.cpp
M clang/tools/clang-linker-wrapper/ClangLinkerWrapper.cpp
M llvm/lib/Frontend/OpenMP/OMPContext.cpp
M offload/CMakeLists.txt
M offload/plugins-nextgen/common/src/Utils/ELF.cpp
M offload/plugins-nextgen/host/CMakeLists.txt
M offload/plugins-nextgen/host/dynamic_ffi/ffi.h
M offload/plugins-nextgen/host/src/rtl.cpp
Log Message:
-----------
[Offload] Add support for loongarch64 to host plugin
This adds support for the loongarch64 architecture to the offload host
plugin.
Similar to #115773
To fix some test issues, I've had to add the LoongArch64 target to:
- CompilerInvocation::ParseLangArgs
- linkDevice in ClangLinuxWrapper.cpp
- OMPContext::OMPContext (to set the device_kind_cpu trait)
Reviewed By: jhuber6
Pull Request: https://github.com/llvm/llvm-project/pull/120173
Commit: 37e48e4a7360a6faf1b157e843160d9e65223890
https://github.com/llvm/llvm-project/commit/37e48e4a7360a6faf1b157e843160d9e65223890
Author: aurelien35 <aurelien35 at users.noreply.github.com>
Date: 2024-12-17 (Tue, 17 Dec 2024)
Changed paths:
M llvm/lib/DebugInfo/LogicalView/LVReaderHandler.cpp
M llvm/unittests/DebugInfo/LogicalView/CodeViewReaderTest.cpp
A llvm/unittests/DebugInfo/LogicalView/Inputs/README.md
A llvm/unittests/DebugInfo/LogicalView/Inputs/test-codeview-msvc.lib
Log Message:
-----------
Fix crash due to un-checked error in LVReaderHandler::handleArchive method (#118951)
[llvm-debuginfo-analyzer] Fix crash due to un-checked error in LVReaderHandler::handleArchive
method.
- Added README describing how to generated the binary files used for the test.
- A follow up patch to add extra ASSERT_NE
Committed on behalf of @aurelien35
Commit: b07e7b76c5d532a611cf19ae083a94d44bfe0c5d
https://github.com/llvm/llvm-project/commit/b07e7b76c5d532a611cf19ae083a94d44bfe0c5d
Author: paperchalice <liujunchang97 at outlook.com>
Date: 2024-12-17 (Tue, 17 Dec 2024)
Changed paths:
M clang/CMakeLists.txt
M compiler-rt/cmake/Modules/CompilerRTAIXUtils.cmake
M compiler-rt/cmake/Modules/CompilerRTDarwinUtils.cmake
M flang/CMakeLists.txt
M libc/CMakeLists.txt
M llvm/cmake/modules/LLVMProcessSources.cmake
M llvm/tools/llvm-config/CMakeLists.txt
M polly/cmake/polly_macros.cmake
Log Message:
-----------
[cmake] Drop `AddFileDependencies` and `CMakeParseArguments` (#120002)
Theses modules are deprecated and have trivial implementations in modern
cmake.
Commit: 24c2744a189eef9dfd39789df4983e4ffd219197
https://github.com/llvm/llvm-project/commit/24c2744a189eef9dfd39789df4983e4ffd219197
Author: Lang Hames <lhames at gmail.com>
Date: 2024-12-17 (Tue, 17 Dec 2024)
Changed paths:
M llvm/include/llvm/ExecutionEngine/Orc/LazyReexports.h
M llvm/lib/ExecutionEngine/Orc/LazyReexports.cpp
Log Message:
-----------
[ORC] Fix LazyReexports resource key management.
Multiple reentry points may be associated with a single key.
Commit: 449af81f922cdb7a1f24b4c1e989f30848e1d762
https://github.com/llvm/llvm-project/commit/449af81f922cdb7a1f24b4c1e989f30848e1d762
Author: AdUhTkJm <30948580+AdUhTkJm at users.noreply.github.com>
Date: 2024-12-17 (Tue, 17 Dec 2024)
Changed paths:
M clang/lib/Sema/SemaStmtAsm.cpp
M clang/test/Sema/asm.c
Log Message:
-----------
[Clang] Fix crash for incompatible types in inline assembly (#119098)
Fixed issue #118892.
Commit: 908e30658ddf634f7c929f0c7e78dd40405c795a
https://github.com/llvm/llvm-project/commit/908e30658ddf634f7c929f0c7e78dd40405c795a
Author: SpencerAbson <Spencer.Abson at arm.com>
Date: 2024-12-17 (Tue, 17 Dec 2024)
Changed paths:
M clang/include/clang/Basic/arm_sme.td
M clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_mla.c
M clang/test/Sema/aarch64-fp8-intrinsics/acle_sme2_fp8_mla.c
M llvm/include/llvm/IR/IntrinsicsAArch64.td
M llvm/lib/Target/AArch64/AArch64SMEInstrInfo.td
M llvm/lib/Target/AArch64/SMEInstrFormats.td
M llvm/test/CodeGen/AArch64/sme2-fp8-intrinsics-mla.ll
Log Message:
-----------
[AArch64] Implement intrinsics for FP8 SME FMLAL/FMLALL (multi) (#119546)
This patch implements the following intrinsics:
Multi-vector 8-bit floating-point multiply-add long (multiple vectors).
``` c
// Only if __ARM_FEATURE_SME_F8F16 != 0
void svmla_za16[_mf8]_vg2x2_fpm(uint32_t slice, svmfloat8x2_t zn, svmfloat8x2_t zm,
fpm_t fpm) __arm_streaming __arm_inout("za");
void svmla_za16[_mf8]_vg2x4_fpm(uint32_t slice, svmfloat8x4_t zn, svmfloat8x4_t zm,
fpm_t fpm) __arm_streaming __arm_inout("za");
// Only if __ARM_FEATURE_SME_F8F32 != 0
void svmla_za32[_mf8]_vg4x2_fpm(uint32_t slice, svmfloat8x2_t zn, svmfloat8x2_t zm,
fpm_t fpm) __arm_streaming __arm_inout("za");
void svmla_za32[_mf8]_vg4x4_fpm(uint32_t slice, svmfloat8x4_t zn, svmfloat8x4_t zm,
fpm_t fpm) __arm_streaming __arm_inout("za");
```
In accordance with https://github.com/ARM-software/acle/pull/323
Commit: 1b8099040e9a919794eba3854486d46fa9018b94
https://github.com/llvm/llvm-project/commit/1b8099040e9a919794eba3854486d46fa9018b94
Author: Sander de Smalen <sander.desmalen at arm.com>
Date: 2024-12-17 (Tue, 17 Dec 2024)
Changed paths:
M compiler-rt/lib/builtins/aarch64/sme-abi.S
M compiler-rt/lib/builtins/aarch64/sme-libc-mem-routines.S
Log Message:
-----------
Reland "[compiler-rt][AArch64] Allow platform-specific mangling of SME routines. (#119864)"
Avoid issues caused by `.subsections_via_symbols` directive, by using
numbered labels instead of named labels for the branch locations.
This reverts commit 4032ce3413d0230b0ccba1203536f9cb35e5c3b5.
Commit: c1f5937eb4bf4002b8205873189f900364868fd5
https://github.com/llvm/llvm-project/commit/c1f5937eb4bf4002b8205873189f900364868fd5
Author: Florian Hahn <flo at fhahn.com>
Date: 2024-12-17 (Tue, 17 Dec 2024)
Changed paths:
M llvm/lib/CodeGen/SelectOptimize.cpp
M llvm/test/CodeGen/AArch64/selectopt-cast.ll
Log Message:
-----------
[SelectOpt] Support BinOps with SExt operands. (#115879)
Building on top of https://github.com/llvm/llvm-project/pull/115489
extend support for binops with SExt operand.
PR: https://github.com/llvm/llvm-project/pull/115879
Commit: 8ea9576d94ec6b15a2a3ba181af15d136283bde4
https://github.com/llvm/llvm-project/commit/8ea9576d94ec6b15a2a3ba181af15d136283bde4
Author: Florian Hahn <flo at fhahn.com>
Date: 2024-12-17 (Tue, 17 Dec 2024)
Changed paths:
M llvm/include/llvm/Analysis/ScalarEvolutionPatternMatch.h
M llvm/lib/Analysis/ScalarEvolution.cpp
Log Message:
-----------
[SCEV] Add initial matchers for SCEV expressions. (NFC) (#119390)
This patch adds initial matchers for unary and binary SCEV expressions
and specializes it for SExt, ZExt and binary add expressions.
Also adds matchers for SCEVConstant and SCEVUnknown.
This patch only converts a few instances to use the new matchers to make
sure everything builds as expected for now.
The goal of the matchers is to hopefully make it slightly easier to
write code matching SCEV patterns.
Depends on https://github.com/llvm/llvm-project/pull/119389
PR: https://github.com/llvm/llvm-project/pull/119390
Commit: 56fd46edb38e4bab7e48c668683ba72709beb64f
https://github.com/llvm/llvm-project/commit/56fd46edb38e4bab7e48c668683ba72709beb64f
Author: Timm Baeder <tbaeder at redhat.com>
Date: 2024-12-17 (Tue, 17 Dec 2024)
Changed paths:
M clang/lib/AST/ByteCode/Compiler.cpp
M clang/lib/AST/ByteCode/Interp.h
M clang/lib/AST/ByteCode/Opcodes.td
M clang/test/AST/ByteCode/builtin-bit-cast.cpp
Log Message:
-----------
[clang][bytecode] Remove a bitcast nullptr_t special case (#120188)
We still need to check the input pointer, so let this go through
BitCastPrim.
Commit: 52b07d971c89ab8fbcc497f22c43931b488256ea
https://github.com/llvm/llvm-project/commit/52b07d971c89ab8fbcc497f22c43931b488256ea
Author: Nathan Gauër <brioche at google.com>
Date: 2024-12-17 (Tue, 17 Dec 2024)
Changed paths:
M clang/lib/CodeGen/CGHLSLRuntime.cpp
A clang/test/CodeGenHLSL/builtins/RWBuffer-constructor-opt.hlsl
Log Message:
-----------
[HLSL] Fix call convention mismatch for ctor/dtor (#118651)
Before this patch, there was a calling-convention mismatch between the
constructors and the actual call emitted for the entrypoint wrapper.
Such mismatch causes the InstCombine pass to replace this call with an
`unreachable`, breaking the whole function.
Signed-off-by: Nathan Gauër <brioche at google.com>
Commit: 794cd814ee0260c094b98e453c89faf5a1a1df01
https://github.com/llvm/llvm-project/commit/794cd814ee0260c094b98e453c89faf5a1a1df01
Author: Michael Buch <michaelbuch12 at gmail.com>
Date: 2024-12-17 (Tue, 17 Dec 2024)
Changed paths:
M lldb/source/Plugins/SymbolFile/DWARF/DWARFASTParserClang.cpp
Log Message:
-----------
[lldb][DWARFASTParserClang][ObjC] Remove workaround for old ObjC DWARF (#120218)
With all the recent versions of Clang that I tested, ObjC forward
declarations like
```
@class ForwardObjcClass;
```
don't emit the kind of DWARF that this workaround was put in place for.
Also, zero-sized structures are valid in C (and thus Objective-C), so
this workaround makes things confusing to reason about when mixing the
two languages.
This workaround has been in place for at least a decade, and given that
recent compilers don't produce this anymore, we think it's a good time
to remove it.
Commit: 34c4f6f9375ba8193327f2706d05b90e363a33d1
https://github.com/llvm/llvm-project/commit/34c4f6f9375ba8193327f2706d05b90e363a33d1
Author: Mikhail Goncharov <goncharov.mikhail at gmail.com>
Date: 2024-12-17 (Tue, 17 Dec 2024)
Changed paths:
M utils/bazel/llvm-project-overlay/mlir/BUILD.bazel
Log Message:
-----------
[MLIR][bazel] port 0693b9e9ccdec5f09a3080b1bec73f5004a8dfa3
Commit: 1157187496afbbb203b8ec7aa320769ec6eed8c4
https://github.com/llvm/llvm-project/commit/1157187496afbbb203b8ec7aa320769ec6eed8c4
Author: Nikita Popov <npopov at redhat.com>
Date: 2024-12-17 (Tue, 17 Dec 2024)
Changed paths:
M llvm/lib/Transforms/Vectorize/LoopVectorizationPlanner.h
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
M llvm/lib/Transforms/Vectorize/VPlan.h
M llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
M llvm/test/Transforms/LoopVectorize/AArch64/low_trip_count_predicates.ll
M llvm/test/Transforms/LoopVectorize/AArch64/scalable-fp-ext-trunc-illegal-type.ll
M llvm/test/Transforms/LoopVectorize/PowerPC/widened-massv-call.ll
M llvm/test/Transforms/LoopVectorize/X86/cost-model.ll
M llvm/test/Transforms/LoopVectorize/X86/drop-poison-generating-flags.ll
M llvm/test/Transforms/LoopVectorize/X86/float-induction-x86.ll
M llvm/test/Transforms/LoopVectorize/X86/interleave-cost.ll
M llvm/test/Transforms/LoopVectorize/X86/metadata-enable.ll
M llvm/test/Transforms/LoopVectorize/interleaved-accesses-different-insert-position.ll
M llvm/test/Transforms/PhaseOrdering/AArch64/hoist-runtime-checks.ll
M llvm/test/Transforms/PhaseOrdering/AArch64/hoisting-sinking-required-for-vectorization.ll
M llvm/test/Transforms/PhaseOrdering/AArch64/interleavevectorization.ll
M llvm/test/Transforms/PhaseOrdering/AArch64/matrix-extract-insert.ll
M llvm/test/Transforms/PhaseOrdering/AArch64/predicated-reduction.ll
M llvm/test/Transforms/PhaseOrdering/X86/pixel-splat.ll
M llvm/test/Transforms/PhaseOrdering/X86/pr88239.ll
M llvm/test/Transforms/PhaseOrdering/X86/preserve-access-group.ll
M llvm/test/Transforms/PhaseOrdering/X86/vdiv-nounroll.ll
M llvm/test/Transforms/PhaseOrdering/X86/vdiv.ll
M llvm/test/Transforms/PhaseOrdering/X86/vector-reduction-known-first-value.ll
Log Message:
-----------
[VPlan] Propagate all GEP flags (#119899)
Store GEPNoWrapFlags instead of only InBounds and propagate them.
Commit: e0a79eeca27b894bca6aa3f5dfdd8f1ac6644381
https://github.com/llvm/llvm-project/commit/e0a79eeca27b894bca6aa3f5dfdd8f1ac6644381
Author: Michael Buch <michaelbuch12 at gmail.com>
Date: 2024-12-17 (Tue, 17 Dec 2024)
Changed paths:
M lldb/source/Plugins/SymbolFile/DWARF/DWARFUnit.cpp
M lldb/source/Plugins/SymbolFile/DWARF/DWARFUnit.h
M lldb/test/API/functionalities/conditional_break/TestConditionalBreak.py
M lldb/test/API/functionalities/data-formatter/data-formatter-cpp/TestDataFormatterCpp.py
M lldb/test/API/functionalities/data-formatter/data-formatter-skip-summary/TestDataFormatterSkipSummary.py
M lldb/test/API/lang/cpp/namespace/TestNamespace.py
M lldb/unittests/SymbolFile/DWARF/DWARFUnitTest.cpp
Log Message:
-----------
[lldb] Remove references to llvm-gcc (#120225)
The `llvm-gcc` front-end has been EOL'd at least since 2011 (based on
some `git` archeology). And Clang/LLVM has been removing references to
it ever since.
This patch removes the remaining references to it from LLDB. One benefit
of this is that it will allow us to remove the code checking for
`DW_AT_decl_file_attributes_are_invalid` and
`Supports_DW_AT_APPLE_objc_complete_type`.
Commit: f1763888bb96c9c4069d8d069083371965561111
https://github.com/llvm/llvm-project/commit/f1763888bb96c9c4069d8d069083371965561111
Author: Michael Buch <michaelbuch12 at gmail.com>
Date: 2024-12-17 (Tue, 17 Dec 2024)
Changed paths:
M lldb/source/Plugins/SymbolFile/DWARF/DWARFASTParserClang.cpp
M lldb/source/Plugins/SymbolFile/DWARF/DWARFBaseDIE.cpp
M lldb/source/Plugins/SymbolFile/DWARF/DWARFUnit.cpp
M lldb/source/Plugins/SymbolFile/DWARF/DWARFUnit.h
M lldb/source/Plugins/SymbolFile/DWARF/DebugNamesDWARFIndex.cpp
M lldb/source/Plugins/SymbolFile/DWARF/SymbolFileDWARF.cpp
M lldb/source/Plugins/SymbolFile/DWARF/SymbolFileDWARF.h
M lldb/source/Plugins/SymbolFile/DWARF/SymbolFileDWARFDebugMap.cpp
M lldb/source/Plugins/SymbolFile/DWARF/SymbolFileDWARFDebugMap.h
Log Message:
-----------
[lldb][DWARF] Remove obsolete calls to Supports_DW_AT_APPLE_objc_complete_type and DW_AT_decl_file_attributes_are_invalid (#120226)
Depends on https://github.com/llvm/llvm-project/pull/120225
With `llvm-gcc` support being removed from LLDB, these APIs
are now trivial and can be removed too.
Commit: fbbf1bed746c335b970aee7bd135676e534ffa05
https://github.com/llvm/llvm-project/commit/fbbf1bed746c335b970aee7bd135676e534ffa05
Author: Mariya Podchishchaeva <mariya.podchishchaeva at intel.com>
Date: 2024-12-17 (Tue, 17 Dec 2024)
Changed paths:
M clang/lib/Sema/HLSLExternalSemaSource.cpp
Log Message:
-----------
[HLSL][NFC] Fix static analyzer concerns (#120090)
Class BuiltinTypeMethodBuilder has a user-defined destructor so likely
compiler generated special functions may behave incorrectly. Delete
explicitly copy constructor and copy assignment operator to avoid
potential errors.
Commit: b4c1ded7d54858972c27250f4b6b882e74da1444
https://github.com/llvm/llvm-project/commit/b4c1ded7d54858972c27250f4b6b882e74da1444
Author: Youngsuk Kim <youngsuk.kim at hpe.com>
Date: 2024-12-17 (Tue, 17 Dec 2024)
Changed paths:
M clang/lib/CodeGen/ItaniumCXXABI.cpp
A clang/test/OpenMP/amdgpu_threadprivate.cpp
Log Message:
-----------
[clang] Recover necessary AddrSpaceCast (#119246)
A necessary AddrSpaceCast was wrongfully deleted in
5c91b2886f6bf400b60ca7839069839ac3980f8f . Recover the AddrSpaceCast.
This fixes #86791 .
Commit: 2072ec1ff957cb08a054e5ce7a1e916232d3bc6b
https://github.com/llvm/llvm-project/commit/2072ec1ff957cb08a054e5ce7a1e916232d3bc6b
Author: Joseph Huber <huberjn at outlook.com>
Date: 2024-12-17 (Tue, 17 Dec 2024)
Changed paths:
M llvm/utils/merge-json.py
Log Message:
-----------
[LLVM] Remove warning print when merging fails
Summary:
This message is only confusing and shouldn't have been added in the
first place.
Commit: f6f4744176c8838a55fabd6f978ac08c3612aabc
https://github.com/llvm/llvm-project/commit/f6f4744176c8838a55fabd6f978ac08c3612aabc
Author: Joseph Huber <huberjn at outlook.com>
Date: 2024-12-17 (Tue, 17 Dec 2024)
Changed paths:
M libc/utils/gpu/server/CMakeLists.txt
Log Message:
-----------
[libc] Install RPC server to `shared/rpc.h` (#120170)
Summary:
This installs the shared header to the users installation. I couldn't
decide if this should be a standalone thing or use the existing support
in `include/` mostly because this is completely separate from hdrgen
stuff and it's C++.
Commit: a487b792e2dabcec02c63d19e32958572a257408
https://github.com/llvm/llvm-project/commit/a487b792e2dabcec02c63d19e32958572a257408
Author: Florian Hahn <flo at fhahn.com>
Date: 2024-12-17 (Tue, 17 Dec 2024)
Changed paths:
M llvm/include/llvm/Analysis/TypeBasedAliasAnalysis.h
M llvm/include/llvm/Bitcode/LLVMBitCodes.h
M llvm/include/llvm/IR/Attributes.td
A llvm/include/llvm/Transforms/Instrumentation/TypeSanitizer.h
M llvm/lib/Analysis/TypeBasedAliasAnalysis.cpp
M llvm/lib/Bitcode/Reader/BitcodeReader.cpp
M llvm/lib/Bitcode/Writer/BitcodeWriter.cpp
M llvm/lib/CodeGen/ShrinkWrap.cpp
M llvm/lib/Passes/PassBuilder.cpp
M llvm/lib/Passes/PassRegistry.def
M llvm/lib/Transforms/Instrumentation/CMakeLists.txt
A llvm/lib/Transforms/Instrumentation/TypeSanitizer.cpp
M llvm/lib/Transforms/Utils/CodeExtractor.cpp
A llvm/test/Instrumentation/TypeSanitizer/access-with-offset.ll
A llvm/test/Instrumentation/TypeSanitizer/alloca-only.ll
A llvm/test/Instrumentation/TypeSanitizer/alloca.ll
A llvm/test/Instrumentation/TypeSanitizer/anon.ll
A llvm/test/Instrumentation/TypeSanitizer/basic-nosan.ll
A llvm/test/Instrumentation/TypeSanitizer/basic.ll
A llvm/test/Instrumentation/TypeSanitizer/byval.ll
A llvm/test/Instrumentation/TypeSanitizer/globals.ll
A llvm/test/Instrumentation/TypeSanitizer/invalid-metadata.ll
A llvm/test/Instrumentation/TypeSanitizer/memintrinsics.ll
A llvm/test/Instrumentation/TypeSanitizer/nosanitize.ll
A llvm/test/Instrumentation/TypeSanitizer/sanitize-no-tbaa.ll
A llvm/test/Instrumentation/TypeSanitizer/swifterror.ll
M llvm/unittests/Analysis/AliasSetTrackerTest.cpp
Log Message:
-----------
[TySan] Add initial Type Sanitizer (LLVM) (#76259)
This patch introduces the LLVM components of a type sanitizer: a
sanitizer for type-based aliasing violations.
It is based on Hal Finkel's https://reviews.llvm.org/D32198.
C/C++ have type-based aliasing rules, and LLVM's optimizer can exploit
these given TBAA metadata added by Clang. Roughly, a pointer of given
type cannot be used to access an object of a different type (with, of
course, certain exceptions). Unfortunately, there's a lot of code in the
wild that violates these rules (e.g. for type punning), and such code
often must be built with -fno-strict-aliasing. Performance is often
sacrificed as a result. Part of the problem is the difficulty of finding
TBAA violations. Hopefully, this sanitizer will help.
For each TBAA type-access descriptor, encoded in LLVM's IR using
metadata, the corresponding instrumentation pass generates descriptor
tables. Thus, for each type (and access descriptor), we have a unique
pointer representation. Excepting anonymous-namespace types, these
tables are comdat, so the pointer values should be unique across the
program. The descriptors refer to other descriptors to form a type
aliasing tree (just like LLVM's TBAA metadata does). The instrumentation
handles the "fast path" (where the types match exactly and no
partial-overlaps are detected), and defers to the runtime to handle all
of the more-complicated cases. The runtime, of course, is also
responsible for reporting errors when those are detected.
The runtime uses essentially the same shadow memory region as tsan, and
we use 8 bytes of shadow memory, the size of the pointer to the type
descriptor, for every byte of accessed data in the program. The value 0
is used to represent an unknown type. The value -1 is used to represent
an interior byte (a byte that is part of a type, but not the first
byte). The instrumentation first checks for an exact match between the
type of the current access and the type for that address recorded in the
shadow memory. If it matches, it then checks the shadow for the
remainder of the bytes in the type to make sure that they're all -1. If
not, we call the runtime. If the exact match fails, we next check if the
value is 0 (i.e. unknown). If it is, then we check the shadow for the
remainder of the byes in the type (to make sure they're all 0). If
they're not, we call the runtime. We then set the shadow for the access
address and set the shadow for the remaining bytes in the type to -1
(i.e. marking them as interior bytes). If the type indicated by the
shadow memory for the access address is neither an exact match nor 0, we
call the runtime.
The instrumentation pass inserts calls to the memset intrinsic to set
the memory updated by memset, memcpy, and memmove, as well as
allocas/byval (and for lifetime.start/end) to reset the shadow memory to
reflect that the type is now unknown. The runtime intercepts memset,
memcpy, etc. to perform the same function for the library calls.
The runtime essentially repeats these checks, but uses the full TBAA
algorithm, just as the compiler does, to determine when two types are
permitted to alias. In a situation where access overlap has occurred and
aliasing is not permitted, an error is generated.
Clang's TBAA representation currently has a problem representing unions,
as demonstrated by the one XFAIL'd test in the runtime patch. We'll
update the TBAA representation to fix this, and at the same time, update
the sanitizer.
When the sanitizer is active, we disable actually using the TBAA
metadata for AA. This way we're less likely to use TBAA to remove memory
accesses that we'd like to verify.
As a note, this implementation does not use the compressed shadow-memory
scheme discussed previously
(http://lists.llvm.org/pipermail/llvm-dev/2017-April/111766.html). That
scheme would not handle the struct-path (i.e. structure offset)
information that our TBAA represents. I expect we'll want to further
work on compressing the shadow-memory representation, but I think it
makes sense to do that as follow-up work.
It goes together with the corresponding clang changes
(https://github.com/llvm/llvm-project/pull/76260) and compiler-rt
changes (https://github.com/llvm/llvm-project/pull/76261)
PR: https://github.com/llvm/llvm-project/pull/76259
Commit: e6ced4da4499007a366ada31cfb07e0b4fbf2393
https://github.com/llvm/llvm-project/commit/e6ced4da4499007a366ada31cfb07e0b4fbf2393
Author: Ivan G. <dreamos82 at yahoo.it>
Date: 2024-12-17 (Tue, 17 Dec 2024)
Changed paths:
M lld/docs/ELF/large_sections.rst
Log Message:
-----------
Typo fix in large_sections.rst (#120101)
Remove duplicate word.
Commit: 70c5887958623dee20273ec04999b69fe3e470da
https://github.com/llvm/llvm-project/commit/70c5887958623dee20273ec04999b69fe3e470da
Author: LLVM GN Syncbot <llvmgnsyncbot at gmail.com>
Date: 2024-12-17 (Tue, 17 Dec 2024)
Changed paths:
M llvm/utils/gn/secondary/llvm/lib/Transforms/Instrumentation/BUILD.gn
Log Message:
-----------
[gn build] Port a487b792e2da
Commit: 17b3dd03a05dfa938aacd57027189271a62e2fda
https://github.com/llvm/llvm-project/commit/17b3dd03a05dfa938aacd57027189271a62e2fda
Author: Mikhail Goncharov <goncharov.mikhail at gmail.com>
Date: 2024-12-17 (Tue, 17 Dec 2024)
Changed paths:
M llvm/test/CodeGen/NVPTX/surf-write.ll
Log Message:
-----------
[NVPTX][test] fix CodeGen/NVPTX/surf-write.ll
ptxas needs a proper triplet
for 133352feb30605ec51b15f77826ed3a2fbf8db56
Commit: ce4ac994529eb33a67b0f450fd6fe847918247e1
https://github.com/llvm/llvm-project/commit/ce4ac994529eb33a67b0f450fd6fe847918247e1
Author: Louis Dionne <ldionne.2 at gmail.com>
Date: 2024-12-17 (Tue, 17 Dec 2024)
Changed paths:
M libcxx/include/module.modulemap
M libcxx/include/stdio.h
M libcxx/include/stdlib.h
M libcxx/include/wchar.h
M libcxx/test/libcxx/clang_modules_include.gen.py
Log Message:
-----------
[libc++] Remove explicit mentions of __need_FOO macros (#119025)
This change has a long history. It was first attempted naively in
https://reviews.llvm.org/D131425, which didn't work because we broke the
ability for code to include e.g. <stdio.h> multiple times and get
different definitions based on the pre-defined macros.
However, in #86843 we managed to simplify <stddef.h> by including the
underlying system header outside of any include guards, which worked.
This patch applies the same simplification we did to <stddef.h> to the
other headers that currently mention __need_FOO macros explicitly.
Commit: cf4375d107e8055e52ff43f66b65092b075d8442
https://github.com/llvm/llvm-project/commit/cf4375d107e8055e52ff43f66b65092b075d8442
Author: Sergei Barannikov <barannikov88 at gmail.com>
Date: 2024-12-17 (Tue, 17 Dec 2024)
Changed paths:
M llvm/test/TableGen/GlobalISelEmitter-nested-subregs.td
M llvm/utils/TableGen/GlobalISelEmitter.cpp
Log Message:
-----------
[TableGen][GISel] Extract common function for determining MI's regclass (#120135)
Add some comments that hopefully clarify a few things.
This was supposed to be NFC, but there is a difference in the inferred
register class for EXTRACT_SUBREG.
Pull Request: https://github.com/llvm/llvm-project/pull/120135
Commit: c135f6ffe2542bdde5a2a3e1d6515a6fc7031967
https://github.com/llvm/llvm-project/commit/c135f6ffe2542bdde5a2a3e1d6515a6fc7031967
Author: Florian Hahn <flo at fhahn.com>
Date: 2024-12-17 (Tue, 17 Dec 2024)
Changed paths:
M clang/docs/ReleaseNotes.rst
M clang/include/clang/Basic/Features.def
M clang/include/clang/Basic/Sanitizers.def
M clang/include/clang/Driver/SanitizerArgs.h
M clang/lib/CodeGen/BackendUtil.cpp
M clang/lib/CodeGen/CGDeclCXX.cpp
M clang/lib/CodeGen/CodeGenFunction.cpp
M clang/lib/CodeGen/CodeGenModule.cpp
M clang/lib/CodeGen/CodeGenTBAA.cpp
M clang/lib/CodeGen/SanitizerMetadata.cpp
M clang/lib/Driver/SanitizerArgs.cpp
M clang/lib/Driver/ToolChains/CommonArgs.cpp
M clang/lib/Driver/ToolChains/Darwin.cpp
M clang/lib/Driver/ToolChains/Linux.cpp
A clang/test/CodeGen/sanitize-type-attr.cpp
M clang/test/Driver/sanitizer-ld.c
Log Message:
-----------
[TySan] Add initial Type Sanitizer support to Clang) (#76260)
This patch introduces the Clang components of type sanitizer: a
sanitizer for type-based aliasing violations.
It is based on Hal Finkel's https://reviews.llvm.org/D32198.
The Clang changes are mostly formulaic, the one specific change being
that when the TBAA sanitizer is enabled, TBAA is always generated, even
at -O0.
It goes together with the corresponding LLVM changes
(https://github.com/llvm/llvm-project/pull/76259) and compiler-rt
changes (https://github.com/llvm/llvm-project/pull/76261)
PR: https://github.com/llvm/llvm-project/pull/76260
Commit: d8a0709b1090350a7fe3604d8ab78c7d62f10698
https://github.com/llvm/llvm-project/commit/d8a0709b1090350a7fe3604d8ab78c7d62f10698
Author: Louis Dionne <ldionne.2 at gmail.com>
Date: 2024-12-17 (Tue, 17 Dec 2024)
Changed paths:
M libcxx/utils/ci/Dockerfile
Log Message:
-----------
[libc++] Bump the version of CMake built in the CI Docker image (#120240)
This will allow using the $<LINK_LIBRARY> generator expression in some
of our configurations. We should separately pursue officially bumping
the minimum CMake version across all LLVM so we can use this feature
more widely.
Commit: 6a7d6c5f69dda254ec92f982985fd10fa51c63ef
https://github.com/llvm/llvm-project/commit/6a7d6c5f69dda254ec92f982985fd10fa51c63ef
Author: Mehdi Amini <joker.eph at gmail.com>
Date: 2024-12-17 (Tue, 17 Dec 2024)
Changed paths:
M mlir/lib/Target/LLVM/CMakeLists.txt
M mlir/lib/Target/LLVM/NVVM/Target.cpp
Log Message:
-----------
[MLIR] Add a MLIR_NVVM_EMBED_LIBDEVICE CMake option that embeds libdevice in the binary (#120238)
This removes a runtime dependency on the CUDA Toolkit path, instead of
looking up the filesystem we use a version of libdevice embedded in the
binary at build time.
Commit: f539e00c702b4e5732d76e093c2d909fd8702683
https://github.com/llvm/llvm-project/commit/f539e00c702b4e5732d76e093c2d909fd8702683
Author: Maksim Levental <maksim.levental at gmail.com>
Date: 2024-12-17 (Tue, 17 Dec 2024)
Changed paths:
M mlir/docs/PassManagement.md
M mlir/include/mlir/IR/OperationSupport.h
M mlir/lib/IR/AsmPrinter.cpp
A mlir/test/IR/print-use-nameloc-as-prefix.mlir
Log Message:
-----------
[mlir] add option to print SSA IDs using `NameLoc`s as prefixes (#119996)
This PR adds an `AsmPrinter` option `-mlir-use-nameloc-as-prefix` which
uses trailing `NameLoc`s, if the source IR provides them, as prefixes
when printing SSA IDs.
Commit: 146240ef1c0f25259ef30d9d14c124e574764a01
https://github.com/llvm/llvm-project/commit/146240ef1c0f25259ef30d9d14c124e574764a01
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-12-17 (Tue, 17 Dec 2024)
Changed paths:
M llvm/lib/Transforms/Instrumentation/TypeSanitizer.cpp
Log Message:
-----------
Fix MSVC " 32-bit shift implicitly converted to 64 bits" warnings. NFC.
Commit: 57c161a6479fb70a31553e2f9bc1efa46262aa92
https://github.com/llvm/llvm-project/commit/57c161a6479fb70a31553e2f9bc1efa46262aa92
Author: Gedare Bloom <gedare at rtems.org>
Date: 2024-12-17 (Tue, 17 Dec 2024)
Changed paths:
M clang/lib/Format/ContinuationIndenter.cpp
M clang/unittests/Format/FormatTestJS.cpp
Log Message:
-----------
[clang-format] Detect nesting in template strings (#119989)
The helper to check if a token is in a template string scans too far
backward. It should stop if a different scope is found.
Fixes #107571
Commit: 62bd10f7d18ca6f544286767cae2c9026d493888
https://github.com/llvm/llvm-project/commit/62bd10f7d18ca6f544286767cae2c9026d493888
Author: Petr Hosek <phosek at google.com>
Date: 2024-12-17 (Tue, 17 Dec 2024)
Changed paths:
M libcxx/src/include/overridable_function.h
M libcxx/src/new.cpp
M libcxxabi/src/stdlib_new_delete.cpp
Log Message:
-----------
[libcxx] Use alias for detecting overriden function (#114961)
This mechanism is preferable in environments like embedded since it
doesn't require special handling of the custom section.
Commit: edf9439e00971b55bae19e40ef6a8e132645a56a
https://github.com/llvm/llvm-project/commit/edf9439e00971b55bae19e40ef6a8e132645a56a
Author: Petr Hosek <phosek at google.com>
Date: 2024-12-17 (Tue, 17 Dec 2024)
Changed paths:
M clang/cmake/caches/Fuchsia-stage2.cmake
M libcxx/src/chrono.cpp
M libcxx/src/filesystem/filesystem_clock.cpp
Log Message:
-----------
[libcxx] Support for using timespec_get (#117362)
clock_gettime is a POSIX API that may not be available on platforms like
baremetal; timespec_get is the C11 equivalent. This change adds support
for using timespec_get instead of clock_gettime to improve compatibility
with non-POSIX platforms. For now, this is only enabled with LLVM libc
which implemented timespec_get in #116102, but in the future this can be
expanded to other platforms.
Related to #84879.
Commit: 7ab8dd7c31c9a595b183aa857bb3536be01f350d
https://github.com/llvm/llvm-project/commit/7ab8dd7c31c9a595b183aa857bb3536be01f350d
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-12-17 (Tue, 17 Dec 2024)
Changed paths:
M llvm/lib/Target/X86/X86ISelLowering.cpp
Log Message:
-----------
[X86] LowerShift - pull out repeated getVectorNumElements calls. NFC. (#120241)
Commit: 34a44b20888479cf934014e3aa85c563725df69a
https://github.com/llvm/llvm-project/commit/34a44b20888479cf934014e3aa85c563725df69a
Author: Nico Weber <thakis at chromium.org>
Date: 2024-12-17 (Tue, 17 Dec 2024)
Changed paths:
M lld/COFF/Driver.cpp
M lld/COFF/Driver.h
M lld/test/COFF/linkrepro.test
Log Message:
-----------
[lld/COFF] Handle -start-lib / -end-lib better in /reproduce: output (#119752)
Previously, we'd collect all input files in Driver::filePaths, and then
write filePaths after all other flags in
createResponseFile(). This meant that `-start-lib foo.obj -end-lib`
would be written as `-start-lib -end-lib foo.obj`, changing semantics.
Instead, remove Driver::filePaths, and handle things that fed into it
directly:
* OPT_INPUT is now handled in the same way as other flags, so that we
now get `-start-lib foo.obj -end-lib` in response.txt as desired. Add a
test for -start-lib / -end-lib and /reproduce:.
* OPT_wholearchive_file needs explicit handling now -- but before, this
was buggy as well: We'd put the flag without a rewritten path in
response.txt, but also the rewritten input file without wholearchive
semantics via filePaths. So this commit makes --whole-archive work with
/reproduce: too, and adds test coverage.
* /defaultlib:foo is now written as /defaultlib:foo into response.txt,
instead of writing the resolved path previously. While response.txt
looks slightly differently, both should have the same semantics, and
this should be mostly a no-op. (It does require updating a test.)
* /defaultlib: from .drectve sections are no longer recorded in
response.txt. This seems like a progression -- in the non-repro case
they come from .obj files, so they should come (only) from there in the
repro case too. This adds test coverage for this case.
Makes createResponseFile() look more like the versions in the ELF and
MachO ports too.
Commit: 9fc54c0e8049553a30c17a3698445d58800916c9
https://github.com/llvm/llvm-project/commit/9fc54c0e8049553a30c17a3698445d58800916c9
Author: Michael Buch <michaelbuch12 at gmail.com>
Date: 2024-12-17 (Tue, 17 Dec 2024)
Changed paths:
M clang/lib/CodeGen/CGDebugInfo.cpp
M clang/test/Modules/ExtDebugInfo.m
M clang/test/Modules/ModuleDebugInfo.m
A lldb/test/Shell/SymbolFile/DWARF/objc-gmodules-class-extension.test
Log Message:
-----------
[clang][DebugInfo][gmodules] Set runtimeLang on ObjC forward declarations (#120154)
In Objective-C, forward declarations are currently represented as:
```
DW_TAG_structure_type
DW_AT_name ("Foo")
DW_AT_declaration (true)
DW_AT_APPLE_runtime_class (DW_LANG_ObjC)
```
However, when compiling with `-gmodules`, when a class definition is
turned into a forward declaration within a `DW_TAG_module`, the DIE for
the forward declaration looks as follows:
```
DW_TAG_structure_type
DW_AT_name ("Foo")
DW_AT_declaration (true)
```
Note the absence of `DW_AT_APPLE_runtime_class`. With recent changes in
LLDB, not being able to differentiate between C++ and Objective-C
forward declarations has become problematic (see attached test-case and
explanation in https://github.com/llvm/llvm-project/pull/119860).
Commit: 8bb1bdf919c76ec047fd5c646fa210837e88cc75
https://github.com/llvm/llvm-project/commit/8bb1bdf919c76ec047fd5c646fa210837e88cc75
Author: Kazu Hirata <kazu at google.com>
Date: 2024-12-17 (Tue, 17 Dec 2024)
Changed paths:
M llvm/lib/Target/X86/X86ISelLowering.cpp
Log Message:
-----------
[X86] Fix warnings
This patch fixes:
llvm/lib/Target/X86/X86ISelLowering.cpp:30127:23: error: comparison
of integers of different signs: 'int' and 'unsigned int'
[-Werror,-Wsign-compare]
llvm/lib/Target/X86/X86ISelLowering.cpp:30205:35: error: comparison
of integers of different signs: 'int' and 'unsigned int'
[-Werror,-Wsign-compare]
llvm/lib/Target/X86/X86ISelLowering.cpp:30453:23: error: comparison
of integers of different signs: 'int' and 'unsigned int'
[-Werror,-Wsign-compare]
Commit: 558de0e1f993f413a9c8b93d969b28b651c6e437
https://github.com/llvm/llvm-project/commit/558de0e1f993f413a9c8b93d969b28b651c6e437
Author: alx32 <103613512+alx32 at users.noreply.github.com>
Date: 2024-12-17 (Tue, 17 Dec 2024)
Changed paths:
M llvm/include/llvm/DebugInfo/GSYM/DwarfTransformer.h
M llvm/lib/DebugInfo/GSYM/DwarfTransformer.cpp
M llvm/test/tools/llvm-gsymutil/ARM_AArch64/macho-gsym-merged-callsites-dsym.yaml
M llvm/tools/llvm-gsymutil/Opts.td
M llvm/tools/llvm-gsymutil/llvm-gsymutil.cpp
Log Message:
-----------
[llvm-gsymutil] Add option to load callsites from DWARF (#119913)
This change adds support for loading gSYM callsite information from
DWARF. Previously the only support was for loading callsites info from
YAML.
For testing, we add a pass where `macho-gsym-merged-callsites-dsym`
loads callsite info from DWARF rather than YAML.
Commit: 525c818f08e097cd123839b8d96a543e2c9da26e
https://github.com/llvm/llvm-project/commit/525c818f08e097cd123839b8d96a543e2c9da26e
Author: Mikhail Goncharov <goncharov.mikhail at gmail.com>
Date: 2024-12-17 (Tue, 17 Dec 2024)
Changed paths:
M utils/bazel/llvm-project-overlay/mlir/BUILD.bazel
Log Message:
-----------
[bazel] port 6a7d6c5f69dda254ec92f982985fd10fa51c63ef
Commit: 9d33874936d83b8ddf5d028d313d810214f00f20
https://github.com/llvm/llvm-project/commit/9d33874936d83b8ddf5d028d313d810214f00f20
Author: Slava Zakharin <szakharin at nvidia.com>
Date: 2024-12-17 (Tue, 17 Dec 2024)
Changed paths:
M clang/include/clang/Driver/Options.td
M clang/lib/Driver/ToolChains/Flang.cpp
M flang/include/flang/Lower/LoweringOptions.def
M flang/lib/Frontend/CompilerInvocation.cpp
M flang/lib/Lower/Bridge.cpp
A flang/test/Driver/frealloc-lhs.f90
A flang/test/Lower/reallocate-lhs.f90
M flang/tools/bbc/bbc.cpp
Log Message:
-----------
[flang] Support -f[no-]realloc-lhs. (#120165)
-frealloc-lhs is the default.
If -fno-realloc-lhs is specified, then an allocatable on the left
side of an intrinsic assignment is not implicitly (re)allocated
to conform with the right hand side. Fortran runtime will issue
an error if there is a mismatch in shape/type/allocation-status.
Commit: fbbbd65b2573dc92c3c2272ce57da29cf8227a35
https://github.com/llvm/llvm-project/commit/fbbbd65b2573dc92c3c2272ce57da29cf8227a35
Author: Timothy Hoffman <4001421+tim-hoffman at users.noreply.github.com>
Date: 2024-12-17 (Tue, 17 Dec 2024)
Changed paths:
M mlir/lib/Dialect/GPU/IR/GPUDialect.cpp
M mlir/lib/Dialect/LLVMIR/IR/LLVMAttrs.cpp
M mlir/test/lib/Dialect/Test/TestTypes.cpp
Log Message:
-----------
[MLIR] correct return type of parse() functions (#120180)
The `parseX()` functions that are defined to support `custom<X>` in
`assemblyFormat` should return `ParseResult` rather than
`LogicalResult`. The `ParseResult` type is necessary due to tablegen
generating code that expects this type within an Op `parseX()` function.
Commit: 345a35259ccfdc5031bc4c4bdb0f47959fa75806
https://github.com/llvm/llvm-project/commit/345a35259ccfdc5031bc4c4bdb0f47959fa75806
Author: Michael Maitland <michaeltmaitland at gmail.com>
Date: 2024-12-17 (Tue, 17 Dec 2024)
Changed paths:
M llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp
A llvm/test/CodeGen/RISCV/rvv/vl-opt-user-scalar-def.mir
Log Message:
-----------
[RISCV][VLOPT] Avoid crash when user produces scalar def (#120255)
I found this crash when trying to enable the VLOptimizer pass. We need
this patch before we can enable by default. The old assert was not
checking that USE and DEF were vector registers. The correct condition
is guarded at the callsite of tryReduceVL.
Commit: 30916b6942371fc314f3ce1bfa4042cae3e6ff28
https://github.com/llvm/llvm-project/commit/30916b6942371fc314f3ce1bfa4042cae3e6ff28
Author: Kazu Hirata <kazu at google.com>
Date: 2024-12-17 (Tue, 17 Dec 2024)
Changed paths:
M mlir/lib/Dialect/MemRef/IR/MemRefOps.cpp
M mlir/lib/Dialect/MemRef/Transforms/ComposeSubView.cpp
M mlir/lib/Dialect/MemRef/Transforms/ExpandStridedMetadata.cpp
M mlir/lib/Dialect/MemRef/Transforms/IndependenceTransforms.cpp
Log Message:
-----------
[MemRef] Migrate away from PointerUnion::{is,get} (NFC) (#120202)
Note that PointerUnion::{is,get} have been soft deprecated in
PointerUnion.h:
// FIXME: Replace the uses of is(), get() and dyn_cast() with
// isa<T>, cast<T> and the llvm::dyn_cast<T>
I'm not touching PointerUnion::dyn_cast for now because it's a bit
complicated; we could blindly migrate it to dyn_cast_if_present, but
we should probably use dyn_cast when the operand is known to be
non-null.
Commit: e8a6563768579e6f555b2d9192f2c2a0cb27534a
https://github.com/llvm/llvm-project/commit/e8a6563768579e6f555b2d9192f2c2a0cb27534a
Author: Thurston Dang <thurston at google.com>
Date: 2024-12-17 (Tue, 17 Dec 2024)
Changed paths:
M llvm/lib/CodeGen/RegAllocFast.cpp
Log Message:
-----------
Fix-forward 'RegAllocFast: Avoid using temporary DiagnosticInfo #120184' (#120268)
There was a buildbot breakage
(https://lab.llvm.org/buildbot/#/builders/24/builds/3329/steps/11/logs/stdio):
/home/b/sanitizer-aarch64-linux-bootstrap-asan/build/llvm-project/llvm/test/CodeGen/AMDGPU/ran-out-of-registers-error-all-regs-reserved.ll:9:10:
error: CHECK: expected string not found in input
; CHECK: error: <unknown>:0:0: no registers from class available to
allocate in function 'no_registers_from_class_available_to_allocate'
2: ==75198==ERROR: AddressSanitizer: stack-use-after-scope on address
0xfa23f9f1c270 at pc 0xb2660dda9340 bp 0xfffffe8ab340 sp 0xfffffe8ab338
caused by https://github.com/llvm/llvm-project/pull/120184, which made a
partial fix but also renabled the tests. This patch attempts to fix
forward by applying the same fix to the error message highlighted in the
buildbot.
Commit: a57f4c7009cd5eacc64cc78a1788c87318218d79
https://github.com/llvm/llvm-project/commit/a57f4c7009cd5eacc64cc78a1788c87318218d79
Author: lntue <lntue at google.com>
Date: 2024-12-17 (Tue, 17 Dec 2024)
Changed paths:
M compiler-rt/lib/builtins/fp_div_impl.inc
M compiler-rt/test/builtins/Unit/divdf3_test.c
M compiler-rt/test/builtins/Unit/divsf3_test.c
M compiler-rt/test/builtins/Unit/divtf3_test.c
Log Message:
-----------
[compiler-rt] Fix a bug in fp_div_impl when an intermediate result is out of expected range. (#119449)
Before this fix, `1.0L / (1.0L - 0x1.0p-113L)` will return `2 * (1 +
eps(1))`.
Commit: 90c7600f25b54f9b977a571e9c4f067e15d48316
https://github.com/llvm/llvm-project/commit/90c7600f25b54f9b977a571e9c4f067e15d48316
Author: Guray Ozen <guray.ozen at gmail.com>
Date: 2024-12-17 (Tue, 17 Dec 2024)
Changed paths:
M mlir/include/mlir/Dialect/LLVMIR/NVVMOps.td
M mlir/test/Target/LLVMIR/nvvmir.mlir
Log Message:
-----------
[MLIR][NVVM] Add exit (#120251)
PR adds `exit` instruction to nvvm dialect.
Commit: 904849f2973eb8ab517f8a805cf8a747924220ef
https://github.com/llvm/llvm-project/commit/904849f2973eb8ab517f8a805cf8a747924220ef
Author: Michael Maitland <michaeltmaitland at gmail.com>
Date: 2024-12-17 (Tue, 17 Dec 2024)
Changed paths:
M llvm/test/CodeGen/RISCV/rvv/vl-opt-instrs.ll
M llvm/test/CodeGen/RISCV/rvv/vl-opt-op-info.mir
Log Message:
-----------
[RISCV][VLOPT] Add support for more instructions in vl-opt-op-info.mir (#119416)
Specifically, some more where EMUL=LMUL and EEW=SEW.
Commit: 5287299f8809ae927a0acafb179c4b37ce9ff21d
https://github.com/llvm/llvm-project/commit/5287299f8809ae927a0acafb179c4b37ce9ff21d
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-12-17 (Tue, 17 Dec 2024)
Changed paths:
M llvm/lib/Transforms/Vectorize/VectorCombine.cpp
M llvm/test/Transforms/VectorCombine/X86/concat-boolmasks.ll
Log Message:
-----------
[VectorCombine] foldShuffleOfBinops - prefer same cost fold if it reduces instruction count (#120216)
We don't fold "shuffle (binop), (binop)" -> "binop (shuffle), (shuffle)" if the old/new costs are equal, but we can relax this if either new shuffle will constant fold as it will reduce instruction count.
Commit: 8bbbcaddbb0f4d39b8da3c5c90eb8627a1cab1ee
https://github.com/llvm/llvm-project/commit/8bbbcaddbb0f4d39b8da3c5c90eb8627a1cab1ee
Author: Brox Chen <guochen2 at amd.com>
Date: 2024-12-17 (Tue, 17 Dec 2024)
Changed paths:
M llvm/lib/Target/AMDGPU/VOP2Instructions.td
M llvm/test/MC/AMDGPU/gfx11_asm_vop2.s
M llvm/test/MC/AMDGPU/gfx11_asm_vop2_dpp16.s
M llvm/test/MC/AMDGPU/gfx11_asm_vop2_dpp8.s
M llvm/test/MC/AMDGPU/gfx11_asm_vop2_t16_err.s
M llvm/test/MC/AMDGPU/gfx11_asm_vop2_t16_promote.s
M llvm/test/MC/AMDGPU/gfx11_asm_vop3_dpp16_from_vop2.s
M llvm/test/MC/AMDGPU/gfx11_asm_vop3_dpp8_from_vop2.s
M llvm/test/MC/AMDGPU/gfx11_asm_vop3_from_vop2.s
Log Message:
-----------
[AMDGPU][True16][MC] test update for v_max_f16/v_min_f16 in true16 (#119291)
This is a NFC change. Update mc test for v_max/min_f16 in true16 format.
MC source change was done by previous patch and automatically enabled by
t16 pesudo
Commit: 2a922903bf5d5b0012c1f8f2a5396d44cfff4630
https://github.com/llvm/llvm-project/commit/2a922903bf5d5b0012c1f8f2a5396d44cfff4630
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-12-17 (Tue, 17 Dec 2024)
Changed paths:
M llvm/test/CodeGen/X86/vector-shift-ashr-128.ll
M llvm/test/CodeGen/X86/vector-shift-ashr-256.ll
M llvm/test/CodeGen/X86/vector-shift-ashr-512.ll
M llvm/test/CodeGen/X86/vector-shift-ashr-sub128.ll
M llvm/test/CodeGen/X86/vector-shift-shl-256.ll
M llvm/test/CodeGen/X86/vector-shift-shl-512.ll
Log Message:
-----------
[X86] vector-shift tests - regenerate VPTERNLOG comments
Commit: f9a9173b6ca065441d8432f268fb4eeae5e8abb6
https://github.com/llvm/llvm-project/commit/f9a9173b6ca065441d8432f268fb4eeae5e8abb6
Author: Brox Chen <guochen2 at amd.com>
Date: 2024-12-17 (Tue, 17 Dec 2024)
Changed paths:
M llvm/lib/Target/AMDGPU/VOP2Instructions.td
M llvm/test/MC/AMDGPU/gfx11_asm_vop2.s
M llvm/test/MC/AMDGPU/gfx11_asm_vop2_dpp16.s
M llvm/test/MC/AMDGPU/gfx11_asm_vop2_dpp8.s
M llvm/test/MC/AMDGPU/gfx11_asm_vop2_t16_err.s
M llvm/test/MC/AMDGPU/gfx11_asm_vop2_t16_promote.s
M llvm/test/MC/AMDGPU/gfx11_asm_vop3_dpp16_from_vop2.s
M llvm/test/MC/AMDGPU/gfx11_asm_vop3_dpp8_from_vop2.s
M llvm/test/MC/AMDGPU/gfx11_asm_vop3_from_vop2.s
M llvm/test/MC/AMDGPU/gfx12_asm_vop2.s
M llvm/test/MC/AMDGPU/gfx12_asm_vop2_dpp16.s
M llvm/test/MC/AMDGPU/gfx12_asm_vop2_dpp8.s
M llvm/test/MC/AMDGPU/gfx12_asm_vop2_t16_err.s
M llvm/test/MC/AMDGPU/gfx12_asm_vop2_t16_promote.s
M llvm/test/MC/AMDGPU/gfx12_asm_vop3_from_vop2.s
M llvm/test/MC/AMDGPU/gfx12_asm_vop3_from_vop2_dpp16.s
M llvm/test/MC/AMDGPU/gfx12_asm_vop3_from_vop2_dpp8.s
Log Message:
-----------
[AMDGPU][True16][MC] test update for v_mul_f16 in true16 (#119314)
This is a NFC change. Update mc test for v_mul_f16 in true16 format.
MC source change was done by previous patch and automatically enabled by
t16 pesudo
Commit: 659dbb632980552b39918e726b8bb35371f6e61a
https://github.com/llvm/llvm-project/commit/659dbb632980552b39918e726b8bb35371f6e61a
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-12-17 (Tue, 17 Dec 2024)
Changed paths:
M llvm/lib/Target/RISCV/RISCVInstrInfoA.td
Log Message:
-----------
[RISCV] Remove unnecessary patterns from RISCVInstrInfoA.td. NFC
Looks like they got left behind in the Zalasr patch after I removed
i32 patterns for RV64.
Commit: 9c8214ff31d7d515b1789cd6cbc21c9663be53df
https://github.com/llvm/llvm-project/commit/9c8214ff31d7d515b1789cd6cbc21c9663be53df
Author: Jacek Caban <jacek at codeweavers.com>
Date: 2024-12-17 (Tue, 17 Dec 2024)
Changed paths:
M lld/COFF/Driver.cpp
M lld/COFF/InputFiles.cpp
M lld/COFF/InputFiles.h
M lld/COFF/LTO.cpp
Log Message:
-----------
[LLD][COFF] Create COFFObjectFile instance when constructing ObjFile (NFC) (#120144)
This change moves the creation of COFFObjectFile to the construction of
ObjFile, instead of delaying it until parsing.
Commit: b26f534980b6c10e74bfbebe4a1296ef5e9b1486
https://github.com/llvm/llvm-project/commit/b26f534980b6c10e74bfbebe4a1296ef5e9b1486
Author: Brox Chen <guochen2 at amd.com>
Date: 2024-12-17 (Tue, 17 Dec 2024)
Changed paths:
M llvm/lib/Target/AMDGPU/VOP3Instructions.td
M llvm/test/MC/AMDGPU/gfx11_asm_vop3.s
M llvm/test/MC/AMDGPU/gfx11_asm_vop3_dpp16.s
M llvm/test/MC/AMDGPU/gfx11_asm_vop3_dpp8.s
M llvm/test/MC/AMDGPU/gfx12_asm_vop3.s
M llvm/test/MC/AMDGPU/gfx12_asm_vop3_dpp16.s
M llvm/test/MC/AMDGPU/gfx12_asm_vop3_dpp8.s
M llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop3.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop3_dpp16.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop3_dpp8.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3_dpp16.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3_dpp8.txt
Log Message:
-----------
[AMDGPU][True16][MC] test update for v_and/or/xor_b16 in true16 (#119489)
This is a NFC change. Update mc test for v_and/or/xor_b16 in true16
format.
MC source change was done by previous patch and automatically enabled by
t16 pesudo
Commit: 1c16807d0dd740ace0f21ed29d1381a0078f745e
https://github.com/llvm/llvm-project/commit/1c16807d0dd740ace0f21ed29d1381a0078f745e
Author: Nick Sarnie <nick.sarnie at intel.com>
Date: 2024-12-17 (Tue, 17 Dec 2024)
Changed paths:
M llvm/include/llvm/TargetParser/Triple.h
M llvm/lib/TargetParser/Triple.cpp
M llvm/unittests/TargetParser/TripleTest.cpp
Log Message:
-----------
[LLVM] Add Intel vendor in Triple (#120250)
We plan to make use of this in SPIR-V-based OpenMP offloading, for which
there is already an initial patch in review.
Signed-off-by: Sarnie, Nick <nick.sarnie at intel.com>
Commit: 4c5ddc9ed4992e3c5147441cd7057724618f30da
https://github.com/llvm/llvm-project/commit/4c5ddc9ed4992e3c5147441cd7057724618f30da
Author: Nick Desaulniers <nickdesaulniers at users.noreply.github.com>
Date: 2024-12-17 (Tue, 17 Dec 2024)
Changed paths:
M libc/docs/conf.py
M llvm/docs/requirements.txt
Log Message:
-----------
[libc][docs] add redirect for math/index.html (#120274)
commit a9aff440d9dd ("[libc][docs] reorganize documentation (#118836)")
moved https://libc.llvm.org/math/index.html to
https://libc.llvm.org/headers/math/index.html which makes links from
various slide decks stale.
There's an extension for sphinx that can generate redirects. Add a dependency
on that, then use it to create a redirect so that those older links still work.
I was able to install this sphinx extension via:
$ sudo apt install python3-sphinx-reredirects
We may need to install this on whatever server generates the llvm
documentation.
Commit: 7477b61b2416ca130bd3ed9bbc96988e5de17623
https://github.com/llvm/llvm-project/commit/7477b61b2416ca130bd3ed9bbc96988e5de17623
Author: Tristan Ross <tristan.ross at midstall.com>
Date: 2024-12-17 (Tue, 17 Dec 2024)
Changed paths:
M libc/hdr/CMakeLists.txt
M libc/hdr/types/CMakeLists.txt
M libc/hdr/types/ssize_t.h
A libc/hdr/types/uid_t.h
M libc/hdr/unistd_macros.h
A libc/hdr/unistd_overlay.h
M libc/src/unistd/dup.h
M libc/src/unistd/dup2.h
M libc/src/unistd/dup3.h
M libc/src/unistd/fork.h
M libc/src/unistd/ftruncate.h
M libc/src/unistd/getcwd.h
M libc/src/unistd/geteuid.h
M libc/src/unistd/getopt.h
M libc/src/unistd/getpid.h
M libc/src/unistd/getppid.h
M libc/src/unistd/getuid.h
M libc/src/unistd/isatty.h
M libc/src/unistd/link.h
M libc/src/unistd/linux/CMakeLists.txt
M libc/src/unistd/linux/ftruncate.cpp
M libc/src/unistd/linux/lseek.cpp
M libc/src/unistd/linux/sysconf.cpp
M libc/src/unistd/linux/truncate.cpp
M libc/src/unistd/lseek.h
M libc/src/unistd/pread.h
M libc/src/unistd/pwrite.h
M libc/src/unistd/read.h
M libc/src/unistd/readlink.h
M libc/src/unistd/readlinkat.h
M libc/src/unistd/swab.h
M libc/src/unistd/symlink.h
M libc/src/unistd/symlinkat.h
M libc/src/unistd/syscall.h
M libc/src/unistd/sysconf.h
M libc/src/unistd/truncate.h
M libc/src/unistd/write.h
M libc/test/src/sys/mman/linux/remap_file_pages_test.cpp
M utils/bazel/llvm-project-overlay/libc/BUILD.bazel
Log Message:
-----------
[libc] Add unistd overlay (#119312)
Reverts the revert #119295 of #118882 by expanding #118882 with
additional fixes which made CI unhappy.
Commit: 5d4e4b35030cd103884b89a184ae02a6e8871388
https://github.com/llvm/llvm-project/commit/5d4e4b35030cd103884b89a184ae02a6e8871388
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-12-17 (Tue, 17 Dec 2024)
Changed paths:
M llvm/lib/Target/X86/X86ISelLowering.cpp
Log Message:
-----------
[X86] LowerShift - use getConstant directly to create vector splat constants. NFC.
Commit: 641fbf1524338c86c952ebb1ec8d2b497ada3cef
https://github.com/llvm/llvm-project/commit/641fbf1524338c86c952ebb1ec8d2b497ada3cef
Author: Florian Hahn <flo at fhahn.com>
Date: 2024-12-17 (Tue, 17 Dec 2024)
Changed paths:
M clang/runtime/CMakeLists.txt
M compiler-rt/cmake/Modules/AllSupportedArchDefs.cmake
M compiler-rt/cmake/config-ix.cmake
A compiler-rt/lib/tysan/CMakeLists.txt
A compiler-rt/lib/tysan/lit.cfg
A compiler-rt/lib/tysan/lit.site.cfg.in
A compiler-rt/lib/tysan/tysan.cpp
A compiler-rt/lib/tysan/tysan.h
A compiler-rt/lib/tysan/tysan.syms.extra
A compiler-rt/lib/tysan/tysan_flags.inc
A compiler-rt/lib/tysan/tysan_interceptors.cpp
A compiler-rt/lib/tysan/tysan_platform.h
A compiler-rt/test/tysan/CMakeLists.txt
A compiler-rt/test/tysan/anon-ns.cpp
A compiler-rt/test/tysan/anon-same-struct.c
A compiler-rt/test/tysan/anon-struct.c
A compiler-rt/test/tysan/basic.c
A compiler-rt/test/tysan/char-memcpy.c
A compiler-rt/test/tysan/constexpr-subobject.cpp
A compiler-rt/test/tysan/global.c
A compiler-rt/test/tysan/int-long.c
A compiler-rt/test/tysan/lit.cfg.py
A compiler-rt/test/tysan/lit.site.cfg.py.in
A compiler-rt/test/tysan/ptr-float.c
A compiler-rt/test/tysan/struct-offset-multiple-compilation-units.cpp
A compiler-rt/test/tysan/struct-offset.c
A compiler-rt/test/tysan/struct.c
A compiler-rt/test/tysan/union-wr-wr.c
A compiler-rt/test/tysan/violation-pr45282.c
A compiler-rt/test/tysan/violation-pr47137.c
A compiler-rt/test/tysan/violation-pr51837.c
A compiler-rt/test/tysan/violation-pr62544.c
A compiler-rt/test/tysan/violation-pr62828.cpp
A compiler-rt/test/tysan/violation-pr68655.cpp
A compiler-rt/test/tysan/violation-pr86685.c
Log Message:
-----------
[TySan] Add initial Type Sanitizer runtime (#76261)
This patch introduces the runtime components for type sanitizer: a
sanitizer for type-based aliasing violations.
It is based on Hal Finkel's https://reviews.llvm.org/D32197.
C/C++ have type-based aliasing rules, and LLVM's optimizer can exploit
these given TBAA metadata added by Clang. Roughly, a pointer of given
type cannot be used to access an object of a different type (with, of
course, certain exceptions). Unfortunately, there's a lot of code in the
wild that violates these rules (e.g. for type punning), and such code
often must be built with -fno-strict-aliasing. Performance is often
sacrificed as a result. Part of the problem is the difficulty of finding
TBAA violations. Hopefully, this sanitizer will help.
For each TBAA type-access descriptor, encoded in LLVM's IR using
metadata, the corresponding instrumentation pass generates descriptor
tables. Thus, for each type (and access descriptor), we have a unique
pointer representation. Excepting anonymous-namespace types, these
tables are comdat, so the pointer values should be unique across the
program. The descriptors refer to other descriptors to form a type
aliasing tree (just like LLVM's TBAA metadata does). The instrumentation
handles the "fast path" (where the types match exactly and no
partial-overlaps are detected), and defers to the runtime to handle all
of the more-complicated cases. The runtime, of course, is also
responsible for reporting errors when those are detected.
The runtime uses essentially the same shadow memory region as tsan, and
we use 8 bytes of shadow memory, the size of the pointer to the type
descriptor, for every byte of accessed data in the program. The value 0
is used to represent an unknown type. The value -1 is used to represent
an interior byte (a byte that is part of a type, but not the first
byte). The instrumentation first checks for an exact match between the
type of the current access and the type for that address recorded in the
shadow memory. If it matches, it then checks the shadow for the
remainder of the bytes in the type to make sure that they're all -1. If
not, we call the runtime. If the exact match fails, we next check if the
value is 0 (i.e. unknown). If it is, then we check the shadow for the
remainder of the byes in the type (to make sure they're all 0). If
they're not, we call the runtime. We then set the shadow for the access
address and set the shadow for the remaining bytes in the type to -1
(i.e. marking them as interior bytes). If the type indicated by the
shadow memory for the access address is neither an exact match nor 0, we
call the runtime.
The instrumentation pass inserts calls to the memset intrinsic to set
the memory updated by memset, memcpy, and memmove, as well as
allocas/byval (and for lifetime.start/end) to reset the shadow memory to
reflect that the type is now unknown. The runtime intercepts memset,
memcpy, etc. to perform the same function for the library calls.
The runtime essentially repeats these checks, but uses the full TBAA
algorithm, just as the compiler does, to determine when two types are
permitted to alias. In a situation where access overlap has occurred and
aliasing is not permitted, an error is generated.
As a note, this implementation does not use the compressed shadow-memory
scheme discussed previously
(http://lists.llvm.org/pipermail/llvm-dev/2017-April/111766.html). That
scheme would not handle the struct-path (i.e. structure offset)
information that our TBAA represents. I expect we'll want to further
work on compressing the shadow-memory representation, but I think it
makes sense to do that as follow-up work.
This includes build fixes for Linux from Mingjie Xu.
Depends on #76260 (Clang support), #76259 (LLVM support)
PR: https://github.com/llvm/llvm-project/pull/76261
Commit: 4c2a46f5fe2eaa41f851ff4ca37dcc8794312542
https://github.com/llvm/llvm-project/commit/4c2a46f5fe2eaa41f851ff4ca37dcc8794312542
Author: Nico Weber <thakis at chromium.org>
Date: 2024-12-17 (Tue, 17 Dec 2024)
Changed paths:
R lld/test/COFF/Inputs/start-lib1.ll
R lld/test/COFF/Inputs/start-lib2.ll
M lld/test/COFF/start-lib.ll
Log Message:
-----------
[lld/COFF] Make test/COFF/start-lib.ll use split-file
The two input files were only used by this one test, so put them inline.
No behavior change.
Commit: de2acda3dfafc1fb81b1eba1a326272f704e62e6
https://github.com/llvm/llvm-project/commit/de2acda3dfafc1fb81b1eba1a326272f704e62e6
Author: Brox Chen <guochen2 at amd.com>
Date: 2024-12-17 (Tue, 17 Dec 2024)
Changed paths:
M llvm/lib/Target/AMDGPU/SIInstructions.td
M llvm/lib/Target/AMDGPU/VOP3Instructions.td
M llvm/lib/Target/AMDGPU/VOPInstructions.td
M llvm/test/MC/AMDGPU/gfx11_asm_vop3.s
M llvm/test/MC/AMDGPU/gfx11_asm_vop3_dpp16.s
M llvm/test/MC/AMDGPU/gfx11_asm_vop3_dpp8.s
M llvm/test/MC/AMDGPU/gfx12_asm_vop3.s
M llvm/test/MC/AMDGPU/gfx12_asm_vop3_dpp16.s
M llvm/test/MC/AMDGPU/gfx12_asm_vop3_dpp8.s
M llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop3.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop3_dpp16.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop3_dpp8.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3_dpp16.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3_dpp8.txt
Log Message:
-----------
[AMDGPU][True16][MC] support more VOP3 inst in true16/fake16 format (#113603)
Support true16 and fake16 format for more VOP3 instructions in MC
This patch updates the true16 and fake16 vop_profile for the following
instructions and update the asm/dasm tests:
v_mad_u16
v_mad_i16
v_med3_f16
v_med3_i16
v_med3_u16
v_max3_f16
v_max3_i16
v_max3_u16
v_min3_f16
v_min3_i16
v_min3_u16
v_med3_num_f16
Commit: ad32576cffc88bf7c359a528afbed7c2ae7ddb2d
https://github.com/llvm/llvm-project/commit/ad32576cffc88bf7c359a528afbed7c2ae7ddb2d
Author: alx32 <103613512+alx32 at users.noreply.github.com>
Date: 2024-12-17 (Tue, 17 Dec 2024)
Changed paths:
M llvm/include/llvm/DebugInfo/DWARF/DWARFVerifier.h
M llvm/lib/DebugInfo/DWARF/DWARFVerifier.cpp
A llvm/test/tools/llvm-dwarfdump/X86/verify_no_overlap_error_icf.yaml
M llvm/test/tools/llvm-dwarfdump/X86/verify_parent_zero_length.yaml
M llvm/test/tools/llvm-dwarfutil/ELF/X86/verify.test
Log Message:
-----------
[DWARFVerifier] Allow overlapping ranges for ICF-merged functions (#117952)
This patch modifies the DWARF verifier to handle a valid case where two
or more functions have identical address ranges due to being merged by
ICF (Identical Code Folding). Previously, the verifier would incorrectly
report these as errors, but functions merged via ICF (such as when using
LLD's --keep-icf-stabs option) can legitimately share the same address
range.
A new test case has been added to verify this behavior using YAML-based
DWARF data that simulates two DW_TAG_subprogram entries with identical
address ranges. The test ensures that the verifier correctly identifies
this as a valid case and doesn't emit any errors, while still
maintaining the existing verification for truly invalid overlapping
ranges in other scenarios. Before this change, the newly added test case
would have failed, with `llvm-dwarfdump` marking the overlapping address
ranges in the DWARF as an error.
We also modify the existing tests `llvm-dwarfutil/ELF/X86/verify.test` and
`llvm/test/tools/llvm-dwarfdump/X86/verify_parent_zero_length.yaml`
which rely on the existence of the error that we're trying to
suppress. We slightly change one offset so that the ranges don't
perfectly overlap and an error is still generated.
Commit: 56cb55429199435a78f6e836f52cf41577406e90
https://github.com/llvm/llvm-project/commit/56cb55429199435a78f6e836f52cf41577406e90
Author: joaosaffran <126493771+joaosaffran at users.noreply.github.com>
Date: 2024-12-17 (Tue, 17 Dec 2024)
Changed paths:
M clang/lib/CodeGen/CGDebugInfo.cpp
Log Message:
-----------
[NFC] Updating Debug Info generation for 'this' (#119445)
This is PR is updating the debug info generation for `this`. This is
required to fix the generation of debug information for HLSL RWBuffer
type. This was required from another PR:
https://github.com/llvm/llvm-project/pull/119041/files
Co-authored-by: Joao Saffran <jderezende at microsoft.com>
Commit: 83643ddf2f53d269f2350510c11a02704b333393
https://github.com/llvm/llvm-project/commit/83643ddf2f53d269f2350510c11a02704b333393
Author: Jonas Devlieghere <jonas at devlieghere.com>
Date: 2024-12-17 (Tue, 17 Dec 2024)
Changed paths:
M lldb/include/lldb/Expression/DWARFExpression.h
M lldb/source/Expression/DWARFExpression.cpp
M lldb/source/Plugins/SymbolFile/DWARF/SymbolFileDWARF.cpp
Log Message:
-----------
[lldb] Improve error reporting in GetLocation_DW_OP_addr (#120162)
Instead of simply raising an error flag, use an llvm::Expected to
propagate a meaningful error to the caller, who can report it.
rdar://139705570
Commit: e5521fae944c1f3f6905ce5902819a5c9be7f802
https://github.com/llvm/llvm-project/commit/e5521fae944c1f3f6905ce5902819a5c9be7f802
Author: Malte Dehling <mdehling at gmail.com>
Date: 2024-12-17 (Tue, 17 Dec 2024)
Changed paths:
M mlir/tools/mlir-tblgen/OpDocGen.cpp
Log Message:
-----------
[mlir-tblgen] Fix bug in emitEnumDoc (#118131)
Fixes a crash (assertion failure) in `mlir-tblgen -emit-enum-doc` caused
by calling `EnumAttr()` for the wrong type of `Record *`: `EnumAttr`
rather than `EnumAttrInfo` as asserted.
Compare the corresponding line in `emitDialectDoc()`:
https://github.com/llvm/llvm-project/blob/0ad6be1927f89cef09aa5d0fb244873f687997c9/mlir/tools/mlir-tblgen/OpDocGen.cpp#L532
Co-authored-by: Malte Dehling <m.dehling at samsung.com>
Commit: ec636cf3c5048039bd3c52b1ebdb66dabcd273fe
https://github.com/llvm/llvm-project/commit/ec636cf3c5048039bd3c52b1ebdb66dabcd273fe
Author: serge-sans-paille <sguelton at mozilla.com>
Date: 2024-12-17 (Tue, 17 Dec 2024)
Changed paths:
M llvm/test/tools/llvm-split/target-specific-split.ll
M llvm/tools/llvm-split/llvm-split.cpp
Log Message:
-----------
[llvm-split][nfc] Harmonize help and error message (#120062)
Somme error / help message refer to options with a single dash while
help refer to options with a double dash.
Commit: c9a5a6d18bd71b203798b9188f565bdf173ad91b
https://github.com/llvm/llvm-project/commit/c9a5a6d18bd71b203798b9188f565bdf173ad91b
Author: Nico Weber <thakis at chromium.org>
Date: 2024-12-17 (Tue, 17 Dec 2024)
Changed paths:
M lld/COFF/InputFiles.h
Log Message:
-----------
[lld/COFF] Remove unused InputFile::LazyObjectKind
Its use was removed in d496abbe2a037. No behavior change.
Commit: 0e11e194167ff4e4959f0b908b9de5d3f5f801f5
https://github.com/llvm/llvm-project/commit/0e11e194167ff4e4959f0b908b9de5d3f5f801f5
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2024-12-17 (Tue, 17 Dec 2024)
Changed paths:
M llvm/test/Transforms/SLPVectorizer/X86/revectorized_rdx_crash.ll
M llvm/test/Transforms/SLPVectorizer/X86/undef_vect.ll
Log Message:
-----------
[SLP][NFC]Remove undef and update tests
Commit: b2c363e2616dc6ac6ee76c223d84ec512e118d5d
https://github.com/llvm/llvm-project/commit/b2c363e2616dc6ac6ee76c223d84ec512e118d5d
Author: Peter Klausler <pklausler at nvidia.com>
Date: 2024-12-17 (Tue, 17 Dec 2024)
Changed paths:
M flang/lib/Semantics/expression.cpp
A flang/test/Semantics/generic11.f90
Log Message:
-----------
[flang] Fix generic resolution with actual/dummy procedure incompatib… (#120105)
…ility
We generally allow any legal procedure pointer target as an actual
argument for association with a dummy procedure, since many actual
procedures are underspecified EXTERNALs. But for proper generic
resolution, it is necessary to disallow incompatible functions with
explicit result types.
Fixes https://github.com/llvm/llvm-project/issues/119151.
Commit: a957cedea9657addbe8b860852cc98306aa437e7
https://github.com/llvm/llvm-project/commit/a957cedea9657addbe8b860852cc98306aa437e7
Author: Peter Klausler <pklausler at nvidia.com>
Date: 2024-12-17 (Tue, 17 Dec 2024)
Changed paths:
M flang/include/flang/Parser/parse-tree.h
M flang/lib/Parser/Fortran-parsers.cpp
M flang/lib/Parser/expr-parsers.cpp
M flang/lib/Parser/type-parsers.h
A flang/test/Parser/lit-substr-data.f90
Log Message:
-----------
[flang] Handle substring in data statement constant (#120130)
The case of a constant substring wasn't handled in the parser for data
statement constants.
Fixes https://github.com/llvm/llvm-project/issues/119005.
Commit: 0b91d77bf4e4ff65ebeed90acd141018d9889e0f
https://github.com/llvm/llvm-project/commit/0b91d77bf4e4ff65ebeed90acd141018d9889e0f
Author: Roland McGrath <mcgrathr at google.com>
Date: 2024-12-17 (Tue, 17 Dec 2024)
Changed paths:
M libc/include/__llvm-libc-common.h
Log Message:
-----------
[libc] Use __attribute__((__nothrow__)) for __NOEXCEPT in C (#114653)
Consistent with glibc headers, where `noexcept` is used in C++
(or `throw()` in older C++ which llvm-libc doesn't support) in
the public function declarations, `__attribute__((__nothrow__))` is
used in C for compilers that support it.
Commit: 16ef239520d7bca2002346fe2b4003947ad21ecc
https://github.com/llvm/llvm-project/commit/16ef239520d7bca2002346fe2b4003947ad21ecc
Author: Jacek Caban <jacek at codeweavers.com>
Date: 2024-12-17 (Tue, 17 Dec 2024)
Changed paths:
M lld/COFF/COFFLinkerContext.h
M lld/COFF/Driver.cpp
M lld/COFF/InputFiles.cpp
M lld/COFF/SymbolTable.h
M lld/test/COFF/arm64ec-codemap.test
M lld/test/COFF/arm64ec-entry-thunk.s
M lld/test/COFF/arm64ec-lib.test
M lld/test/COFF/arm64ec-range-thunks.s
A lld/test/COFF/arm64x-symtab.s
Log Message:
-----------
[LLD][COFF] Introduce hybrid symbol table for EC input files on ARM64X (#119294)
Commit: e8ce6c4e69745b1b2cd6f7479c48fbae44622cb3
https://github.com/llvm/llvm-project/commit/e8ce6c4e69745b1b2cd6f7479c48fbae44622cb3
Author: Philipp van Kempen <phvankempen at googlemail.com>
Date: 2024-12-17 (Tue, 17 Dec 2024)
Changed paths:
M llvm/lib/Target/RISCV/RISCVInstrInfoXCV.td
Log Message:
-----------
[RISCV] Fix typo in CV_SH_rr_inc pattern (#120246)
This typo in
https://github.com/llvm/llvm-project/blob/main/llvm/lib/Target/RISCV/RISCVInstrInfoXCV.td#L701:L701
caused a compiler crash in 'RISC-V Assembly Printer' because
CV_SH_ri_inc was selected, leading to `getImmOpValue` being called for a
register operand.
This bug did not affect the Assembler output and therefore does not
trigger any existing unit tests, but is visible by examining the final
MIR function.
Commit: c98e79d85663d6a5a5fcd6475b662a750fcf4b8e
https://github.com/llvm/llvm-project/commit/c98e79d85663d6a5a5fcd6475b662a750fcf4b8e
Author: Shourya Goel <shouryagoel10000 at gmail.com>
Date: 2024-12-18 (Wed, 18 Dec 2024)
Changed paths:
M libc/config/linux/aarch64/entrypoints.txt
M libc/config/linux/arm/entrypoints.txt
M libc/config/linux/riscv/entrypoints.txt
M libc/config/linux/x86_64/entrypoints.txt
M libc/docs/headers/complex.rst
M libc/hdrgen/yaml/complex.yaml
M libc/src/__support/CMakeLists.txt
M libc/src/__support/complex_type.h
M libc/src/complex/CMakeLists.txt
M libc/src/complex/conjf128.h
M libc/src/complex/conjf16.h
A libc/src/complex/cproj.h
A libc/src/complex/cprojf.h
A libc/src/complex/cprojf128.h
A libc/src/complex/cprojf16.h
A libc/src/complex/cprojl.h
M libc/src/complex/generic/CMakeLists.txt
M libc/src/complex/generic/conj.cpp
M libc/src/complex/generic/conjf.cpp
M libc/src/complex/generic/conjf128.cpp
M libc/src/complex/generic/conjf16.cpp
M libc/src/complex/generic/conjl.cpp
A libc/src/complex/generic/cproj.cpp
A libc/src/complex/generic/cprojf.cpp
A libc/src/complex/generic/cprojf128.cpp
A libc/src/complex/generic/cprojf16.cpp
A libc/src/complex/generic/cprojl.cpp
M libc/test/src/complex/CMakeLists.txt
A libc/test/src/complex/CprojTest.h
A libc/test/src/complex/cproj_test.cpp
A libc/test/src/complex/cprojf128_test.cpp
A libc/test/src/complex/cprojf16_test.cpp
A libc/test/src/complex/cprojf_test.cpp
A libc/test/src/complex/cprojl_test.cpp
Log Message:
-----------
[libc][complex] Implement different flavors of the `cproj` function (#119722)
Refer section 7.3.9.5 of ISO/IEC 9899:2023
Commit: 2a0091fb4abb5f89198d7e9c039da01921e2b7ee
https://github.com/llvm/llvm-project/commit/2a0091fb4abb5f89198d7e9c039da01921e2b7ee
Author: Mark Danial <118996571+madanial0 at users.noreply.github.com>
Date: 2024-12-17 (Tue, 17 Dec 2024)
Changed paths:
M clang/test/Format/lit.local.cfg
Log Message:
-----------
[AIX] fix unsupported diff flag on AIX (-strip-trailing-cr) (#120276)
https://github.com/llvm/llvm-project/pull/119666 adds the
`-strip-trailing-cr` flag to diff which is not supported on AIX switch
to use the python implementation of diff instead
Commit: 4ad0fdd1631eeae432714c03ede01a10dc00025d
https://github.com/llvm/llvm-project/commit/4ad0fdd1631eeae432714c03ede01a10dc00025d
Author: Florian Hahn <flo at fhahn.com>
Date: 2024-12-17 (Tue, 17 Dec 2024)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
M llvm/test/Transforms/LoopVectorize/AArch64/conditional-branches-cost.ll
M llvm/test/Transforms/LoopVectorize/AArch64/deterministic-type-shrinkage.ll
M llvm/test/Transforms/LoopVectorize/AArch64/divs-with-scalable-vfs.ll
M llvm/test/Transforms/LoopVectorize/AArch64/epilog-vectorization-factors.ll
M llvm/test/Transforms/LoopVectorize/AArch64/epilog-vectorization-widen-inductions.ll
M llvm/test/Transforms/LoopVectorize/AArch64/force-target-instruction-cost.ll
M llvm/test/Transforms/LoopVectorize/AArch64/induction-costs-sve.ll
M llvm/test/Transforms/LoopVectorize/AArch64/induction-costs.ll
M llvm/test/Transforms/LoopVectorize/AArch64/interleave-allocsize-not-equal-typesize.ll
M llvm/test/Transforms/LoopVectorize/AArch64/interleaving-load-store.ll
M llvm/test/Transforms/LoopVectorize/AArch64/interleaving-reduction.ll
M llvm/test/Transforms/LoopVectorize/AArch64/intrinsiccost.ll
M llvm/test/Transforms/LoopVectorize/AArch64/loop-vectorization-factors.ll
M llvm/test/Transforms/LoopVectorize/AArch64/low_trip_count_predicates.ll
M llvm/test/Transforms/LoopVectorize/AArch64/pr60831-sve-inv-store-crash.ll
M llvm/test/Transforms/LoopVectorize/AArch64/store-costs-sve.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve-epilog-vect-inloop-reductions.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve-epilog-vect-reductions.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve-epilog-vect-strict-reductions.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve-epilog-vect.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve-fneg.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve-interleaved-accesses.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve-multiexit.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve-runtime-check-size-based-threshold.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve-vector-reverse.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve2-histcnt-epilogue.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve2-histcnt-too-many-deps.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve2-histcnt.ll
M llvm/test/Transforms/LoopVectorize/ARM/mve-gather-scatter-tailpred.ll
M llvm/test/Transforms/LoopVectorize/ARM/mve-hoist-runtime-checks.ll
M llvm/test/Transforms/LoopVectorize/ARM/mve-multiexit.ll
M llvm/test/Transforms/LoopVectorize/PowerPC/exit-branch-cost.ll
M llvm/test/Transforms/LoopVectorize/PowerPC/optimal-epilog-vectorization.ll
M llvm/test/Transforms/LoopVectorize/RISCV/blocks-with-dead-instructions.ll
M llvm/test/Transforms/LoopVectorize/RISCV/dead-ops-cost.ll
M llvm/test/Transforms/LoopVectorize/RISCV/induction-costs.ll
M llvm/test/Transforms/LoopVectorize/RISCV/masked_gather_scatter.ll
M llvm/test/Transforms/LoopVectorize/RISCV/strided-accesses.ll
M llvm/test/Transforms/LoopVectorize/RISCV/vectorize-force-tail-with-evl-bin-unary-ops-args.ll
M llvm/test/Transforms/LoopVectorize/RISCV/vectorize-force-tail-with-evl-call-intrinsics.ll
M llvm/test/Transforms/LoopVectorize/RISCV/vectorize-force-tail-with-evl-cast-intrinsics.ll
M llvm/test/Transforms/LoopVectorize/RISCV/vectorize-force-tail-with-evl-intermediate-store.ll
M llvm/test/Transforms/LoopVectorize/RISCV/vf-will-not-generate-any-vector-insts.ll
M llvm/test/Transforms/LoopVectorize/X86/conversion-cost.ll
M llvm/test/Transforms/LoopVectorize/X86/cost-model.ll
M llvm/test/Transforms/LoopVectorize/X86/divs-with-tail-folding.ll
M llvm/test/Transforms/LoopVectorize/X86/drop-poison-generating-flags.ll
M llvm/test/Transforms/LoopVectorize/X86/epilog-vectorization-inductions.ll
M llvm/test/Transforms/LoopVectorize/X86/float-induction-x86.ll
M llvm/test/Transforms/LoopVectorize/X86/gather_scatter.ll
M llvm/test/Transforms/LoopVectorize/X86/illegal-parallel-loop-uniform-write.ll
M llvm/test/Transforms/LoopVectorize/X86/induction-costs.ll
M llvm/test/Transforms/LoopVectorize/X86/interleave-cost.ll
M llvm/test/Transforms/LoopVectorize/X86/intrinsiccost.ll
M llvm/test/Transforms/LoopVectorize/X86/invariant-load-gather.ll
M llvm/test/Transforms/LoopVectorize/X86/invariant-store-vectorization.ll
M llvm/test/Transforms/LoopVectorize/X86/limit-vf-by-tripcount.ll
M llvm/test/Transforms/LoopVectorize/X86/masked-store-cost.ll
M llvm/test/Transforms/LoopVectorize/X86/masked_load_store.ll
M llvm/test/Transforms/LoopVectorize/X86/multi-exit-cost.ll
M llvm/test/Transforms/LoopVectorize/X86/pr23997.ll
M llvm/test/Transforms/LoopVectorize/X86/pr35432.ll
M llvm/test/Transforms/LoopVectorize/X86/pr36524.ll
M llvm/test/Transforms/LoopVectorize/X86/pr47437.ll
M llvm/test/Transforms/LoopVectorize/X86/pr54634.ll
M llvm/test/Transforms/LoopVectorize/X86/pr56319-vector-exit-cond-optimization-epilogue-vectorization.ll
M llvm/test/Transforms/LoopVectorize/X86/pr72969.ll
M llvm/test/Transforms/LoopVectorize/X86/scatter_crash.ll
M llvm/test/Transforms/LoopVectorize/X86/strided_load_cost.ll
M llvm/test/Transforms/LoopVectorize/X86/uniform_mem_op.ll
M llvm/test/Transforms/LoopVectorize/X86/vect.omp.force.small-tc.ll
M llvm/test/Transforms/LoopVectorize/X86/vectorize-force-tail-with-evl.ll
M llvm/test/Transforms/LoopVectorize/dead_instructions.ll
M llvm/test/Transforms/LoopVectorize/epilog-iv-select-cmp.ll
M llvm/test/Transforms/LoopVectorize/epilog-vectorization-any-of-reductions.ll
M llvm/test/Transforms/LoopVectorize/epilog-vectorization-reductions.ll
M llvm/test/Transforms/LoopVectorize/epilog-vectorization-trunc-induction-steps.ll
M llvm/test/Transforms/LoopVectorize/first-order-recurrence-complex.ll
M llvm/test/Transforms/LoopVectorize/fpsat.ll
M llvm/test/Transforms/LoopVectorize/if-conversion-nest.ll
M llvm/test/Transforms/LoopVectorize/if-pred-non-void.ll
M llvm/test/Transforms/LoopVectorize/induction.ll
M llvm/test/Transforms/LoopVectorize/interleaved-accesses-3.ll
M llvm/test/Transforms/LoopVectorize/interleaved-accesses.ll
M llvm/test/Transforms/LoopVectorize/invariant-store-vectorization-2.ll
M llvm/test/Transforms/LoopVectorize/invariant-store-vectorization.ll
M llvm/test/Transforms/LoopVectorize/load-deref-pred-align.ll
M llvm/test/Transforms/LoopVectorize/multiple-strides-vectorization.ll
M llvm/test/Transforms/LoopVectorize/no-fold-tail-by-masking-iv-external-uses.ll
M llvm/test/Transforms/LoopVectorize/no_outside_user.ll
M llvm/test/Transforms/LoopVectorize/opaque-ptr.ll
M llvm/test/Transforms/LoopVectorize/optimal-epilog-vectorization-liveout.ll
M llvm/test/Transforms/LoopVectorize/optimal-epilog-vectorization.ll
M llvm/test/Transforms/LoopVectorize/optsize.ll
M llvm/test/Transforms/LoopVectorize/pointer-select-runtime-checks.ll
M llvm/test/Transforms/LoopVectorize/pr30654-phiscev-sext-trunc.ll
M llvm/test/Transforms/LoopVectorize/pr37248.ll
M llvm/test/Transforms/LoopVectorize/pr45259.ll
M llvm/test/Transforms/LoopVectorize/pr47343-expander-lcssa-after-cfg-update.ll
M llvm/test/Transforms/LoopVectorize/pr50686.ll
M llvm/test/Transforms/LoopVectorize/pr59319-loop-access-info-invalidation.ll
M llvm/test/Transforms/LoopVectorize/reduction-align.ll
M llvm/test/Transforms/LoopVectorize/reverse_induction.ll
M llvm/test/Transforms/LoopVectorize/runtime-check-needed-but-empty.ll
M llvm/test/Transforms/LoopVectorize/runtime-check-small-clamped-bounds.ll
M llvm/test/Transforms/LoopVectorize/runtime-check.ll
M llvm/test/Transforms/LoopVectorize/runtime-checks-difference-simplifications.ll
M llvm/test/Transforms/LoopVectorize/runtime-checks-hoist.ll
M llvm/test/Transforms/LoopVectorize/scev-exit-phi-invalidation.ll
M llvm/test/Transforms/LoopVectorize/scev-predicate-reasoning.ll
M llvm/test/Transforms/LoopVectorize/select-cmp-multiuse.ll
M llvm/test/Transforms/LoopVectorize/single_early_exit.ll
M llvm/test/Transforms/LoopVectorize/skeleton-lcssa-crash.ll
M llvm/test/Transforms/LoopVectorize/version-stride-with-integer-casts.ll
M llvm/test/Transforms/PhaseOrdering/AArch64/indvars-vectorization.ll
M llvm/test/Transforms/PhaseOrdering/AArch64/matrix-extract-insert.ll
M llvm/test/Transforms/PhaseOrdering/X86/pr48844-br-to-switch-vectorization.ll
M llvm/test/Transforms/PhaseOrdering/X86/vdiv.ll
Log Message:
-----------
[VPlan] Remove reverse() of predecessors from VPInstruction::generate.
This was originally done to reduce the diff for the change. Remove it
and update the remaining tests. NFC modulo reordering of incoming
values.
Clean up after https://github.com/llvm/llvm-project/pull/114292.
Commit: 984cb791db347689c4df222e85069ac58929d5ed
https://github.com/llvm/llvm-project/commit/984cb791db347689c4df222e85069ac58929d5ed
Author: Philip Reames <preames at rivosinc.com>
Date: 2024-12-17 (Tue, 17 Dec 2024)
Changed paths:
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/test/CodeGen/RISCV/rvv/vector-deinterleave-load.ll
M llvm/test/CodeGen/RISCV/rvv/vector-deinterleave.ll
Log Message:
-----------
[RISCV] Use vmv.v.x to materialize masks in deinterleave2 lowering (#118500)
This is a follow up to 2af2634 to use vmv.v.x of i8 constants instead of
the prior vid/vand/vmsne sequence. The advantage of the vmv.v.x sequence
is that it's always m1 (so cheaper at high LMUL), and can be
rematerialized by the register allocator if needed to locally reduce
register pressure.
Commit: d7d0e740cc170d471e080fd5bb09633870272073
https://github.com/llvm/llvm-project/commit/d7d0e740cc170d471e080fd5bb09633870272073
Author: Teresa Johnson <tejohnson at google.com>
Date: 2024-12-17 (Tue, 17 Dec 2024)
Changed paths:
M llvm/include/llvm/Analysis/MemoryProfileInfo.h
M llvm/lib/Analysis/MemoryProfileInfo.cpp
M llvm/test/Transforms/PGOProfile/memprof_loop_unroll.ll
Log Message:
-----------
[MemProf] Refactor single alloc type handling and use in more cases (#120290)
Emit message when we have aliased contexts that are conservatively
hinted not cold. This is not a change in behavior, just in message when
the -memprof-report-hinted-sizes flag is enabled.
Commit: bbeafe4b94bb3db89b579d8a6fd914cc96b0af06
https://github.com/llvm/llvm-project/commit/bbeafe4b94bb3db89b579d8a6fd914cc96b0af06
Author: Valentin Clement (バレンタイン クレメン) <clementval at gmail.com>
Date: 2024-12-17 (Tue, 17 Dec 2024)
Changed paths:
M flang/lib/Semantics/resolve-names.cpp
M flang/test/Semantics/cuf09.cuf
Log Message:
-----------
[flang][cuda] Apply implict data attribute to local arrays (#120293)
Add the implicit data attribute to local arrays that don't have one.
This simplifies the host array detection in semantic.
Commit: 48c20e7106bb15398b55a13d0a2ec74cb51d055e
https://github.com/llvm/llvm-project/commit/48c20e7106bb15398b55a13d0a2ec74cb51d055e
Author: Michael Maitland <michaeltmaitland at gmail.com>
Date: 2024-12-17 (Tue, 17 Dec 2024)
Changed paths:
M llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp
Log Message:
-----------
[RISCV][VLOPT] Do not optimize VL when isVectorOpUsedAsScalarOp (#120291)
This does not have tests, so we will remove this for now and add it back
later with tests.
Commit: 7f2fb8061e97ff21caa04b9c44cac2f599202232
https://github.com/llvm/llvm-project/commit/7f2fb8061e97ff21caa04b9c44cac2f599202232
Author: Kazu Hirata <kazu at google.com>
Date: 2024-12-17 (Tue, 17 Dec 2024)
Changed paths:
M llvm/unittests/ProfileData/MemProfTest.cpp
Log Message:
-----------
[memprof] Don't use Frame::hash or hashCallStacks in unit test (#119984)
This patch checks the result of YAML parsing at the level of
MemProfRecord instead of IndexedMemProfRecord, thereby avoiding use of
Frame::hash and hashCallStacks. This makes sense because we
ultimately care about consumers like MemProfiler.cpp obtaining
MemProfRecord correctly; IndexedMemProfData and hash values are just
intermediaries.
Once this patch lands, we call Frame::hash and hashCallStacks only
when adding Frames or call stacks to their respective data structures.
In other words, the hash functions are pretty much business internal
to IndexedMemProfRecord.
Commit: b0fbddde381616d1f0e82899b0fc8c3cf7072c4d
https://github.com/llvm/llvm-project/commit/b0fbddde381616d1f0e82899b0fc8c3cf7072c4d
Author: Joseph Huber <huberjn at outlook.com>
Date: 2024-12-17 (Tue, 17 Dec 2024)
Changed paths:
M offload/DeviceRTL/src/Misc.cpp
Log Message:
-----------
[OpenMP] Only put `retain` for NVPTX so it can be optimized out for AMD
Summary:
This is a hack that only NVPTX needs.
Commit: 169c32eb49fa9b559d388b9b8f4374ff9e1be9be
https://github.com/llvm/llvm-project/commit/169c32eb49fa9b559d388b9b8f4374ff9e1be9be
Author: Michael Maitland <michaeltmaitland at gmail.com>
Date: 2024-12-17 (Tue, 17 Dec 2024)
Changed paths:
M llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
M llvm/test/CodeGen/RISCV/O3-pipeline.ll
M llvm/test/CodeGen/RISCV/rvv/ctlz-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-abs.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-buildvec.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-shuffles.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-changes-length.ll
M llvm/test/CodeGen/RISCV/rvv/setcc-int-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vdiv-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vdivu-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vfma-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vl-opt-op-info.ll
M llvm/test/CodeGen/RISCV/rvv/vl-opt.ll
M llvm/test/CodeGen/RISCV/rvv/vmax-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vmaxu-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vmin-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vminu-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vmul-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vrem-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vremu-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vsadd-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vsaddu-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-crossbb.ll
M llvm/test/CodeGen/RISCV/rvv/vshl-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vsitofp-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vsra-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vsra-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vsrl-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vssub-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vssubu-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vuitofp-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vwsll-vp.ll
M llvm/test/CodeGen/RISCV/srem-seteq-illegal-types.ll
Log Message:
-----------
[RISCV][VLOPT] Enable the RISCVVLOptimizer by default (#119461)
Now that we have testing of all instructions in the isSupportedInstr
switch, and better coverage of getOperandInfo, I think it is a good time
to enable this by default.
Commit: cde996c31d6fb6ae1bbbc79aa71dff2b7fc0a8ae
https://github.com/llvm/llvm-project/commit/cde996c31d6fb6ae1bbbc79aa71dff2b7fc0a8ae
Author: Nico Weber <thakis at chromium.org>
Date: 2024-12-17 (Tue, 17 Dec 2024)
Changed paths:
M lld/COFF/SymbolTable.cpp
Log Message:
-----------
[lld/COFF] Remove needless indirection
`symtab.ctx.symtab` is just `symtab`. Looks like #119296 added
this using a global find-and-replace.
This was the only instance of `symtab.ctx.symtab` in lld/.
No behavior change.
Commit: 1d06157b9ea4bc76eff0ae670e8d3411eaaa6e42
https://github.com/llvm/llvm-project/commit/1d06157b9ea4bc76eff0ae670e8d3411eaaa6e42
Author: Nick Desaulniers <nickdesaulniers at users.noreply.github.com>
Date: 2024-12-17 (Tue, 17 Dec 2024)
Changed paths:
M libc/test/include/stdbit_stub.h
Log Message:
-----------
[libc] fix -Wgcc-compat (#120303)
I don't quite recall why I added those in the first place. These tests build
without diagnostics for both clang and GCC with this fix.
Fixes: #114653
Commit: 958de20b30e73d898cf538435da5bab42ffd4987
https://github.com/llvm/llvm-project/commit/958de20b30e73d898cf538435da5bab42ffd4987
Author: Joseph Huber <huberjn at outlook.com>
Date: 2024-12-17 (Tue, 17 Dec 2024)
Changed paths:
M libc/config/gpu/entrypoints.txt
M libc/src/__support/time/gpu/time_utils.h
M libc/src/time/gpu/nanosleep.cpp
M libc/src/time/gpu/timespec_get.cpp
Log Message:
-----------
[libc] Enable 'timespec_get' for the GPU build (#120304)
Summary:
Currently fails to build libc++ because this is missing.
Commit: eb59fe8d04a594da4ac0cdba2bb2ca828adcf833
https://github.com/llvm/llvm-project/commit/eb59fe8d04a594da4ac0cdba2bb2ca828adcf833
Author: Florian Hahn <flo at fhahn.com>
Date: 2024-12-17 (Tue, 17 Dec 2024)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
Log Message:
-----------
[VPlan] Remove redundant assignment in VPReductionPHIRecipe (NFC)
Suggested post-commit for 0e528ac404e13ed2d952a2d83aaf8383293c851e.
Commit: 97b7bace67c4fb7d62892f5bc6d7614a65d0fb3e
https://github.com/llvm/llvm-project/commit/97b7bace67c4fb7d62892f5bc6d7614a65d0fb3e
Author: Valentin Clement (バレンタイン クレメン) <clementval at gmail.com>
Date: 2024-12-17 (Tue, 17 Dec 2024)
Changed paths:
M flang/lib/Semantics/check-cuda.cpp
M flang/test/Semantics/cuf09.cuf
Log Message:
-----------
[flang][cuda] Allow host array with PARAMETER attribute in device context (#120298)
Host arrays are normally not allowed in device context unless they have
a `PARAMETER` attribute. This patch update the check so no error is
emitted.
Commit: 15c61a208ffdd0bfe6add667cf9e56df1fdbf16e
https://github.com/llvm/llvm-project/commit/15c61a208ffdd0bfe6add667cf9e56df1fdbf16e
Author: Valentin Clement (バレンタイン クレメン) <clementval at gmail.com>
Date: 2024-12-17 (Tue, 17 Dec 2024)
Changed paths:
M flang/lib/Semantics/check-cuda.cpp
M flang/test/Semantics/cuf09.cuf
Log Message:
-----------
[flang][cuda] Do not consider SHARED array as host array (#120306)
Update the current `FindHostArray` to not return shared array as host
array.
Commit: 9f231a85004fad080980e80ef881c81d1d5bb60e
https://github.com/llvm/llvm-project/commit/9f231a85004fad080980e80ef881c81d1d5bb60e
Author: Alex MacLean <amaclean at nvidia.com>
Date: 2024-12-17 (Tue, 17 Dec 2024)
Changed paths:
M llvm/lib/Target/NVPTX/NVPTXInstrInfo.td
M llvm/lib/Target/NVPTX/NVPTXIntrinsics.td
Log Message:
-----------
[NVPTX] Prefer ValueType when defining DAG patterns (NFC) (#120161)
Replace uses of register class in dag patterns with value types. These
types are much more concise and in cases where a single register class
maps to multiple types, they avoid the need for both.
Commit: 7153a21916fa985dfba604c0edf04a8d3c44b389
https://github.com/llvm/llvm-project/commit/7153a21916fa985dfba604c0edf04a8d3c44b389
Author: Nick Desaulniers <nickdesaulniers at users.noreply.github.com>
Date: 2024-12-17 (Tue, 17 Dec 2024)
Changed paths:
M llvm/docs/requirements-hashed.txt
Log Message:
-----------
[libc][docs] update sphinx requirement hashes (#120315)
Link: #120274
Commit: 65d2177ae1d7b891a5bd939aa30f922ceae57da9
https://github.com/llvm/llvm-project/commit/65d2177ae1d7b891a5bd939aa30f922ceae57da9
Author: Justin Bogner <mail at justinbogner.com>
Date: 2024-12-17 (Tue, 17 Dec 2024)
Changed paths:
M llvm/unittests/Analysis/DXILResourceTest.cpp
Log Message:
-----------
[DXIL] Simplify MDBuilder in resource unit tests. NFC (#120275)
Commit: c03fc929ffc1ee5439bf547e5f0bf5319c818982
https://github.com/llvm/llvm-project/commit/c03fc929ffc1ee5439bf547e5f0bf5319c818982
Author: Farzon Lotfi <farzonlotfi at microsoft.com>
Date: 2024-12-17 (Tue, 17 Dec 2024)
Changed paths:
M llvm/lib/Target/DirectX/DXILIntrinsicExpansion.cpp
A llvm/test/CodeGen/DirectX/vector_reduce_add.ll
Log Message:
-----------
[DirectX] Add support for vector_reduce_add (#117646)
Use of `vector_reduce_add` will make it easier to write more intrinsics
in `hlsl_intrinsics.h`.
Commit: 09f449263e6e9b0e7ba9f972f73734b08575b172
https://github.com/llvm/llvm-project/commit/09f449263e6e9b0e7ba9f972f73734b08575b172
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-12-17 (Tue, 17 Dec 2024)
Changed paths:
M llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
Log Message:
-----------
[RISCV] Check for register where immediate should be in RISCVInstrInfo::verifyInstruction. (#120286)
The generic verifier will do this if the operand type is
OPERAND_IMMEDIATE, but we use our own custom operand types. Immediate
operands are still allowed to be globals, constant pools, blockaddress,
etc. so we can't check !isImm().
Commit: bb4007e56274d70ed3a8367eb245bec7d80b9fac
https://github.com/llvm/llvm-project/commit/bb4007e56274d70ed3a8367eb245bec7d80b9fac
Author: alx32 <103613512+alx32 at users.noreply.github.com>
Date: 2024-12-17 (Tue, 17 Dec 2024)
Changed paths:
M llvm/test/tools/llvm-dwarfdump/X86/verify_no_overlap_error_icf.yaml
Log Message:
-----------
[DWARFVerifier] Disable failing test llvm/include/llvm/DebugInfo/DWARF/DWARFVerifier.h (#120322)
Disabling and forward fixing later.
Commit: 8a62104f642e469e62aa839cc25c31adf2fa5805
https://github.com/llvm/llvm-project/commit/8a62104f642e469e62aa839cc25c31adf2fa5805
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2024-12-17 (Tue, 17 Dec 2024)
Changed paths:
M .github/workflows/docs.yml
Log Message:
-----------
[Github] Use hashed dependencies in docs job (#120319)
This patch forces the docs test build job to use the hashed dpendencies
file rather than the normal requirements.txt. This ensures that we get
the exact transitive closure specified rather than whatever the
dependency solver feels like it should use in the CI job.
Commit: 932d9c13faa3de1deca3874d3b864901aa5ec9a5
https://github.com/llvm/llvm-project/commit/932d9c13faa3de1deca3874d3b864901aa5ec9a5
Author: Drew Kersnar <dakersnar at me.com>
Date: 2024-12-17 (Tue, 17 Dec 2024)
Changed paths:
M llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp
M llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp
M llvm/test/CodeGen/NVPTX/LoadStoreVectorizer.ll
M llvm/test/CodeGen/NVPTX/i8x4-instructions.ll
M llvm/test/CodeGen/NVPTX/ldg-invariant.ll
A llvm/test/CodeGen/NVPTX/load-store-scalars.ll
A llvm/test/CodeGen/NVPTX/load-store-vectors.ll
R llvm/test/CodeGen/NVPTX/load-store.ll
M llvm/test/CodeGen/NVPTX/shuffle-vec-undef-init.ll
M llvm/test/CodeGen/NVPTX/vector-stores.ll
Log Message:
-----------
[NVPTX] Generalize and extend upsizing when lowering 8/16-bit-element vector loads/stores (#119622)
This addresses the following issue I opened:
https://github.com/llvm/llvm-project/issues/118851.
This change generalizes the Type Legalization mechanism that currently
handles `v8[i/f/bf]16` upsizing to include loads _and_ stores of `v8i8`
+ `v16i8`, allowing all of the mentioned vectors to be lowered to ptx as
vectors of `b32`. This extension also allows us to remove the DagCombine
that only handled exactly `load v16i8`, thus centralizing all the
upsizing logic into one place.
Test changes include adding v8i8, v16i8, and v8i16 cases to
load-store.ll, and updating the CHECKs for other tests to match the
improved codegen.
Commit: f3a8f879795fcc515f86793c18b366c8ece1a8db
https://github.com/llvm/llvm-project/commit/f3a8f879795fcc515f86793c18b366c8ece1a8db
Author: Jie Fu <jiefu at tencent.com>
Date: 2024-12-18 (Wed, 18 Dec 2024)
Changed paths:
M llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp
Log Message:
-----------
[NVPTX] Remove extra ';' outside of a function (NFC)
/llvm-project/llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp:224:2:
error: extra ';' outside of a function is incompatible with C++98 [-Werror,-Wc++98-compat-extra-semi]
};
^
1 error generated.
Commit: a15e7b11da701a5810cc8cd67b393021b0f2ef0c
https://github.com/llvm/llvm-project/commit/a15e7b11da701a5810cc8cd67b393021b0f2ef0c
Author: Teresa Johnson <tejohnson at google.com>
Date: 2024-12-17 (Tue, 17 Dec 2024)
Changed paths:
M llvm/lib/Transforms/Instrumentation/MemProfiler.cpp
M llvm/test/Transforms/PGOProfile/memprof.ll
Log Message:
-----------
[MemProf] Add option to hint allocations at a given cold byte percentage (#120301)
Optionally unconditionally hint allocations as cold or not cold during
the matching step if the percentage of bytes allocated is at least that
of the given threshold.
Commit: f8d9f8ed9524ef01aeedca7833001efabc6cd223
https://github.com/llvm/llvm-project/commit/f8d9f8ed9524ef01aeedca7833001efabc6cd223
Author: Paul Kirth <paulkirth at google.com>
Date: 2024-12-17 (Tue, 17 Dec 2024)
Changed paths:
A clang-tools-extra/test/clang-doc/builtin_types.cpp
Log Message:
-----------
[clang-doc] Add test for functions with builtin return types (#120318)
This is a precommit test for #120308, since we lack non-template
functions that use builtin types.
Commit: 09e0dcbb5fe87dd83781d45a0b1bd027172f69ef
https://github.com/llvm/llvm-project/commit/09e0dcbb5fe87dd83781d45a0b1bd027172f69ef
Author: Paul Kirth <paulkirth at google.com>
Date: 2024-12-17 (Tue, 17 Dec 2024)
Changed paths:
M .ci/monolithic-linux.sh
M .ci/monolithic-windows.sh
M .git-blame-ignore-revs
M .github/new-prs-labeler.yml
M .github/workflows/build-ci-container-windows.yml
M .github/workflows/build-ci-container.yml
M .github/workflows/containers/github-action-ci/Dockerfile
M .github/workflows/docs.yml
A .github/workflows/premerge.yaml
M bolt/docs/CommandLineArgumentReference.md
M bolt/include/bolt/Core/BinaryFunction.h
M bolt/include/bolt/Passes/ADRRelaxationPass.h
M bolt/include/bolt/Passes/IdenticalCodeFolding.h
M bolt/lib/Core/BinaryEmitter.cpp
M bolt/lib/Core/BinaryFunction.cpp
M bolt/lib/Core/DebugNames.cpp
M bolt/lib/Passes/IdenticalCodeFolding.cpp
M bolt/lib/Passes/LongJmp.cpp
M bolt/lib/Rewrite/BinaryPassManager.cpp
M bolt/lib/Rewrite/BoltDiff.cpp
M bolt/lib/Rewrite/RewriteInstance.cpp
A bolt/test/AArch64/long-jmp-one-stub.s
A bolt/test/X86/dwarf5-debug-names-gnu-push-tls-address.s
A bolt/test/X86/icf-safe-icp.test
A bolt/test/X86/icf-safe-process-rela-data.test
A bolt/test/X86/icf-safe-test1-no-relocs.test
A bolt/test/X86/icf-safe-test1.test
A bolt/test/X86/icf-safe-test2GlobalConstPtrNoPic.test
M bolt/test/X86/linux-static-keys.s
M bolt/test/merge-fdata-lbr-mode.test
M bolt/test/merge-fdata-mixed-bat-no-lbr.test
M bolt/test/merge-fdata-mixed-mode.test
M bolt/tools/merge-fdata/merge-fdata.cpp
M clang-tools-extra/clang-tidy/bugprone/UncheckedOptionalAccessCheck.h
M clang-tools-extra/clang-tidy/cppcoreguidelines/ProTypeMemberInitCheck.cpp
M clang-tools-extra/clang-tidy/cppcoreguidelines/RvalueReferenceParamNotMovedCheck.cpp
M clang-tools-extra/clang-tidy/performance/InefficientVectorOperationCheck.cpp
M clang-tools-extra/clang-tidy/readability/RedundantAccessSpecifiersCheck.h
M clang-tools-extra/clang-tidy/readability/RedundantCastingCheck.cpp
M clang-tools-extra/clang-tidy/utils/RenamerClangTidyCheck.cpp
M clang-tools-extra/clangd/index/SymbolCollector.cpp
M clang-tools-extra/clangd/unittests/SymbolCollectorTests.cpp
M clang-tools-extra/docs/clang-tidy/index.rst
M clang/CMakeLists.txt
M clang/cmake/caches/Fuchsia-stage2.cmake
M clang/docs/MatrixTypes.rst
M clang/docs/ReleaseNotes.rst
M clang/include/clang/AST/OpenACCClause.h
M clang/include/clang/AST/StmtOpenACC.h
M clang/include/clang/Basic/Builtins.h
M clang/include/clang/Basic/Builtins.td
M clang/include/clang/Basic/BuiltinsPPC.def
M clang/include/clang/Basic/DiagnosticSemaKinds.td
M clang/include/clang/Basic/Features.def
M clang/include/clang/Basic/OpenACCClauses.def
M clang/include/clang/Basic/Sanitizers.def
M clang/include/clang/Basic/TargetInfo.h
M clang/include/clang/Basic/arm_sme.td
M clang/include/clang/Basic/arm_sve.td
M clang/include/clang/Driver/Options.td
M clang/include/clang/Driver/SanitizerArgs.h
M clang/include/clang/Sema/SemaOpenACC.h
M clang/include/clang/Serialization/ASTBitCodes.h
M clang/include/clang/Serialization/ASTReader.h
M clang/include/clang/Serialization/ASTWriter.h
M clang/lib/AST/ByteCode/Compiler.cpp
M clang/lib/AST/ByteCode/Integral.h
M clang/lib/AST/ByteCode/Interp.h
M clang/lib/AST/ByteCode/InterpBuiltin.cpp
M clang/lib/AST/ByteCode/Opcodes.td
M clang/lib/AST/OpenACCClause.cpp
M clang/lib/AST/StmtProfile.cpp
M clang/lib/AST/TextNodeDumper.cpp
M clang/lib/Analysis/ThreadSafetyCommon.cpp
M clang/lib/Basic/Builtins.cpp
M clang/lib/Basic/Targets/AArch64.cpp
M clang/lib/Basic/Targets/AArch64.h
M clang/lib/Basic/Targets/AMDGPU.cpp
M clang/lib/Basic/Targets/AMDGPU.h
M clang/lib/Basic/Targets/ARC.h
M clang/lib/Basic/Targets/ARM.cpp
M clang/lib/Basic/Targets/ARM.h
M clang/lib/Basic/Targets/AVR.h
M clang/lib/Basic/Targets/BPF.cpp
M clang/lib/Basic/Targets/BPF.h
M clang/lib/Basic/Targets/CSKY.cpp
M clang/lib/Basic/Targets/CSKY.h
M clang/lib/Basic/Targets/DirectX.h
M clang/lib/Basic/Targets/Hexagon.cpp
M clang/lib/Basic/Targets/Hexagon.h
M clang/lib/Basic/Targets/Lanai.h
M clang/lib/Basic/Targets/LoongArch.cpp
M clang/lib/Basic/Targets/LoongArch.h
M clang/lib/Basic/Targets/M68k.cpp
M clang/lib/Basic/Targets/M68k.h
M clang/lib/Basic/Targets/MSP430.h
M clang/lib/Basic/Targets/Mips.cpp
M clang/lib/Basic/Targets/Mips.h
M clang/lib/Basic/Targets/NVPTX.cpp
M clang/lib/Basic/Targets/NVPTX.h
M clang/lib/Basic/Targets/PNaCl.h
M clang/lib/Basic/Targets/PPC.cpp
M clang/lib/Basic/Targets/PPC.h
M clang/lib/Basic/Targets/RISCV.cpp
M clang/lib/Basic/Targets/RISCV.h
M clang/lib/Basic/Targets/SPIR.cpp
M clang/lib/Basic/Targets/SPIR.h
M clang/lib/Basic/Targets/Sparc.h
M clang/lib/Basic/Targets/SystemZ.cpp
M clang/lib/Basic/Targets/SystemZ.h
M clang/lib/Basic/Targets/TCE.h
M clang/lib/Basic/Targets/VE.cpp
M clang/lib/Basic/Targets/VE.h
M clang/lib/Basic/Targets/WebAssembly.cpp
M clang/lib/Basic/Targets/WebAssembly.h
M clang/lib/Basic/Targets/X86.cpp
M clang/lib/Basic/Targets/X86.h
M clang/lib/Basic/Targets/XCore.cpp
M clang/lib/Basic/Targets/XCore.h
M clang/lib/CodeGen/BackendUtil.cpp
M clang/lib/CodeGen/CGBuiltin.cpp
M clang/lib/CodeGen/CGDebugInfo.cpp
M clang/lib/CodeGen/CGDeclCXX.cpp
M clang/lib/CodeGen/CGHLSLRuntime.cpp
M clang/lib/CodeGen/CGHLSLRuntime.h
M clang/lib/CodeGen/CodeGenFunction.cpp
M clang/lib/CodeGen/CodeGenModule.cpp
M clang/lib/CodeGen/CodeGenTBAA.cpp
M clang/lib/CodeGen/ItaniumCXXABI.cpp
M clang/lib/CodeGen/SanitizerMetadata.cpp
M clang/lib/Driver/SanitizerArgs.cpp
M clang/lib/Driver/ToolChains/CommonArgs.cpp
M clang/lib/Driver/ToolChains/CommonArgs.h
M clang/lib/Driver/ToolChains/Darwin.cpp
M clang/lib/Driver/ToolChains/Flang.cpp
M clang/lib/Driver/ToolChains/FreeBSD.cpp
M clang/lib/Driver/ToolChains/Fuchsia.cpp
M clang/lib/Driver/ToolChains/Gnu.cpp
M clang/lib/Driver/ToolChains/Hexagon.cpp
M clang/lib/Driver/ToolChains/Linux.cpp
M clang/lib/Driver/ToolChains/NetBSD.cpp
M clang/lib/Driver/ToolChains/OHOS.cpp
M clang/lib/Driver/ToolChains/OpenBSD.cpp
M clang/lib/Driver/ToolChains/Solaris.cpp
M clang/lib/ExtractAPI/Serialization/SymbolGraphSerializer.cpp
M clang/lib/Format/ContinuationIndenter.cpp
M clang/lib/Frontend/CompilerInvocation.cpp
M clang/lib/Headers/hlsl/hlsl_intrinsics.h
M clang/lib/Interpreter/Interpreter.cpp
M clang/lib/Parse/ParseOpenACC.cpp
M clang/lib/Sema/HLSLExternalSemaSource.cpp
M clang/lib/Sema/SemaExprCXX.cpp
M clang/lib/Sema/SemaOpenACC.cpp
M clang/lib/Sema/SemaStmtAsm.cpp
M clang/lib/Sema/SemaTemplateInstantiateDecl.cpp
M clang/lib/Sema/SemaType.cpp
M clang/lib/Sema/TreeTransform.h
M clang/lib/Serialization/ASTReader.cpp
M clang/lib/Serialization/ASTReaderDecl.cpp
M clang/lib/Serialization/ASTWriter.cpp
M clang/lib/Serialization/ASTWriterDecl.cpp
M clang/lib/StaticAnalyzer/Checkers/WebKit/UncountedLambdaCapturesChecker.cpp
M clang/lib/Tooling/Inclusions/Stdlib/StdSpecialSymbolMap.inc
M clang/lib/Tooling/Inclusions/Stdlib/StdSymbolMap.inc
M clang/runtime/CMakeLists.txt
M clang/test/AST/ByteCode/builtin-bit-cast.cpp
M clang/test/AST/ByteCode/builtin-functions.cpp
M clang/test/AST/ByteCode/functions.cpp
M clang/test/AST/ByteCode/shifts.cpp
M clang/test/AST/HLSL/TypedBuffers-AST.hlsl
M clang/test/AST/ast-print-openacc-data-construct.cpp
M clang/test/Analysis/Checkers/WebKit/uncounted-lambda-captures.cpp
A clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_mla.c
A clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_fmla.c
M clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_fp8_fdot.c
A clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_fp8_fvdot.c
M clang/test/CodeGen/memtag-globals.cpp
M clang/test/CodeGen/ptrauth-module-flags.c
A clang/test/CodeGen/sanitize-type-attr.cpp
M clang/test/CodeGenCXX/matrix-type.cpp
A clang/test/CodeGenCXX/matrix-vector-bit-int.cpp
A clang/test/CodeGenHLSL/builtins/RWBuffer-constructor-opt.hlsl
M clang/test/CodeGenHLSL/builtins/RWBuffer-subscript.hlsl
A clang/test/CodeGenHLSL/builtins/WaveActiveAllTrue.hlsl
M clang/test/CodeGenOpenCL/opencl_types.cl
M clang/test/Driver/print-enabled-extensions/riscv-rocket-rv64.c
M clang/test/Driver/print-supported-extensions-riscv.c
M clang/test/Driver/riscv-cpus.c
M clang/test/Driver/sanitizer-ld.c
A clang/test/Driver/unknown-arg-drivermodes.test
M clang/test/ExtractAPI/objc_external_category.m
M clang/test/Format/lit.local.cfg
A clang/test/Headers/crash-instantiated-in-scope-cxx-modules4.cpp
R clang/test/Interpreter/crash.cpp
M clang/test/Misc/target-invalid-cpu-note/riscv.c
M clang/test/Modules/ExtDebugInfo.m
M clang/test/Modules/ModuleDebugInfo.m
A clang/test/Modules/friend-inline-function-body.cpp
A clang/test/OpenMP/amdgpu_threadprivate.cpp
M clang/test/ParserOpenACC/parse-clauses.c
M clang/test/ParserOpenACC/parse-clauses.cpp
M clang/test/ParserOpenACC/parse-constructs.c
M clang/test/Preprocessor/predefined-arch-macros.c
M clang/test/Sema/aarch64-fp8-intrinsics/acle_sme2_fp8_imm.c
A clang/test/Sema/aarch64-fp8-intrinsics/acle_sme2_fp8_mla.c
M clang/test/Sema/aarch64-sme2-intrinsics/acle_sme2_fp8_fdot.c
A clang/test/Sema/aarch64-sme2-intrinsics/acle_sme2_fp8_fvdot.c
M clang/test/Sema/aarch64-sve2-intrinsics/acle_sve2_fp8.c
M clang/test/Sema/asm.c
M clang/test/SemaCXX/matrix-type.cpp
A clang/test/SemaCXX/matrix-types-pseudo-destructor.cpp
M clang/test/SemaCXX/msvc-pragma-function-no-builtin-attr.cpp
M clang/test/SemaCXX/warn-thread-safety-analysis.cpp
A clang/test/SemaHLSL/BuiltIns/WaveActiveAllTrue-errors.hlsl
M clang/test/SemaOpenACC/combined-construct-auto_seq_independent-clauses.c
M clang/test/SemaOpenACC/combined-construct-collapse-clause.cpp
M clang/test/SemaOpenACC/combined-construct-device_type-clause.c
M clang/test/SemaOpenACC/combined-construct-if-clause.c
M clang/test/SemaOpenACC/compute-construct-device_type-clause.c
M clang/test/SemaOpenACC/compute-construct-if-clause.c
M clang/test/SemaOpenACC/data-construct-ast.cpp
M clang/test/SemaOpenACC/data-construct-async-ast.cpp
M clang/test/SemaOpenACC/data-construct-async-clause.c
M clang/test/SemaOpenACC/data-construct-attach-clause.c
M clang/test/SemaOpenACC/data-construct-copy-clause.c
M clang/test/SemaOpenACC/data-construct-copyin-clause.c
M clang/test/SemaOpenACC/data-construct-copyout-clause.c
M clang/test/SemaOpenACC/data-construct-create-clause.c
M clang/test/SemaOpenACC/data-construct-default-clause.c
A clang/test/SemaOpenACC/data-construct-delete-ast.cpp
A clang/test/SemaOpenACC/data-construct-delete-clause.c
A clang/test/SemaOpenACC/data-construct-detach-ast.cpp
A clang/test/SemaOpenACC/data-construct-detach-clause.c
M clang/test/SemaOpenACC/data-construct-device_type-ast.cpp
M clang/test/SemaOpenACC/data-construct-device_type-clause.c
M clang/test/SemaOpenACC/data-construct-deviceptr-clause.c
A clang/test/SemaOpenACC/data-construct-finalize-ast.cpp
A clang/test/SemaOpenACC/data-construct-finalize-clause.c
M clang/test/SemaOpenACC/data-construct-if-ast.cpp
M clang/test/SemaOpenACC/data-construct-if-clause.c
A clang/test/SemaOpenACC/data-construct-if_present-ast.cpp
A clang/test/SemaOpenACC/data-construct-if_present-clause.c
M clang/test/SemaOpenACC/data-construct-no_create-clause.c
M clang/test/SemaOpenACC/data-construct-present-clause.c
A clang/test/SemaOpenACC/data-construct-use_device-ast.cpp
A clang/test/SemaOpenACC/data-construct-use_device-clause.c
M clang/test/SemaOpenACC/data-construct-wait-clause.c
M clang/test/SemaOpenACC/data-construct.cpp
M clang/test/SemaOpenACC/loop-construct-auto_seq_independent-clauses.c
M clang/test/SemaOpenACC/loop-construct-collapse-clause.cpp
M clang/test/SemaOpenACC/loop-construct-device_type-clause.c
M clang/tools/clang-linker-wrapper/ClangLinkerWrapper.cpp
M clang/tools/libclang/CIndex.cpp
M clang/unittests/AST/ASTImporterTest.cpp
M clang/unittests/Format/FormatTestJS.cpp
M compiler-rt/cmake/Modules/AllSupportedArchDefs.cmake
M compiler-rt/cmake/Modules/CompilerRTAIXUtils.cmake
M compiler-rt/cmake/Modules/CompilerRTDarwinUtils.cmake
M compiler-rt/cmake/config-ix.cmake
M compiler-rt/lib/builtins/aarch64/sme-abi.S
M compiler-rt/lib/builtins/aarch64/sme-libc-mem-routines.S
M compiler-rt/lib/builtins/fp_div_impl.inc
M compiler-rt/lib/msan/msan_interceptors.cpp
M compiler-rt/lib/orc/CMakeLists.txt
A compiler-rt/lib/orc/sysv_reenter.x86-64.S
M compiler-rt/lib/sanitizer_common/sanitizer_common_interceptors.inc
M compiler-rt/lib/sanitizer_common/sanitizer_platform_interceptors.h
A compiler-rt/lib/tysan/CMakeLists.txt
A compiler-rt/lib/tysan/lit.cfg
A compiler-rt/lib/tysan/lit.site.cfg.in
A compiler-rt/lib/tysan/tysan.cpp
A compiler-rt/lib/tysan/tysan.h
A compiler-rt/lib/tysan/tysan.syms.extra
A compiler-rt/lib/tysan/tysan_flags.inc
A compiler-rt/lib/tysan/tysan_interceptors.cpp
A compiler-rt/lib/tysan/tysan_platform.h
M compiler-rt/lib/ubsan_minimal/ubsan_minimal_handlers.cpp
M compiler-rt/test/builtins/Unit/divdf3_test.c
M compiler-rt/test/builtins/Unit/divsf3_test.c
M compiler-rt/test/builtins/Unit/divtf3_test.c
R compiler-rt/test/msan/Linux/dn_expand.cpp
M compiler-rt/test/orc/TestCases/Generic/lazy-link.ll
A compiler-rt/test/sanitizer_common/TestCases/Linux/b64.cpp
A compiler-rt/test/sanitizer_common/TestCases/Linux/dn_expand.cpp
A compiler-rt/test/tysan/CMakeLists.txt
A compiler-rt/test/tysan/anon-ns.cpp
A compiler-rt/test/tysan/anon-same-struct.c
A compiler-rt/test/tysan/anon-struct.c
A compiler-rt/test/tysan/basic.c
A compiler-rt/test/tysan/char-memcpy.c
A compiler-rt/test/tysan/constexpr-subobject.cpp
A compiler-rt/test/tysan/global.c
A compiler-rt/test/tysan/int-long.c
A compiler-rt/test/tysan/lit.cfg.py
A compiler-rt/test/tysan/lit.site.cfg.py.in
A compiler-rt/test/tysan/ptr-float.c
A compiler-rt/test/tysan/struct-offset-multiple-compilation-units.cpp
A compiler-rt/test/tysan/struct-offset.c
A compiler-rt/test/tysan/struct.c
A compiler-rt/test/tysan/union-wr-wr.c
A compiler-rt/test/tysan/violation-pr45282.c
A compiler-rt/test/tysan/violation-pr47137.c
A compiler-rt/test/tysan/violation-pr51837.c
A compiler-rt/test/tysan/violation-pr62544.c
A compiler-rt/test/tysan/violation-pr62828.cpp
A compiler-rt/test/tysan/violation-pr68655.cpp
A compiler-rt/test/tysan/violation-pr86685.c
A compiler-rt/test/ubsan_minimal/TestCases/override-callback.c
M flang/CMakeLists.txt
M flang/include/flang/Lower/LoweringOptions.def
M flang/include/flang/Optimizer/Builder/HLFIRTools.h
M flang/include/flang/Parser/parse-tree.h
M flang/lib/Evaluate/tools.cpp
M flang/lib/Frontend/CompilerInvocation.cpp
M flang/lib/Lower/Bridge.cpp
M flang/lib/Optimizer/Builder/HLFIRTools.cpp
M flang/lib/Optimizer/CodeGen/CodeGen.cpp
M flang/lib/Optimizer/CodeGen/TargetRewrite.cpp
M flang/lib/Optimizer/HLFIR/Transforms/OptimizedBufferization.cpp
M flang/lib/Optimizer/HLFIR/Transforms/SimplifyHLFIRIntrinsics.cpp
M flang/lib/Parser/Fortran-parsers.cpp
M flang/lib/Parser/expr-parsers.cpp
M flang/lib/Parser/parsing.cpp
M flang/lib/Parser/type-parsers.h
M flang/lib/Semantics/check-cuda.cpp
M flang/lib/Semantics/expression.cpp
M flang/lib/Semantics/resolve-names.cpp
A flang/test/Driver/frealloc-lhs.f90
A flang/test/Fir/CUDA/cuda-code-gen.mlir
M flang/test/Fir/CUDA/cuda-target-rewrite.mlir
M flang/test/HLFIR/opt-array-slice-assign.fir
M flang/test/HLFIR/simplify-hlfir-intrinsics-cshift.fir
M flang/test/HLFIR/simplify-hlfir-intrinsics-sum.fir
M flang/test/HLFIR/simplify-hlfir-intrinsics.fir
M flang/test/Lower/CUDA/cuda-program-global.cuf
A flang/test/Lower/reallocate-lhs.f90
A flang/test/Parser/lit-substr-data.f90
M flang/test/Preprocessing/pp132.f90
M flang/test/Semantics/cuf09.cuf
A flang/test/Semantics/generic11.f90
M flang/test/Semantics/modfile55.cuf
M flang/tools/bbc/bbc.cpp
M libc/CMakeLists.txt
M libc/config/baremetal/aarch64/entrypoints.txt
M libc/config/baremetal/arm/entrypoints.txt
M libc/config/baremetal/riscv/entrypoints.txt
M libc/config/gpu/entrypoints.txt
M libc/config/linux/aarch64/entrypoints.txt
M libc/config/linux/arm/entrypoints.txt
M libc/config/linux/riscv/entrypoints.txt
M libc/config/linux/x86_64/entrypoints.txt
A libc/docs/arch_support.rst
M libc/docs/conf.py
M libc/docs/gpu/rpc.rst
M libc/docs/gpu/using.rst
M libc/docs/headers/complex.rst
M libc/docs/headers/math/index.rst
M libc/docs/index.rst
A libc/docs/platform_support.rst
M libc/docs/talks.rst
M libc/fuzzing/__support/CMakeLists.txt
A libc/fuzzing/__support/fake_heap.s
M libc/hdr/CMakeLists.txt
M libc/hdr/types/CMakeLists.txt
M libc/hdr/types/ssize_t.h
A libc/hdr/types/uid_t.h
M libc/hdr/unistd_macros.h
A libc/hdr/unistd_overlay.h
M libc/hdrgen/yaml/complex.yaml
M libc/hdrgen/yaml/math.yaml
M libc/include/__llvm-libc-common.h
M libc/shared/rpc.h
M libc/shared/rpc_util.h
M libc/src/__support/CMakeLists.txt
M libc/src/__support/CPP/atomic.h
M libc/src/__support/CPP/type_traits.h
A libc/src/__support/CPP/type_traits/has_unique_object_representations.h
M libc/src/__support/complex_type.h
A libc/src/__support/freelist_heap.cpp
M libc/src/__support/time/gpu/time_utils.h
M libc/src/complex/CMakeLists.txt
M libc/src/complex/conjf128.h
M libc/src/complex/conjf16.h
A libc/src/complex/cproj.h
A libc/src/complex/cprojf.h
A libc/src/complex/cprojf128.h
A libc/src/complex/cprojf16.h
A libc/src/complex/cprojl.h
M libc/src/complex/generic/CMakeLists.txt
M libc/src/complex/generic/conj.cpp
M libc/src/complex/generic/conjf.cpp
M libc/src/complex/generic/conjf128.cpp
M libc/src/complex/generic/conjf16.cpp
M libc/src/complex/generic/conjl.cpp
A libc/src/complex/generic/cproj.cpp
A libc/src/complex/generic/cprojf.cpp
A libc/src/complex/generic/cprojf128.cpp
A libc/src/complex/generic/cprojf16.cpp
A libc/src/complex/generic/cprojl.cpp
M libc/src/math/CMakeLists.txt
A libc/src/math/cosf16.h
M libc/src/math/generic/CMakeLists.txt
A libc/src/math/generic/cosf16.cpp
M libc/src/math/generic/cospif16.cpp
M libc/src/math/generic/sinf16.cpp
M libc/src/stdlib/CMakeLists.txt
M libc/src/stdlib/baremetal/CMakeLists.txt
A libc/src/stdlib/baremetal/aligned_alloc.cpp
A libc/src/stdlib/baremetal/calloc.cpp
A libc/src/stdlib/baremetal/free.cpp
A libc/src/stdlib/baremetal/malloc.cpp
A libc/src/stdlib/baremetal/realloc.cpp
R libc/src/stdlib/freelist_malloc.cpp
M libc/src/time/gpu/nanosleep.cpp
M libc/src/time/gpu/timespec_get.cpp
M libc/src/unistd/dup.h
M libc/src/unistd/dup2.h
M libc/src/unistd/dup3.h
M libc/src/unistd/fork.h
M libc/src/unistd/ftruncate.h
M libc/src/unistd/getcwd.h
M libc/src/unistd/geteuid.h
M libc/src/unistd/getopt.h
M libc/src/unistd/getpid.h
M libc/src/unistd/getppid.h
M libc/src/unistd/getuid.h
M libc/src/unistd/isatty.h
M libc/src/unistd/link.h
M libc/src/unistd/linux/CMakeLists.txt
M libc/src/unistd/linux/ftruncate.cpp
M libc/src/unistd/linux/lseek.cpp
M libc/src/unistd/linux/sysconf.cpp
M libc/src/unistd/linux/truncate.cpp
M libc/src/unistd/lseek.h
M libc/src/unistd/pread.h
M libc/src/unistd/pwrite.h
M libc/src/unistd/read.h
M libc/src/unistd/readlink.h
M libc/src/unistd/readlinkat.h
M libc/src/unistd/swab.h
M libc/src/unistd/symlink.h
M libc/src/unistd/symlinkat.h
M libc/src/unistd/syscall.h
M libc/src/unistd/sysconf.h
M libc/src/unistd/truncate.h
M libc/src/unistd/write.h
M libc/test/include/stdbit_stub.h
M libc/test/src/__support/CMakeLists.txt
M libc/test/src/__support/CPP/type_traits_test.cpp
R libc/test/src/__support/freelist_malloc_test.cpp
M libc/test/src/complex/CMakeLists.txt
A libc/test/src/complex/CprojTest.h
A libc/test/src/complex/cproj_test.cpp
A libc/test/src/complex/cprojf128_test.cpp
A libc/test/src/complex/cprojf16_test.cpp
A libc/test/src/complex/cprojf_test.cpp
A libc/test/src/complex/cprojl_test.cpp
M libc/test/src/math/CMakeLists.txt
A libc/test/src/math/cosf16_test.cpp
M libc/test/src/math/smoke/CMakeLists.txt
A libc/test/src/math/smoke/cosf16_test.cpp
M libc/test/src/stdlib/CMakeLists.txt
M libc/test/src/sys/mman/linux/remap_file_pages_test.cpp
M libc/utils/gpu/loader/Loader.h
M libc/utils/gpu/server/CMakeLists.txt
M libc/utils/gpu/server/rpc_server.cpp
M libcxx/docs/ReleaseNotes/20.rst
M libcxx/include/CMakeLists.txt
M libcxx/include/__algorithm/inplace_merge.h
M libcxx/include/__algorithm/stable_partition.h
M libcxx/include/__algorithm/stable_sort.h
M libcxx/include/__exception/exception_ptr.h
M libcxx/include/__functional/function.h
M libcxx/include/__hash_table
M libcxx/include/__locale_dir/locale_base_api.h
R libcxx/include/__locale_dir/locale_base_api/win32.h
M libcxx/include/__locale_dir/locale_guard.h
A libcxx/include/__locale_dir/support/windows.h
M libcxx/include/__memory/allocator.h
M libcxx/include/__memory/builtin_new_allocator.h
M libcxx/include/__memory/construct_at.h
M libcxx/include/__memory/ranges_construct_at.h
M libcxx/include/__memory/ranges_uninitialized_algorithms.h
M libcxx/include/__memory/raw_storage_iterator.h
M libcxx/include/__memory/shared_ptr.h
M libcxx/include/__memory/uninitialized_algorithms.h
M libcxx/include/__memory/unique_temporary_buffer.h
M libcxx/include/__memory_resource/polymorphic_allocator.h
A libcxx/include/__new/align_val_t.h
A libcxx/include/__new/allocate.h
A libcxx/include/__new/destroying_delete_t.h
A libcxx/include/__new/exceptions.h
A libcxx/include/__new/global_new_delete.h
A libcxx/include/__new/interference_size.h
A libcxx/include/__new/launder.h
A libcxx/include/__new/new_handler.h
A libcxx/include/__new/nothrow_t.h
A libcxx/include/__new/placement_new_delete.h
M libcxx/include/__ostream/basic_ostream.h
M libcxx/include/__pstl/backends/libdispatch.h
M libcxx/include/__pstl/cpu_algos/transform_reduce.h
M libcxx/include/__pstl/handle_exception.h
M libcxx/include/__utility/forward_like.h
M libcxx/include/__utility/no_destroy.h
M libcxx/include/__utility/small_buffer.h
M libcxx/include/array
M libcxx/include/charconv
M libcxx/include/exception
M libcxx/include/forward_list
M libcxx/include/future
M libcxx/include/list
M libcxx/include/locale
M libcxx/include/map
M libcxx/include/module.modulemap
M libcxx/include/new
M libcxx/include/optional
M libcxx/include/stdexcept
M libcxx/include/stdio.h
M libcxx/include/stdlib.h
M libcxx/include/unordered_map
M libcxx/include/valarray
M libcxx/include/variant
M libcxx/include/wchar.h
M libcxx/src/chrono.cpp
M libcxx/src/filesystem/filesystem_clock.cpp
M libcxx/src/include/overridable_function.h
M libcxx/src/new.cpp
M libcxx/src/support/win32/locale_win32.cpp
M libcxx/src/support/win32/support.cpp
M libcxx/test/libcxx/clang_modules_include.gen.py
M libcxx/test/libcxx/transitive_includes/cxx03.csv
M libcxx/test/libcxx/transitive_includes/cxx11.csv
M libcxx/test/libcxx/transitive_includes/cxx14.csv
M libcxx/test/libcxx/transitive_includes/cxx23.csv
M libcxx/test/libcxx/transitive_includes/cxx26.csv
M libcxx/test/std/language.support/support.dynamic/alloc.errors/bad.alloc/bad_alloc.pass.cpp
M libcxx/test/std/language.support/support.dynamic/new.delete/new.delete.placement/new_array.pass.cpp
M libcxx/test/std/language.support/support.dynamic/ptr.launder/launder.types.verify.cpp
M libcxx/test/std/localization/locale.categories/category.monetary/locale.moneypunct.byname/grouping.pass.cpp
M libcxx/test/std/localization/locale.categories/facet.numpunct/locale.numpunct.byname/grouping.pass.cpp
M libcxx/test/std/utilities/memory/default.allocator/allocator.members/allocate.size.pass.cpp
M libcxx/utils/ci/Dockerfile
M libcxx/utils/libcxx/test/format.py
M libcxxabi/src/cxa_default_handlers.cpp
M libcxxabi/src/stdlib_new_delete.cpp
M libcxxabi/test/cxa_vec_new_overflow_PR41395.pass.cpp
M libcxxabi/test/test_demangle.pass.cpp
M libunwind/include/__libunwind_config.h
M lld/COFF/COFFLinkerContext.h
M lld/COFF/Chunks.cpp
M lld/COFF/DLL.cpp
M lld/COFF/Driver.cpp
M lld/COFF/Driver.h
M lld/COFF/InputFiles.cpp
M lld/COFF/InputFiles.h
M lld/COFF/LTO.cpp
M lld/COFF/PDB.cpp
M lld/COFF/SymbolTable.cpp
M lld/COFF/SymbolTable.h
M lld/COFF/Symbols.cpp
M lld/COFF/Symbols.h
M lld/ELF/Arch/AArch64.cpp
M lld/ELF/Config.h
M lld/ELF/Driver.cpp
M lld/ELF/InputSection.cpp
M lld/ELF/LinkerScript.cpp
M lld/ELF/LinkerScript.h
M lld/ELF/Options.td
M lld/ELF/OutputSections.h
M lld/ELF/Relocations.cpp
M lld/ELF/Relocations.h
M lld/ELF/Symbols.h
M lld/ELF/SyntheticSections.cpp
M lld/ELF/SyntheticSections.h
M lld/ELF/Writer.cpp
M lld/MachO/Arch/ARM64.cpp
M lld/MachO/ConcatOutputSection.cpp
M lld/MachO/EhFrame.cpp
M lld/MachO/ICF.cpp
M lld/MachO/InputFiles.cpp
M lld/MachO/InputSection.cpp
M lld/MachO/MarkLive.cpp
M lld/MachO/ObjC.cpp
M lld/MachO/Relocations.cpp
M lld/MachO/SyntheticSections.cpp
M lld/MachO/UnwindInfoSection.cpp
M lld/docs/ELF/large_sections.rst
M lld/docs/ld.lld.1
R lld/test/COFF/Inputs/start-lib1.ll
R lld/test/COFF/Inputs/start-lib2.ll
M lld/test/COFF/arm64ec-codemap.test
M lld/test/COFF/arm64ec-entry-thunk.s
M lld/test/COFF/arm64ec-lib.test
M lld/test/COFF/arm64ec-range-thunks.s
A lld/test/COFF/arm64x-symtab.s
M lld/test/COFF/linkrepro.test
M lld/test/COFF/reloc-discarded.s
M lld/test/COFF/start-lib.ll
A lld/test/ELF/aarch64-got-relocations-pauth.s
A lld/test/ELF/randomize-section-padding.test
M lld/wasm/Config.h
M lld/wasm/Driver.cpp
M lldb/docs/resources/formatterbytecode.rst
M lldb/include/lldb/API/SBDebugger.h
M lldb/include/lldb/Core/Debugger.h
M lldb/include/lldb/Core/Progress.h
M lldb/include/lldb/Expression/DWARFExpression.h
M lldb/include/lldb/Host/Editline.h
M lldb/source/API/SBDebugger.cpp
M lldb/source/Core/CoreProperties.td
M lldb/source/Core/Debugger.cpp
M lldb/source/Core/Progress.cpp
M lldb/source/DataFormatters/FormatterSection.cpp
M lldb/source/Expression/DWARFExpression.cpp
M lldb/source/Host/common/Editline.cpp
M lldb/source/Plugins/SymbolFile/DWARF/DWARFASTParserClang.cpp
M lldb/source/Plugins/SymbolFile/DWARF/DWARFBaseDIE.cpp
M lldb/source/Plugins/SymbolFile/DWARF/DWARFUnit.cpp
M lldb/source/Plugins/SymbolFile/DWARF/DWARFUnit.h
M lldb/source/Plugins/SymbolFile/DWARF/DebugNamesDWARFIndex.cpp
M lldb/source/Plugins/SymbolFile/DWARF/ManualDWARFIndex.cpp
M lldb/source/Plugins/SymbolFile/DWARF/SymbolFileDWARF.cpp
M lldb/source/Plugins/SymbolFile/DWARF/SymbolFileDWARF.h
M lldb/source/Plugins/SymbolFile/DWARF/SymbolFileDWARFDebugMap.cpp
M lldb/source/Plugins/SymbolFile/DWARF/SymbolFileDWARFDebugMap.h
M lldb/test/API/CMakeLists.txt
M lldb/test/API/functionalities/completion/TestCompletion.py
M lldb/test/API/functionalities/conditional_break/TestConditionalBreak.py
M lldb/test/API/functionalities/data-formatter/data-formatter-cpp/TestDataFormatterCpp.py
M lldb/test/API/functionalities/data-formatter/data-formatter-skip-summary/TestDataFormatterSkipSummary.py
M lldb/test/API/functionalities/data-formatter/embedded-summary/TestEmbeddedTypeSummary.py
M lldb/test/API/functionalities/data-formatter/embedded-summary/main.c
M lldb/test/API/iohandler/resize/TestIOHandlerResizeNoEditline.py
M lldb/test/API/lang/cpp/namespace/TestNamespace.py
M lldb/test/API/terminal/TestEditlineCompletions.py
A lldb/test/Shell/SymbolFile/DWARF/objc-gmodules-class-extension.test
M lldb/tools/driver/Driver.cpp
M lldb/tools/driver/Driver.h
M lldb/unittests/Core/ProgressReportTest.cpp
M lldb/unittests/SymbolFile/DWARF/DWARFUnitTest.cpp
M llvm/cmake/modules/AddLLVM.cmake
M llvm/cmake/modules/LLVMProcessSources.cmake
M llvm/docs/CommandGuide/llvm-mc.rst
M llvm/docs/RISCVUsage.rst
M llvm/docs/ReleaseNotes.md
M llvm/docs/SPIRVUsage.rst
M llvm/docs/requirements-hashed.txt
M llvm/docs/requirements.txt
M llvm/include/llvm/Analysis/DXILResource.h
M llvm/include/llvm/Analysis/MemoryProfileInfo.h
M llvm/include/llvm/Analysis/PtrUseVisitor.h
M llvm/include/llvm/Analysis/ScalarEvolution.h
M llvm/include/llvm/Analysis/ScalarEvolutionPatternMatch.h
M llvm/include/llvm/Analysis/TypeBasedAliasAnalysis.h
M llvm/include/llvm/Bitcode/LLVMBitCodes.h
M llvm/include/llvm/CodeGen/GlobalISel/GIMatchTableExecutorImpl.h
M llvm/include/llvm/CodeGen/GlobalISel/LegalizationArtifactCombiner.h
M llvm/include/llvm/CodeGen/LiveVariables.h
M llvm/include/llvm/CodeGen/MachineFunction.h
M llvm/include/llvm/CodeGen/MachineModuleInfoImpls.h
M llvm/include/llvm/CodeGen/SDPatternMatch.h
M llvm/include/llvm/CodeGen/SelectionDAG.h
M llvm/include/llvm/CodeGen/TargetLoweringObjectFileImpl.h
M llvm/include/llvm/CodeGenTypes/LowLevelType.h
M llvm/include/llvm/DebugInfo/DWARF/DWARFVerifier.h
M llvm/include/llvm/DebugInfo/GSYM/DwarfTransformer.h
M llvm/include/llvm/DebugInfo/GSYM/GsymReader.h
M llvm/include/llvm/ExecutionEngine/JITLink/x86_64.h
M llvm/include/llvm/ExecutionEngine/Orc/COFFPlatform.h
M llvm/include/llvm/ExecutionEngine/Orc/Core.h
M llvm/include/llvm/ExecutionEngine/Orc/LazyObjectLinkingLayer.h
M llvm/include/llvm/ExecutionEngine/Orc/LazyReexports.h
A llvm/include/llvm/ExecutionEngine/Orc/LinkGraphLayer.h
A llvm/include/llvm/ExecutionEngine/Orc/LinkGraphLinkingLayer.h
M llvm/include/llvm/ExecutionEngine/Orc/ObjectLinkingLayer.h
M llvm/include/llvm/IR/Attributes.td
M llvm/include/llvm/IR/CmpPredicate.h
M llvm/include/llvm/IR/DiagnosticInfo.h
M llvm/include/llvm/IR/Instructions.h
M llvm/include/llvm/IR/IntrinsicsAArch64.td
M llvm/include/llvm/IR/IntrinsicsDirectX.td
M llvm/include/llvm/IR/IntrinsicsSPIRV.td
M llvm/include/llvm/ProfileData/InstrProfWriter.h
M llvm/include/llvm/Support/TypeName.h
M llvm/include/llvm/Target/TargetLoweringObjectFile.h
M llvm/include/llvm/TargetParser/Triple.h
A llvm/include/llvm/Transforms/Instrumentation/TypeSanitizer.h
M llvm/include/llvm/Transforms/Utils/Cloning.h
M llvm/include/llvm/Transforms/Utils/SSAUpdater.h
M llvm/include/llvm/Transforms/Vectorize/SandboxVectorizer/Interval.h
M llvm/lib/Analysis/DXILResource.cpp
M llvm/lib/Analysis/InstructionSimplify.cpp
M llvm/lib/Analysis/MemoryProfileInfo.cpp
M llvm/lib/Analysis/ScalarEvolution.cpp
M llvm/lib/Analysis/TypeBasedAliasAnalysis.cpp
M llvm/lib/Bitcode/Reader/BitcodeReader.cpp
M llvm/lib/Bitcode/Writer/BitcodeWriter.cpp
M llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
M llvm/lib/CodeGen/AsmPrinter/DwarfCFIException.cpp
M llvm/lib/CodeGen/BranchFolding.cpp
M llvm/lib/CodeGen/FixupStatepointCallerSaved.cpp
M llvm/lib/CodeGen/GlobalISel/CSEInfo.cpp
M llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
M llvm/lib/CodeGen/LiveVariables.cpp
M llvm/lib/CodeGen/MIRCanonicalizerPass.cpp
M llvm/lib/CodeGen/MLRegAllocEvictAdvisor.cpp
M llvm/lib/CodeGen/MachineCombiner.cpp
M llvm/lib/CodeGen/MachineFunction.cpp
M llvm/lib/CodeGen/MachineLateInstrsCleanup.cpp
M llvm/lib/CodeGen/MachineModuleInfoImpls.cpp
M llvm/lib/CodeGen/MachineOutliner.cpp
M llvm/lib/CodeGen/MachinePipeliner.cpp
M llvm/lib/CodeGen/MachineVerifier.cpp
M llvm/lib/CodeGen/ModuloSchedule.cpp
M llvm/lib/CodeGen/RegAllocBase.cpp
M llvm/lib/CodeGen/RegAllocBase.h
M llvm/lib/CodeGen/RegAllocFast.cpp
M llvm/lib/CodeGen/RegAllocGreedy.cpp
M llvm/lib/CodeGen/ScheduleDAGInstrs.cpp
M llvm/lib/CodeGen/SelectOptimize.cpp
M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
M llvm/lib/CodeGen/SelectionDAG/FastISel.cpp
M llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
M llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
M llvm/lib/CodeGen/ShrinkWrap.cpp
M llvm/lib/CodeGen/StackMaps.cpp
M llvm/lib/CodeGen/TargetLoweringObjectFileImpl.cpp
M llvm/lib/CodeGen/VirtRegMap.cpp
M llvm/lib/CodeGenTypes/LowLevelType.cpp
M llvm/lib/DebugInfo/DWARF/DWARFVerifier.cpp
M llvm/lib/DebugInfo/GSYM/CallSiteInfo.cpp
M llvm/lib/DebugInfo/GSYM/DwarfTransformer.cpp
M llvm/lib/DebugInfo/GSYM/GsymReader.cpp
M llvm/lib/DebugInfo/LogicalView/LVReaderHandler.cpp
M llvm/lib/ExecutionEngine/JITLink/x86_64.cpp
M llvm/lib/ExecutionEngine/Orc/CMakeLists.txt
M llvm/lib/ExecutionEngine/Orc/JITLinkReentryTrampolines.cpp
M llvm/lib/ExecutionEngine/Orc/LazyReexports.cpp
A llvm/lib/ExecutionEngine/Orc/LinkGraphLayer.cpp
A llvm/lib/ExecutionEngine/Orc/LinkGraphLinkingLayer.cpp
M llvm/lib/ExecutionEngine/Orc/ObjectLinkingLayer.cpp
M llvm/lib/Frontend/OpenMP/OMPContext.cpp
M llvm/lib/IR/ConstantFold.cpp
M llvm/lib/IR/Constants.cpp
M llvm/lib/IR/DiagnosticInfo.cpp
M llvm/lib/IR/Instructions.cpp
M llvm/lib/IR/Verifier.cpp
M llvm/lib/MC/MCAsmStreamer.cpp
M llvm/lib/MC/TargetRegistry.cpp
M llvm/lib/Passes/PassBuilder.cpp
M llvm/lib/Passes/PassRegistry.def
M llvm/lib/Target/AArch64/AArch64.h
M llvm/lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp
R llvm/lib/Target/AArch64/AArch64GlobalsTagging.cpp
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
M llvm/lib/Target/AArch64/AArch64ISelLowering.h
M llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
M llvm/lib/Target/AArch64/AArch64PBQPRegAlloc.cpp
M llvm/lib/Target/AArch64/AArch64SMEInstrInfo.td
M llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
M llvm/lib/Target/AArch64/AArch64TargetMachine.cpp
M llvm/lib/Target/AArch64/AArch64TargetObjectFile.cpp
M llvm/lib/Target/AArch64/AArch64TargetObjectFile.h
M llvm/lib/Target/AArch64/CMakeLists.txt
M llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
M llvm/lib/Target/AArch64/MCTargetDesc/AArch64TargetStreamer.cpp
M llvm/lib/Target/AArch64/MCTargetDesc/AArch64TargetStreamer.h
M llvm/lib/Target/AArch64/SMEInstrFormats.td
M llvm/lib/Target/AArch64/SVEInstrFormats.td
M llvm/lib/Target/AMDGPU/AMDGPULibCalls.cpp
M llvm/lib/Target/AMDGPU/AMDGPULibFunc.cpp
M llvm/lib/Target/AMDGPU/AMDGPULibFunc.h
M llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
A llvm/lib/Target/AMDGPU/AMDGPUSelectionDAGInfo.cpp
A llvm/lib/Target/AMDGPU/AMDGPUSelectionDAGInfo.h
M llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
M llvm/lib/Target/AMDGPU/CMakeLists.txt
M llvm/lib/Target/AMDGPU/GCNSubtarget.cpp
M llvm/lib/Target/AMDGPU/GCNSubtarget.h
M llvm/lib/Target/AMDGPU/R600Subtarget.cpp
M llvm/lib/Target/AMDGPU/R600Subtarget.h
M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
M llvm/lib/Target/AMDGPU/SIInstructions.td
M llvm/lib/Target/AMDGPU/SILowerSGPRSpills.cpp
M llvm/lib/Target/AMDGPU/SIPreEmitPeephole.cpp
M llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
M llvm/lib/Target/AMDGPU/SOPInstructions.td
M llvm/lib/Target/AMDGPU/VOP2Instructions.td
M llvm/lib/Target/AMDGPU/VOP3Instructions.td
M llvm/lib/Target/AMDGPU/VOPInstructions.td
M llvm/lib/Target/ARM/ARMConstantIslandPass.cpp
M llvm/lib/Target/ARM/ARMISelLowering.cpp
M llvm/lib/Target/ARM/ARMInstrInfo.td
M llvm/lib/Target/ARM/ARMInstrThumb2.td
M llvm/lib/Target/ARM/Thumb2ITBlockPass.cpp
M llvm/lib/Target/DirectX/DXIL.td
M llvm/lib/Target/DirectX/DXILIntrinsicExpansion.cpp
M llvm/lib/Target/DirectX/DXILOpLowering.cpp
M llvm/lib/Target/DirectX/DXILPrettyPrinter.cpp
M llvm/lib/Target/DirectX/DXILTranslateMetadata.cpp
M llvm/lib/Target/LoongArch/LoongArchOptWInstrs.cpp
M llvm/lib/Target/Mips/CMakeLists.txt
A llvm/lib/Target/Mips/MipsSelectionDAGInfo.cpp
A llvm/lib/Target/Mips/MipsSelectionDAGInfo.h
M llvm/lib/Target/Mips/MipsSubtarget.cpp
M llvm/lib/Target/Mips/MipsSubtarget.h
M llvm/lib/Target/NVPTX/CMakeLists.txt
M llvm/lib/Target/NVPTX/NVPTXAsmPrinter.cpp
M llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp
M llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.h
M llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp
M llvm/lib/Target/NVPTX/NVPTXISelLowering.h
M llvm/lib/Target/NVPTX/NVPTXInstrInfo.td
M llvm/lib/Target/NVPTX/NVPTXIntrinsics.td
M llvm/lib/Target/NVPTX/NVPTXMachineFunctionInfo.h
M llvm/lib/Target/NVPTX/NVPTXReplaceImageHandles.cpp
A llvm/lib/Target/NVPTX/NVPTXSelectionDAGInfo.cpp
A llvm/lib/Target/NVPTX/NVPTXSelectionDAGInfo.h
M llvm/lib/Target/NVPTX/NVPTXSubtarget.cpp
M llvm/lib/Target/NVPTX/NVPTXSubtarget.h
M llvm/lib/Target/NVPTX/NVPTXTargetMachine.cpp
M llvm/lib/Target/PowerPC/CMakeLists.txt
A llvm/lib/Target/PowerPC/PPCSelectionDAGInfo.cpp
A llvm/lib/Target/PowerPC/PPCSelectionDAGInfo.h
M llvm/lib/Target/PowerPC/PPCSubtarget.cpp
M llvm/lib/Target/PowerPC/PPCSubtarget.h
M llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
M llvm/lib/Target/RISCV/CMakeLists.txt
M llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
M llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
M llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
M llvm/lib/Target/RISCV/RISCVFeatures.td
M llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/lib/Target/RISCV/RISCVISelLowering.h
M llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
M llvm/lib/Target/RISCV/RISCVInstrInfo.td
M llvm/lib/Target/RISCV/RISCVInstrInfoA.td
M llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
M llvm/lib/Target/RISCV/RISCVInstrInfoXCV.td
M llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
M llvm/lib/Target/RISCV/RISCVInstrInfoZalasr.td
M llvm/lib/Target/RISCV/RISCVProcessors.td
A llvm/lib/Target/RISCV/RISCVSelectionDAGInfo.cpp
A llvm/lib/Target/RISCV/RISCVSelectionDAGInfo.h
M llvm/lib/Target/RISCV/RISCVSubtarget.cpp
M llvm/lib/Target/RISCV/RISCVSubtarget.h
M llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
M llvm/lib/Target/RISCV/RISCVTargetMachine.h
M llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp
M llvm/lib/Target/SPIRV/MCTargetDesc/SPIRVMCCodeEmitter.cpp
M llvm/lib/Target/SPIRV/SPIRVBuiltins.cpp
M llvm/lib/Target/SPIRV/SPIRVBuiltins.h
M llvm/lib/Target/SPIRV/SPIRVCommandLine.cpp
M llvm/lib/Target/SPIRV/SPIRVEmitIntrinsics.cpp
M llvm/lib/Target/SPIRV/SPIRVGlobalRegistry.cpp
M llvm/lib/Target/SPIRV/SPIRVInstrInfo.td
M llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
M llvm/lib/Target/SPIRV/SPIRVLegalizerInfo.cpp
M llvm/lib/Target/SPIRV/SPIRVModuleAnalysis.cpp
M llvm/lib/Target/SPIRV/SPIRVPostLegalizer.cpp
M llvm/lib/Target/SPIRV/SPIRVPreLegalizer.cpp
M llvm/lib/Target/SPIRV/SPIRVSymbolicOperands.td
M llvm/lib/Target/Sparc/AsmParser/SparcAsmParser.cpp
M llvm/lib/Target/Sparc/DelaySlotFiller.cpp
M llvm/lib/Target/Sparc/SparcInstrInfo.td
M llvm/lib/Target/SystemZ/SystemZInstrInfo.td
M llvm/lib/Target/SystemZ/SystemZOperators.td
M llvm/lib/Target/TargetLoweringObjectFile.cpp
M llvm/lib/Target/X86/X86.td
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/lib/Target/X86/X86TargetTransformInfo.cpp
M llvm/lib/TargetParser/RISCVISAInfo.cpp
M llvm/lib/TargetParser/Triple.cpp
M llvm/lib/TargetParser/X86TargetParser.cpp
M llvm/lib/Transforms/IPO/MemProfContextDisambiguation.cpp
M llvm/lib/Transforms/InstCombine/InstCombineSelect.cpp
M llvm/lib/Transforms/Instrumentation/CMakeLists.txt
M llvm/lib/Transforms/Instrumentation/MemProfiler.cpp
A llvm/lib/Transforms/Instrumentation/TypeSanitizer.cpp
M llvm/lib/Transforms/Scalar/ConstraintElimination.cpp
M llvm/lib/Transforms/Scalar/EarlyCSE.cpp
M llvm/lib/Transforms/Scalar/SROA.cpp
M llvm/lib/Transforms/Utils/CloneFunction.cpp
M llvm/lib/Transforms/Utils/CodeExtractor.cpp
M llvm/lib/Transforms/Utils/LoopVersioning.cpp
M llvm/lib/Transforms/Utils/SSAUpdater.cpp
M llvm/lib/Transforms/Utils/SimplifyCFG.cpp
M llvm/lib/Transforms/Vectorize/LoopVectorizationPlanner.h
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
M llvm/lib/Transforms/Vectorize/VPlan.cpp
M llvm/lib/Transforms/Vectorize/VPlan.h
M llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
M llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
M llvm/lib/Transforms/Vectorize/VectorCombine.cpp
M llvm/test/Analysis/CostModel/X86/scalarize.ll
M llvm/test/Analysis/CostModel/X86/shuffle-non-pow-2-codesize.ll
M llvm/test/Analysis/CostModel/X86/shuffle-non-pow-2-latency.ll
M llvm/test/Analysis/CostModel/X86/shuffle-non-pow-2-sizelatency.ll
M llvm/test/Analysis/CostModel/X86/shuffle-non-pow-2.ll
M llvm/test/Analysis/DXILResource/buffer-frombinding.ll
M llvm/test/Analysis/LoopAccessAnalysis/memcheck-wrapping-pointers.ll
M llvm/test/Analysis/LoopAccessAnalysis/nssw-predicate-implied.ll
M llvm/test/CodeGen/AArch64/GlobalISel/legalize-ext.mir
M llvm/test/CodeGen/AArch64/GlobalISel/legalize-threeway-cmp.mir
M llvm/test/CodeGen/AArch64/O0-pipeline.ll
M llvm/test/CodeGen/AArch64/O3-pipeline.ll
M llvm/test/CodeGen/AArch64/aarch64-dup-ext-crash.ll
M llvm/test/CodeGen/AArch64/aarch64-dup-ext.ll
M llvm/test/CodeGen/AArch64/arm64-anyregcc-crash.ll
M llvm/test/CodeGen/AArch64/dup.ll
A llvm/test/CodeGen/AArch64/fp8-sve-fmla.ll
A llvm/test/CodeGen/AArch64/ptrauth-sign-personality.ll
M llvm/test/CodeGen/AArch64/scmp.ll
M llvm/test/CodeGen/AArch64/selectopt-cast.ll
M llvm/test/CodeGen/AArch64/sincos-stack-slots.ll
A llvm/test/CodeGen/AArch64/sme2-fp8-intrinsics-mla.ll
M llvm/test/CodeGen/AArch64/sme2-intrinsics-fp8-fdot.ll
A llvm/test/CodeGen/AArch64/sme2-intrinsics-fp8-fvdot.ll
M llvm/test/CodeGen/AArch64/stack-tagging-ex-2.ll
A llvm/test/CodeGen/AArch64/sve-load-store-strict-align.ll
A llvm/test/CodeGen/AArch64/sve-unaligned-load-store-strict-align.ll
M llvm/test/CodeGen/AArch64/ucmp.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-and.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-merge-values.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-or.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-phi.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-shuffle-vector.s16.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-xor.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-zext.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/mmra.ll
M llvm/test/CodeGen/AMDGPU/alloc-all-regs-reserved-in-class.mir
A llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-image-function-signatures.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-ldexp.ll
A llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-unexpected-types.ll
M llvm/test/CodeGen/AMDGPU/bf16-conversions.ll
M llvm/test/CodeGen/AMDGPU/bitreverse-inline-immediates.ll
M llvm/test/CodeGen/AMDGPU/gfx12_scalar_subword_loads.ll
M llvm/test/CodeGen/AMDGPU/illegal-eviction-assert.mir
M llvm/test/CodeGen/AMDGPU/invalid-inline-asm-constraint-crash.ll
M llvm/test/CodeGen/AMDGPU/issue48473.mir
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.bitop3.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.read.tr.gfx950.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.gfx950.bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.gfx950.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.prng.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.atomic.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.atomic.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.buffer.prefetch.data.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.prefetch.data.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.smfmac.gfx950.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.atomic.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.atomic.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.update.dpp.gfx90a.ll
M llvm/test/CodeGen/AMDGPU/llvm.set.rounding.ll
M llvm/test/CodeGen/AMDGPU/load-store-opt-addc0.mir
M llvm/test/CodeGen/AMDGPU/mai-hazards-mfma-scale.gfx950.mir
M llvm/test/CodeGen/AMDGPU/mmra.ll
A llvm/test/CodeGen/AMDGPU/ran-out-of-registers-error-all-regs-reserved.ll
A llvm/test/CodeGen/AMDGPU/ran-out-of-registers-errors.ll
M llvm/test/CodeGen/AMDGPU/regalloc-illegal-eviction-assert.ll
M llvm/test/CodeGen/AMDGPU/remaining-virtual-register-operands.ll
A llvm/test/CodeGen/AMDGPU/remove-not-short-exec-branch-on-unconditional-jump.mir
M llvm/test/CodeGen/AMDGPU/sgpr-regalloc-flags.ll
M llvm/test/CodeGen/AMDGPU/sgpr-spill-partially-undef.mir
M llvm/test/CodeGen/AMDGPU/spill-agpr-partially-undef.mir
M llvm/test/CodeGen/AMDGPU/v_swap_b16.ll
M llvm/test/CodeGen/AMDGPU/vgpr-spill.mir
M llvm/test/CodeGen/ARC/addrmode.ll
M llvm/test/CodeGen/ARC/alu.ll
M llvm/test/CodeGen/ARC/brcc.ll
M llvm/test/CodeGen/ARC/call.ll
M llvm/test/CodeGen/ARC/intrinsics.ll
M llvm/test/CodeGen/ARC/ldst.ll
M llvm/test/CodeGen/ARM/dagcombine-ld-op-st.ll
M llvm/test/CodeGen/AVR/PR31344.ll
M llvm/test/CodeGen/AVR/PR31345.ll
M llvm/test/CodeGen/AVR/PR37143.ll
M llvm/test/CodeGen/AVR/add.ll
M llvm/test/CodeGen/AVR/alloca.ll
M llvm/test/CodeGen/AVR/and.ll
M llvm/test/CodeGen/AVR/atomics/fence.ll
M llvm/test/CodeGen/AVR/atomics/load-store-16-unexpected-register-bug.ll
M llvm/test/CodeGen/AVR/atomics/load16.ll
M llvm/test/CodeGen/AVR/atomics/load32.ll
M llvm/test/CodeGen/AVR/atomics/load64.ll
M llvm/test/CodeGen/AVR/atomics/load8.ll
M llvm/test/CodeGen/AVR/atomics/store.ll
M llvm/test/CodeGen/AVR/atomics/store16.ll
M llvm/test/CodeGen/AVR/atomics/swap.ll
M llvm/test/CodeGen/AVR/avr-rust-issue-123.ll
M llvm/test/CodeGen/AVR/block-address-is-in-progmem-space.ll
M llvm/test/CodeGen/AVR/branch-relaxation-long.ll
M llvm/test/CodeGen/AVR/branch-relaxation.ll
M llvm/test/CodeGen/AVR/brind.ll
M llvm/test/CodeGen/AVR/calling-conv/c/call.ll
M llvm/test/CodeGen/AVR/calling-conv/c/call_aggr.ll
M llvm/test/CodeGen/AVR/calling-conv/c/return.ll
M llvm/test/CodeGen/AVR/calling-conv/c/return_aggr.ll
M llvm/test/CodeGen/AVR/clear-bss.ll
M llvm/test/CodeGen/AVR/cmp.ll
M llvm/test/CodeGen/AVR/copy-data-to-ram.ll
M llvm/test/CodeGen/AVR/ctlz.ll
M llvm/test/CodeGen/AVR/ctpop.ll
M llvm/test/CodeGen/AVR/cttz.ll
M llvm/test/CodeGen/AVR/directmem.ll
M llvm/test/CodeGen/AVR/div.ll
M llvm/test/CodeGen/AVR/dynalloca.ll
M llvm/test/CodeGen/AVR/eor.ll
M llvm/test/CodeGen/AVR/expand-integer-failure.ll
M llvm/test/CodeGen/AVR/features/avr25.ll
M llvm/test/CodeGen/AVR/features/xmega_io.ll
M llvm/test/CodeGen/AVR/frame.ll
M llvm/test/CodeGen/AVR/frmidx-iterator-bug.ll
M llvm/test/CodeGen/AVR/high-pressure-on-ptrregs.ll
M llvm/test/CodeGen/AVR/icall-func-pointer-correct-addr-space.ll
M llvm/test/CodeGen/AVR/impossible-reg-to-reg-copy.ll
M llvm/test/CodeGen/AVR/inline-asm/inline-asm.ll
M llvm/test/CodeGen/AVR/inline-asm/inline-asm2.ll
M llvm/test/CodeGen/AVR/integration/blink.ll
M llvm/test/CodeGen/AVR/interrupts.ll
M llvm/test/CodeGen/AVR/intrinsics/named-reg-alloc.ll
M llvm/test/CodeGen/AVR/intrinsics/named-reg-special.ll
M llvm/test/CodeGen/AVR/intrinsics/stacksave-restore.ll
M llvm/test/CodeGen/AVR/io.ll
M llvm/test/CodeGen/AVR/issue-cannot-select-bswap.ll
M llvm/test/CodeGen/AVR/issue-regalloc-stackframe-folding-earlyclobber.ll
M llvm/test/CodeGen/AVR/large-return-size.ll
M llvm/test/CodeGen/AVR/ldd-immediate-overflow.ll
M llvm/test/CodeGen/AVR/load.ll
M llvm/test/CodeGen/AVR/lower-formal-args-struct-return.ll
M llvm/test/CodeGen/AVR/lower-formal-arguments-assertion.ll
M llvm/test/CodeGen/AVR/no-clear-bss.ll
M llvm/test/CodeGen/AVR/no-copy-data.ll
M llvm/test/CodeGen/AVR/no-print-operand-twice.ll
M llvm/test/CodeGen/AVR/or.ll
M llvm/test/CodeGen/AVR/pre-schedule.ll
M llvm/test/CodeGen/AVR/progmem-extended.ll
M llvm/test/CodeGen/AVR/progmem.ll
M llvm/test/CodeGen/AVR/pseudo/LDDWRdYQ.mir
M llvm/test/CodeGen/AVR/rem.ll
M llvm/test/CodeGen/AVR/runtime-trig.ll
M llvm/test/CodeGen/AVR/rust-avr-bug-112.ll
M llvm/test/CodeGen/AVR/rust-avr-bug-37.ll
M llvm/test/CodeGen/AVR/rust-avr-bug-95.ll
M llvm/test/CodeGen/AVR/rust-avr-bug-99.ll
M llvm/test/CodeGen/AVR/rust-bug-98167.ll
M llvm/test/CodeGen/AVR/select-must-add-unconditional-jump.ll
M llvm/test/CodeGen/AVR/sext.ll
M llvm/test/CodeGen/AVR/shift.ll
M llvm/test/CodeGen/AVR/sign-extension.ll
M llvm/test/CodeGen/AVR/smul-with-overflow.ll
M llvm/test/CodeGen/AVR/software-mul.ll
M llvm/test/CodeGen/AVR/std-immediate-overflow.ll
M llvm/test/CodeGen/AVR/std-ldd-immediate-overflow.ll
M llvm/test/CodeGen/AVR/stdwstk.ll
M llvm/test/CodeGen/AVR/store-undef.ll
M llvm/test/CodeGen/AVR/store.ll
M llvm/test/CodeGen/AVR/sub.ll
M llvm/test/CodeGen/AVR/trunc.ll
M llvm/test/CodeGen/AVR/umul-with-overflow.ll
M llvm/test/CodeGen/AVR/umul.with.overflow.i16-bug.ll
M llvm/test/CodeGen/AVR/unaligned-atomic-ops.ll
M llvm/test/CodeGen/AVR/varargs.ll
M llvm/test/CodeGen/AVR/xor.ll
M llvm/test/CodeGen/AVR/zeroreg.ll
M llvm/test/CodeGen/AVR/zext.ll
M llvm/test/CodeGen/BPF/32-bit-subreg-alu.ll
M llvm/test/CodeGen/BPF/32-bit-subreg-cond-select.ll
M llvm/test/CodeGen/BPF/32-bit-subreg-load-store.ll
M llvm/test/CodeGen/BPF/32-bit-subreg-peephole-phi-1.ll
M llvm/test/CodeGen/BPF/32-bit-subreg-peephole-phi-2.ll
M llvm/test/CodeGen/BPF/32-bit-subreg-peephole-phi-3.ll
M llvm/test/CodeGen/BPF/32-bit-subreg-peephole.ll
M llvm/test/CodeGen/BPF/32-bit-subreg-zext.ll
M llvm/test/CodeGen/BPF/BTF/array-1d-char.ll
M llvm/test/CodeGen/BPF/BTF/array-1d-int.ll
M llvm/test/CodeGen/BPF/BTF/array-2d-int.ll
M llvm/test/CodeGen/BPF/BTF/array-size-0.ll
M llvm/test/CodeGen/BPF/BTF/array-typedef.ll
M llvm/test/CodeGen/BPF/BTF/atomics.ll
M llvm/test/CodeGen/BPF/BTF/char-no-debuginfo.ll
M llvm/test/CodeGen/BPF/BTF/char.ll
M llvm/test/CodeGen/BPF/BTF/double.ll
M llvm/test/CodeGen/BPF/BTF/empty-btf.ll
M llvm/test/CodeGen/BPF/BTF/enum-basic.ll
M llvm/test/CodeGen/BPF/BTF/extern-builtin.ll
M llvm/test/CodeGen/BPF/BTF/extern-func-arg.ll
M llvm/test/CodeGen/BPF/BTF/extern-func-ptr.ll
M llvm/test/CodeGen/BPF/BTF/extern-global-var.ll
M llvm/test/CodeGen/BPF/BTF/extern-var-func-weak-section.ll
M llvm/test/CodeGen/BPF/BTF/extern-var-func-weak.ll
M llvm/test/CodeGen/BPF/BTF/extern-var-func.ll
M llvm/test/CodeGen/BPF/BTF/extern-var-func2.ll
M llvm/test/CodeGen/BPF/BTF/extern-var-section.ll
M llvm/test/CodeGen/BPF/BTF/extern-var-struct-weak.ll
M llvm/test/CodeGen/BPF/BTF/extern-var-struct.ll
M llvm/test/CodeGen/BPF/BTF/extern-var-weak-section.ll
M llvm/test/CodeGen/BPF/BTF/filename.ll
M llvm/test/CodeGen/BPF/BTF/float.ll
M llvm/test/CodeGen/BPF/BTF/func-func-ptr.ll
M llvm/test/CodeGen/BPF/BTF/func-non-void.ll
M llvm/test/CodeGen/BPF/BTF/func-source.ll
M llvm/test/CodeGen/BPF/BTF/func-typedef.ll
M llvm/test/CodeGen/BPF/BTF/func-unused-arg.ll
M llvm/test/CodeGen/BPF/BTF/func-void.ll
M llvm/test/CodeGen/BPF/BTF/fwd-no-define.ll
M llvm/test/CodeGen/BPF/BTF/fwd-with-define.ll
M llvm/test/CodeGen/BPF/BTF/global-var-bss-and-data.ll
M llvm/test/CodeGen/BPF/BTF/global-var-inited.ll
M llvm/test/CodeGen/BPF/BTF/global-var-sec-readonly.ll
M llvm/test/CodeGen/BPF/BTF/global-var-sec.ll
M llvm/test/CodeGen/BPF/BTF/incomplete-debuginfo.ll
M llvm/test/CodeGen/BPF/BTF/int.ll
M llvm/test/CodeGen/BPF/BTF/local-var-readonly-1.ll
M llvm/test/CodeGen/BPF/BTF/local-var-readonly-2.ll
M llvm/test/CodeGen/BPF/BTF/local-var.ll
M llvm/test/CodeGen/BPF/BTF/longlong.ll
M llvm/test/CodeGen/BPF/BTF/map-def-2.ll
M llvm/test/CodeGen/BPF/BTF/map-def-3.ll
M llvm/test/CodeGen/BPF/BTF/map-def.ll
M llvm/test/CodeGen/BPF/BTF/pruning-const.ll
M llvm/test/CodeGen/BPF/BTF/pruning-dup-ptr-struct.ll
M llvm/test/CodeGen/BPF/BTF/pruning-multi-derived-type.ll
M llvm/test/CodeGen/BPF/BTF/pruning-typedef.ll
M llvm/test/CodeGen/BPF/BTF/ptr-const-void.ll
M llvm/test/CodeGen/BPF/BTF/ptr-func-1.ll
M llvm/test/CodeGen/BPF/BTF/ptr-func-2.ll
M llvm/test/CodeGen/BPF/BTF/ptr-func-3.ll
M llvm/test/CodeGen/BPF/BTF/ptr-int.ll
M llvm/test/CodeGen/BPF/BTF/ptr-prune-type.ll
M llvm/test/CodeGen/BPF/BTF/ptr-void.ll
M llvm/test/CodeGen/BPF/BTF/ptr-volatile-const-void.ll
M llvm/test/CodeGen/BPF/BTF/ptr-volatile-void.ll
M llvm/test/CodeGen/BPF/BTF/restrict-ptr.ll
M llvm/test/CodeGen/BPF/BTF/short.ll
M llvm/test/CodeGen/BPF/BTF/static-func.ll
M llvm/test/CodeGen/BPF/BTF/static-var-derived-type.ll
M llvm/test/CodeGen/BPF/BTF/static-var-inited-sec.ll
M llvm/test/CodeGen/BPF/BTF/static-var-inited.ll
M llvm/test/CodeGen/BPF/BTF/static-var-readonly-sec.ll
M llvm/test/CodeGen/BPF/BTF/static-var-readonly.ll
M llvm/test/CodeGen/BPF/BTF/static-var-sec.ll
M llvm/test/CodeGen/BPF/BTF/static-var-zerolen-array.ll
M llvm/test/CodeGen/BPF/BTF/static-var.ll
M llvm/test/CodeGen/BPF/BTF/struct-anon-2.ll
M llvm/test/CodeGen/BPF/BTF/struct-anon.ll
M llvm/test/CodeGen/BPF/BTF/struct-basic.ll
M llvm/test/CodeGen/BPF/BTF/struct-bitfield-typedef.ll
M llvm/test/CodeGen/BPF/BTF/struct-enum.ll
M llvm/test/CodeGen/BPF/BTF/tag-1.ll
M llvm/test/CodeGen/BPF/BTF/tag-2.ll
M llvm/test/CodeGen/BPF/BTF/tag-extern-func.ll
M llvm/test/CodeGen/BPF/BTF/tag-typedef.ll
M llvm/test/CodeGen/BPF/BTF/type-tag-fixup-fwd.ll
M llvm/test/CodeGen/BPF/BTF/type-tag-fixup-resolved.ll
M llvm/test/CodeGen/BPF/BTF/type-tag-var.ll
M llvm/test/CodeGen/BPF/BTF/uchar.ll
M llvm/test/CodeGen/BPF/BTF/uint.ll
M llvm/test/CodeGen/BPF/BTF/ulonglong.ll
M llvm/test/CodeGen/BPF/BTF/union-array-typedef.ll
M llvm/test/CodeGen/BPF/BTF/ushort.ll
M llvm/test/CodeGen/BPF/BTF/weak-global-2.ll
M llvm/test/CodeGen/BPF/BTF/weak-global-3.ll
M llvm/test/CodeGen/BPF/BTF/weak-global.ll
M llvm/test/CodeGen/BPF/CORE/field-reloc-st-imm.ll
M llvm/test/CodeGen/BPF/CORE/simplifypatable-nullptr.ll
M llvm/test/CodeGen/BPF/addr-space-cast.ll
M llvm/test/CodeGen/BPF/addr-space-globals.ll
M llvm/test/CodeGen/BPF/addr-space-globals2.ll
M llvm/test/CodeGen/BPF/alu8.ll
M llvm/test/CodeGen/BPF/atomics.ll
M llvm/test/CodeGen/BPF/atomics_2.ll
M llvm/test/CodeGen/BPF/atomics_mem_order_v1.ll
M llvm/test/CodeGen/BPF/atomics_mem_order_v3.ll
M llvm/test/CodeGen/BPF/atomics_sub64_relaxed_v1.ll
M llvm/test/CodeGen/BPF/basictest.ll
M llvm/test/CodeGen/BPF/bpf-fastcall-1.ll
M llvm/test/CodeGen/BPF/bpf-fastcall-2.ll
M llvm/test/CodeGen/BPF/bpf-fastcall-3.ll
M llvm/test/CodeGen/BPF/bpf-fastcall-4.ll
M llvm/test/CodeGen/BPF/bpf-fastcall-5.ll
M llvm/test/CodeGen/BPF/bpf-fastcall-regmask-1.ll
M llvm/test/CodeGen/BPF/bswap.ll
M llvm/test/CodeGen/BPF/byval.ll
M llvm/test/CodeGen/BPF/callx.ll
M llvm/test/CodeGen/BPF/cc_args.ll
M llvm/test/CodeGen/BPF/cc_args_be.ll
M llvm/test/CodeGen/BPF/cc_ret.ll
M llvm/test/CodeGen/BPF/cmp.ll
M llvm/test/CodeGen/BPF/cttz-ctlz.ll
M llvm/test/CodeGen/BPF/dwarfdump.ll
M llvm/test/CodeGen/BPF/ex1.ll
M llvm/test/CodeGen/BPF/fi_ri.ll
M llvm/test/CodeGen/BPF/gotol.ll
M llvm/test/CodeGen/BPF/i128.ll
M llvm/test/CodeGen/BPF/inline_asm.ll
M llvm/test/CodeGen/BPF/inlineasm-wreg.ll
M llvm/test/CodeGen/BPF/intrinsics.ll
M llvm/test/CodeGen/BPF/is_trunc_free.ll
M llvm/test/CodeGen/BPF/is_zext_free.ll
M llvm/test/CodeGen/BPF/ldsx.ll
M llvm/test/CodeGen/BPF/load.ll
M llvm/test/CodeGen/BPF/loops.ll
M llvm/test/CodeGen/BPF/many_args1.ll
M llvm/test/CodeGen/BPF/many_args2.ll
M llvm/test/CodeGen/BPF/mem_offset.ll
M llvm/test/CodeGen/BPF/mem_offset_be.ll
M llvm/test/CodeGen/BPF/memcmp.ll
M llvm/test/CodeGen/BPF/memcpy-expand-in-order.ll
M llvm/test/CodeGen/BPF/movsx.ll
M llvm/test/CodeGen/BPF/no-merge-attr.ll
M llvm/test/CodeGen/BPF/optnone-1.ll
M llvm/test/CodeGen/BPF/optnone-2.ll
M llvm/test/CodeGen/BPF/remove_truncate_1.ll
M llvm/test/CodeGen/BPF/remove_truncate_2.ll
M llvm/test/CodeGen/BPF/remove_truncate_3.ll
M llvm/test/CodeGen/BPF/remove_truncate_4.ll
M llvm/test/CodeGen/BPF/remove_truncate_5.ll
M llvm/test/CodeGen/BPF/remove_truncate_6.ll
M llvm/test/CodeGen/BPF/remove_truncate_7.ll
M llvm/test/CodeGen/BPF/remove_truncate_8.ll
M llvm/test/CodeGen/BPF/remove_truncate_9.ll
M llvm/test/CodeGen/BPF/rodata_1.ll
M llvm/test/CodeGen/BPF/rodata_2.ll
M llvm/test/CodeGen/BPF/rodata_3.ll
M llvm/test/CodeGen/BPF/rodata_4.ll
M llvm/test/CodeGen/BPF/rodata_5.ll
M llvm/test/CodeGen/BPF/rodata_6.ll
M llvm/test/CodeGen/BPF/rodata_7.ll
M llvm/test/CodeGen/BPF/sdiv_smod.ll
M llvm/test/CodeGen/BPF/sdiv_to_mul.ll
M llvm/test/CodeGen/BPF/select_ri.ll
M llvm/test/CodeGen/BPF/selectiondag-bug.ll
M llvm/test/CodeGen/BPF/setcc.ll
M llvm/test/CodeGen/BPF/shifts.ll
M llvm/test/CodeGen/BPF/sockex2.ll
M llvm/test/CodeGen/BPF/spill-alu32.ll
M llvm/test/CodeGen/BPF/store_imm.ll
M llvm/test/CodeGen/BPF/struct-arg.ll
M llvm/test/CodeGen/BPF/struct_ret1.ll
M llvm/test/CodeGen/BPF/struct_ret2.ll
M llvm/test/CodeGen/BPF/undef.ll
M llvm/test/CodeGen/BPF/vararg1.ll
M llvm/test/CodeGen/BPF/warn-call.ll
M llvm/test/CodeGen/BPF/warn-stack.ll
M llvm/test/CodeGen/BPF/xadd.ll
M llvm/test/CodeGen/BPF/xadd_legal.ll
M llvm/test/CodeGen/BPF/xaddd_v1.ll
A llvm/test/CodeGen/DirectX/WaveActiveAllTrue.ll
A llvm/test/CodeGen/DirectX/vector_reduce_add.ll
M llvm/test/CodeGen/Hexagon/64bit_tstbit.ll
M llvm/test/CodeGen/Hexagon/Atomics.ll
M llvm/test/CodeGen/Hexagon/BranchPredict.ll
M llvm/test/CodeGen/Hexagon/Halide_vec_cast_trunc1.ll
M llvm/test/CodeGen/Hexagon/Halide_vec_cast_trunc2.ll
M llvm/test/CodeGen/Hexagon/M4_mpyri_addi_global.ll
M llvm/test/CodeGen/Hexagon/M4_mpyrr_addi_global.ll
M llvm/test/CodeGen/Hexagon/NVJumpCmp.ll
M llvm/test/CodeGen/Hexagon/P08214.ll
M llvm/test/CodeGen/Hexagon/PR33749.ll
M llvm/test/CodeGen/Hexagon/SUnit-boundary-prob.ll
M llvm/test/CodeGen/Hexagon/V60-VDblNew.ll
M llvm/test/CodeGen/Hexagon/abi-padding-2.ll
M llvm/test/CodeGen/Hexagon/abi-padding.ll
M llvm/test/CodeGen/Hexagon/abs.ll
M llvm/test/CodeGen/Hexagon/absaddr-store.ll
M llvm/test/CodeGen/Hexagon/absimm.ll
M llvm/test/CodeGen/Hexagon/add-use.ll
M llvm/test/CodeGen/Hexagon/add_int_double.ll
M llvm/test/CodeGen/Hexagon/add_mpi_RRR.ll
M llvm/test/CodeGen/Hexagon/addaddi.ll
M llvm/test/CodeGen/Hexagon/addasl-address.ll
M llvm/test/CodeGen/Hexagon/addh-sext-trunc.ll
M llvm/test/CodeGen/Hexagon/addh-shifted.ll
M llvm/test/CodeGen/Hexagon/addh.ll
M llvm/test/CodeGen/Hexagon/addr-calc-opt.ll
M llvm/test/CodeGen/Hexagon/addr-mode-opt.ll
M llvm/test/CodeGen/Hexagon/addrmode-align.ll
M llvm/test/CodeGen/Hexagon/addrmode-globoff.mir
M llvm/test/CodeGen/Hexagon/addrmode-immop.mir
M llvm/test/CodeGen/Hexagon/addrmode-indoff.ll
M llvm/test/CodeGen/Hexagon/addrmode-keepdeadphis.ll
M llvm/test/CodeGen/Hexagon/addrmode-keepdeadphis.mir
M llvm/test/CodeGen/Hexagon/addrmode-no-rdef.mir
M llvm/test/CodeGen/Hexagon/addrmode-offset.ll
M llvm/test/CodeGen/Hexagon/addrmode-opt-assert.mir
M llvm/test/CodeGen/Hexagon/addrmode-rr-to-io.mir
M llvm/test/CodeGen/Hexagon/addsubcarry.ll
M llvm/test/CodeGen/Hexagon/adjust-latency-stackST.ll
M llvm/test/CodeGen/Hexagon/aggr-antidep-tied.ll
M llvm/test/CodeGen/Hexagon/aggr-copy-order.ll
M llvm/test/CodeGen/Hexagon/aggr-licm.ll
M llvm/test/CodeGen/Hexagon/aggressive_licm.ll
M llvm/test/CodeGen/Hexagon/align_Os.ll
M llvm/test/CodeGen/Hexagon/align_test.ll
M llvm/test/CodeGen/Hexagon/alu64.ll
M llvm/test/CodeGen/Hexagon/always-ext.ll
M llvm/test/CodeGen/Hexagon/anti-dep-partial.mir
M llvm/test/CodeGen/Hexagon/args.ll
M llvm/test/CodeGen/Hexagon/ashift-left-right.ll
M llvm/test/CodeGen/Hexagon/asr-rnd.ll
M llvm/test/CodeGen/Hexagon/asr-rnd64.ll
M llvm/test/CodeGen/Hexagon/assert-postinc-ptr-not-value.ll
M llvm/test/CodeGen/Hexagon/atomic-opaque-basic.ll
M llvm/test/CodeGen/Hexagon/atomic-rmw-add.ll
M llvm/test/CodeGen/Hexagon/atomicrmw-cond-sub-clamp.ll
M llvm/test/CodeGen/Hexagon/atomicrmw-uinc-udec-wrap.ll
M llvm/test/CodeGen/Hexagon/autohvx/abs.ll
M llvm/test/CodeGen/Hexagon/autohvx/addi-offset-opt-addr-mode.ll
M llvm/test/CodeGen/Hexagon/autohvx/addi-opt-predicated-def-bug.ll
M llvm/test/CodeGen/Hexagon/autohvx/align-128b.ll
M llvm/test/CodeGen/Hexagon/autohvx/align-64b.ll
M llvm/test/CodeGen/Hexagon/autohvx/align2-128b.ll
M llvm/test/CodeGen/Hexagon/autohvx/align2-64b.ll
M llvm/test/CodeGen/Hexagon/autohvx/arith-float.ll
M llvm/test/CodeGen/Hexagon/autohvx/arith.ll
M llvm/test/CodeGen/Hexagon/autohvx/bitcount-128b.ll
M llvm/test/CodeGen/Hexagon/autohvx/bitcount-64b.ll
M llvm/test/CodeGen/Hexagon/autohvx/bitwise-pred-128b.ll
M llvm/test/CodeGen/Hexagon/autohvx/bitwise-pred-64b.ll
M llvm/test/CodeGen/Hexagon/autohvx/bswap.ll
M llvm/test/CodeGen/Hexagon/autohvx/build-vector-float-type.ll
M llvm/test/CodeGen/Hexagon/autohvx/build-vector-i32-128b.ll
M llvm/test/CodeGen/Hexagon/autohvx/build-vector-i32-64b.ll
M llvm/test/CodeGen/Hexagon/autohvx/build-vector-i32-type.ll
M llvm/test/CodeGen/Hexagon/autohvx/calling-conv.ll
M llvm/test/CodeGen/Hexagon/autohvx/concat-vectors-128b.ll
M llvm/test/CodeGen/Hexagon/autohvx/concat-vectors-64b.ll
M llvm/test/CodeGen/Hexagon/autohvx/contract-128b.ll
M llvm/test/CodeGen/Hexagon/autohvx/contract-64b.ll
M llvm/test/CodeGen/Hexagon/autohvx/conv-fp-fp.ll
M llvm/test/CodeGen/Hexagon/autohvx/conv-fp-int-ieee.ll
M llvm/test/CodeGen/Hexagon/autohvx/ctpop-split.ll
M llvm/test/CodeGen/Hexagon/autohvx/deal-128b.ll
M llvm/test/CodeGen/Hexagon/autohvx/deal-64b.ll
M llvm/test/CodeGen/Hexagon/autohvx/delta-128b.ll
M llvm/test/CodeGen/Hexagon/autohvx/delta-64b.ll
M llvm/test/CodeGen/Hexagon/autohvx/delta2-64b.ll
M llvm/test/CodeGen/Hexagon/autohvx/extract-element.ll
M llvm/test/CodeGen/Hexagon/autohvx/float-cost.ll
M llvm/test/CodeGen/Hexagon/autohvx/fp-to-int.ll
M llvm/test/CodeGen/Hexagon/autohvx/funnel-128b.ll
M llvm/test/CodeGen/Hexagon/autohvx/hfinsert.ll
M llvm/test/CodeGen/Hexagon/autohvx/hvx-idiom-empty-results.ll
M llvm/test/CodeGen/Hexagon/autohvx/int-to-fp.ll
M llvm/test/CodeGen/Hexagon/autohvx/interleave.ll
M llvm/test/CodeGen/Hexagon/autohvx/isel-anyext-inreg.ll
M llvm/test/CodeGen/Hexagon/autohvx/isel-anyext-pair.ll
M llvm/test/CodeGen/Hexagon/autohvx/isel-bitcast-vsplat.ll
M llvm/test/CodeGen/Hexagon/autohvx/isel-bitcast-vsplat2.ll
M llvm/test/CodeGen/Hexagon/autohvx/isel-bool-vector.ll
M llvm/test/CodeGen/Hexagon/autohvx/isel-build-undef.ll
M llvm/test/CodeGen/Hexagon/autohvx/isel-build-vector.ll
M llvm/test/CodeGen/Hexagon/autohvx/isel-concat-multiple.ll
M llvm/test/CodeGen/Hexagon/autohvx/isel-concat-vectors-bool.ll
M llvm/test/CodeGen/Hexagon/autohvx/isel-concat-vectors.ll
M llvm/test/CodeGen/Hexagon/autohvx/isel-const-splat-bitcast.ll
M llvm/test/CodeGen/Hexagon/autohvx/isel-const-splat-imm.ll
M llvm/test/CodeGen/Hexagon/autohvx/isel-const-splat.ll
M llvm/test/CodeGen/Hexagon/autohvx/isel-const-vector.ll
M llvm/test/CodeGen/Hexagon/autohvx/isel-expand-unaligned-loads-noindexed.ll
M llvm/test/CodeGen/Hexagon/autohvx/isel-expand-unaligned-loads.ll
M llvm/test/CodeGen/Hexagon/autohvx/isel-extractelt-illegal-type.ll
M llvm/test/CodeGen/Hexagon/autohvx/isel-hvx-concat-truncate.ll
M llvm/test/CodeGen/Hexagon/autohvx/isel-hvx-pred-bitcast.ll
M llvm/test/CodeGen/Hexagon/autohvx/isel-insert-subvector-v4i8.ll
M llvm/test/CodeGen/Hexagon/autohvx/isel-intrinsics.ll
M llvm/test/CodeGen/Hexagon/autohvx/isel-mstore-fp16.ll
M llvm/test/CodeGen/Hexagon/autohvx/isel-q-legalization-loop.ll
M llvm/test/CodeGen/Hexagon/autohvx/isel-q2v-pair.ll
M llvm/test/CodeGen/Hexagon/autohvx/isel-qfalse.ll
M llvm/test/CodeGen/Hexagon/autohvx/isel-select-const.ll
M llvm/test/CodeGen/Hexagon/autohvx/isel-select-q.ll
M llvm/test/CodeGen/Hexagon/autohvx/isel-setcc-pair-fp.ll
M llvm/test/CodeGen/Hexagon/autohvx/isel-setcc-pair.ll
M llvm/test/CodeGen/Hexagon/autohvx/isel-setcc-v256i1.ll
M llvm/test/CodeGen/Hexagon/autohvx/isel-sext-inreg.ll
M llvm/test/CodeGen/Hexagon/autohvx/isel-shift-byte.ll
M llvm/test/CodeGen/Hexagon/autohvx/isel-shuff-single.ll
M llvm/test/CodeGen/Hexagon/autohvx/isel-shuffle-gather.ll
M llvm/test/CodeGen/Hexagon/autohvx/isel-shuffle-isdisel.ll
M llvm/test/CodeGen/Hexagon/autohvx/isel-shuffle-no-perfect-completion.ll
M llvm/test/CodeGen/Hexagon/autohvx/isel-shuffle-pack.ll
M llvm/test/CodeGen/Hexagon/autohvx/isel-split-masked.ll
M llvm/test/CodeGen/Hexagon/autohvx/isel-store-bitcast-v128i1.ll
M llvm/test/CodeGen/Hexagon/autohvx/isel-truncate-legal.ll
M llvm/test/CodeGen/Hexagon/autohvx/isel-truncate.ll
M llvm/test/CodeGen/Hexagon/autohvx/isel-undef-not-zero.ll
M llvm/test/CodeGen/Hexagon/autohvx/isel-vec-ext.ll
M llvm/test/CodeGen/Hexagon/autohvx/isel-vpackew.ll
M llvm/test/CodeGen/Hexagon/autohvx/isel-vsplat-pair.ll
M llvm/test/CodeGen/Hexagon/autohvx/isel-widen-memop.ll
M llvm/test/CodeGen/Hexagon/autohvx/isel-widen-store.ll
M llvm/test/CodeGen/Hexagon/autohvx/isel-widen-truncate-illegal-elem.ll
M llvm/test/CodeGen/Hexagon/autohvx/isel-widen-truncate-op.ll
M llvm/test/CodeGen/Hexagon/autohvx/isel-widen-truncate-pair.ll
M llvm/test/CodeGen/Hexagon/autohvx/isel-widen-truncate.ll
M llvm/test/CodeGen/Hexagon/autohvx/logical-128b.ll
M llvm/test/CodeGen/Hexagon/autohvx/logical-64b.ll
M llvm/test/CodeGen/Hexagon/autohvx/lower-insert-elt.ll
M llvm/test/CodeGen/Hexagon/autohvx/masked-vmem-basic.ll
M llvm/test/CodeGen/Hexagon/autohvx/maximize-bandwidth.ll
M llvm/test/CodeGen/Hexagon/autohvx/minmax-128b.ll
M llvm/test/CodeGen/Hexagon/autohvx/minmax-64b.ll
M llvm/test/CodeGen/Hexagon/autohvx/minmax-float.ll
M llvm/test/CodeGen/Hexagon/autohvx/mulh.ll
M llvm/test/CodeGen/Hexagon/autohvx/non-simple-hvx-type.ll
M llvm/test/CodeGen/Hexagon/autohvx/perfect-single.ll
M llvm/test/CodeGen/Hexagon/autohvx/pred-vmem-128b.ll
M llvm/test/CodeGen/Hexagon/autohvx/pred-vmem-64b.ll
M llvm/test/CodeGen/Hexagon/autohvx/qmul-add-over-32-bit.ll
M llvm/test/CodeGen/Hexagon/autohvx/qmul-chop.ll
M llvm/test/CodeGen/Hexagon/autohvx/qmul.ll
M llvm/test/CodeGen/Hexagon/autohvx/reg-sequence.ll
M llvm/test/CodeGen/Hexagon/autohvx/shift-128b.ll
M llvm/test/CodeGen/Hexagon/autohvx/shift-64b.ll
M llvm/test/CodeGen/Hexagon/autohvx/shuff-128b.ll
M llvm/test/CodeGen/Hexagon/autohvx/shuff-64b.ll
M llvm/test/CodeGen/Hexagon/autohvx/shuff-combos-128b.ll
M llvm/test/CodeGen/Hexagon/autohvx/shuff-combos-64b.ll
M llvm/test/CodeGen/Hexagon/autohvx/shuff-perfect-inverted-pair.ll
M llvm/test/CodeGen/Hexagon/autohvx/shuff-single.ll
M llvm/test/CodeGen/Hexagon/autohvx/shuffle-expanding-128b.ll
M llvm/test/CodeGen/Hexagon/autohvx/shuffle-expanding-64b.ll
M llvm/test/CodeGen/Hexagon/autohvx/shuffle-half-128b.ll
M llvm/test/CodeGen/Hexagon/autohvx/shuffle-half-64b.ll
M llvm/test/CodeGen/Hexagon/autohvx/splat.ll
M llvm/test/CodeGen/Hexagon/autohvx/vdd0.ll
M llvm/test/CodeGen/Hexagon/autohvx/vector-align-addr.ll
M llvm/test/CodeGen/Hexagon/autohvx/vector-align-bad-move.ll
M llvm/test/CodeGen/Hexagon/autohvx/vector-align-bad-move3.ll
M llvm/test/CodeGen/Hexagon/autohvx/vector-align-base-type-mismatch.ll
M llvm/test/CodeGen/Hexagon/autohvx/vector-align-basic.ll
M llvm/test/CodeGen/Hexagon/autohvx/vector-align-interleaved.ll
M llvm/test/CodeGen/Hexagon/autohvx/vector-align-only-phi-use.ll
M llvm/test/CodeGen/Hexagon/autohvx/vector-align-order.ll
M llvm/test/CodeGen/Hexagon/autohvx/vector-align-rescale-nonint.ll
M llvm/test/CodeGen/Hexagon/autohvx/vector-align-scalar-mask.ll
M llvm/test/CodeGen/Hexagon/autohvx/vector-align-store-mask.ll
M llvm/test/CodeGen/Hexagon/autohvx/vector-align-store.ll
M llvm/test/CodeGen/Hexagon/autohvx/vector-align-terminator.ll
M llvm/test/CodeGen/Hexagon/autohvx/vector-align-use-in-different-block.ll
M llvm/test/CodeGen/Hexagon/autohvx/vector-compare-128b.ll
M llvm/test/CodeGen/Hexagon/autohvx/vector-compare-64b.ll
M llvm/test/CodeGen/Hexagon/autohvx/vector-compare-float.ll
M llvm/test/CodeGen/Hexagon/autohvx/vector-load-store-basic.ll
M llvm/test/CodeGen/Hexagon/autohvx/vector-predicate-typecast.ll
M llvm/test/CodeGen/Hexagon/autohvx/vext-128b.ll
M llvm/test/CodeGen/Hexagon/autohvx/vext-64b.ll
M llvm/test/CodeGen/Hexagon/autohvx/vmpy-parts.ll
M llvm/test/CodeGen/Hexagon/autohvx/vmux-order.ll
M llvm/test/CodeGen/Hexagon/autohvx/widen-ext.ll
M llvm/test/CodeGen/Hexagon/autohvx/widen-setcc.ll
M llvm/test/CodeGen/Hexagon/autohvx/widen-trunc.ll
M llvm/test/CodeGen/Hexagon/avoid-predspill-calleesaved.ll
M llvm/test/CodeGen/Hexagon/avoid-predspill.ll
M llvm/test/CodeGen/Hexagon/avoidVectorLowering.ll
M llvm/test/CodeGen/Hexagon/bank-conflict-load.mir
M llvm/test/CodeGen/Hexagon/bank-conflict.mir
M llvm/test/CodeGen/Hexagon/barrier-flag.ll
M llvm/test/CodeGen/Hexagon/base-offset-addr.ll
M llvm/test/CodeGen/Hexagon/base-offset-post.ll
M llvm/test/CodeGen/Hexagon/base-offset-stv4.ll
M llvm/test/CodeGen/Hexagon/bit-addr-align.mir
M llvm/test/CodeGen/Hexagon/bit-bitsplit-at.ll
M llvm/test/CodeGen/Hexagon/bit-bitsplit-regclass.ll
M llvm/test/CodeGen/Hexagon/bit-bitsplit-src.ll
M llvm/test/CodeGen/Hexagon/bit-bitsplit.ll
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M llvm/test/CodeGen/Hexagon/bit-ext-sat.ll
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M llvm/test/CodeGen/Hexagon/bit-extract.ll
M llvm/test/CodeGen/Hexagon/bit-extractu-half.ll
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M llvm/test/CodeGen/Hexagon/bit-has.ll
M llvm/test/CodeGen/Hexagon/bit-loop-rc-mismatch.ll
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M llvm/test/CodeGen/Hexagon/bit-phi.ll
M llvm/test/CodeGen/Hexagon/bit-rie.ll
M llvm/test/CodeGen/Hexagon/bit-skip-byval.ll
M llvm/test/CodeGen/Hexagon/bit-store-upper-sub-hi.mir
M llvm/test/CodeGen/Hexagon/bit-validate-reg.ll
M llvm/test/CodeGen/Hexagon/bit-visit-flowq.ll
M llvm/test/CodeGen/Hexagon/bitcast-i128-to-v128i1.ll
M llvm/test/CodeGen/Hexagon/bitconvert-vector.ll
M llvm/test/CodeGen/Hexagon/bitmanip.ll
M llvm/test/CodeGen/Hexagon/bkfir.ll
M llvm/test/CodeGen/Hexagon/block-addr.ll
M llvm/test/CodeGen/Hexagon/block-address.ll
M llvm/test/CodeGen/Hexagon/block-ranges-nodef.ll
M llvm/test/CodeGen/Hexagon/blockaddr-fpic.ll
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M llvm/test/CodeGen/Hexagon/branch-non-mbb.ll
M llvm/test/CodeGen/Hexagon/branchfolder-insert-impdef.mir
M llvm/test/CodeGen/Hexagon/branchfolder-keep-impdef.ll
M llvm/test/CodeGen/Hexagon/brcond-setne.ll
M llvm/test/CodeGen/Hexagon/brev_ld.ll
M llvm/test/CodeGen/Hexagon/brev_st.ll
M llvm/test/CodeGen/Hexagon/bss-local.ll
M llvm/test/CodeGen/Hexagon/bug-aa4463-ifconv-vecpred.ll
M llvm/test/CodeGen/Hexagon/bug-allocframe-size.ll
M llvm/test/CodeGen/Hexagon/bug-hcp-tied-kill.ll
M llvm/test/CodeGen/Hexagon/bug14859-iv-cleanup-lpad.ll
M llvm/test/CodeGen/Hexagon/bug14859-split-const-block-addr.ll
M llvm/test/CodeGen/Hexagon/bug15515-shuffle.ll
M llvm/test/CodeGen/Hexagon/bug17276.ll
M llvm/test/CodeGen/Hexagon/bug17386.ll
M llvm/test/CodeGen/Hexagon/bug18008.ll
M llvm/test/CodeGen/Hexagon/bug18491-optsize.ll
M llvm/test/CodeGen/Hexagon/bug19076.ll
M llvm/test/CodeGen/Hexagon/bug19119.ll
M llvm/test/CodeGen/Hexagon/bug19254-ifconv-vec.ll
M llvm/test/CodeGen/Hexagon/bug27085.ll
M llvm/test/CodeGen/Hexagon/bug31839.ll
M llvm/test/CodeGen/Hexagon/bug6757-endloop.ll
M llvm/test/CodeGen/Hexagon/bug9049.ll
M llvm/test/CodeGen/Hexagon/bug9963.ll
M llvm/test/CodeGen/Hexagon/bugAsmHWloop.ll
M llvm/test/CodeGen/Hexagon/build-vector-shuffle.ll
M llvm/test/CodeGen/Hexagon/build-vector-v4i8-zext.ll
M llvm/test/CodeGen/Hexagon/builtin-expect.ll
M llvm/test/CodeGen/Hexagon/builtin-prefetch-offset.ll
M llvm/test/CodeGen/Hexagon/builtin-prefetch.ll
M llvm/test/CodeGen/Hexagon/call-long1.ll
M llvm/test/CodeGen/Hexagon/call-ret-i1.ll
M llvm/test/CodeGen/Hexagon/call-v4.ll
M llvm/test/CodeGen/Hexagon/callR_noreturn.ll
M llvm/test/CodeGen/Hexagon/calling-conv-2.ll
M llvm/test/CodeGen/Hexagon/calling-conv.ll
M llvm/test/CodeGen/Hexagon/callr-dep-edge.ll
M llvm/test/CodeGen/Hexagon/cext-check.ll
M llvm/test/CodeGen/Hexagon/cext-ice.ll
M llvm/test/CodeGen/Hexagon/cext-opt-basic.mir
M llvm/test/CodeGen/Hexagon/cext-opt-block-addr.mir
M llvm/test/CodeGen/Hexagon/cext-opt-negative-fi.mir
M llvm/test/CodeGen/Hexagon/cext-opt-numops.mir
M llvm/test/CodeGen/Hexagon/cext-opt-range-assert.mir
M llvm/test/CodeGen/Hexagon/cext-opt-range-offset.mir
M llvm/test/CodeGen/Hexagon/cext-opt-shifted-range.mir
M llvm/test/CodeGen/Hexagon/cext-opt-stack-no-rr.mir
M llvm/test/CodeGen/Hexagon/cext-unnamed-global.mir
M llvm/test/CodeGen/Hexagon/cext-valid-packet1.ll
M llvm/test/CodeGen/Hexagon/cext-valid-packet2.ll
M llvm/test/CodeGen/Hexagon/cext.ll
M llvm/test/CodeGen/Hexagon/cexti16.ll
M llvm/test/CodeGen/Hexagon/cfgopt-fall-through.ll
M llvm/test/CodeGen/Hexagon/cfi-late-and-regpressure-init.ll
M llvm/test/CodeGen/Hexagon/cfi-late.ll
M llvm/test/CodeGen/Hexagon/cfi-offset.ll
M llvm/test/CodeGen/Hexagon/cfi_offset.ll
M llvm/test/CodeGen/Hexagon/cfi_offset2.ll
M llvm/test/CodeGen/Hexagon/check-dot-new.ll
M llvm/test/CodeGen/Hexagon/check-subregister-for-latency.ll
M llvm/test/CodeGen/Hexagon/checktabs.ll
M llvm/test/CodeGen/Hexagon/circ-load-isel.ll
M llvm/test/CodeGen/Hexagon/circ_ld.ll
M llvm/test/CodeGen/Hexagon/circ_ldd_bug.ll
M llvm/test/CodeGen/Hexagon/circ_ldw.ll
M llvm/test/CodeGen/Hexagon/circ_new.ll
M llvm/test/CodeGen/Hexagon/circ_pcr_assert.ll
M llvm/test/CodeGen/Hexagon/circ_st.ll
M llvm/test/CodeGen/Hexagon/clr_set_toggle.ll
M llvm/test/CodeGen/Hexagon/cmp-extend.ll
M llvm/test/CodeGen/Hexagon/cmp-promote.ll
M llvm/test/CodeGen/Hexagon/cmp-to-genreg.ll
M llvm/test/CodeGen/Hexagon/cmp-to-predreg.ll
M llvm/test/CodeGen/Hexagon/cmp_pred.ll
M llvm/test/CodeGen/Hexagon/cmp_pred2.ll
M llvm/test/CodeGen/Hexagon/cmp_pred_reg.ll
M llvm/test/CodeGen/Hexagon/cmpb-dec-imm.ll
M llvm/test/CodeGen/Hexagon/cmpb-eq.ll
M llvm/test/CodeGen/Hexagon/cmpb_gtu.ll
M llvm/test/CodeGen/Hexagon/cmpb_pred.ll
M llvm/test/CodeGen/Hexagon/cmpbeq.ll
M llvm/test/CodeGen/Hexagon/cmph-gtu.ll
M llvm/test/CodeGen/Hexagon/cmpy-round.ll
M llvm/test/CodeGen/Hexagon/coalesce_tfri.ll
M llvm/test/CodeGen/Hexagon/coalescing-hvx-across-calls.ll
M llvm/test/CodeGen/Hexagon/combine-imm-ext.ll
M llvm/test/CodeGen/Hexagon/combine-imm-ext2.ll
M llvm/test/CodeGen/Hexagon/combine.ll
M llvm/test/CodeGen/Hexagon/combine_ir.ll
M llvm/test/CodeGen/Hexagon/combine_lh.ll
M llvm/test/CodeGen/Hexagon/combiner-lts.ll
M llvm/test/CodeGen/Hexagon/common-gep-basic.ll
M llvm/test/CodeGen/Hexagon/common-gep-icm.ll
M llvm/test/CodeGen/Hexagon/common-gep-inbounds.ll
M llvm/test/CodeGen/Hexagon/common-global-addr.ll
M llvm/test/CodeGen/Hexagon/concat-vectors-legalize.ll
M llvm/test/CodeGen/Hexagon/const-combine.ll
M llvm/test/CodeGen/Hexagon/const-pool-tf.ll
M llvm/test/CodeGen/Hexagon/constant_compound.ll
M llvm/test/CodeGen/Hexagon/constext-call.ll
M llvm/test/CodeGen/Hexagon/constext-immstore.ll
M llvm/test/CodeGen/Hexagon/constext-replace.ll
M llvm/test/CodeGen/Hexagon/constp-andir-global.mir
M llvm/test/CodeGen/Hexagon/constp-clb.ll
M llvm/test/CodeGen/Hexagon/constp-combine-neg.ll
M llvm/test/CodeGen/Hexagon/constp-ctb.ll
M llvm/test/CodeGen/Hexagon/constp-extract.ll
M llvm/test/CodeGen/Hexagon/constp-rewrite-branches.ll
M llvm/test/CodeGen/Hexagon/constp-rseq.ll
M llvm/test/CodeGen/Hexagon/constp-vsplat.ll
M llvm/test/CodeGen/Hexagon/convert_const_i1_to_i8.ll
M llvm/test/CodeGen/Hexagon/convertdptoint.ll
M llvm/test/CodeGen/Hexagon/convertdptoll.ll
M llvm/test/CodeGen/Hexagon/convertsptoint.ll
M llvm/test/CodeGen/Hexagon/convertsptoll.ll
M llvm/test/CodeGen/Hexagon/copy-to-combine-const64.mir
M llvm/test/CodeGen/Hexagon/copy-to-combine-dbg.ll
M llvm/test/CodeGen/Hexagon/count_0s.ll
M llvm/test/CodeGen/Hexagon/countbits-basic.ll
M llvm/test/CodeGen/Hexagon/csr-func-usedef.ll
M llvm/test/CodeGen/Hexagon/csr_stub_calls_dwarf_frame_info.ll
M llvm/test/CodeGen/Hexagon/ctor.ll
M llvm/test/CodeGen/Hexagon/dadd.ll
M llvm/test/CodeGen/Hexagon/dag-combine-select-or0.ll
M llvm/test/CodeGen/Hexagon/dag-indexed.ll
M llvm/test/CodeGen/Hexagon/dccleana.ll
M llvm/test/CodeGen/Hexagon/dead-store-stack.ll
M llvm/test/CodeGen/Hexagon/dealloc-store.ll
M llvm/test/CodeGen/Hexagon/dealloc_return.ll
M llvm/test/CodeGen/Hexagon/debug-line_table_start.ll
M llvm/test/CodeGen/Hexagon/debug-prologue-loc.ll
M llvm/test/CodeGen/Hexagon/debug-prologue.ll
M llvm/test/CodeGen/Hexagon/def-undef-deps.ll
M llvm/test/CodeGen/Hexagon/default-align.ll
M llvm/test/CodeGen/Hexagon/deflate.ll
M llvm/test/CodeGen/Hexagon/df-min-max.ll
M llvm/test/CodeGen/Hexagon/dfp.ll
M llvm/test/CodeGen/Hexagon/dhry.ll
M llvm/test/CodeGen/Hexagon/dhry_proc8.ll
M llvm/test/CodeGen/Hexagon/dhry_stall.ll
M llvm/test/CodeGen/Hexagon/disable-const64.ll
M llvm/test/CodeGen/Hexagon/dmul.ll
M llvm/test/CodeGen/Hexagon/dont_rotate_pregs_at_O2.ll
M llvm/test/CodeGen/Hexagon/double.ll
M llvm/test/CodeGen/Hexagon/dsub.ll
M llvm/test/CodeGen/Hexagon/duplex-addi-global-imm.mir
M llvm/test/CodeGen/Hexagon/dwarf-discriminator.ll
M llvm/test/CodeGen/Hexagon/early-if-conv-lifetime.mir
M llvm/test/CodeGen/Hexagon/early-if-conversion-bug1.ll
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M llvm/test/CodeGen/Hexagon/early-if-low8.mir
M llvm/test/CodeGen/Hexagon/early-if-merge-loop.ll
M llvm/test/CodeGen/Hexagon/early-if-phi-i1.ll
M llvm/test/CodeGen/Hexagon/early-if-predicator.mir
M llvm/test/CodeGen/Hexagon/early-if-spare.ll
M llvm/test/CodeGen/Hexagon/early-if-vecpi.ll
M llvm/test/CodeGen/Hexagon/early-if-vecpred.ll
M llvm/test/CodeGen/Hexagon/early-if.ll
M llvm/test/CodeGen/Hexagon/eh_return-r30.ll
M llvm/test/CodeGen/Hexagon/eh_return.ll
M llvm/test/CodeGen/Hexagon/eh_save_restore.ll
M llvm/test/CodeGen/Hexagon/ehabi.ll
M llvm/test/CodeGen/Hexagon/eliminate-pred-spill.ll
M llvm/test/CodeGen/Hexagon/entryBB-isLoopHdr.ll
M llvm/test/CodeGen/Hexagon/expand-condsets-basic.ll
M llvm/test/CodeGen/Hexagon/expand-condsets-copy-lis.ll
M llvm/test/CodeGen/Hexagon/expand-condsets-dead-bad.ll
M llvm/test/CodeGen/Hexagon/expand-condsets-dead-pred.ll
M llvm/test/CodeGen/Hexagon/expand-condsets-dead.ll
M llvm/test/CodeGen/Hexagon/expand-condsets-def-undef.mir
M llvm/test/CodeGen/Hexagon/expand-condsets-extend.ll
M llvm/test/CodeGen/Hexagon/expand-condsets-imm.mir
M llvm/test/CodeGen/Hexagon/expand-condsets-impuse.mir
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M llvm/test/CodeGen/Hexagon/expand-condsets-phys-reg.mir
M llvm/test/CodeGen/Hexagon/expand-condsets-pred-undef.ll
M llvm/test/CodeGen/Hexagon/expand-condsets-pred-undef2.ll
M llvm/test/CodeGen/Hexagon/expand-condsets-rm-reg.mir
M llvm/test/CodeGen/Hexagon/expand-condsets-rm-segment.ll
M llvm/test/CodeGen/Hexagon/expand-condsets-same-inputs.mir
M llvm/test/CodeGen/Hexagon/expand-condsets-undef2.ll
M llvm/test/CodeGen/Hexagon/expand-condsets-undefvni.ll
M llvm/test/CodeGen/Hexagon/expand-condsets.ll
M llvm/test/CodeGen/Hexagon/expand-copyw-undef.mir
M llvm/test/CodeGen/Hexagon/expand-vselect-kill.mir
M llvm/test/CodeGen/Hexagon/expand-vstorerw-undef.ll
M llvm/test/CodeGen/Hexagon/expand-vstorerw-undef2.ll
M llvm/test/CodeGen/Hexagon/expand-wselect.mir
M llvm/test/CodeGen/Hexagon/extload-combine.ll
M llvm/test/CodeGen/Hexagon/extract-basic.ll
M llvm/test/CodeGen/Hexagon/extract_0bits.ll
M llvm/test/CodeGen/Hexagon/extractu_0bits.ll
M llvm/test/CodeGen/Hexagon/fadd.ll
M llvm/test/CodeGen/Hexagon/fcmp.ll
M llvm/test/CodeGen/Hexagon/feature-compound.ll
M llvm/test/CodeGen/Hexagon/feature-memops.ll
M llvm/test/CodeGen/Hexagon/find-loop-instr.ll
M llvm/test/CodeGen/Hexagon/find-loop.ll
M llvm/test/CodeGen/Hexagon/fixed-spill-mutable.ll
M llvm/test/CodeGen/Hexagon/float-amode.ll
M llvm/test/CodeGen/Hexagon/float-bitcast.ll
M llvm/test/CodeGen/Hexagon/float-const64-G0.ll
M llvm/test/CodeGen/Hexagon/float-gen-cmpop.ll
M llvm/test/CodeGen/Hexagon/float.ll
M llvm/test/CodeGen/Hexagon/floatconvert-ieee-rnd-near.ll
M llvm/test/CodeGen/Hexagon/fltnvjump.ll
M llvm/test/CodeGen/Hexagon/fmadd.ll
M llvm/test/CodeGen/Hexagon/fminmax.ll
M llvm/test/CodeGen/Hexagon/fmul-v67.ll
M llvm/test/CodeGen/Hexagon/fmul.ll
M llvm/test/CodeGen/Hexagon/formal-args-i1.ll
M llvm/test/CodeGen/Hexagon/fp16.ll
M llvm/test/CodeGen/Hexagon/fp_latency.ll
M llvm/test/CodeGen/Hexagon/fpelim-basic.ll
M llvm/test/CodeGen/Hexagon/frame-offset-overflow.ll
M llvm/test/CodeGen/Hexagon/fsel.ll
M llvm/test/CodeGen/Hexagon/fsub.ll
M llvm/test/CodeGen/Hexagon/funnel-shift.ll
M llvm/test/CodeGen/Hexagon/fusedandshift.ll
M llvm/test/CodeGen/Hexagon/generate-const-buildvector32.ll
M llvm/test/CodeGen/Hexagon/getBlockAddress.ll
M llvm/test/CodeGen/Hexagon/glob-align-volatile.ll
M llvm/test/CodeGen/Hexagon/global-const-gep.ll
M llvm/test/CodeGen/Hexagon/global-ctor-pcrel.ll
M llvm/test/CodeGen/Hexagon/global64bitbug.ll
M llvm/test/CodeGen/Hexagon/gp-plus-offset-load.ll
M llvm/test/CodeGen/Hexagon/gp-plus-offset-store.ll
M llvm/test/CodeGen/Hexagon/gp-rel.ll
M llvm/test/CodeGen/Hexagon/hasfp-crash1.ll
M llvm/test/CodeGen/Hexagon/hasfp-crash2.ll
M llvm/test/CodeGen/Hexagon/hello-world-v55.ll
M llvm/test/CodeGen/Hexagon/hello-world-v60.ll
M llvm/test/CodeGen/Hexagon/hexagon-cond-jumpr31.ll
M llvm/test/CodeGen/Hexagon/hexagon-copy-hoisting.mir
M llvm/test/CodeGen/Hexagon/hexagon-tfr-add.ll
M llvm/test/CodeGen/Hexagon/hexagon-verify-implicit-use.ll
M llvm/test/CodeGen/Hexagon/hexagon_cfi_offset.ll
M llvm/test/CodeGen/Hexagon/hidden-relocation.ll
M llvm/test/CodeGen/Hexagon/honor-optsize.ll
M llvm/test/CodeGen/Hexagon/hrc-stack-coloring.ll
M llvm/test/CodeGen/Hexagon/hvx-bitcast-v64i1.ll
M llvm/test/CodeGen/Hexagon/hvx-byte-store-double.ll
M llvm/test/CodeGen/Hexagon/hvx-byte-store.ll
M llvm/test/CodeGen/Hexagon/hvx-concat-lower.ll
M llvm/test/CodeGen/Hexagon/hvx-dbl-dual-output.ll
M llvm/test/CodeGen/Hexagon/hvx-double-vzero.ll
M llvm/test/CodeGen/Hexagon/hvx-dual-output.ll
M llvm/test/CodeGen/Hexagon/hvx-isel-vselect-v256i16.ll
M llvm/test/CodeGen/Hexagon/hvx-nontemporal.ll
M llvm/test/CodeGen/Hexagon/hvx-reuse-fi-base.ll
M llvm/test/CodeGen/Hexagon/hvx-vzero.ll
M llvm/test/CodeGen/Hexagon/hwloop-cleanup.ll
M llvm/test/CodeGen/Hexagon/hwloop-const.ll
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M llvm/test/CodeGen/Hexagon/hwloop-dbg-register.mir
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M llvm/test/CodeGen/Hexagon/hwloop-le.ll
M llvm/test/CodeGen/Hexagon/hwloop-long.ll
M llvm/test/CodeGen/Hexagon/hwloop-loop1.ll
M llvm/test/CodeGen/Hexagon/hwloop-lt.ll
M llvm/test/CodeGen/Hexagon/hwloop-lt1.ll
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M llvm/test/CodeGen/Hexagon/hwloop-ne.ll
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M llvm/test/CodeGen/Hexagon/hwloop-ph-deadcode.ll
M llvm/test/CodeGen/Hexagon/hwloop-phi-subreg.ll
M llvm/test/CodeGen/Hexagon/hwloop-pos-ivbump1.ll
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M llvm/test/CodeGen/Hexagon/hwloop-preheader.ll
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M llvm/test/CodeGen/Hexagon/hwloop-recursion.ll
M llvm/test/CodeGen/Hexagon/hwloop-redef-imm.mir
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M llvm/test/CodeGen/Hexagon/hwloop-swap.ll
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M llvm/test/CodeGen/Hexagon/hwloop-wrap.ll
M llvm/test/CodeGen/Hexagon/hwloop-wrap2.ll
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M llvm/test/CodeGen/Hexagon/hwloop2.ll
M llvm/test/CodeGen/Hexagon/hwloop3.ll
M llvm/test/CodeGen/Hexagon/hwloop4.ll
M llvm/test/CodeGen/Hexagon/hwloop5.ll
M llvm/test/CodeGen/Hexagon/hx_V6_lo_hi.ll
M llvm/test/CodeGen/Hexagon/i128-bitop.ll
M llvm/test/CodeGen/Hexagon/i16_VarArg.ll
M llvm/test/CodeGen/Hexagon/i1_VarArg.ll
M llvm/test/CodeGen/Hexagon/i8_VarArg.ll
M llvm/test/CodeGen/Hexagon/idxload-with-zero-offset.ll
M llvm/test/CodeGen/Hexagon/ifcvt-common-kill.mir
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M llvm/test/CodeGen/Hexagon/split-vecpred.ll
M llvm/test/CodeGen/Hexagon/stack-align-reset.ll
M llvm/test/CodeGen/Hexagon/stack-align1.ll
M llvm/test/CodeGen/Hexagon/stack-align2.ll
M llvm/test/CodeGen/Hexagon/stack-alloca1.ll
M llvm/test/CodeGen/Hexagon/stack-alloca2.ll
M llvm/test/CodeGen/Hexagon/stack-guard-acceptable-type.ll
M llvm/test/CodeGen/Hexagon/static.ll
M llvm/test/CodeGen/Hexagon/store-AbsSet.ll
M llvm/test/CodeGen/Hexagon/store-abs.ll
M llvm/test/CodeGen/Hexagon/store-const-extend-opt.ll
M llvm/test/CodeGen/Hexagon/store-constant.ll
M llvm/test/CodeGen/Hexagon/store-imm-amode.ll
M llvm/test/CodeGen/Hexagon/store-imm-byte.ll
M llvm/test/CodeGen/Hexagon/store-imm-halword.ll
M llvm/test/CodeGen/Hexagon/store-imm-large-stack.ll
M llvm/test/CodeGen/Hexagon/store-imm-stack-object.ll
M llvm/test/CodeGen/Hexagon/store-imm-word.ll
M llvm/test/CodeGen/Hexagon/store-shift.ll
M llvm/test/CodeGen/Hexagon/store-vector-pred.ll
M llvm/test/CodeGen/Hexagon/store-widen-aliased-load.ll
M llvm/test/CodeGen/Hexagon/store-widen-negv.ll
M llvm/test/CodeGen/Hexagon/store-widen-negv2.ll
M llvm/test/CodeGen/Hexagon/store-widen-subreg.ll
M llvm/test/CodeGen/Hexagon/store-widen.ll
M llvm/test/CodeGen/Hexagon/store1.ll
M llvm/test/CodeGen/Hexagon/store_abs.ll
M llvm/test/CodeGen/Hexagon/storerd-io-over-rr.ll
M llvm/test/CodeGen/Hexagon/storerinewabs.ll
M llvm/test/CodeGen/Hexagon/struct-const.ll
M llvm/test/CodeGen/Hexagon/struct_args.ll
M llvm/test/CodeGen/Hexagon/struct_args_large.ll
M llvm/test/CodeGen/Hexagon/struct_copy.ll
M llvm/test/CodeGen/Hexagon/struct_copy_sched_r16.ll
M llvm/test/CodeGen/Hexagon/sub-add.ll
M llvm/test/CodeGen/Hexagon/subh-shifted.ll
M llvm/test/CodeGen/Hexagon/subh.ll
M llvm/test/CodeGen/Hexagon/subi-asl.ll
M llvm/test/CodeGen/Hexagon/swp-art-deps-rec.ll
M llvm/test/CodeGen/Hexagon/swp-bad-sched.ll
M llvm/test/CodeGen/Hexagon/swp-badorder.ll
M llvm/test/CodeGen/Hexagon/swp-carried-1.ll
M llvm/test/CodeGen/Hexagon/swp-chain-refs.ll
M llvm/test/CodeGen/Hexagon/swp-change-dep-cycle.ll
M llvm/test/CodeGen/Hexagon/swp-change-dep.ll
M llvm/test/CodeGen/Hexagon/swp-change-dep1.ll
M llvm/test/CodeGen/Hexagon/swp-change-deps.ll
M llvm/test/CodeGen/Hexagon/swp-check-offset.ll
M llvm/test/CodeGen/Hexagon/swp-const-tc.ll
M llvm/test/CodeGen/Hexagon/swp-const-tc1.ll
M llvm/test/CodeGen/Hexagon/swp-const-tc2.ll
M llvm/test/CodeGen/Hexagon/swp-const-tc3.ll
M llvm/test/CodeGen/Hexagon/swp-conv3x3-nested.ll
M llvm/test/CodeGen/Hexagon/swp-copytophi-dag.ll
M llvm/test/CodeGen/Hexagon/swp-crash-iter.ll
M llvm/test/CodeGen/Hexagon/swp-cse-phi.ll
M llvm/test/CodeGen/Hexagon/swp-dag-phi.ll
M llvm/test/CodeGen/Hexagon/swp-dag-phi1.ll
M llvm/test/CodeGen/Hexagon/swp-dead-regseq.ll
M llvm/test/CodeGen/Hexagon/swp-dep-neg-offset.ll
M llvm/test/CodeGen/Hexagon/swp-disable-Os.ll
M llvm/test/CodeGen/Hexagon/swp-epilog-numphis.ll
M llvm/test/CodeGen/Hexagon/swp-epilog-phi10.ll
M llvm/test/CodeGen/Hexagon/swp-epilog-phi12.ll
M llvm/test/CodeGen/Hexagon/swp-epilog-phi13.ll
M llvm/test/CodeGen/Hexagon/swp-epilog-phi2.ll
M llvm/test/CodeGen/Hexagon/swp-epilog-phi4.ll
M llvm/test/CodeGen/Hexagon/swp-epilog-phi5.ll
M llvm/test/CodeGen/Hexagon/swp-epilog-phi6.ll
M llvm/test/CodeGen/Hexagon/swp-epilog-phi7.ll
M llvm/test/CodeGen/Hexagon/swp-epilog-phi8.ll
M llvm/test/CodeGen/Hexagon/swp-epilog-phi9.ll
M llvm/test/CodeGen/Hexagon/swp-epilog-reuse-1.ll
M llvm/test/CodeGen/Hexagon/swp-epilog-reuse.ll
M llvm/test/CodeGen/Hexagon/swp-epilog-reuse2.ll
M llvm/test/CodeGen/Hexagon/swp-epilog-reuse3.ll
M llvm/test/CodeGen/Hexagon/swp-epilog-reuse4.ll
M llvm/test/CodeGen/Hexagon/swp-exit-fixup.ll
M llvm/test/CodeGen/Hexagon/swp-fix-last-use.ll
M llvm/test/CodeGen/Hexagon/swp-fix-last-use1.ll
M llvm/test/CodeGen/Hexagon/swp-intreglow8.ll
M llvm/test/CodeGen/Hexagon/swp-kernel-last-use.ll
M llvm/test/CodeGen/Hexagon/swp-kernel-phi1.ll
M llvm/test/CodeGen/Hexagon/swp-large-rec.ll
M llvm/test/CodeGen/Hexagon/swp-listen-loop3.ll
M llvm/test/CodeGen/Hexagon/swp-loop-carried-crash.ll
M llvm/test/CodeGen/Hexagon/swp-loop-carried-unknown.ll
M llvm/test/CodeGen/Hexagon/swp-loop-carried.ll
M llvm/test/CodeGen/Hexagon/swp-loopval.ll
M llvm/test/CodeGen/Hexagon/swp-lots-deps.ll
M llvm/test/CodeGen/Hexagon/swp-matmul-bitext.ll
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M llvm/test/CodeGen/Hexagon/swp-max.ll
M llvm/test/CodeGen/Hexagon/swp-maxstart.ll
M llvm/test/CodeGen/Hexagon/swp-memrefs-epilog.ll
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M llvm/test/CodeGen/Hexagon/swp-multi-phi-refs.ll
M llvm/test/CodeGen/Hexagon/swp-new-phi.ll
M llvm/test/CodeGen/Hexagon/swp-node-order.ll
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M llvm/test/CodeGen/Hexagon/swp-order-copies.ll
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M llvm/test/CodeGen/Hexagon/swp-order-deps3.ll
M llvm/test/CodeGen/Hexagon/swp-order-deps4.ll
M llvm/test/CodeGen/Hexagon/swp-order-deps5.ll
M llvm/test/CodeGen/Hexagon/swp-order-deps6.ll
M llvm/test/CodeGen/Hexagon/swp-order-deps7.ll
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M llvm/test/CodeGen/Hexagon/swp-order1.ll
M llvm/test/CodeGen/Hexagon/swp-phi-ch-offset.ll
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M llvm/test/CodeGen/Hexagon/swp-phi-def-use.ll
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M llvm/test/CodeGen/Hexagon/swp-phi-dep1.ll
M llvm/test/CodeGen/Hexagon/swp-phi-order.ll
M llvm/test/CodeGen/Hexagon/swp-phi-ref.ll
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M llvm/test/CodeGen/Hexagon/swp-prolog-phi4.ll
M llvm/test/CodeGen/Hexagon/swp-regseq.ll
M llvm/test/CodeGen/Hexagon/swp-remove-dep-ice.ll
M llvm/test/CodeGen/Hexagon/swp-rename-dead-phi.ll
M llvm/test/CodeGen/Hexagon/swp-rename.ll
M llvm/test/CodeGen/Hexagon/swp-replace-uses1.ll
M llvm/test/CodeGen/Hexagon/swp-resmii-1.ll
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M llvm/test/CodeGen/Hexagon/swp-stages.ll
M llvm/test/CodeGen/Hexagon/swp-stages3.ll
M llvm/test/CodeGen/Hexagon/swp-stages4.ll
M llvm/test/CodeGen/Hexagon/swp-stages5.ll
M llvm/test/CodeGen/Hexagon/swp-subreg.ll
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M llvm/test/CodeGen/Hexagon/tail-call-mem-intrinsics.ll
M llvm/test/CodeGen/Hexagon/tail-call-trunc.ll
M llvm/test/CodeGen/Hexagon/tail-dup-subreg-abort.ll
M llvm/test/CodeGen/Hexagon/tail-dup-subreg-map.ll
M llvm/test/CodeGen/Hexagon/tailcall_fastcc_ccc.ll
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M llvm/test/CodeGen/Hexagon/tc_duplex.ll
M llvm/test/CodeGen/Hexagon/tc_sched.ll
M llvm/test/CodeGen/Hexagon/tc_sched1.ll
M llvm/test/CodeGen/Hexagon/tcm-zext.ll
M llvm/test/CodeGen/Hexagon/testbits.ll
M llvm/test/CodeGen/Hexagon/tfr-cleanup.ll
M llvm/test/CodeGen/Hexagon/tfr-mux-nvj.ll
M llvm/test/CodeGen/Hexagon/tfr-to-combine.ll
M llvm/test/CodeGen/Hexagon/tied_oper.ll
M llvm/test/CodeGen/Hexagon/tiny_bkfir_artdeps.ll
M llvm/test/CodeGen/Hexagon/tiny_bkfir_loop_align.ll
M llvm/test/CodeGen/Hexagon/tinycore.ll
M llvm/test/CodeGen/Hexagon/tls_gd.ll
M llvm/test/CodeGen/Hexagon/tls_pic.ll
M llvm/test/CodeGen/Hexagon/trap-crash.ll
M llvm/test/CodeGen/Hexagon/trap-unreachable.ll
M llvm/test/CodeGen/Hexagon/trivialmemaliascheck.ll
M llvm/test/CodeGen/Hexagon/trunc-mpy.ll
M llvm/test/CodeGen/Hexagon/two-crash.ll
M llvm/test/CodeGen/Hexagon/twoaddressbug.ll
M llvm/test/CodeGen/Hexagon/undef-ret.ll
M llvm/test/CodeGen/Hexagon/undo-dag-shift.ll
M llvm/test/CodeGen/Hexagon/union-1.ll
M llvm/test/CodeGen/Hexagon/unordered-fcmp.ll
M llvm/test/CodeGen/Hexagon/unreachable-mbb-phi-subreg.mir
M llvm/test/CodeGen/Hexagon/upper-mpy.ll
M llvm/test/CodeGen/Hexagon/v5_insns.ll
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M llvm/test/CodeGen/Hexagon/v6-inlasm1.ll
M llvm/test/CodeGen/Hexagon/v6-inlasm2.ll
M llvm/test/CodeGen/Hexagon/v6-inlasm3.ll
M llvm/test/CodeGen/Hexagon/v6-inlasm4.ll
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M llvm/test/CodeGen/Hexagon/v6-spill1.ll
M llvm/test/CodeGen/Hexagon/v6-unaligned-spill.ll
M llvm/test/CodeGen/Hexagon/v6-vecpred-copy.ll
M llvm/test/CodeGen/Hexagon/v60-align.ll
M llvm/test/CodeGen/Hexagon/v60-cur.ll
M llvm/test/CodeGen/Hexagon/v60-haar-postinc.ll
M llvm/test/CodeGen/Hexagon/v60-halide-vcombinei8.ll
M llvm/test/CodeGen/Hexagon/v60-vec-128b-1.ll
M llvm/test/CodeGen/Hexagon/v60-vecpred-spill.ll
M llvm/test/CodeGen/Hexagon/v60-vsel1.ll
M llvm/test/CodeGen/Hexagon/v60-vsel2.ll
M llvm/test/CodeGen/Hexagon/v60Intrins.ll
M llvm/test/CodeGen/Hexagon/v60Vasr.ll
M llvm/test/CodeGen/Hexagon/v60_Q6_P_rol_PI.ll
M llvm/test/CodeGen/Hexagon/v60_sort16.ll
M llvm/test/CodeGen/Hexagon/v60rol-instrs.ll
M llvm/test/CodeGen/Hexagon/v60small.ll
M llvm/test/CodeGen/Hexagon/v62-CJAllSlots.ll
M llvm/test/CodeGen/Hexagon/v62-inlasm4.ll
M llvm/test/CodeGen/Hexagon/v6vassignp.ll
M llvm/test/CodeGen/Hexagon/v6vec-vmemcur-prob.mir
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M llvm/test/CodeGen/Hexagon/v6vec-vmemu2.ll
M llvm/test/CodeGen/Hexagon/v6vec-vprint.ll
M llvm/test/CodeGen/Hexagon/v6vec-vshuff.ll
M llvm/test/CodeGen/Hexagon/v6vec_inc1.ll
M llvm/test/CodeGen/Hexagon/v6vec_zero.ll
M llvm/test/CodeGen/Hexagon/v6vect-dbl-fail1.ll
M llvm/test/CodeGen/Hexagon/v6vect-dbl-spill.ll
M llvm/test/CodeGen/Hexagon/v6vect-dbl.ll
M llvm/test/CodeGen/Hexagon/v6vect-dh1.ll
M llvm/test/CodeGen/Hexagon/v6vect-locals1.ll
M llvm/test/CodeGen/Hexagon/v6vect-no-sideeffects.ll
M llvm/test/CodeGen/Hexagon/v6vect-pred2.ll
M llvm/test/CodeGen/Hexagon/v6vect-spill-kill.ll
M llvm/test/CodeGen/Hexagon/v6vect-vmem1.ll
M llvm/test/CodeGen/Hexagon/v6vect-vsplat.ll
M llvm/test/CodeGen/Hexagon/vacopy.ll
M llvm/test/CodeGen/Hexagon/vadd1.ll
M llvm/test/CodeGen/Hexagon/vaddh.ll
M llvm/test/CodeGen/Hexagon/validate-offset.ll
M llvm/test/CodeGen/Hexagon/vararg-deallocate-sp.ll
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M llvm/test/CodeGen/Hexagon/vararg_double_onstack.ll
M llvm/test/CodeGen/Hexagon/vararg_named.ll
M llvm/test/CodeGen/Hexagon/varargs-memv.ll
M llvm/test/CodeGen/Hexagon/vassign-to-combine.ll
M llvm/test/CodeGen/Hexagon/vcombine128_to_req_seq.ll
M llvm/test/CodeGen/Hexagon/vcombine_subreg.ll
M llvm/test/CodeGen/Hexagon/vcombine_to_req_seq.ll
M llvm/test/CodeGen/Hexagon/vcombine_zero_diff_ptrs.ll
M llvm/test/CodeGen/Hexagon/vdmpy-halide-test.ll
M llvm/test/CodeGen/Hexagon/vdotprod.ll
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M llvm/test/CodeGen/Hexagon/vec-call-full1.ll
M llvm/test/CodeGen/Hexagon/vec-pred-spill1.ll
M llvm/test/CodeGen/Hexagon/vec-vararg-align.ll
M llvm/test/CodeGen/Hexagon/vecPred2Vec.ll
M llvm/test/CodeGen/Hexagon/vect-any_extend.ll
M llvm/test/CodeGen/Hexagon/vect-dbl-post-inc.ll
M llvm/test/CodeGen/Hexagon/vect-downscale.ll
M llvm/test/CodeGen/Hexagon/vect-set_cc_v2i32.ll
M llvm/test/CodeGen/Hexagon/vect-vd0.ll
M llvm/test/CodeGen/Hexagon/vect-zero_extend.ll
M llvm/test/CodeGen/Hexagon/vect/bit4x8.ll
M llvm/test/CodeGen/Hexagon/vect/build-vect64.ll
M llvm/test/CodeGen/Hexagon/vect/extract-elt-vNi1.ll
M llvm/test/CodeGen/Hexagon/vect/extract-v4i1.ll
M llvm/test/CodeGen/Hexagon/vect/setcc-not.ll
M llvm/test/CodeGen/Hexagon/vect/setcc-v2i32.ll
M llvm/test/CodeGen/Hexagon/vect/setcc-v32.ll
M llvm/test/CodeGen/Hexagon/vect/shuff-32.ll
M llvm/test/CodeGen/Hexagon/vect/shuff-64.ll
M llvm/test/CodeGen/Hexagon/vect/vect-anyextend.ll
M llvm/test/CodeGen/Hexagon/vect/vect-apint-truncate.ll
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M llvm/test/CodeGen/Hexagon/vect/vect-bitcast-1.ll
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M llvm/test/CodeGen/Hexagon/vect/vect-bool-basic-compile.ll
M llvm/test/CodeGen/Hexagon/vect/vect-bool-isel-crash.ll
M llvm/test/CodeGen/Hexagon/vect/vect-cst-v4i32.ll
M llvm/test/CodeGen/Hexagon/vect/vect-cst-v4i8.ll
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M llvm/test/CodeGen/Hexagon/vect/vect-extract-i1.ll
M llvm/test/CodeGen/Hexagon/vect/vect-extract.ll
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M llvm/test/CodeGen/Hexagon/vsplat-ext.ll
M llvm/test/CodeGen/Hexagon/vsplat-isel.ll
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M llvm/test/CodeGen/Hexagon/widen-not-load.ll
M llvm/test/CodeGen/Hexagon/widen-volatile.ll
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M llvm/test/CodeGen/Lanai/delay_filler.ll
M llvm/test/CodeGen/Lanai/lowering-128.ll
M llvm/test/CodeGen/LoongArch/sextw-removal.ll
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M llvm/test/CodeGen/NVPTX/fence-sm-90.ll
M llvm/test/CodeGen/NVPTX/fence.ll
M llvm/test/CodeGen/NVPTX/filetype-null.ll
M llvm/test/CodeGen/NVPTX/fma-assoc.ll
M llvm/test/CodeGen/NVPTX/fma-disable.ll
M llvm/test/CodeGen/NVPTX/fma-relu-contract.ll
M llvm/test/CodeGen/NVPTX/fma-relu-fma-intrinsic.ll
M llvm/test/CodeGen/NVPTX/fma-relu-instruction-flag.ll
M llvm/test/CodeGen/NVPTX/fma.ll
M llvm/test/CodeGen/NVPTX/fminimum-fmaximum.ll
M llvm/test/CodeGen/NVPTX/fns.ll
M llvm/test/CodeGen/NVPTX/fp-contract.ll
M llvm/test/CodeGen/NVPTX/fp-literals.ll
M llvm/test/CodeGen/NVPTX/fp16.ll
M llvm/test/CodeGen/NVPTX/fsin-no-fast-math.ll
M llvm/test/CodeGen/NVPTX/function-align.ll
M llvm/test/CodeGen/NVPTX/funnel-shift-clamp.ll
M llvm/test/CodeGen/NVPTX/generic-to-nvvm.ll
M llvm/test/CodeGen/NVPTX/global-addrspace.ll
M llvm/test/CodeGen/NVPTX/global-ctor-empty.ll
M llvm/test/CodeGen/NVPTX/global-ctor.ll
M llvm/test/CodeGen/NVPTX/global-dtor.ll
M llvm/test/CodeGen/NVPTX/global-incomplete-init.ll
M llvm/test/CodeGen/NVPTX/global-ordering.ll
M llvm/test/CodeGen/NVPTX/global-visibility.ll
M llvm/test/CodeGen/NVPTX/globals_init.ll
M llvm/test/CodeGen/NVPTX/gvar-init.ll
M llvm/test/CodeGen/NVPTX/half.ll
M llvm/test/CodeGen/NVPTX/i1-array-global.ll
M llvm/test/CodeGen/NVPTX/i1-ext-load.ll
M llvm/test/CodeGen/NVPTX/i1-global.ll
M llvm/test/CodeGen/NVPTX/i1-icmp.ll
M llvm/test/CodeGen/NVPTX/i1-int-to-fp.ll
M llvm/test/CodeGen/NVPTX/i1-load-lower.ll
M llvm/test/CodeGen/NVPTX/i1-param.ll
M llvm/test/CodeGen/NVPTX/i128-global.ll
M llvm/test/CodeGen/NVPTX/i128-param.ll
M llvm/test/CodeGen/NVPTX/i128-retval.ll
M llvm/test/CodeGen/NVPTX/i128-struct.ll
M llvm/test/CodeGen/NVPTX/i16x2-instructions.ll
M llvm/test/CodeGen/NVPTX/i8-param.ll
M llvm/test/CodeGen/NVPTX/i8x4-instructions.ll
M llvm/test/CodeGen/NVPTX/idioms.ll
M llvm/test/CodeGen/NVPTX/imad.ll
M llvm/test/CodeGen/NVPTX/indirect_byval.ll
M llvm/test/CodeGen/NVPTX/inline-asm-b128-test1.ll
M llvm/test/CodeGen/NVPTX/inline-asm-b128-test2.ll
M llvm/test/CodeGen/NVPTX/inline-asm-b128-test3.ll
M llvm/test/CodeGen/NVPTX/inline-asm.ll
M llvm/test/CodeGen/NVPTX/inlineasm-output-template.ll
M llvm/test/CodeGen/NVPTX/intrinsic-old.ll
M llvm/test/CodeGen/NVPTX/intrinsics-sm90.ll
M llvm/test/CodeGen/NVPTX/intrinsics.ll
M llvm/test/CodeGen/NVPTX/isspacep.ll
M llvm/test/CodeGen/NVPTX/kernel-param-align.ll
M llvm/test/CodeGen/NVPTX/ld-addrspace.ll
M llvm/test/CodeGen/NVPTX/ld-generic.ll
M llvm/test/CodeGen/NVPTX/ld-st-addrrspace.py
M llvm/test/CodeGen/NVPTX/ldg-invariant.ll
M llvm/test/CodeGen/NVPTX/ldparam-v4.ll
M llvm/test/CodeGen/NVPTX/ldu-i8.ll
M llvm/test/CodeGen/NVPTX/ldu-ldg.ll
M llvm/test/CodeGen/NVPTX/ldu-reg-plus-offset.ll
M llvm/test/CodeGen/NVPTX/load-sext-i1.ll
A llvm/test/CodeGen/NVPTX/load-store-scalars.ll
M llvm/test/CodeGen/NVPTX/load-store-sm-70.ll
M llvm/test/CodeGen/NVPTX/load-store-sm-90.ll
A llvm/test/CodeGen/NVPTX/load-store-vectors.ll
R llvm/test/CodeGen/NVPTX/load-store.ll
M llvm/test/CodeGen/NVPTX/load-with-non-coherent-cache.ll
M llvm/test/CodeGen/NVPTX/local-stack-frame.ll
M llvm/test/CodeGen/NVPTX/lower-aggr-copies.ll
M llvm/test/CodeGen/NVPTX/lower-alloca.ll
M llvm/test/CodeGen/NVPTX/lower-kernel-ptr-arg.ll
M llvm/test/CodeGen/NVPTX/machine-sink.ll
M llvm/test/CodeGen/NVPTX/managed.ll
M llvm/test/CodeGen/NVPTX/match.ll
M llvm/test/CodeGen/NVPTX/math-intrins-sm53-ptx42.ll
M llvm/test/CodeGen/NVPTX/math-intrins-sm80-ptx70-autoupgrade.ll
M llvm/test/CodeGen/NVPTX/math-intrins-sm80-ptx70.ll
M llvm/test/CodeGen/NVPTX/math-intrins-sm86-ptx72-autoupgrade.ll
M llvm/test/CodeGen/NVPTX/math-intrins-sm86-ptx72.ll
M llvm/test/CodeGen/NVPTX/max-align.ll
M llvm/test/CodeGen/NVPTX/maxclusterrank.ll
M llvm/test/CodeGen/NVPTX/mbarrier.ll
M llvm/test/CodeGen/NVPTX/minmax-negative.ll
M llvm/test/CodeGen/NVPTX/misaligned-vector-ldst.ll
M llvm/test/CodeGen/NVPTX/misched_func_call.ll
M llvm/test/CodeGen/NVPTX/mma-no-sink-after-laneid-check.ll
M llvm/test/CodeGen/NVPTX/module-inline-asm.ll
M llvm/test/CodeGen/NVPTX/mulwide.ll
M llvm/test/CodeGen/NVPTX/named-barriers.ll
M llvm/test/CodeGen/NVPTX/nanosleep.ll
M llvm/test/CodeGen/NVPTX/no-extra-parens.ll
M llvm/test/CodeGen/NVPTX/nofunc.ll
M llvm/test/CodeGen/NVPTX/noreturn.ll
M llvm/test/CodeGen/NVPTX/nounroll.ll
M llvm/test/CodeGen/NVPTX/nvcl-param-align.ll
M llvm/test/CodeGen/NVPTX/nvvm-reflect-arch-O0.ll
M llvm/test/CodeGen/NVPTX/packed-aggr.ll
M llvm/test/CodeGen/NVPTX/param-align.ll
M llvm/test/CodeGen/NVPTX/param-load-store.ll
M llvm/test/CodeGen/NVPTX/param-overalign.ll
M llvm/test/CodeGen/NVPTX/pass-name.ll
M llvm/test/CodeGen/NVPTX/pow2_mask_cmp.ll
M llvm/test/CodeGen/NVPTX/pr13291-i1-store.ll
M llvm/test/CodeGen/NVPTX/pr16278.ll
M llvm/test/CodeGen/NVPTX/pr17529.ll
M llvm/test/CodeGen/NVPTX/proxy-reg-erasure-ptx.ll
M llvm/test/CodeGen/NVPTX/proxy-reg-erasure.mir
M llvm/test/CodeGen/NVPTX/rcp-opt.ll
M llvm/test/CodeGen/NVPTX/read-global-variable-constant.ll
M llvm/test/CodeGen/NVPTX/redux-sync.ll
M llvm/test/CodeGen/NVPTX/refl1.ll
M llvm/test/CodeGen/NVPTX/reg-copy.ll
M llvm/test/CodeGen/NVPTX/reg-types.ll
M llvm/test/CodeGen/NVPTX/rotate_64.ll
M llvm/test/CodeGen/NVPTX/rsqrt-opt.ll
M llvm/test/CodeGen/NVPTX/rsqrt.ll
M llvm/test/CodeGen/NVPTX/sched1.ll
M llvm/test/CodeGen/NVPTX/sched2.ll
M llvm/test/CodeGen/NVPTX/setmaxnreg.ll
M llvm/test/CodeGen/NVPTX/sext-in-reg.ll
M llvm/test/CodeGen/NVPTX/sext-params.ll
M llvm/test/CodeGen/NVPTX/sext-setcc.ll
M llvm/test/CodeGen/NVPTX/shfl-p.ll
M llvm/test/CodeGen/NVPTX/shfl-sync-p.ll
M llvm/test/CodeGen/NVPTX/shfl-sync.ll
M llvm/test/CodeGen/NVPTX/shfl.ll
M llvm/test/CodeGen/NVPTX/shift-parts.ll
M llvm/test/CodeGen/NVPTX/short-ptr.ll
M llvm/test/CodeGen/NVPTX/shuffle-vec-undef-init.ll
M llvm/test/CodeGen/NVPTX/simple-call.ll
M llvm/test/CodeGen/NVPTX/sm-version.ll
M llvm/test/CodeGen/NVPTX/sqrt-approx.ll
M llvm/test/CodeGen/NVPTX/st-addrspace.ll
M llvm/test/CodeGen/NVPTX/st-generic.ll
M llvm/test/CodeGen/NVPTX/st-param-imm.ll
M llvm/test/CodeGen/NVPTX/stacksaverestore.ll
M llvm/test/CodeGen/NVPTX/store-undef.ll
M llvm/test/CodeGen/NVPTX/surf-read-cuda.ll
M llvm/test/CodeGen/NVPTX/surf-read.ll
M llvm/test/CodeGen/NVPTX/surf-tex.py
M llvm/test/CodeGen/NVPTX/surf-write-cuda.ll
M llvm/test/CodeGen/NVPTX/surf-write.ll
M llvm/test/CodeGen/NVPTX/symbol-naming.ll
M llvm/test/CodeGen/NVPTX/tex-read-cuda.ll
M llvm/test/CodeGen/NVPTX/tex-read.ll
M llvm/test/CodeGen/NVPTX/texsurf-queries.ll
M llvm/test/CodeGen/NVPTX/tid-range.ll
M llvm/test/CodeGen/NVPTX/unaligned-param-load-store.ll
M llvm/test/CodeGen/NVPTX/unreachable.ll
M llvm/test/CodeGen/NVPTX/variadics-backend.ll
M llvm/test/CodeGen/NVPTX/vec-param-load.ll
M llvm/test/CodeGen/NVPTX/vec8.ll
Log Message:
-----------
Rebase on main
Created using spr 1.3.6-beta.1
Compare: https://github.com/llvm/llvm-project/compare/082b20e17253...09e0dcbb5fe8
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