[all-commits] [llvm/llvm-project] 932d9c: [NVPTX] Generalize and extend upsizing when loweri...

[Drew Kersnar via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 932d9c13faa3de1deca3874d3b864901aa5ec9a5
      https://github.com/llvm/llvm-project/commit/932d9c13faa3de1deca3874d3b864901aa5ec9a5
  Author: Drew Kersnar <dakersnar at me.com>
  Date:   2024-12-17 (Tue, 17 Dec 2024)

  Changed paths:
    M llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp
    M llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp
    M llvm/test/CodeGen/NVPTX/LoadStoreVectorizer.ll
    M llvm/test/CodeGen/NVPTX/i8x4-instructions.ll
    M llvm/test/CodeGen/NVPTX/ldg-invariant.ll
    A llvm/test/CodeGen/NVPTX/load-store-scalars.ll
    A llvm/test/CodeGen/NVPTX/load-store-vectors.ll
    R llvm/test/CodeGen/NVPTX/load-store.ll
    M llvm/test/CodeGen/NVPTX/shuffle-vec-undef-init.ll
    M llvm/test/CodeGen/NVPTX/vector-stores.ll

  Log Message:
  -----------
  [NVPTX] Generalize and extend upsizing when lowering 8/16-bit-element vector loads/stores (#119622)

This addresses the following issue I opened:
https://github.com/llvm/llvm-project/issues/118851.

This change generalizes the Type Legalization mechanism that currently
handles `v8[i/f/bf]16` upsizing to include loads _and_ stores of `v8i8`
+ `v16i8`, allowing all of the mentioned vectors to be lowered to ptx as
vectors of `b32`. This extension also allows us to remove the DagCombine
that only handled exactly `load v16i8`, thus centralizing all the
upsizing logic into one place.

Test changes include adding v8i8, v16i8, and v8i16 cases to
load-store.ll, and updating the CHECKs for other tests to match the
improved codegen.



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