[all-commits] [llvm/llvm-project] 169c32: [RISCV][VLOPT] Enable the RISCVVLOptimizer by defa...

[Michael Maitland via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 169c32eb49fa9b559d388b9b8f4374ff9e1be9be
      https://github.com/llvm/llvm-project/commit/169c32eb49fa9b559d388b9b8f4374ff9e1be9be
  Author: Michael Maitland <michaeltmaitland at gmail.com>
  Date:   2024-12-17 (Tue, 17 Dec 2024)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
    M llvm/test/CodeGen/RISCV/O3-pipeline.ll
    M llvm/test/CodeGen/RISCV/rvv/ctlz-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-abs.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-buildvec.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-shuffles.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-changes-length.ll
    M llvm/test/CodeGen/RISCV/rvv/setcc-int-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vdiv-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vdivu-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vfma-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vl-opt-op-info.ll
    M llvm/test/CodeGen/RISCV/rvv/vl-opt.ll
    M llvm/test/CodeGen/RISCV/rvv/vmax-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vmaxu-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vmin-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vminu-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vmul-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vrem-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vremu-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vsadd-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vsaddu-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-crossbb.ll
    M llvm/test/CodeGen/RISCV/rvv/vshl-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vsitofp-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vsra-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vsra-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vsrl-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vssub-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vssubu-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vuitofp-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vwsll-vp.ll
    M llvm/test/CodeGen/RISCV/srem-seteq-illegal-types.ll

  Log Message:
  -----------
  [RISCV][VLOPT] Enable the RISCVVLOptimizer by default (#119461)

Now that we have testing of all instructions in the isSupportedInstr
switch, and better coverage of getOperandInfo, I think it is a good time
to enable this by default.



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