[all-commits] [llvm/llvm-project] 912523: RegAllocGreedy: Fix subrange based instruction spl...
Matt Arsenault via All-commits
all-commits at lists.llvm.org
Tue Dec 17 00:39:49 PST 2024
Branch: refs/heads/users/arsenm/greedy-fix-subrange-instruction-split-logic
Home: https://github.com/llvm/llvm-project
Commit: 9125238e4a31dfa3d68507fe12e304053ee29d67
https://github.com/llvm/llvm-project/commit/9125238e4a31dfa3d68507fe12e304053ee29d67
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2024-12-17 (Tue, 17 Dec 2024)
Changed paths:
M llvm/lib/CodeGen/RegAllocGreedy.cpp
M llvm/test/CodeGen/AMDGPU/gfx-callable-return-types.ll
A llvm/test/CodeGen/AMDGPU/inflated-reg-class-snippet-copy-inst-reads-lane-subset-use-after-free.mir
A llvm/test/CodeGen/AMDGPU/inflated-reg-class-snippet-copy-use-after-free.mir
M llvm/test/CodeGen/AMDGPU/remat-smrd.mir
M llvm/test/CodeGen/AMDGPU/splitkit-copy-live-lanes.mir
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-interleaved-access.ll
M llvm/test/CodeGen/RISCV/rvv/vector-deinterleave-load.ll
M llvm/test/CodeGen/RISCV/rvv/vector-deinterleave.ll
Log Message:
-----------
RegAllocGreedy: Fix subrange based instruction split logic
Fix the logic for readsLaneSubset. Check at the correct point
for the use operands of the instruction, instead of the result.
Only consider the use register operands, and stop considering
whether the subranges are actually live at this point.
This avoids some unproductive splits. This also happens to avoid
a use after free due to a split of an unspillable register. That
issue still exists if the instruction does not reference the full
set of register lanes.
To unsubscribe from these emails, change your notification settings at https://github.com/llvm/llvm-project/settings/notifications
More information about the All-commits
mailing list