[all-commits] [llvm/llvm-project] 04379c: [SystemZ][z/OS] Update autoconversion functions to...
Florian Mayer via All-commits
all-commits at lists.llvm.org
Mon Dec 16 02:46:39 PST 2024
Branch: refs/heads/users/fmayer/spr/apply-alignment-size-in-linker-rather-than-ir
Home: https://github.com/llvm/llvm-project
Commit: 04379c98638ac3901257b5fa319f9ece828af767
https://github.com/llvm/llvm-project/commit/04379c98638ac3901257b5fa319f9ece828af767
Author: Abhina Sree <Abhina.Sreeskantharajan at ibm.com>
Date: 2024-12-11 (Wed, 11 Dec 2024)
Changed paths:
M clang/include/clang/Basic/FileEntry.h
M clang/lib/Basic/SourceManager.cpp
M llvm/include/llvm/Support/AutoConvert.h
M llvm/lib/Support/AutoConvert.cpp
M llvm/lib/Support/MemoryBuffer.cpp
Log Message:
-----------
[SystemZ][z/OS] Update autoconversion functions to improve support for UTF-8 (#98652)
This fixes the following error when reading source and header files on
z/OS: error: source file is not valid UTF-8
Commit: 5e007afa9d4f175decc328ee89533a5fe89be99b
https://github.com/llvm/llvm-project/commit/5e007afa9d4f175decc328ee89533a5fe89be99b
Author: Pravin Jagtap <Pravin.Jagtap at amd.com>
Date: 2024-12-11 (Wed, 11 Dec 2024)
Changed paths:
M llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp
M llvm/lib/Target/AMDGPU/SIInstrInfo.td
M llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
M llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h
M llvm/lib/Target/AMDGPU/VOP3Instructions.td
M llvm/lib/Target/AMDGPU/VOPInstructions.td
M llvm/test/CodeGen/AMDGPU/hazards-gfx950.mir
Log Message:
-----------
[AMDGPU] Handle hazard in v_scalef32_sr_fp4_* conversions (#118589)
Presently, compiler selectivelly adds nop when opsel != 0 i.e. only when
partially writing to high bytes.
Experiments in SWDEV-499733 and SWDEV-501347 suggest that we need nop
for above cases irrespective of opsel values.
Note: We might need to add few others into the same table.
Commit: b1d8c60dd479d9c5d58bcfe33db57b68f834938d
https://github.com/llvm/llvm-project/commit/b1d8c60dd479d9c5d58bcfe33db57b68f834938d
Author: Momchil Velikov <momchil.velikov at arm.com>
Date: 2024-12-11 (Wed, 11 Dec 2024)
Changed paths:
M clang/include/clang/Basic/arm_sve.td
A clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_cvtn.c
M clang/test/Sema/aarch64-sve2-intrinsics/acle_sve2_fp8.c
M llvm/include/llvm/IR/IntrinsicsAArch64.td
M llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
M llvm/lib/Target/AArch64/SVEInstrFormats.td
A llvm/test/CodeGen/AArch64/fp8-sve-cvtn.ll
Log Message:
-----------
[AArch64] Implement FP8 SVE Intrinsics for narrowing conversions (#118124)
This patch adds the following instrinsics:
* Half-precision and BFloat16 convert, narrow, and interleave to 8-bit
floating-point.
// Variant is also available for: _bf16_x2
svmfloat8_t svcvtn_mf8[_f16_x2]_fpm(svfloat16x2_t zn, fpm_t fpm);
* Single-precision convert, narrow, and interleave to 8-bit
floating-point (top and bottom).
svmfloat8_t svcvtnt_mf8[_f32_x2]_fpm(svmfloat8_t zd, svfloat32x2_t zn,
fpm_t fpm);
svmfloat8_t svcvtnb_mf8[_f32_x2]_fpm(svfloat32x2_t zn, fpm_t fpm);
Commit: 854ea0cf18e71608b2354a50872251c99628a6c2
https://github.com/llvm/llvm-project/commit/854ea0cf18e71608b2354a50872251c99628a6c2
Author: bernhardu <bernhardu at mailbox.org>
Date: 2024-12-11 (Wed, 11 Dec 2024)
Changed paths:
M compiler-rt/lib/interception/interception_win.cpp
M compiler-rt/lib/interception/tests/interception_win_test.cpp
Log Message:
-----------
[win/asan] GetInstructionSize: Make `83 EC XX` a generic entry. (#119537)
This consolidates the two different lines for x86 and x86_64 into a
single line for both architectures.
And adds a test line.
CC: @zmodem
Commit: 03019c687f00cdd9d05fc1ace329a438c3ff6364
https://github.com/llvm/llvm-project/commit/03019c687f00cdd9d05fc1ace329a438c3ff6364
Author: Paul Osmialowski <pawel.osmialowski at arm.com>
Date: 2024-12-11 (Wed, 11 Dec 2024)
Changed paths:
M clang/lib/Driver/ToolChains/CommonArgs.cpp
M clang/lib/Driver/ToolChains/MSVC.cpp
M clang/test/Driver/fveclib.c
M flang/test/Driver/fveclib.f90
Log Message:
-----------
[clang][driver] When -fveclib=ArmPL flag is in use, always link against libamath (#116432)
Using `-fveclib=ArmPL` without `-lamath` likely effects in the link-time
errors.
Commit: bc1f3eb59333d32797db234c0edf4dc270469b0e
https://github.com/llvm/llvm-project/commit/bc1f3eb59333d32797db234c0edf4dc270469b0e
Author: Bjorn Pettersson <bjorn.a.pettersson at ericsson.com>
Date: 2024-12-11 (Wed, 11 Dec 2024)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
A llvm/test/CodeGen/ARM/dagcombine-ld-op-st.ll
Log Message:
-----------
[DAGCombiner] Pre-commit test case for ReduceLoadOpStoreWidth. NFC
Adding test cases related to narrowing of load-op-store sequences.
ReduceLoadOpStoreWidth isn't careful enough, so it may end up
creating load/store operations that access memory outside the region
touched by the original load/store. Using ARM as a target for the
test cases to show what happens for both little-endian and big-endian.
This patch also adds a way to override the TLI.isNarrowingProfitable
check in DAGCombiner::ReduceLoadOpStoreWidth by using the option
-combiner-reduce-load-op-store-width-force-narrowing-profitable.
Idea is that it should be simpler to for example add lit tests
verifying that the code is correct for big-endian (which otherwise
is difficult since there are no in-tree big-endian targets that
is overriding TLI.isNarrowingProfitable).
This is a pre-commit for
https://github.com/llvm/llvm-project/pull/119203
Commit: 22780f808a6dba83bad9390f762095f263324df9
https://github.com/llvm/llvm-project/commit/22780f808a6dba83bad9390f762095f263324df9
Author: Bjorn Pettersson <bjorn.a.pettersson at ericsson.com>
Date: 2024-12-11 (Wed, 11 Dec 2024)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
M llvm/test/CodeGen/ARM/dagcombine-ld-op-st.ll
M llvm/test/CodeGen/X86/store_op_load_fold.ll
Log Message:
-----------
[DAGCombiner] Fix to avoid writing outside original store in ReduceLoadOpStoreWidth (#119203)
DAGCombiner::ReduceLoadOpStoreWidth could replace memory accesses
with more narrow loads/store, although sometimes the new load/store
would touch memory outside the original object. That seemed wrong
and this patch is simply avoiding doing the DAG combine in such
situations.
Also simplifying the expression used to align ShAmt down to a multiple
of NewBW. Subtracting (ShAmt % NewBW) should do the same thing as the
old more complicated expression.
Intention is to follow up with a patch that make more attempts, trying
to align the memory accesses at other offsets, allowing to trigger
the transform in more situations. The current strategy for deciding
size (NewBW) and offset (ShAmt) for the narrowed operations are a bit
ad-hoc, and not really considering big endian memory order in same
way as little endian.
Commit: b4b819ce98f1d77d29ec492f0230018fd633a117
https://github.com/llvm/llvm-project/commit/b4b819ce98f1d77d29ec492f0230018fd633a117
Author: Durgadoss R <durgadossr at nvidia.com>
Date: 2024-12-11 (Wed, 11 Dec 2024)
Changed paths:
M mlir/include/mlir/Dialect/LLVMIR/NVVMOps.td
M mlir/lib/Dialect/LLVMIR/IR/NVVMDialect.cpp
A mlir/test/Target/LLVMIR/nvvm/tma_store_reduce.mlir
M mlir/test/Target/LLVMIR/nvvmir-invalid.mlir
Log Message:
-----------
[MLIR][NVVM] Add Op for TMA Store with reduction (#118853)
PR #116854 adds intrinsics for TMA Store with reduction.
This patch adds an NVVM Dialect Op for the same.
* Lit tests are added to verify the lowering to LLVM intrinsics and
invalid cases.
* The common verifier method is updated to handle im2col modes without
offsets.
This helps Ops like TMA Store, TMA StoreReduce etc.
* The nvvmir.mlir test file is already large. So, this patch adds the
tests for this Op
in a new file under a separate "nvvm/" directory.
[mlir/test/Target/LLVMIR/"nvvm"/tma_store_reduce.mlir]
PTX Spec reference:
https://docs.nvidia.com/cuda/parallel-thread-execution/index.html#data-movement-and-conversion-instructions-cp-reduce-async-bulk-tensor
Signed-off-by: Durgadoss R <durgadossr at nvidia.com>
Commit: d416cae180a5c7e7325c0b55818056e328633a61
https://github.com/llvm/llvm-project/commit/d416cae180a5c7e7325c0b55818056e328633a61
Author: Timm Baeder <tbaeder at redhat.com>
Date: 2024-12-11 (Wed, 11 Dec 2024)
Changed paths:
M clang/lib/AST/ByteCode/InterpBuiltin.cpp
Log Message:
-----------
[clang][bytecode][NFC] Use Pointer::pointToSameBlock (#119552)
block() requires the pointer to be a block pointer.
Commit: e0c6088bcb5746795f04ab0bf53cec1cfea2480e
https://github.com/llvm/llvm-project/commit/e0c6088bcb5746795f04ab0bf53cec1cfea2480e
Author: Andrzej Warzyński <andrzej.warzynski at arm.com>
Date: 2024-12-11 (Wed, 11 Dec 2024)
Changed paths:
M mlir/test/Dialect/Linalg/vectorize-tensor-extract.mlir
Log Message:
-----------
[mlir][nfc] Update vectorize-tensor-extract.mlir (3/N) (#119121)
Tests in "vectorize-tensor-extract.mlir" are inconsistent and would
benefit from refactoring to:
* Clearly categorize tests into "contiguous load," "gather load," and
"scalar load + broadcast" cases, reflecting the structure of
tensor.extract vectorization.
* Unify variable naming (both MLIR and FileCheck).
* Ensure all tests exercise unmasked vectorization (masked vectorization
is covered in "vectorize-tensor-extract-masked.mlir").
* Improve and standardize formatting.
These changes will make it easier to identify the test cases being
exercised and simplify future maintenance or refactoring.
This is patch 3/N in the series. Below is a summary of the changes in
this patch.
----------------------------------------------------------------------
Summary of patch 3/N
----------------------------------------------------------------------
* Cluster all tests for "scalar load + broadcast" together
* Unify MLIR and FileCheck variable names, e.g. `%input`, `%output` ->
`%src`, `%init`.
Note, I haven't changed test function names to make it easier to track
changes (this PR is mostly about moving code). I will send a seperate PR
to rename the tests.
----------------------------------------------------------------------
Previous patches
----------------------------------------------------------------------
* https://github.com/llvm/llvm-project/pull/118977
* https://github.com/llvm/llvm-project/pull/119080
Commit: ad0fbb033d26edafab51e67232c189a52afc4c52
https://github.com/llvm/llvm-project/commit/ad0fbb033d26edafab51e67232c189a52afc4c52
Author: Michael Maitland <michaeltmaitland at gmail.com>
Date: 2024-12-11 (Wed, 11 Dec 2024)
Changed paths:
M llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp
M llvm/test/CodeGen/RISCV/rvv/vl-opt-op-info.mir
Log Message:
-----------
[RISCV][VLOPT] Add vl-opt-op-info tests for unit strided and strided stores (#119465)
I don't include getOperandInfo for the loads, since they don't take a
vector use operand, and we don't include the loads in isSupportedInstr
so we will never call getOperandInfo on the vector destination of these
instructions.
Don't add support for VSM since we don't have any mask producing
instructions in isSupportedInstr at the moment.
Commit: 323bedd0d60a9f4c04015687326eba1e96f34b04
https://github.com/llvm/llvm-project/commit/323bedd0d60a9f4c04015687326eba1e96f34b04
Author: Nikolas Klauser <nikolasklauser at berlin.de>
Date: 2024-12-11 (Wed, 11 Dec 2024)
Changed paths:
M libcxx/include/experimental/iterator
M libcxx/include/experimental/memory
M libcxx/include/experimental/propagate_const
M libcxx/include/experimental/simd
M libcxx/include/experimental/type_traits
M libcxx/include/experimental/utility
M libcxx/include/ext/hash_map
M libcxx/include/ext/hash_set
Log Message:
-----------
[libc++][C++03] Add #if 0 to the experimental/ and ext/ headers as well (#119541)
This has already been done for the most headers in
https://github.com/llvm/llvm-project/pull/119234, but I
forgot to also do it for the experimental/ and ext/ headers.
This is part of https://discourse.llvm.org/t/rfc-freezing-c-03-headers-in-libc.
Commit: 40986feda8b1437ed475b144d5b9a208b008782a
https://github.com/llvm/llvm-project/commit/40986feda8b1437ed475b144d5b9a208b008782a
Author: Vitaly Buka <vitalybuka at google.com>
Date: 2024-12-11 (Wed, 11 Dec 2024)
Changed paths:
M llvm/include/llvm/CodeGen/MachineInstr.h
M llvm/include/llvm/IR/DiagnosticInfo.h
M llvm/include/llvm/IR/LLVMContext.h
M llvm/lib/CodeGen/AsmPrinter/AsmPrinterInlineAsm.cpp
M llvm/lib/CodeGen/MachineInstr.cpp
M llvm/lib/CodeGen/RegAllocBase.cpp
M llvm/lib/CodeGen/RegAllocFast.cpp
M llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
M llvm/lib/CodeGen/XRayInstrumentation.cpp
M llvm/lib/IR/DiagnosticInfo.cpp
M llvm/lib/IR/LLVMContext.cpp
M llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
M llvm/lib/Target/ARM/ARMMCInstLower.cpp
M llvm/lib/Target/X86/X86FloatingPoint.cpp
M llvm/test/CodeGen/AMDGPU/sgpr-spill-to-vmem-scc-clobber-unhandled.mir
Log Message:
-----------
Revert "DiagnosticInfo: Clean up usage of DiagnosticInfoInlineAsm" (#119575)
Reverts llvm/llvm-project#119485
Breaks builders, details in llvm/llvm-project#119485
Commit: cb4f4a8a4dd18bf00604b49faadd7b0ee4394d3d
https://github.com/llvm/llvm-project/commit/cb4f4a8a4dd18bf00604b49faadd7b0ee4394d3d
Author: Sander de Smalen <sander.desmalen at arm.com>
Date: 2024-12-11 (Wed, 11 Dec 2024)
Changed paths:
M compiler-rt/lib/builtins/CMakeLists.txt
A compiler-rt/lib/builtins/aarch64/sme-abi-assert.c
R compiler-rt/lib/builtins/aarch64/sme-abi-init.c
M compiler-rt/lib/builtins/aarch64/sme-abi.S
M compiler-rt/lib/builtins/cpu_model/aarch64.c
A compiler-rt/lib/builtins/cpu_model/aarch64/fmv/baremetal.inc
Log Message:
-----------
[compiler-rt][AArch64] Rewrite SME routines to all use __aarch64_cpu_features. (#119414)
When #92921 added the `__arm_get_current_vg` functionality, it used the
FMV feature bits mechanism rather than the mechanism that was previously
added for SME which called `getauxval` on Linux platforms or
`__aarch64_sme_accessible` required for baremetal libraries. It is
better to always use `__aarch64_cpu_features`.
For baremetal we still need to rely on `__arm_sme_accessible` to
initialise the struct.
Commit: 10ad2135ab33302a55fc2e8a42e6001a44aae0bc
https://github.com/llvm/llvm-project/commit/10ad2135ab33302a55fc2e8a42e6001a44aae0bc
Author: Nikita Popov <npopov at redhat.com>
Date: 2024-12-11 (Wed, 11 Dec 2024)
Changed paths:
M llvm/Maintainers.md
Log Message:
-----------
[LLVM] Move Chad Rosier to inactive maintainers
Chad has not been involved with LLVM for more than five years, so
move him to the inactive maintainers.
Unfortunately, there doesn't seem to be a clear person to take up
FastISel maintainership.
Commit: 3787fbf0402b4e03e316c13231f8873769701250
https://github.com/llvm/llvm-project/commit/3787fbf0402b4e03e316c13231f8873769701250
Author: Alex Bradbury <asb at igalia.com>
Date: 2024-12-11 (Wed, 11 Dec 2024)
Changed paths:
M llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
M llvm/test/CodeGen/RISCV/global-merge-minsize-smalldata-nonzero.ll
M llvm/test/CodeGen/RISCV/global-merge-minsize-smalldata-zero.ll
M llvm/test/CodeGen/RISCV/global-merge-minsize.ll
M llvm/test/CodeGen/RISCV/global-merge-offset.ll
M llvm/test/CodeGen/RISCV/global-merge.ll
Log Message:
-----------
[RISCV] Enable merging of external globals by default (#117880)
This follows up #115495 by enabling merging of external globals by
default, which had been left as a next step in order to make the
previous change more incremental and so we can more easily narrow down
on any identified regressions.
Enabling merging of external globals matches what Arm does (for non
mach-o targets), though AArch64 doesn't as there were [some
concerns](https://reviews.llvm.org/D61947) it might cause regressions in
some cases.
See https://github.com/llvm/llvm-project/pull/117880 for benchmark figures and discussion.
Commit: 673c324ae3653cf62d67c5acbee1126e9eb6843e
https://github.com/llvm/llvm-project/commit/673c324ae3653cf62d67c5acbee1126e9eb6843e
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-12-11 (Wed, 11 Dec 2024)
Changed paths:
M llvm/lib/Transforms/Vectorize/VectorCombine.cpp
M llvm/test/Transforms/VectorCombine/X86/extract-binop-inseltpoison.ll
M llvm/test/Transforms/VectorCombine/X86/extract-binop.ll
Log Message:
-----------
[VectorCombine] foldInsExtVectorToShuffle - canonicalize new shuffle(undef,x) -> shuffle(x,undef).
foldInsExtVectorToShuffle is likely to be inserting into an undef value, so make sure we've canonicalized this to the RHS in the folded shuffle to help further VectorCombine folds.
Minor tweak to help #34072
Commit: 00e1cc4c9d002c78cf890b630343b052ebca0399
https://github.com/llvm/llvm-project/commit/00e1cc4c9d002c78cf890b630343b052ebca0399
Author: Mats Petersson <mats.petersson at arm.com>
Date: 2024-12-11 (Wed, 11 Dec 2024)
Changed paths:
M flang/include/flang/Parser/dump-parse-tree.h
M flang/include/flang/Parser/parse-tree.h
M flang/lib/Parser/openmp-parsers.cpp
M flang/lib/Parser/unparse.cpp
M flang/lib/Semantics/check-omp-structure.cpp
M flang/lib/Semantics/check-omp-structure.h
A flang/test/Lower/OpenMP/Todo/atomic-compare-fail.f90
M flang/test/Parser/OpenMP/atomic-unparse.f90
M flang/test/Semantics/OpenMP/atomic-compare.f90
M flang/test/Semantics/OpenMP/atomic01.f90
M flang/test/Semantics/OpenMP/atomic05.f90
M llvm/include/llvm/Frontend/OpenMP/OMP.td
Log Message:
-----------
[flang][OpenMP]Add support for fail clause (#118683)
Support the atomic compare option of a fail(memory-order) clauses.
Additional tests introduced to check that parsing and semantics checks
for the new clause is handled.
Lowering for atomic compare is still unsupported and wil end in a TOOD
(aka "Not yet implemented"). A test for this case with the fail clause
is also present.
Commit: 624cc7048f604ed1087f63fdbe4cbf40f1d35b69
https://github.com/llvm/llvm-project/commit/624cc7048f604ed1087f63fdbe4cbf40f1d35b69
Author: Kazu Hirata <kazu at google.com>
Date: 2024-12-11 (Wed, 11 Dec 2024)
Changed paths:
M clang/include/clang/AST/Decl.h
M clang/include/clang/AST/DeclBase.h
M clang/include/clang/AST/DeclCXX.h
M clang/include/clang/AST/DeclTemplate.h
M clang/include/clang/AST/ExprCXX.h
M clang/include/clang/AST/ExprConcepts.h
M clang/include/clang/AST/ExprObjC.h
M clang/include/clang/AST/Redeclarable.h
M clang/include/clang/AST/TemplateBase.h
Log Message:
-----------
[AST] Migrate away from PointerUnion::{is,get} (NFC) (#119523)
Note that PointerUnion::{is,get} have been soft deprecated in
PointerUnion.h:
// FIXME: Replace the uses of is(), get() and dyn_cast() with
// isa<T>, cast<T> and the llvm::dyn_cast<T>
I'm not touching PointerUnion::dyn_cast for now because it's a bit
complicated; we could blindly migrate it to dyn_cast_if_present, but
we should probably use dyn_cast when the operand is known to be
non-null.
Commit: 8b63bfbf6dd2ad0efd221407755300942a7ca35f
https://github.com/llvm/llvm-project/commit/8b63bfbf6dd2ad0efd221407755300942a7ca35f
Author: qt-tatiana <tatiana.borisova at qt.io>
Date: 2024-12-12 (Thu, 12 Dec 2024)
Changed paths:
M clang-tools-extra/clang-tidy/modernize/CMakeLists.txt
M clang-tools-extra/clang-tidy/modernize/ModernizeTidyModule.cpp
A clang-tools-extra/clang-tidy/modernize/UseIntegerSignComparisonCheck.cpp
A clang-tools-extra/clang-tidy/modernize/UseIntegerSignComparisonCheck.h
M clang-tools-extra/docs/ReleaseNotes.rst
M clang-tools-extra/docs/clang-tidy/checks/list.rst
A clang-tools-extra/docs/clang-tidy/checks/modernize/use-integer-sign-comparison.rst
A clang-tools-extra/test/clang-tidy/checkers/modernize/use-integer-sign-comparison.cpp
Log Message:
-----------
[clang-tidy] Create a check for signed and unsigned integers comparison (#113144)
- modernize-use-integer-sign-comparison replaces comparisons between
signed and unsigned integers with their safe C++20 ``std::cmp_*``
alternative, if available.
Commit: 08f904011f4b17e46b7616737a5dec01e3563c80
https://github.com/llvm/llvm-project/commit/08f904011f4b17e46b7616737a5dec01e3563c80
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-12-11 (Wed, 11 Dec 2024)
Changed paths:
M llvm/lib/Transforms/Vectorize/VectorCombine.cpp
M llvm/test/Transforms/PhaseOrdering/X86/concat-boolmasks.ll
Log Message:
-----------
[VectorCombine] Fold "(or (zext (bitcast X)), (shl (zext (bitcast Y)), C))" -> "(bitcast (concat X, Y))" MOVMSK bool mask style patterns (#119559)
Mask/Bool vectors are often bitcast to/from scalar integers, in particular when concatenating mask results, often this is due to the difficulties of working with vector of bools on C/C++. On x86 this typically involves the MOVMSK/KMOV instructions.
To concatenate bool masks, these are typically cast to scalars, which are then zero-extended, shifted and OR'd together.
This patch attempts to match these scalar concatenation patterns and convert them to vector shuffles instead. This in turn often assists with further vector combines, depending on the cost model.
Fixes #111431
Commit: 03661fbe45e70bde2984a5fc0feab6396407a33b
https://github.com/llvm/llvm-project/commit/03661fbe45e70bde2984a5fc0feab6396407a33b
Author: Nuno Lopes <nuno.lopes at tecnico.ulisboa.pt>
Date: 2024-12-11 (Wed, 11 Dec 2024)
Changed paths:
M llvm/docs/UndefinedBehavior.rst
Log Message:
-----------
[docs][UB] add section on poison propagation through select
Examples from Nikita Popov, thank you!
Commit: 53544fc15f08687c14becced4ecc22c2356265cd
https://github.com/llvm/llvm-project/commit/53544fc15f08687c14becced4ecc22c2356265cd
Author: Fangrui Song <i at maskray.me>
Date: 2024-12-11 (Wed, 11 Dec 2024)
Changed paths:
M lld/ELF/InputFiles.cpp
M lld/test/ELF/lto/internalize-exportdyn.ll
Log Message:
-----------
[ELF] Respect ltoCanOmit for symbols in non-prevailing COMDAT
A linkonce_odr definition can be omitted in LTO compilation if
`canBeOmittedFromSymbolTable()` is true in all bitcode files.
Currently, we don't respect the `canBeOmittedFromSymbolTable()` bit from
symbols in a non-prevailing COMDAT, which could lead to incorrect
omission of a definition when merging a prevailing linkonce_odr and a
non-prevailing weak_odr, e.g. an implicit template instantiation and an
explicit template instantiation.
To fix #111341, allow the non-prevailing COMDAT code path to clear the
`ltoCanOmit` bit, so that `VisibleToRegularObj` could be false in
LTO.cpp. We could resolve either an Undefined or a Defined. For
simplicity, just use a Defined like the prevailing case (similar to how
we resolve symbols in ObjectFile COMDAT reviews.llvm.org/D120626).
Pull Request: https://github.com/llvm/llvm-project/pull/119332
Commit: 0663a73104424a1e9e7416bddb4fe3bec7129a2b
https://github.com/llvm/llvm-project/commit/0663a73104424a1e9e7416bddb4fe3bec7129a2b
Author: Haopeng Liu <153236845+haopliu at users.noreply.github.com>
Date: 2024-12-11 (Wed, 11 Dec 2024)
Changed paths:
M llvm/lib/Transforms/Scalar/DeadStoreElimination.cpp
Log Message:
-----------
Revert "[DSE] Enable initializes improvement" (#119590)
Reverts llvm/llvm-project#119116
Commit: 1946d32f1fdfb2c4d5e866a5c1c5c32b8cdad5b8
https://github.com/llvm/llvm-project/commit/1946d32f1fdfb2c4d5e866a5c1c5c32b8cdad5b8
Author: Csanád Hajdú <csanad.hajdu at arm.com>
Date: 2024-12-11 (Wed, 11 Dec 2024)
Changed paths:
M clang/lib/Driver/SanitizerArgs.cpp
M clang/test/Driver/fsanitize.c
Log Message:
-----------
[Clang] Improve error for `-fsanitize=function/kcfi -mexecute-only` incompatibility (#118816)
The current error message when using the `-fsanitize=function
-mexecute-only` flags together points to the target triple as the reason
that `-fsanitize=function` is not allowed to be used, even when the
function sanitizer is otherwise supported on the target when not using
`-mexecute-only`.
The error message is improved to give `-mexecute-only` as the reason for
disallowing `-fsanitize=function` if it was passed to the driver.
Fixes https://github.com/llvm/llvm-project/issues/117974
Commit: 92bf1aa399a00c6902e80090074fff66fc5416a9
https://github.com/llvm/llvm-project/commit/92bf1aa399a00c6902e80090074fff66fc5416a9
Author: LLVM GN Syncbot <llvmgnsyncbot at gmail.com>
Date: 2024-12-11 (Wed, 11 Dec 2024)
Changed paths:
M llvm/utils/gn/secondary/clang-tools-extra/clang-tidy/modernize/BUILD.gn
Log Message:
-----------
[gn build] Port 8b63bfbf6dd2
Commit: 9b94869942bb71daeb119e7701d806ae0003cc0d
https://github.com/llvm/llvm-project/commit/9b94869942bb71daeb119e7701d806ae0003cc0d
Author: Kazu Hirata <kazu at google.com>
Date: 2024-12-11 (Wed, 11 Dec 2024)
Changed paths:
M llvm/unittests/ProfileData/MemProfTest.cpp
Log Message:
-----------
[memprof] Use front instead of begin in a unit test (NFC) (#119501)
"front" allows us to drop a dereference.
Commit: 9aa5848d5cb03cd024b1ebb2f8a5225917f63881
https://github.com/llvm/llvm-project/commit/9aa5848d5cb03cd024b1ebb2f8a5225917f63881
Author: Kazu Hirata <kazu at google.com>
Date: 2024-12-11 (Wed, 11 Dec 2024)
Changed paths:
M llvm/unittests/ProfileData/MemProfTest.cpp
Log Message:
-----------
[memprof] Drop curly braces on small for loops (NFC) (#119516)
Commit: 66edefaee5e87baabe2367cf1dd82ef40cee8c86
https://github.com/llvm/llvm-project/commit/66edefaee5e87baabe2367cf1dd82ef40cee8c86
Author: Kazu Hirata <kazu at google.com>
Date: 2024-12-11 (Wed, 11 Dec 2024)
Changed paths:
M llvm/include/llvm/ProfileData/InstrProfReader.h
M llvm/include/llvm/ProfileData/MemProf.h
A llvm/include/llvm/ProfileData/MemProfYAML.h
M llvm/lib/ProfileData/MemProfReader.cpp
M llvm/tools/llvm-profdata/llvm-profdata.cpp
M llvm/unittests/ProfileData/MemProfTest.cpp
Log Message:
-----------
[memprof] Move YAML support to MemProfYAML.h (NFC) (#119515)
The YAML support is increasing in size, so this patch moves it to a
separate file.
Commit: 7b2d592a1971fccb8d3cf386d1bc9185b3b1198f
https://github.com/llvm/llvm-project/commit/7b2d592a1971fccb8d3cf386d1bc9185b3b1198f
Author: Louis Dionne <ldionne.2 at gmail.com>
Date: 2024-12-11 (Wed, 11 Dec 2024)
Changed paths:
M libcxx/test/libcxx/feature_test_macro/version_header.sh.py
M libcxx/utils/generate_feature_test_macro_components.py
Log Message:
-----------
[libc++] Fix test FTM header guard
That template is actually not used to generate the version header yet,
but we can at least fix the include guards which are clearly incorrect.
Commit: b0b546d44777eb1fa25995384876bd14a006a929
https://github.com/llvm/llvm-project/commit/b0b546d44777eb1fa25995384876bd14a006a929
Author: Louis Dionne <ldionne.2 at gmail.com>
Date: 2024-12-11 (Wed, 11 Dec 2024)
Changed paths:
M libcxxabi/CMakeLists.txt
M libunwind/CMakeLists.txt
Log Message:
-----------
[libc++abi] Provide an explicit error when trying to build for MSVC (#119370)
Fixes #119322
Commit: 3c464d23682b0f9e6f70965e8f8f3861c9ba5417
https://github.com/llvm/llvm-project/commit/3c464d23682b0f9e6f70965e8f8f3861c9ba5417
Author: Eliud de León <eliud.deleon.10 at gmail.com>
Date: 2024-12-11 (Wed, 11 Dec 2024)
Changed paths:
A mlir/include/mlir-c/Dialect/EmitC.h
M mlir/lib/CAPI/Dialect/CMakeLists.txt
A mlir/lib/CAPI/Dialect/EmitC.cpp
M mlir/python/CMakeLists.txt
A mlir/python/mlir/dialects/EmitC.td
A mlir/python/mlir/dialects/emitc.py
A mlir/test/python/dialects/emitc_dialect.py
Log Message:
-----------
[mlir][emitc] Add support for C-API/python binding to EmitC dialect (#119476)
Added EmitC dialect bindings.
Commit: 62fcd451b6004cea3f1bb7783300cac76237dd81
https://github.com/llvm/llvm-project/commit/62fcd451b6004cea3f1bb7783300cac76237dd81
Author: Florian Hahn <flo at fhahn.com>
Date: 2024-12-11 (Wed, 11 Dec 2024)
Changed paths:
M llvm/include/llvm/Transforms/Utils/ExtraPassManager.h
M llvm/lib/Passes/PassRegistry.def
Log Message:
-----------
[Passes] Manage extra passes using inner pass managers (NFC). (#119348)
As suggested post-commit for
https://github.com/llvm/llvm-project/pull/118323, adjust the extra pass
managers to no inherit from Function/LoopPassManager, but manage the
extra passes via member pass managers.
PR: https://github.com/llvm/llvm-project/pull/119348
Commit: 89b7aea5733da47c57ea0514fa9795574d84199d
https://github.com/llvm/llvm-project/commit/89b7aea5733da47c57ea0514fa9795574d84199d
Author: Vitaly Buka <vitalybuka at google.com>
Date: 2024-12-11 (Wed, 11 Dec 2024)
Changed paths:
M llvm/lib/Transforms/Vectorize/VectorCombine.cpp
M llvm/test/Transforms/PhaseOrdering/X86/concat-boolmasks.ll
Log Message:
-----------
Revert "[VectorCombine] Fold "(or (zext (bitcast X)), (shl (zext (bitcast Y)), C))" -> "(bitcast (concat X, Y))" MOVMSK bool mask style patterns" (#119594)
Reverts llvm/llvm-project#119559
Introduce use after free, see llvm/llvm-project#119559
Commit: 412ab602f13adb637e6c80e9d5f32631c00ca2bd
https://github.com/llvm/llvm-project/commit/412ab602f13adb637e6c80e9d5f32631c00ca2bd
Author: Michael Maitland <michaeltmaitland at gmail.com>
Date: 2024-12-11 (Wed, 11 Dec 2024)
Changed paths:
M llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp
M llvm/test/CodeGen/RISCV/rvv/vl-opt-instrs.ll
Log Message:
-----------
[RISCV][VLOPT] Add vector narrowing integer right shift instructions to isSupportedInstr (#119602)
Commit: de56df9eb5248006ac64744e962ee053e72d028c
https://github.com/llvm/llvm-project/commit/de56df9eb5248006ac64744e962ee053e72d028c
Author: Abhay Kanhere <abhay at kanhere.net>
Date: 2024-12-11 (Wed, 11 Dec 2024)
Changed paths:
M llvm/docs/Security.rst
Log Message:
-----------
[Nomination] Add additional Apple representative to the Security Group (#118571)
I'd like to nominate myself as an additional Apple representative
(vendor contact) on the llvm security group.
I met many of you at the llvm-dev meeting roundtable(s) in Santa Clara.
I closely work with @ahmedbougacha @jroelofs at Apple.
- Abhay
Commit: e7c626cdd154b3c7b36ba0243cf75ff1cec76952
https://github.com/llvm/llvm-project/commit/e7c626cdd154b3c7b36ba0243cf75ff1cec76952
Author: Michael Maitland <michaeltmaitland at gmail.com>
Date: 2024-12-11 (Wed, 11 Dec 2024)
Changed paths:
M llvm/test/CodeGen/RISCV/rvv/vl-opt-op-info.mir
Log Message:
-----------
[RISCV][VLOPT] Fix test case as a result of changes in #119602
Commit: 6ce6b1d3850dab3d389a8cfa1455fcbc9a5cb27c
https://github.com/llvm/llvm-project/commit/6ce6b1d3850dab3d389a8cfa1455fcbc9a5cb27c
Author: Michael Maitland <michaeltmaitland at gmail.com>
Date: 2024-12-11 (Wed, 11 Dec 2024)
Changed paths:
M llvm/test/CodeGen/RISCV/rvv/vl-opt-op-info.mir
Log Message:
-----------
[RISCV][VLOPT] Use noreg where possible in vl-opt-op-info.mir
Commit: ccfcc9117b70828390019979219fa26ce77c3900
https://github.com/llvm/llvm-project/commit/ccfcc9117b70828390019979219fa26ce77c3900
Author: Philip Reames <preames at rivosinc.com>
Date: 2024-12-11 (Wed, 11 Dec 2024)
Changed paths:
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-shuffles.ll
Log Message:
-----------
[RISCV] Add coverage for zipeven/zipodd shuffles
Commit: db9856b516a36c259fb17af422cd80d6ebc67406
https://github.com/llvm/llvm-project/commit/db9856b516a36c259fb17af422cd80d6ebc67406
Author: Leandro Lupori <leandro.lupori at linaro.org>
Date: 2024-12-11 (Wed, 11 Dec 2024)
Changed paths:
M flang/lib/Lower/OpenMP/DataSharingProcessor.cpp
M flang/lib/Lower/OpenMP/DataSharingProcessor.h
M flang/lib/Lower/OpenMP/OpenMP.cpp
Log Message:
-----------
[flang][OpenMP][NFC] Turn symTable into a reference (#119435)
Convert `DataSharingProcessor::symTable` from pointer to reference.
This avoids accidental null pointer dereferences and makes it
possible to use `symTable` when delayed privatization is disabled.
Commit: 42d598b591713c2034c3c7138299babb4565ee2c
https://github.com/llvm/llvm-project/commit/42d598b591713c2034c3c7138299babb4565ee2c
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-12-11 (Wed, 11 Dec 2024)
Changed paths:
M llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
Log Message:
-----------
[RISCV] Rename a lambda to have plural nouns to reflect that it contains a loop. NFC
storeRegToStackSlot contains a loop that stores multiple registers
to multiple slots.
Commit: 80f31fa48e4f3cef36d8f464f93b8ac6b2834450
https://github.com/llvm/llvm-project/commit/80f31fa48e4f3cef36d8f464f93b8ac6b2834450
Author: David Green <david.green at arm.com>
Date: 2024-12-11 (Wed, 11 Dec 2024)
Changed paths:
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
M llvm/test/CodeGen/AArch64/dag-combine-setcc.ll
M llvm/test/CodeGen/AArch64/illegal-floating-point-vector-compares.ll
M llvm/test/CodeGen/AArch64/reduce-and.ll
M llvm/test/CodeGen/AArch64/reduce-or.ll
M llvm/test/CodeGen/AArch64/vecreduce-and-legalization.ll
M llvm/test/CodeGen/AArch64/vecreduce-bool.ll
M llvm/test/CodeGen/AArch64/vecreduce-umax-legalization.ll
M llvm/test/CodeGen/AArch64/vector-extract-last-active.ll
Log Message:
-----------
Revert "[AArch64] Improve code generation of bool vector reduce operations (#115713)"
This reverts commit 97ff96173abc0e914d5c8716ccc6356342aca043 as it conflicts
with fast-math and possible denormal flushing.
Commit: 87d2aecc05c378ad2170c15d7dc03aeb9c08641c
https://github.com/llvm/llvm-project/commit/87d2aecc05c378ad2170c15d7dc03aeb9c08641c
Author: Martin Storsjö <martin at martin.st>
Date: 2024-12-11 (Wed, 11 Dec 2024)
Changed paths:
M llvm/Maintainers.md
Log Message:
-----------
[LLVM] Fix a typo in my username in Maintainers.md. NFC.
The typo stems from the rewrite of this file in
bf488ed6e1fbe4c494a1dc0dd199a3d03405784e.
Commit: eac1e13addb147712aa1772df932111feb5c4de1
https://github.com/llvm/llvm-project/commit/eac1e13addb147712aa1772df932111feb5c4de1
Author: Jordan Rupprecht <rupprecht at google.com>
Date: 2024-12-11 (Wed, 11 Dec 2024)
Changed paths:
M utils/bazel/llvm-project-overlay/mlir/BUILD.bazel
M utils/bazel/llvm-project-overlay/mlir/python/BUILD.bazel
Log Message:
-----------
[bzl][mlir][emitc] Add build targets for EmitC C-API/Python bindings (#119610)
Added by 3c464d23682b0f9e6f70965e8f8f3861c9ba5417
Commit: a54fce89fc8aff36c50e3a0ea2f92e1ab7093cf8
https://github.com/llvm/llvm-project/commit/a54fce89fc8aff36c50e3a0ea2f92e1ab7093cf8
Author: Vitaly Buka <vitalybuka at google.com>
Date: 2024-12-11 (Wed, 11 Dec 2024)
Changed paths:
M libcxxabi/src/private_typeinfo.cpp
Log Message:
-----------
[libc++abi] Don't do pointer arithmetic on nullptr (#119520)
`nullptr + offset` is possible after `!is_virtual` branch.
Detected with check-cxxabi on configured with:
```
cmake -DLLVM_APPEND_VC_REV=OFF -GNinja \
-DCMAKE_BUILD_TYPE=Release \
-DLLVM_CCACHE_BUILD=ON \
-DLLVM_USE_LINKER=lld \
-DLLVM_ENABLE_ASSERTIONS=ON \
-DCMAKE_C_COMPILER=clang \
-DCMAKE_CXX_COMPILER=clang++ \
-DLIBCXXABI_USE_LLVM_UNWINDER=OFF \
-DCMAKE_INSTALL_PREFIX=/home/b/sanitizer-aarch64-linux-bootstrap-ubsan/build/libcxx_install_ubsan \
'-DLLVM_ENABLE_RUNTIMES=libcxx;libcxxabi;libunwind' \
-DLIBCXX_TEST_PARAMS=long_tests=False \
-DLIBCXX_INCLUDE_BENCHMARKS=OFF \
-DLLVM_USE_SANITIZER=Undefined \
'-DCMAKE_C_FLAGS=-fsanitize=undefined -fno-sanitize-recover=all -fno-sanitize=vptr' \
'-DCMAKE_CXX_FLAGS=-fsanitize=undefined -fno-sanitize-recover=all -fno-sanitize=vptr' \
/home/b/sanitizer-aarch64-linux-bootstrap-ubsan/build/llvm-project/llvm/../runtimes
********************
Failed Tests (2):
llvm-libc++abi-shared.cfg.in :: catch_null_pointer_to_object_pr64953.pass.cpp
llvm-libc++abi-shared.cfg.in :: catch_ptr_02.pass.cpp
```
Commit: 19bc282320ba4d2e961e287f110b9110297ae3ee
https://github.com/llvm/llvm-project/commit/19bc282320ba4d2e961e287f110b9110297ae3ee
Author: Nuno Lopes <nuno.lopes at tecnico.ulisboa.pt>
Date: 2024-12-11 (Wed, 11 Dec 2024)
Changed paths:
M llvm/utils/git/code-format-helper.py
Log Message:
-----------
Add PR check to suggest alternatives to using undef (#118506)
As discussed in
https://discourse.llvm.org/t/please-dont-use-undef-in-tests-part-2/83388,
this patch adds a comment to PRs that introduce new uses of undef.
It uses the the `git diff -S' command to find new uses, avoiding warning
about old uses. It further trims down with a regex to get only added (+)
lines.
Commit: 5fae408d3a4c073ee43aec9906fa44ffe4026301
https://github.com/llvm/llvm-project/commit/5fae408d3a4c073ee43aec9906fa44ffe4026301
Author: Florian Hahn <flo at fhahn.com>
Date: 2024-12-11 (Wed, 11 Dec 2024)
Changed paths:
M llvm/docs/Vectorizers.rst
A llvm/docs/vplan-early-exit.dot
A llvm/docs/vplan-early-exit.png
M llvm/include/llvm/Transforms/Vectorize/LoopVectorizationLegality.h
M llvm/lib/Transforms/Vectorize/LoopVectorizationLegality.cpp
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
M llvm/lib/Transforms/Vectorize/VPlan.cpp
M llvm/lib/Transforms/Vectorize/VPlan.h
M llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
M llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
M llvm/lib/Transforms/Vectorize/VPlanTransforms.h
M llvm/test/Transforms/LoopVectorize/early_exit_legality.ll
M llvm/test/Transforms/LoopVectorize/single_early_exit.ll
A llvm/test/Transforms/LoopVectorize/uncountable-early-exit-vplan.ll
M llvm/test/Transforms/LoopVectorize/unsupported_early_exit.ll
Log Message:
-----------
[VPlan] Dispatch to multiple exit blocks via middle blocks. (#112138)
A more lightweight variant of
https://github.com/llvm/llvm-project/pull/109193,
which dispatches to multiple exit blocks via the middle blocks.
The patch also introduces a bit of required scaffolding to enable
early-exit vectorization, including an option. At the moment, early-exit
vectorization doesn't come with legality checks, and is only used if the
option is provided and the loop has metadata forcing vectorization. This
is only intended to be used for testing during bring-up, with @david-arm
enabling auto early-exit vectorization plugging in the changes from
https://github.com/llvm/llvm-project/pull/88385.
PR: https://github.com/llvm/llvm-project/pull/112138
Commit: 6f3f08abdc9faac1fe07018bf72d532443f2ec05
https://github.com/llvm/llvm-project/commit/6f3f08abdc9faac1fe07018bf72d532443f2ec05
Author: Owen Anderson <resistor at mac.com>
Date: 2024-12-12 (Thu, 12 Dec 2024)
Changed paths:
M llvm/include/llvm/CodeGen/TargetRegisterInfo.h
M llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
M llvm/lib/Target/Hexagon/HexagonRegisterInfo.cpp
M llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
M llvm/lib/Target/X86/X86RegisterInfo.cpp
M llvm/unittests/CodeGen/MachineInstrTest.cpp
M llvm/utils/TableGen/RegisterInfoEmitter.cpp
Log Message:
-----------
CodeGen: Eliminate dynamic relocations in the register superclass tables. (#119487)
This reapplies #119122 with a fix for UBSAN errors in the X86 backend
related
to incrementing a nullptr.
Commit: 4993a30365309c5a0406fb63647be96e93fa3516
https://github.com/llvm/llvm-project/commit/4993a30365309c5a0406fb63647be96e93fa3516
Author: Florian Hahn <flo at fhahn.com>
Date: 2024-12-11 (Wed, 11 Dec 2024)
Changed paths:
M llvm/test/Transforms/LoopVectorize/uncountable-early-exit-vplan.ll
Log Message:
-----------
[LV] Add missing REQUIRES: asserts to test using -debug.
Fixup for test added in 5fae408d3a4c07.
Commit: 6b2232606d01a029f640b61b4f985d9dea79d4b6
https://github.com/llvm/llvm-project/commit/6b2232606d01a029f640b61b4f985d9dea79d4b6
Author: Sergei Barannikov <barannikov88 at gmail.com>
Date: 2024-12-12 (Thu, 12 Dec 2024)
Changed paths:
M llvm/include/llvm/CodeGen/SDNodeProperties.td
M llvm/include/llvm/Target/TargetSelectionDAG.td
M llvm/lib/Target/AArch64/SMEInstrFormats.td
M llvm/lib/Target/AArch64/SVEInstrFormats.td
M llvm/lib/Target/AMDGPU/BUFInstructions.td
M llvm/lib/Target/AMDGPU/FLATInstructions.td
M llvm/lib/Target/ARM/ARMInstrInfo.td
M llvm/lib/Target/ARM/ARMInstrMVE.td
M llvm/lib/Target/ARM/ARMInstrThumb.td
M llvm/lib/Target/ARM/ARMInstrThumb2.td
M llvm/lib/Target/AVR/AVRInstrInfo.td
M llvm/lib/Target/M68k/M68kInstrInfo.td
M llvm/lib/Target/NVPTX/NVPTXInstrInfo.td
M llvm/lib/Target/PowerPC/PPCInstrInfo.td
M llvm/lib/Target/X86/X86InstrFragments.td
M llvm/utils/TableGen/Basic/SDNodeProperties.h
M llvm/utils/TableGen/Common/CodeGenTarget.cpp
M llvm/utils/TableGen/Common/CodeGenTarget.h
M llvm/utils/TableGen/DAGISelMatcherEmitter.cpp
Log Message:
-----------
[TableGen] Replace WantRoot/WantParent SDNode properties with flags (#119599)
These properties are only valid on ComplexPatterns. Having them as flags
is more convenient because one can now use "let = ... in" syntax to set
these flags on several patterns at a time. This is also less error-prone
as it makes it impossible to specify these properties on records derived
from SDPatternOperator.
Pull Request: https://github.com/llvm/llvm-project/pull/119599
Commit: d5b7b970347fd4aa5591bfee38be4d8e7a53b134
https://github.com/llvm/llvm-project/commit/d5b7b970347fd4aa5591bfee38be4d8e7a53b134
Author: Shourya Goel <shouryagoel10000 at gmail.com>
Date: 2024-12-12 (Thu, 12 Dec 2024)
Changed paths:
M libc/config/linux/aarch64/headers.txt
M libc/config/linux/arm/headers.txt
M libc/config/linux/riscv/headers.txt
M libc/config/linux/x86_64/headers.txt
A libc/hdrgen/yaml/complex.yaml
Log Message:
-----------
[libc][complex] Add complex.yaml in hdrgen. (#119609)
Commit: 7dbd6cd2946ec3a9b4ad2dfd7ead177baac15bd7
https://github.com/llvm/llvm-project/commit/7dbd6cd2946ec3a9b4ad2dfd7ead177baac15bd7
Author: Shilei Tian <i at tianshilei.me>
Date: 2024-12-11 (Wed, 11 Dec 2024)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPUAttributor.cpp
M llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
M llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h
M llvm/test/CodeGen/AMDGPU/addrspacecast-constantexpr.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-attributor-no-agpr.ll
M llvm/test/CodeGen/AMDGPU/annotate-existing-abi-attributes.ll
M llvm/test/CodeGen/AMDGPU/annotate-kernel-features-hsa-call.ll
M llvm/test/CodeGen/AMDGPU/annotate-kernel-features-hsa.ll
M llvm/test/CodeGen/AMDGPU/attr-amdgpu-max-num-workgroups-propagate.ll
M llvm/test/CodeGen/AMDGPU/attributor-flatscratchinit.ll
M llvm/test/CodeGen/AMDGPU/attributor-loop-issue-58639.ll
M llvm/test/CodeGen/AMDGPU/direct-indirect-call.ll
M llvm/test/CodeGen/AMDGPU/duplicate-attribute-indirect.ll
M llvm/test/CodeGen/AMDGPU/implicitarg-offset-attributes.ll
M llvm/test/CodeGen/AMDGPU/indirect-call-set-from-other-function.ll
M llvm/test/CodeGen/AMDGPU/inline-attr.ll
M llvm/test/CodeGen/AMDGPU/propagate-flat-work-group-size.ll
M llvm/test/CodeGen/AMDGPU/propagate-waves-per-eu.ll
M llvm/test/CodeGen/AMDGPU/recursive_global_initializer.ll
M llvm/test/CodeGen/AMDGPU/remove-no-kernel-id-attribute.ll
M llvm/test/CodeGen/AMDGPU/simple-indirect-call-2.ll
M llvm/test/CodeGen/AMDGPU/simple-indirect-call.ll
M llvm/test/CodeGen/AMDGPU/simplify-libcalls.ll
M llvm/test/CodeGen/AMDGPU/uniform-work-group-attribute-missing.ll
M llvm/test/CodeGen/AMDGPU/uniform-work-group-multistep.ll
M llvm/test/CodeGen/AMDGPU/uniform-work-group-nested-function-calls.ll
M llvm/test/CodeGen/AMDGPU/uniform-work-group-prevent-attribute-propagation.ll
M llvm/test/CodeGen/AMDGPU/uniform-work-group-propagate-attribute.ll
M llvm/test/CodeGen/AMDGPU/uniform-work-group-recursion-test.ll
M llvm/test/CodeGen/AMDGPU/uniform-work-group-test.ll
Log Message:
-----------
[AMDGPU][Attributor] Make `AAAMDFlatWorkGroupSize` honor existing attribute (#114357)
If a function has `amdgpu-flat-work-group-size`, honor it in `initialize` by
taking its value directly; otherwise, it uses the default range as a starting
point. We will no longer manipulate the known range, which can cause issues
because the known range is a "throttle" to the assumed range such that the
assumed range can't get widened properly in `updateImpl` if the known range is
not set properly for whatever reasons. Another benefit of not touching the known
range is, if we indicate pessimistic state, it also invalidates the AA such that
`manifest` will not be called. Since we honor the attribute, we don't want and
will not add any half-baked attribute added to a function.
Commit: f4037277bb0220cb1dece91d21d4fdc2995eae7a
https://github.com/llvm/llvm-project/commit/f4037277bb0220cb1dece91d21d4fdc2995eae7a
Author: Shilei Tian <i at tianshilei.me>
Date: 2024-12-11 (Wed, 11 Dec 2024)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPUAttributor.cpp
M llvm/test/CodeGen/AMDGPU/annotate-kernel-features-hsa-call.ll
M llvm/test/CodeGen/AMDGPU/attr-amdgpu-max-num-workgroups-propagate.ll
M llvm/test/CodeGen/AMDGPU/attributor-loop-issue-58639.ll
M llvm/test/CodeGen/AMDGPU/direct-indirect-call.ll
M llvm/test/CodeGen/AMDGPU/propagate-waves-per-eu.ll
M llvm/test/CodeGen/AMDGPU/remove-no-kernel-id-attribute.ll
M llvm/test/CodeGen/AMDGPU/uniform-work-group-multistep.ll
M llvm/test/CodeGen/AMDGPU/uniform-work-group-recursion-test.ll
Log Message:
-----------
[AMDGPU][Attributor] Make `AAAMDWavesPerEU` honor existing attribute (#114438)
Commit: 4b8bf6aac890a1ab35ab3d807b49ab02181e49d9
https://github.com/llvm/llvm-project/commit/4b8bf6aac890a1ab35ab3d807b49ab02181e49d9
Author: Louis Dionne <ldionne.2 at gmail.com>
Date: 2024-12-11 (Wed, 11 Dec 2024)
Changed paths:
M libcxx/include/flat_map
M libcxx/test/libcxx/transitive_includes/cxx03.csv
M libcxx/test/libcxx/transitive_includes/cxx11.csv
M libcxx/test/libcxx/transitive_includes/cxx14.csv
M libcxx/test/libcxx/transitive_includes/cxx17.csv
M libcxx/test/libcxx/transitive_includes/cxx20.csv
Log Message:
-----------
[libc++] Properly guard flat_map includes based on C++ version (#119227)
That's what we (try to) do consistently for all other umbrella headers.
As a drive-by, remove the <__assert> header which is not mandated
anymore.
Commit: fbe3919e5477b64e30cf435618ab643700d0952a
https://github.com/llvm/llvm-project/commit/fbe3919e5477b64e30cf435618ab643700d0952a
Author: Michal Paszkowski <michal at paszkowski.org>
Date: 2024-12-11 (Wed, 11 Dec 2024)
Changed paths:
M llvm/test/CodeGen/SPIRV/constant/local-arbitrary-width-integers-constants-type-promotion.ll
M llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_function_pointers/fp-simple-hierarchy.ll
M llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_function_pointers/fp_const.ll
M llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_function_pointers/fun-ptr-addrcast.ll
M llvm/test/CodeGen/SPIRV/extensions/SPV_KHR_cooperative_matrix/cooperative_matrix.ll
M llvm/test/CodeGen/SPIRV/instructions/vector-shuffle.ll
M llvm/test/CodeGen/SPIRV/spec_const_decoration.ll
M llvm/test/CodeGen/SPIRV/transcoding/OpBitReverse-subbyte.ll
M llvm/test/CodeGen/SPIRV/transcoding/OpBitReverse_i2.ll
M llvm/test/CodeGen/SPIRV/transcoding/OpGroupAsyncCopy.ll
M llvm/test/CodeGen/SPIRV/transcoding/OpVectorExtractDynamic.ll
M llvm/test/CodeGen/SPIRV/trunc-nonstd-bitwidth.ll
Log Message:
-----------
[SPIR-V] Mark XFAIL tests which fail with LLVM_ENABLE_EXPENSIVE_CHECKS (#119497)
The test cases marked with XFAIL by this commit are not yet supported by
the SPIR-V backend with LLVM_ENABLE_EXPENSIVE_CHECKS enabled.
Commit: 6f013dbced67948119fe9ca71336f0284975ba4f
https://github.com/llvm/llvm-project/commit/6f013dbced67948119fe9ca71336f0284975ba4f
Author: Alexandros Lamprineas <alexandros.lamprineas at arm.com>
Date: 2024-12-11 (Wed, 11 Dec 2024)
Changed paths:
M clang/test/CodeGen/AArch64/cpu-supports.c
M clang/test/CodeGen/AArch64/fmv-dependencies.c
M clang/test/CodeGen/AArch64/mixed-target-attributes.c
M clang/test/CodeGen/attr-target-clones-aarch64.c
M clang/test/CodeGen/attr-target-version.c
M clang/test/CodeGenCXX/attr-target-clones-aarch64.cpp
M clang/test/CodeGenCXX/attr-target-version.cpp
M clang/test/CodeGenCXX/fmv-namespace.cpp
M llvm/include/llvm/TargetParser/AArch64TargetParser.h
M llvm/lib/Target/AArch64/AArch64Features.td
M llvm/lib/TargetParser/AArch64TargetParser.cpp
M llvm/test/CodeGen/AArch64/sve-streaming-mode-cvt-fp-int-fp.ll
M llvm/test/MC/AArch64/SME/streaming-mode-neon-negative.s
M llvm/test/MC/AArch64/SME/streaming-sve-feature.s
M llvm/test/MC/AArch64/armv8a-fpmul.s
Log Message:
-----------
[AArch64][FMV] Add missing feature dependencies and detect at runtime. (#119231)
i8mm -> simd
fp16fml -> simd
frintts -> fp
bf16 -> simd
sme -> fp16
Approved in ACLE as https://github.com/ARM-software/acle/pull/368
Commit: 2470cfab63ac14df02dc6df686fcae7b1a4eb84f
https://github.com/llvm/llvm-project/commit/2470cfab63ac14df02dc6df686fcae7b1a4eb84f
Author: Adrian Prantl <aprantl at apple.com>
Date: 2024-12-11 (Wed, 11 Dec 2024)
Changed paths:
M lldb/source/DataFormatters/FormatterBytecode.cpp
M lldb/unittests/DataFormatter/FormatterBytecodeTest.cpp
Log Message:
-----------
[lldb] Disallow left shifts of negative values in the interpreter (#119620)
This trips UBSAN and probably isn't partiuclarly useful either.
Commit: ee090cb83b523e4c8c888ded8ca1a70334ba65fa
https://github.com/llvm/llvm-project/commit/ee090cb83b523e4c8c888ded8ca1a70334ba65fa
Author: erichkeane <ekeane at nvidia.com>
Date: 2024-12-11 (Wed, 11 Dec 2024)
Changed paths:
M clang/lib/Parse/ParseOpenACC.cpp
M clang/test/ParserOpenACC/parse-clauses.c
M clang/test/ParserOpenACC/parse-clauses.cpp
Log Message:
-----------
[OpenACC] Treat 'delete' as a valid clause during parsing in C++ mode
This didn't end up being properly tested, but 'delete' as a keyword
causes us to not properly recognize it as a clause kind. This patch
correctly adds the work to make sure it is recognized correctly.
Commit: 4b825c7417f72ee88ee3e4316d0c01ed463f1241
https://github.com/llvm/llvm-project/commit/4b825c7417f72ee88ee3e4316d0c01ed463f1241
Author: Alexander Yermolovich <43973793+ayermolo at users.noreply.github.com>
Date: 2024-12-11 (Wed, 11 Dec 2024)
Changed paths:
M bolt/include/bolt/Core/DIEBuilder.h
M bolt/include/bolt/Core/DebugNames.h
M bolt/lib/Core/DIEBuilder.cpp
M bolt/lib/Core/DebugNames.cpp
A bolt/test/X86/dwarf5-debug-names-abstract-origin-linkage-name-only.s
A bolt/test/X86/dwarf5-debug-names-abstract-origin-specification.s
Log Message:
-----------
[BOLT][DWARF] Add support for transitive DW_AT_name/DW_AT_linkage_name resolution for DW_AT_name/DW_AT_linkage_name. (#119493)
This fix handles a case where a DIE that does not have
DW_AT_name/DW_AT_linkage_name, but has a reference to another DIE using
DW_AT_abstract_origin/DW_AT_specification. It also fixes a bug where
there are cross CU references for those attributes. Previously it would
use a DWARF Unit of a DIE which was being processed The
warf5-debug-names-cross-cu.s test just happened to work because how it
was constructed where string section was shared by both DWARF Units.
To resolve DW_AT_name/DW_AT_linkage_name this patch iterates over
references until it either reaches the final DIE or finds both of those
names.
Commit: ba373a222fe6f65c45a05e9e1114c92580953b79
https://github.com/llvm/llvm-project/commit/ba373a222fe6f65c45a05e9e1114c92580953b79
Author: Congcong Cai <congcongcai0907 at 163.com>
Date: 2024-12-12 (Thu, 12 Dec 2024)
Changed paths:
M clang-tools-extra/clang-tidy/bugprone/OptionalValueConversionCheck.cpp
M clang-tools-extra/docs/ReleaseNotes.rst
A clang-tools-extra/test/clang-tidy/checkers/bugprone/optional-value-conversion-construct-from-std.cpp
Log Message:
-----------
[clang-tidy]detecting conversion directly by `make_unique` and `make_shared` in bugprone-optional-value-conversion (#119371)
Inspired by #110964
Commit: 5eef9ba7842522f360d7891c642a39b92a6de33a
https://github.com/llvm/llvm-project/commit/5eef9ba7842522f360d7891c642a39b92a6de33a
Author: Slava Zakharin <szakharin at nvidia.com>
Date: 2024-12-11 (Wed, 11 Dec 2024)
Changed paths:
M flang/lib/Optimizer/HLFIR/Transforms/SimplifyHLFIRIntrinsics.cpp
A flang/test/HLFIR/simplify-hlfir-intrinsics-cshift.fir
Log Message:
-----------
[flang] Inline hlfir.cshift as hlfir.elemental. (#119480)
Commit: 36c7d147fcd01492cf9491cb0cddd3702b8fd31c
https://github.com/llvm/llvm-project/commit/36c7d147fcd01492cf9491cb0cddd3702b8fd31c
Author: Caslyn Tonelli <6718161+Caslyn at users.noreply.github.com>
Date: 2024-12-11 (Wed, 11 Dec 2024)
Changed paths:
M libc/test/src/strings/CMakeLists.txt
M libc/test/src/strings/index_test.cpp
M libc/test/src/strings/rindex_test.cpp
Log Message:
-----------
[libc][test] Adjust header paths in tests (#119623)
Since `index_test.cpp` and `rindex_test.cpp` now reside in /strings,
adjust some header paths accordingly.
Link: #118899
Commit: 151901c762b724ef6ffe6f3db163475071e7b215
https://github.com/llvm/llvm-project/commit/151901c762b724ef6ffe6f3db163475071e7b215
Author: Valentin Clement (バレンタイン クレメン) <clementval at gmail.com>
Date: 2024-12-11 (Wed, 11 Dec 2024)
Changed paths:
M flang/include/flang/Common/Fortran-consts.h
Log Message:
-----------
[flang][rt][device] Use enum-set.h as Fortran.h (#119611)
Commit: dd647e3e608ed0b2bac7c588d5859b80ef4a5976
https://github.com/llvm/llvm-project/commit/dd647e3e608ed0b2bac7c588d5859b80ef4a5976
Author: Chandler Carruth <chandlerc at gmail.com>
Date: 2024-12-11 (Wed, 11 Dec 2024)
Changed paths:
M clang-tools-extra/clangd/CompileCommands.cpp
M clang/lib/Driver/DriverOptions.cpp
M clang/lib/Frontend/CompilerInvocation.cpp
M clang/tools/clang-installapi/Options.cpp
M clang/tools/clang-linker-wrapper/ClangLinkerWrapper.cpp
M clang/tools/clang-nvlink-wrapper/ClangNVLinkWrapper.cpp
M clang/tools/clang-scan-deps/ClangScanDeps.cpp
M clang/tools/clang-sycl-linker/ClangSYCLLinker.cpp
M lld/COFF/DriverUtils.cpp
M lld/ELF/DriverUtils.cpp
M lld/MachO/DriverUtils.cpp
M lld/MinGW/Driver.cpp
M lld/wasm/Driver.cpp
M lldb/source/Plugins/Platform/MacOSX/PlatformDarwin.cpp
M lldb/tools/driver/Driver.cpp
M lldb/tools/lldb-dap/lldb-dap.cpp
M lldb/tools/lldb-server/lldb-gdbserver.cpp
M llvm/include/llvm/Option/OptTable.h
M llvm/include/llvm/Option/Option.h
M llvm/lib/ExecutionEngine/JITLink/COFFDirectiveParser.cpp
M llvm/lib/Option/OptTable.cpp
M llvm/lib/Option/Option.cpp
M llvm/lib/ToolDrivers/llvm-dlltool/DlltoolDriver.cpp
M llvm/lib/ToolDrivers/llvm-lib/LibDriver.cpp
M llvm/tools/dsymutil/dsymutil.cpp
M llvm/tools/llvm-cgdata/llvm-cgdata.cpp
M llvm/tools/llvm-cvtres/llvm-cvtres.cpp
M llvm/tools/llvm-cxxfilt/llvm-cxxfilt.cpp
M llvm/tools/llvm-debuginfod-find/llvm-debuginfod-find.cpp
M llvm/tools/llvm-debuginfod/llvm-debuginfod.cpp
M llvm/tools/llvm-dwarfutil/llvm-dwarfutil.cpp
M llvm/tools/llvm-dwp/llvm-dwp.cpp
M llvm/tools/llvm-gsymutil/llvm-gsymutil.cpp
M llvm/tools/llvm-ifs/llvm-ifs.cpp
M llvm/tools/llvm-libtool-darwin/llvm-libtool-darwin.cpp
M llvm/tools/llvm-lipo/llvm-lipo.cpp
M llvm/tools/llvm-ml/llvm-ml.cpp
M llvm/tools/llvm-mt/llvm-mt.cpp
M llvm/tools/llvm-nm/llvm-nm.cpp
M llvm/tools/llvm-objcopy/ObjcopyOptions.cpp
M llvm/tools/llvm-objdump/llvm-objdump.cpp
M llvm/tools/llvm-rc/llvm-rc.cpp
M llvm/tools/llvm-readobj/llvm-readobj.cpp
M llvm/tools/llvm-readtapi/llvm-readtapi.cpp
M llvm/tools/llvm-size/llvm-size.cpp
M llvm/tools/llvm-strings/llvm-strings.cpp
M llvm/tools/llvm-symbolizer/llvm-symbolizer.cpp
M llvm/tools/llvm-tli-checker/llvm-tli-checker.cpp
M llvm/tools/sancov/sancov.cpp
M llvm/unittests/Option/OptionMarshallingTest.cpp
M llvm/unittests/Option/OptionParsingTest.cpp
M llvm/utils/TableGen/OptionParserEmitter.cpp
Log Message:
-----------
Rework the `Option` library to reduce dynamic relocations (#119198)
Apologies for the large change, I looked for ways to break this up and
all of the ones I saw added real complexity. This change focuses on the
option's prefixed names and the array of prefixes. These are present in
every option and the dominant source of dynamic relocations for PIE or
PIC users of LLVM and Clang tooling. In some cases, 100s or 1000s of
them for the Clang driver which has a huge number of options.
This PR addresses this by building a string table and a prefixes table
that can be referenced with indices rather than pointers that require
dynamic relocations. This removes almost 7k dynmaic relocations from the
`clang` binary, roughly 8% of the remaining dynmaic relocations outside
of vtables. For busy-boxing use cases where many different option tables
are linked into the same binary, the savings add up a bit more.
The string table is a straightforward mechanism, but the prefixes
required some subtlety. They are encoded in a Pascal-string fashion with
a size followed by a sequence of offsets. This works relatively well for
the small realistic prefixes arrays in use.
Lots of code has to change in order to land this though: both all the
option library code has to be updated to use the string table and
prefixes table, and all the users of the options library have to be
updated to correctly instantiate the objects.
Some follow-up patches in the works to provide an abstraction for this
style of code, and to start using the same technique for some of the
other strings here now that the infrastructure is in place.
Commit: ea632e1b34e1878b977f8adc406a89e91aa98b7e
https://github.com/llvm/llvm-project/commit/ea632e1b34e1878b977f8adc406a89e91aa98b7e
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2024-12-11 (Wed, 11 Dec 2024)
Changed paths:
M llvm/include/llvm/CodeGen/MachineInstr.h
M llvm/include/llvm/IR/DiagnosticInfo.h
M llvm/include/llvm/IR/LLVMContext.h
M llvm/lib/CodeGen/AsmPrinter/AsmPrinterInlineAsm.cpp
M llvm/lib/CodeGen/MachineInstr.cpp
M llvm/lib/CodeGen/RegAllocBase.cpp
M llvm/lib/CodeGen/RegAllocFast.cpp
M llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
M llvm/lib/CodeGen/XRayInstrumentation.cpp
M llvm/lib/IR/DiagnosticInfo.cpp
M llvm/lib/IR/LLVMContext.cpp
M llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
M llvm/lib/Target/ARM/ARMMCInstLower.cpp
M llvm/lib/Target/X86/X86FloatingPoint.cpp
M llvm/test/CodeGen/AMDGPU/sgpr-spill-to-vmem-scc-clobber-unhandled.mir
Log Message:
-----------
Reapply "DiagnosticInfo: Clean up usage of DiagnosticInfoInlineAsm" (#119575) (#119634)
This reverts commit 40986feda8b1437ed475b144d5b9a208b008782a.
Reapply with fix to prevent temporary Twine from going out of scope.
Commit: be4a18387c61130de1cd2147ceaebdfe278ea370
https://github.com/llvm/llvm-project/commit/be4a18387c61130de1cd2147ceaebdfe278ea370
Author: Andrei Safronov <andrei.safronov at espressif.com>
Date: 2024-12-12 (Thu, 12 Dec 2024)
Changed paths:
M llvm/lib/Target/Xtensa/XtensaISelLowering.cpp
M llvm/lib/Target/Xtensa/XtensaISelLowering.h
M llvm/lib/Target/Xtensa/XtensaMachineFunctionInfo.h
A llvm/test/CodeGen/Xtensa/vararg.ll
Log Message:
-----------
[Xtensa] Implement vararg support. (#117126)
Commit: 956d0dd624758599ec7411997ef65f6ad16823f1
https://github.com/llvm/llvm-project/commit/956d0dd624758599ec7411997ef65f6ad16823f1
Author: Valentin Clement (バレンタイン クレメン) <clementval at gmail.com>
Date: 2024-12-11 (Wed, 11 Dec 2024)
Changed paths:
M flang/lib/Optimizer/Transforms/CUFDeviceGlobal.cpp
M flang/test/Fir/CUDA/cuda-implicit-device-global.f90
Log Message:
-----------
[flang][cuda] Support builtin global in device global pass (#119626)
Commit: 44c05a627ffb4bdd63b477d2d74b2b6db2f87c74
https://github.com/llvm/llvm-project/commit/44c05a627ffb4bdd63b477d2d74b2b6db2f87c74
Author: knickish <knickish at gmail.com>
Date: 2024-12-11 (Wed, 11 Dec 2024)
Changed paths:
M llvm/lib/Target/M68k/M68kInstrControl.td
M llvm/lib/Target/M68k/MCTargetDesc/M68kAsmBackend.cpp
M llvm/test/MC/M68k/Control/bsr.s
A llvm/test/MC/M68k/Control/bsr32.s
A llvm/test/MC/M68k/Relaxations/PIC/branch.s
A llvm/test/MC/M68k/Relaxations/PIC/branch32.s
A llvm/test/MC/M68k/Relaxations/PIC/bsr.s
A llvm/test/MC/M68k/Relaxations/branch32.s
A llvm/test/MC/M68k/Relocations/PIC/data-abs.s
A llvm/test/MC/M68k/Relocations/PIC/data-gotoff.s
A llvm/test/MC/M68k/Relocations/PIC/data-gotpcrel.s
A llvm/test/MC/M68k/Relocations/PIC/data-pc-rel.s
A llvm/test/MC/M68k/Relocations/PIC/text-plt.s
M llvm/test/MC/M68k/Relocations/text-plt.s
Log Message:
-----------
[M68k] add 32 bit branch instrs and relaxations (#117371)
The `Bcc` and `BRA` 32-bit variants were all either not present or not
used, and the `BSR32` instruction was incorrectly being used on <
`M68020` cpu types. This PR adds missing 32 bit branch instructions
(with the `AtLeastM68020` predicate) and updates `M68kAsmBackend` to
allow relaxation to these instructions when an `M68020` or greater is
targeted
Commit: a6742094324d7166b451c749acf81d27a504c47b
https://github.com/llvm/llvm-project/commit/a6742094324d7166b451c749acf81d27a504c47b
Author: Elvis Wang <elvis.wang at sifive.com>
Date: 2024-12-12 (Thu, 12 Dec 2024)
Changed paths:
M llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
M llvm/test/Analysis/CostModel/RISCV/rvv-extractelement.ll
M llvm/test/Analysis/CostModel/RISCV/rvv-insertelement.ll
Log Message:
-----------
[RISCV][TTI] Model the cost of insert/extractelt when the vector split into multiple register group and idx exceed single group. (#118401)
This patch implements the cost when the size of the vector need to split
into multiple groups and the index exceed single vector group.
For extract element, we need to store split vectors to stack and load
the target element.
For insert element, we need to store split vectors to stack and store
the target element and load vectors back.
After this patch, the cost of insert/extract element will close to the
generated assembly.
Commit: f33e2369051e13a54a05dd361d89c1ba77f4f593
https://github.com/llvm/llvm-project/commit/f33e2369051e13a54a05dd361d89c1ba77f4f593
Author: Qiongsi Wu <274595+qiongsiwu at users.noreply.github.com>
Date: 2024-12-11 (Wed, 11 Dec 2024)
Changed paths:
M clang/include/clang/AST/Attr.h
M clang/include/module.modulemap
M clang/utils/TableGen/ClangAttrEmitter.cpp
M llvm/include/llvm/DebugInfo/DWARF/DWARFTypePrinter.h
M llvm/include/llvm/IR/NVVMIntrinsicFlags.h
M llvm/include/llvm/SandboxIR/Type.h
M llvm/include/llvm/Support/Memory.h
M llvm/include/llvm/TargetParser/AArch64TargetParser.h
M llvm/include/module.modulemap
M llvm/lib/SandboxIR/Type.cpp
Log Message:
-----------
[clang][Modules] Fixing Build Breaks When -DLLVM_ENABLE_MODULES=ON (#119473)
A few recent changes are causing build breaks when
`-DLLVM_ENABLE_MODULES=ON` (such as
834dfd23155351c9885eddf7b9664f7697326946 and
7dfdca1961aadc75ca397818bfb9bd32f1879248).
This PR makes the required updates so that clang/llvm builds when
`-DLLVM_ENABLE_MODULES=ON`.
rdar://140803058
Commit: 9f1e9f682d0a85ea013ccbce6a3ec4ac1be83356
https://github.com/llvm/llvm-project/commit/9f1e9f682d0a85ea013ccbce6a3ec4ac1be83356
Author: jijjijj <realjijjijj at gmail.com>
Date: 2024-12-12 (Thu, 12 Dec 2024)
Changed paths:
M clang/docs/ReleaseNotes.rst
M clang/lib/Sema/SemaDeclCXX.cpp
A clang/test/Modules/initializer-list-recognition-through-export-and-linkage-issue-118218.cpp
Log Message:
-----------
[C++20][modules] Fix std::initializer_list recognition if it's exported out of a module (#118537)
If the std::initializer_list is exported out of module, its
`DeclContext` is not a namespace as `Sema::isStdInitializerList`
expects, but an `Decl::Kind::Export` and only its parent is a namespace.
So this commit makes `Sema::isStdInitializerList` account for that.
I'm really new to clang so I'm not 100% sure that was the issue, it
seems so and it fixes compilation. Also I probably need to add tests but
I'd like someone to approve the idea first.
Fixes https://github.com/llvm/llvm-project/issues/118218
Commit: 9040dd469d61f59235ba5d2ef2c05e661159f877
https://github.com/llvm/llvm-project/commit/9040dd469d61f59235ba5d2ef2c05e661159f877
Author: Kazu Hirata <kazu at google.com>
Date: 2024-12-11 (Wed, 11 Dec 2024)
Changed paths:
M llvm/include/llvm/ProfileData/MemProfYAML.h
M llvm/test/tools/llvm-profdata/memprof-yaml.test
M llvm/tools/llvm-profdata/llvm-profdata.cpp
M llvm/unittests/ProfileData/MemProfTest.cpp
Log Message:
-----------
[memprof] Improve the way we express Frames in YAML (#119629)
This patch does two things:
- During deserialization, we accept a function name for Frame as an
alternative to the usual GUID expressed as a hexadecimal number.
- During serialization, we print a GUID of Frame as a 16-digit
hexadecimal number prefixed with 0x in the usual way. (Without this
patch, we print a decimal number, which is not customary.)
The patch uses a machinery called "normalization" in YAML I/O, which
lets us serialize and deserialize into an alternative data structure.
For our use case, we have an alternative Frame data structure, which
is identical to "struct Frame" except that Function is of type
GUIDHex64 instead of GlobalValue::GUID. This alternative type
supports the two bullet points above without modifying "struct Frame"
at all.
Commit: ae5836f6b6a8544e6226f5c1ba6b1beacfe01aef
https://github.com/llvm/llvm-project/commit/ae5836f6b6a8544e6226f5c1ba6b1beacfe01aef
Author: wanglei <wanglei at loongson.cn>
Date: 2024-12-12 (Thu, 12 Dec 2024)
Changed paths:
M lldb/source/Plugins/Process/Utility/CMakeLists.txt
A lldb/source/Plugins/Process/Utility/NativeRegisterContextDBReg.cpp
A lldb/source/Plugins/Process/Utility/NativeRegisterContextDBReg.h
M lldb/source/Plugins/Process/Utility/NativeRegisterContextDBReg_arm64.cpp
M lldb/source/Plugins/Process/Utility/NativeRegisterContextDBReg_arm64.h
Log Message:
-----------
[LLDB][Process/Utility] Introduce NativeRegisterContextDBReg class
Since the setup of debug registers for AArch64 and LoongArch is similar,
we extracted the shared logic from Class:
`NativeRegisterContextDBReg_arm64`
into a new Class:
`NativeRegisterContextDBReg`.
This will simplify the subsequent implementation of hardware breakpoints
and watchpoints on LoongArch.
Reviewed By: DavidSpickett
Pull Request: https://github.com/llvm/llvm-project/pull/118043
Commit: 80e7f5015659d2942d436b3f2c5ffe3a5e39dcf5
https://github.com/llvm/llvm-project/commit/80e7f5015659d2942d436b3f2c5ffe3a5e39dcf5
Author: LLVM GN Syncbot <llvmgnsyncbot at gmail.com>
Date: 2024-12-12 (Thu, 12 Dec 2024)
Changed paths:
M llvm/utils/gn/secondary/lldb/source/Plugins/Process/Utility/BUILD.gn
Log Message:
-----------
[gn build] Port ae5836f6b6a8
Commit: 8420602bc21098a737708f35caf96e696f948503
https://github.com/llvm/llvm-project/commit/8420602bc21098a737708f35caf96e696f948503
Author: Kazu Hirata <kazu at google.com>
Date: 2024-12-11 (Wed, 11 Dec 2024)
Changed paths:
M llvm/unittests/ProfileData/MemProfTest.cpp
Log Message:
-----------
[memprof] Drop testing:: in a unit test (NFC) (#119636)
Note that we already have:
using ::testing::IsEmpty;
Commit: a67bd94fdafce716b42e0cb5409ee451b20f1749
https://github.com/llvm/llvm-project/commit/a67bd94fdafce716b42e0cb5409ee451b20f1749
Author: Yingwei Zheng <dtcxzyw2333 at gmail.com>
Date: 2024-12-12 (Thu, 12 Dec 2024)
Changed paths:
M llvm/lib/Analysis/ValueTracking.cpp
M llvm/test/Transforms/InstCombine/fpclass-from-dom-cond.ll
Log Message:
-----------
[ValueTracking] Add missing operand checks in `computeKnownFPClassFromCond` (#119579)
After https://github.com/llvm/llvm-project/pull/118257, we may call
`computeKnownFPClassFromCond` with unrelated conditions. Then
miscompilations may occur due to a lack of operand checks.
This bug was introduced by
https://github.com/llvm/llvm-project/commit/d2404ea6ced5fce9442260bde08a02d607fdd50d
and https://github.com/llvm/llvm-project/pull/80740. However, the
miscompilation couldn't have happened before
https://github.com/llvm/llvm-project/pull/118257, because we only added
related conditions to `DomConditionCache/AssumptionCache`.
Fix the miscompilation reported in
https://github.com/llvm/llvm-project/pull/118257#issuecomment-2536182166.
Commit: 22f0ebb19cd216a1748263c4dbabcd832206f3ea
https://github.com/llvm/llvm-project/commit/22f0ebb19cd216a1748263c4dbabcd832206f3ea
Author: Owen Anderson <resistor at mac.com>
Date: 2024-12-12 (Thu, 12 Dec 2024)
Changed paths:
M llvm/include/llvm/Analysis/TargetLibraryInfo.h
M llvm/lib/Analysis/TargetLibraryInfo.cpp
M llvm/lib/Transforms/Utils/SimplifyLibCalls.cpp
M llvm/test/Transforms/InstCombine/stdio-custom-dl.ll
M llvm/test/Transforms/InstCombine/strcpy-nonzero-as.ll
M llvm/test/Transforms/MergeICmps/X86/distinct-index-width-crash.ll
Log Message:
-----------
TargetLibraryInfo: Use pointer index size to determine getSizeTSize(). (#118747)
When using non-integral pointer types, such as on CHERI targets, size_t
is equivalent
to the index size, which is allowed to be smaller than the size of the
pointer.
Commit: fd2f8d485df7742320317b14d49b9d808f70625c
https://github.com/llvm/llvm-project/commit/fd2f8d485df7742320317b14d49b9d808f70625c
Author: Vyacheslav Klochkov <vyacheslav.n.klochkov at intel.com>
Date: 2024-12-11 (Wed, 11 Dec 2024)
Changed paths:
M llvm/lib/Transforms/Vectorize/LoadStoreVectorizer.cpp
A llvm/test/Transforms/LoadStoreVectorizer/X86/massive_indirection.ll
Log Message:
-----------
[LoadStoreVectorizer] Postprocess and merge equivalence classes (#114501)
This patch introduces a new method:
void Vectorizer::mergeEquivalenceClasses(EquivalenceClassMap &EQClasses)
const
The method is called at the end of
Vectorizer::collectEquivalenceClasses() and is needed to merge
equivalence classes that differ only by their underlying objects (UO1
and UO2), where UO1 is 1-level-indirection underlying base for UO2. This
situation arises due to the limited lookup depth used during the search
of underlying bases with llvm::getUnderlyingObject(ptr).
Using any fixed lookup depth can result into creation of multiple
equivalence classes that only differ by 1-level indirection bases.
The new approach merges equivalence classes if they have adjacent bases
(1-level indirection). If a series of equivalence classes form ladder
formed of 1-step/level indirections, they are all merged into a single
equivalence class. This provides more opportunities for the load-store
vectorizer to generate better vectors.
---------
Signed-off-by: Klochkov, Vyacheslav N <vyacheslav.n.klochkov at intel.com>
Commit: da71203e6fc6b8e08c9979204506d385e9cb07b8
https://github.com/llvm/llvm-project/commit/da71203e6fc6b8e08c9979204506d385e9cb07b8
Author: Pengcheng Wang <wangpengcheng.pp at bytedance.com>
Date: 2024-12-12 (Thu, 12 Dec 2024)
Changed paths:
M llvm/include/llvm/CodeGen/MachineScheduler.h
M llvm/lib/CodeGen/MachineScheduler.cpp
M llvm/lib/CodeGen/VLIWMachineScheduler.cpp
M llvm/test/CodeGen/AArch64/dump-schedule-trace.mir
M llvm/test/CodeGen/AArch64/force-enable-intervals.mir
M llvm/test/CodeGen/AArch64/misched-detail-resource-booking-01.mir
M llvm/test/CodeGen/AArch64/misched-detail-resource-booking-02.mir
M llvm/test/CodeGen/AArch64/misched-sort-resource-in-trace.mir
M llvm/test/CodeGen/ARM/single-issue-r52.mir
M llvm/test/CodeGen/RISCV/sifive7-enable-intervals.mir
M llvm/test/CodeGen/X86/handle-move.ll
M llvm/test/CodeGen/X86/misched-aa-colored.ll
M llvm/test/CodeGen/X86/misched-matrix.ll
M llvm/test/CodeGen/X86/misched-new.ll
Log Message:
-----------
[MISched] Unify the way to specify scheduling direction (#119518)
For pre-ra scheduling, we use two options `-misched-topdown` and
`-misched-bottomup` to force the direction.
While for post-ra scheduling, we use `-misched-postra-direction`
with enumerated values (`topdown`, `bottomup` and `bidirectional`).
This is not unified and adds some mental burdens. Here we replace
these two options `-misched-topdown` and `-misched-bottomup` with
`-misched-prera-direction` with the same enumerated values.
To avoid the condition of `getNumOccurrences() > 0`, we add a new
enum value `Unspecified` and make it the default initial value.
These options are hidden, so we needn't keep the compatibility.
Commit: 0e80f9a1b51e0e068adeae1278d59cd7baacd5d8
https://github.com/llvm/llvm-project/commit/0e80f9a1b51e0e068adeae1278d59cd7baacd5d8
Author: Shubham Sandeep Rastogi <srastogi22 at apple.com>
Date: 2024-12-11 (Wed, 11 Dec 2024)
Changed paths:
A llvm/include/llvm/CodeGen/DroppedVariableStats.h
M llvm/include/llvm/Passes/StandardInstrumentations.h
M llvm/lib/CodeGen/CMakeLists.txt
A llvm/lib/CodeGen/DroppedVariableStats.cpp
M llvm/lib/Passes/StandardInstrumentations.cpp
M llvm/unittests/IR/CMakeLists.txt
A llvm/unittests/IR/DroppedVariableStatsIRTest.cpp
R llvm/unittests/IR/DroppedVariableStatsTest.cpp
Log Message:
-----------
Reland 2de78815604e9027efd93cac27c517bf732587d2 (#119650)
[NFC] Move DroppedVariableStats to its own file and redesign it to be
extensible. (#115563)
Move DroppedVariableStats code to its own file and change the class to
have an extensible design so that we can use it to add dropped
statistics to MIR passes and the instruction selector.
Removed the default virtual destructor from the base class and added an
empty one instead.
Commit: 990b6f08ad8089790dec52c6a9f8eec164d7caca
https://github.com/llvm/llvm-project/commit/990b6f08ad8089790dec52c6a9f8eec164d7caca
Author: LLVM GN Syncbot <llvmgnsyncbot at gmail.com>
Date: 2024-12-12 (Thu, 12 Dec 2024)
Changed paths:
M llvm/utils/gn/secondary/llvm/lib/CodeGen/BUILD.gn
M llvm/utils/gn/secondary/llvm/unittests/IR/BUILD.gn
Log Message:
-----------
[gn build] Port 0e80f9a1b51e
Commit: 10ed7d94b52c21317a1e02ef1e2c3ff2b2d08301
https://github.com/llvm/llvm-project/commit/10ed7d94b52c21317a1e02ef1e2c3ff2b2d08301
Author: Shubham Sandeep Rastogi <srastogi22 at apple.com>
Date: 2024-12-11 (Wed, 11 Dec 2024)
Changed paths:
M llvm/unittests/CodeGen/CMakeLists.txt
A llvm/unittests/CodeGen/DroppedVariableStatsIRTest.cpp
M llvm/unittests/IR/CMakeLists.txt
R llvm/unittests/IR/DroppedVariableStatsIRTest.cpp
Log Message:
-----------
Move DroppedVariableStatsIRTest.cpp to CodeGen folder
Commit: ed5d897938d4344304a37a7d634b9cc4ed174e8b
https://github.com/llvm/llvm-project/commit/ed5d897938d4344304a37a7d634b9cc4ed174e8b
Author: LLVM GN Syncbot <llvmgnsyncbot at gmail.com>
Date: 2024-12-12 (Thu, 12 Dec 2024)
Changed paths:
M llvm/utils/gn/secondary/llvm/unittests/CodeGen/BUILD.gn
M llvm/utils/gn/secondary/llvm/unittests/IR/BUILD.gn
Log Message:
-----------
[gn build] Port 10ed7d94b52c
Commit: 04313b86a52541b2a618d14f7fa1f23ea7adfa47
https://github.com/llvm/llvm-project/commit/04313b86a52541b2a618d14f7fa1f23ea7adfa47
Author: Michal Paszkowski <michal at paszkowski.org>
Date: 2024-12-11 (Wed, 11 Dec 2024)
Changed paths:
M llvm/lib/Transforms/Vectorize/LoadStoreVectorizer.cpp
R llvm/test/Transforms/LoadStoreVectorizer/X86/massive_indirection.ll
Log Message:
-----------
Revert "[LoadStoreVectorizer] Postprocess and merge equivalence classes" (#119657)
Reverts llvm/llvm-project#114501, due to the following failure:
https://lab.llvm.org/buildbot/#/builders/55/builds/4171
Commit: 64fadf17cf9a2ad26b16a778fc4e2141ae6a8d64
https://github.com/llvm/llvm-project/commit/64fadf17cf9a2ad26b16a778fc4e2141ae6a8d64
Author: Kazu Hirata <kazu at google.com>
Date: 2024-12-11 (Wed, 11 Dec 2024)
Changed paths:
M llvm/unittests/ProfileData/MemProfTest.cpp
Log Message:
-----------
[memprof] Use IndexedMemProfData in unit tests (NFC) (#119648)
This patch uses IndexedMemProfData in unit tests even when we only
need CallStacks. This way, we get to use addCallStack. Also, the
look is more consistent with other unit tests, where we typically do:
IndexMemProfData MemProfData;
MemProfData.addFrame(...);
MemProfData.addCallStack(...);
// Run some tests
Commit: 48ed91871dccf12dbe27e96b457ccee373c68a1e
https://github.com/llvm/llvm-project/commit/48ed91871dccf12dbe27e96b457ccee373c68a1e
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-12-11 (Wed, 11 Dec 2024)
Changed paths:
M llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
Log Message:
-----------
[RISCV] Use OperandType from MCInstrDesc in RISCVInstrInfo::createMIROperandComment. NFCI (#119637)
We can use the OperandType to directly get the type of operand. This
avoids the need to hardcode specific opcodes or match the operand index
against sew operand number or policy operand number.
Commit: 02dd73a5d585af9a950baa38855305fdb17c76af
https://github.com/llvm/llvm-project/commit/02dd73a5d585af9a950baa38855305fdb17c76af
Author: Kazu Hirata <kazu at google.com>
Date: 2024-12-11 (Wed, 11 Dec 2024)
Changed paths:
M clang/include/clang/Lex/PreprocessingRecord.h
M clang/include/clang/Lex/Preprocessor.h
M clang/lib/Analysis/PathDiagnostic.cpp
M clang/lib/Basic/FileManager.cpp
M clang/lib/Index/FileIndexRecord.cpp
M clang/lib/Index/IndexDecl.cpp
M clang/tools/libclang/CIndex.cpp
M clang/tools/libclang/CIndexCXX.cpp
M clang/utils/TableGen/ClangDiagnosticsEmitter.cpp
Log Message:
-----------
[clang] Migrate away from PointerUnion::{is,get} (NFC) (#119654)
Note that PointerUnion::{is,get} have been soft deprecated in
PointerUnion.h:
// FIXME: Replace the uses of is(), get() and dyn_cast() with
// isa<T>, cast<T> and the llvm::dyn_cast<T>
I'm not touching PointerUnion::dyn_cast for now because it's a bit
complicated; we could blindly migrate it to dyn_cast_if_present, but
we should probably use dyn_cast when the operand is known to be
non-null.
Commit: 2698fc699bfd6d62c5f9c2febfdbd2f3505bfdaf
https://github.com/llvm/llvm-project/commit/2698fc699bfd6d62c5f9c2febfdbd2f3505bfdaf
Author: Luke Lau <luke at igalia.com>
Date: 2024-12-12 (Thu, 12 Dec 2024)
Changed paths:
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
Log Message:
-----------
[RISCV] Refactor helper in isDesirableToCommuteWithShift. NFC (#119526)
Instead of duplicating the loop twice, add arguments to the lambda.
I plan on reusing this in #119527
Commit: b26fe5b7e9833b7813459c6a0dc4577b350754f1
https://github.com/llvm/llvm-project/commit/b26fe5b7e9833b7813459c6a0dc4577b350754f1
Author: Luke Lau <luke at igalia.com>
Date: 2024-12-12 (Thu, 12 Dec 2024)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlan.cpp
M llvm/lib/Transforms/Vectorize/VPlanAnalysis.cpp
M llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
Log Message:
-----------
[VPlan] Use variadic isa<> in a few more places. NFC (#119538)
Commit: 088db868f3370ffe01c9750f75732679efecd1fe
https://github.com/llvm/llvm-project/commit/088db868f3370ffe01c9750f75732679efecd1fe
Author: Luke Lau <luke at igalia.com>
Date: 2024-12-12 (Thu, 12 Dec 2024)
Changed paths:
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-shuffles.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-shuffles.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-interleaved-access.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-deinterleave.ll
Log Message:
-----------
[RISCV] Merge shuffle sources if lanes are disjoint (#119401)
In x264, there's a few kernels with shuffles like this:
%41 = add nsw <16 x i32> %39, %40
%42 = sub nsw <16 x i32> %39, %40
%43 = shufflevector <16 x i32> %41, <16 x i32> %42, <16 x i32> <i32 11,
i32 15, i32 7, i32 3, i32 26, i32 30, i32 22, i32 18, i32 9, i32 13, i32
5, i32 1, i32 24, i32 28, i32 20, i32 16>
Because this is a complex two-source shuffle, this will get lowered as
two vrgather.vvs that are blended together.
vadd.vv v20, v16, v12
vsub.vv v12, v16, v12
vrgatherei16.vv v24, v20, v10
vrgatherei16.vv v24, v12, v16, v0.t
However the indices coming from each source are disjoint, so we can
blend the two together and perform a single source shuffle instead:
%41 = add nsw <16 x i32> %39, %40
%42 = sub nsw <16 x i32> %39, %40
%43 = select <0,0,0,0,1,1,1,1,0,0,0,0,1,1,1,1> %41, %42
%44 = shufflevector <16 x i32> %43, <16 x i32> poison, <16 x i32> <i32
11, i32 15, i32 7, i32 3, i32 10, i32 14, i32 6, i32 2, i32 9, i32 13,
i32 5, i32 1, i32 8, i32 12, i32 4, i32 0>
The select will likely get merged into the preceding instruction, and
then we only have to do one vrgather.vv:
vadd.vv v20, v16, v12
vsub.vv v20, v16, v12, v0.t
vrgatherei16.vv v24, v20, v10
This patch bails if either of the sources are a broadcast/splat/identity
shuffle, since that will usually already have some sort of cheaper
lowering.
This improves performance on 525.x264_r by 4.12% with -O3 -flto
-march=rva22u64_v on the spacemit-x60.
Commit: 0614c601b44ca2f214a9868a8b672ea695d5d56a
https://github.com/llvm/llvm-project/commit/0614c601b44ca2f214a9868a8b672ea695d5d56a
Author: quic_hchandel <165007698+hchandel at users.noreply.github.com>
Date: 2024-12-12 (Thu, 12 Dec 2024)
Changed paths:
M clang/test/Driver/print-supported-extensions-riscv.c
M llvm/docs/RISCVUsage.rst
M llvm/docs/ReleaseNotes.md
M llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
M llvm/lib/Target/RISCV/RISCVFeatures.td
M llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
M llvm/lib/TargetParser/RISCVISAInfo.cpp
M llvm/test/CodeGen/RISCV/attributes.ll
A llvm/test/MC/RISCV/xqcics-invalid.s
A llvm/test/MC/RISCV/xqcics-valid.s
M llvm/unittests/TargetParser/RISCVISAInfoTest.cpp
Log Message:
-----------
[RISCV] Add Qualcomm uC Xqcics(Conditional Select) extension (#119504)
The Qualcomm uC Xqcics extension adds 8 conditional select instructions.
The current spec can be found at:
https://github.com/quic/riscv-unified-db/releases/latest
This patch adds assembler only support.
---------
Co-authored-by: Harsh Chandel <hchandel at qti.qualcomm.com>
Commit: 22d26ae3040095c7bfe4e2f1678b9738bf81fd4a
https://github.com/llvm/llvm-project/commit/22d26ae3040095c7bfe4e2f1678b9738bf81fd4a
Author: Piotr Fusik <p.fusik at samsung.com>
Date: 2024-12-12 (Thu, 12 Dec 2024)
Changed paths:
M llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
A llvm/test/CodeGen/RISCV/and-shl.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp2i.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-buildvec.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-gather.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-scatter.ll
Log Message:
-----------
[RISCV] Optimize (slli (srli (slli X, C1), C1), C2) -> (srli (slli X, C1), C1-C2) (#119567)
Masking out most significant bits can be done with shl followed by srl
with same shift amount. If this is followed by a shl, we could instead
srl by a smaller amount of bits.
This transform is already implemented in tablegen for masking out
32 most significant bits.
Emits better code for e.g.
float *index(float *p, int i)
{
return p + (i & (1 << 30) - 1);
}
Commit: 077cc3deeebedbd088c6183a191b4dd67861b350
https://github.com/llvm/llvm-project/commit/077cc3deeebedbd088c6183a191b4dd67861b350
Author: Shubham Sandeep Rastogi <srastogi22 at apple.com>
Date: 2024-12-11 (Wed, 11 Dec 2024)
Changed paths:
R llvm/include/llvm/CodeGen/DroppedVariableStats.h
M llvm/include/llvm/Passes/StandardInstrumentations.h
M llvm/lib/CodeGen/CMakeLists.txt
R llvm/lib/CodeGen/DroppedVariableStats.cpp
M llvm/lib/Passes/StandardInstrumentations.cpp
M llvm/unittests/CodeGen/CMakeLists.txt
R llvm/unittests/CodeGen/DroppedVariableStatsIRTest.cpp
M llvm/unittests/IR/CMakeLists.txt
A llvm/unittests/IR/DroppedVariableStatsTest.cpp
Log Message:
-----------
Revert "Move DroppedVariableStatsIRTest.cpp to CodeGen folder"
This reverts commit 10ed7d94b52c21317a1e02ef1e2c3ff2b2d08301.
Revert "Reland 2de78815604e9027efd93cac27c517bf732587d2 (#119650)"
This reverts commit 0e80f9a1b51e0e068adeae1278d59cd7baacd5d8.
This is because the clang-ppc64le-linux-multistage bot breaks with error
undefined reference to `vtable for llvm::DroppedVariableStatsIR'
Commit: 925471ed903dad871042d7ed0bab89ab6566a564
https://github.com/llvm/llvm-project/commit/925471ed903dad871042d7ed0bab89ab6566a564
Author: Dmitry Vasilyev <dvassiliev at accesssoftek.com>
Date: 2024-12-12 (Thu, 12 Dec 2024)
Changed paths:
M llvm/lib/Support/Windows/Path.inc
Log Message:
-----------
[llvm][Support][Windows] Avoid crash calling remove_directories() (#118677)
We faced an unexpected crash in SHELL32_CallFileCopyHooks() on the buildbot
[lldb-remote-linux-win](https://lab.llvm.org/staging/#/builders/197/builds/1066).
The host is Windows Server 2022 w/o any 3rd party shell extensions. See #118032 for more details.
Based on [this article](https://devblogs.microsoft.com/oldnewthing/20120330-00/?p=7963).
Commit: bff6fee6303909651cd3018b6403f9a709421fa6
https://github.com/llvm/llvm-project/commit/bff6fee6303909651cd3018b6403f9a709421fa6
Author: LLVM GN Syncbot <llvmgnsyncbot at gmail.com>
Date: 2024-12-12 (Thu, 12 Dec 2024)
Changed paths:
M llvm/utils/gn/secondary/llvm/lib/CodeGen/BUILD.gn
M llvm/utils/gn/secondary/llvm/unittests/CodeGen/BUILD.gn
M llvm/utils/gn/secondary/llvm/unittests/IR/BUILD.gn
Log Message:
-----------
[gn build] Port 077cc3deeebe
Commit: ef28e963e3cf5bca8cb37b053f5840f8541987b3
https://github.com/llvm/llvm-project/commit/ef28e963e3cf5bca8cb37b053f5840f8541987b3
Author: Chandler Carruth <chandlerc at gmail.com>
Date: 2024-12-11 (Wed, 11 Dec 2024)
Changed paths:
A llvm/include/llvm/ADT/StringTable.h
M llvm/unittests/ADT/CMakeLists.txt
A llvm/unittests/ADT/StringTableTest.cpp
Log Message:
-----------
Add a super simple wrapper for a merged string table. (#119488)
Suggestions welcome on what to better name this -- `StringTable` as I
currently have it seems too general, but wasn't sure what other name
would be better.
It currently has a *very* minimal API. I'm happy to expand it if folks
have ideas for what API would be useful, but this actually seemed like
it might be all we really need.
Commit: 9992b1624303262407ff82413563f39ba40544a0
https://github.com/llvm/llvm-project/commit/9992b1624303262407ff82413563f39ba40544a0
Author: LLVM GN Syncbot <llvmgnsyncbot at gmail.com>
Date: 2024-12-12 (Thu, 12 Dec 2024)
Changed paths:
M llvm/utils/gn/secondary/llvm/unittests/ADT/BUILD.gn
Log Message:
-----------
[gn build] Port ef28e963e3cf
Commit: 9c50182bf4942f88cc9876eb29e70802448cddc8
https://github.com/llvm/llvm-project/commit/9c50182bf4942f88cc9876eb29e70802448cddc8
Author: Malavika Samak <malavika.samak at gmail.com>
Date: 2024-12-12 (Thu, 12 Dec 2024)
Changed paths:
M clang/lib/Analysis/UnsafeBufferUsage.cpp
M clang/test/SemaCXX/warn-unsafe-buffer-usage-array.cpp
M clang/test/SemaCXX/warn-unsafe-buffer-usage-field-attr.cpp
M clang/test/SemaCXX/warn-unsafe-buffer-usage-fixits-parm-unsupported.cpp
M clang/test/SemaCXX/warn-unsafe-buffer-usage.cpp
Log Message:
-----------
[-Wunsafe-buffer-usage] Suppress warning for multi-dimensional constant arrays (#118249)
Do not warn about unsafe buffer access, when multi-dimensional constant
arrays are accessed and their indices are within the bounds of the
buffer. Warning in such cases would be a false positive. Such a
suppression already exists for 1-d
arrays and it is now extended to multi-dimensional arrays.
(rdar://137926311)
(rdar://140320139)
Co-authored-by: MalavikaSamak <malavika2 at apple.com>
Commit: 8713914d76cb9d6b54278dd75fecb68bb93f6ea5
https://github.com/llvm/llvm-project/commit/8713914d76cb9d6b54278dd75fecb68bb93f6ea5
Author: Timm Baeder <tbaeder at redhat.com>
Date: 2024-12-12 (Thu, 12 Dec 2024)
Changed paths:
M clang/lib/AST/ByteCode/BitcastBuffer.h
M clang/lib/AST/ByteCode/InterpBuiltin.cpp
M clang/lib/AST/ByteCode/InterpBuiltinBitCast.cpp
M clang/lib/AST/ByteCode/InterpBuiltinBitCast.h
M clang/test/AST/ByteCode/builtin-functions.cpp
Log Message:
-----------
[clang][bytecode] Handle __builtin_memcmp (#119544)
Commit: cfad8f14f846860b5c2e413c41c9b2b56466662e
https://github.com/llvm/llvm-project/commit/cfad8f14f846860b5c2e413c41c9b2b56466662e
Author: Timm Bäder <tbaeder at redhat.com>
Date: 2024-12-12 (Thu, 12 Dec 2024)
Changed paths:
M clang/lib/AST/ByteCode/InterpBuiltin.cpp
Log Message:
-----------
[clang][bytecode] Fix a build failure on aarch64
This broke e.g.
https://lab.llvm.org/buildbot/#/builders/190/builds/11216
Commit: 737d78a9785ea3e928de2b36a4e3e7decd8c9491
https://github.com/llvm/llvm-project/commit/737d78a9785ea3e928de2b36a4e3e7decd8c9491
Author: Carlo Cabrera <github at carlo.cab>
Date: 2024-12-12 (Thu, 12 Dec 2024)
Changed paths:
M clang/lib/Driver/ToolChains/Darwin.cpp
M clang/test/Driver/sysroot.c
Log Message:
-----------
[Darwin][Driver][clang] Prioritise command line args over `DEFAULT_SYSROOT` (#115993)
If a toolchain is configured with `DEFAULT_SYSROOT`, then this could
result in an unintended value for `-syslibroot` being passed to the
linker if the user manually sets `-isysroot` or `SDKROOT`.
Let's fix this by prioritising command line flags when determining
`-syslibroot` before checking `getSysRoot`.
Downstream bug report:
https://github.com/Homebrew/homebrew-core/issues/197277
Co-authored-by: Bo Anderson <mail at boanderson.me>
Co-authored-by: Bo Anderson <mail at boanderson.me>
Commit: 0876c11ceeb093904decc4d89bef213d483a5656
https://github.com/llvm/llvm-project/commit/0876c11ceeb093904decc4d89bef213d483a5656
Author: Akshat Oke <Akshat.Oke at amd.com>
Date: 2024-12-12 (Thu, 12 Dec 2024)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
M llvm/test/tools/llc/new-pm/regalloc-amdgpu.mir
Log Message:
-----------
[AMDGPU] Parse wwm filter flag for regalloc fast (#119347)
Commit: b3cba9be41bfa89bc0ec212706c6028a901e127a
https://github.com/llvm/llvm-project/commit/b3cba9be41bfa89bc0ec212706c6028a901e127a
Author: Mel Chen <mel.chen at sifive.com>
Date: 2024-12-12 (Thu, 12 Dec 2024)
Changed paths:
M llvm/include/llvm/Analysis/IVDescriptors.h
M llvm/include/llvm/Transforms/Utils/LoopUtils.h
M llvm/lib/Analysis/IVDescriptors.cpp
M llvm/lib/Transforms/Utils/LoopUtils.cpp
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
M llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
A llvm/test/Transforms/LoopVectorize/iv-select-cmp-blend.ll
M llvm/test/Transforms/LoopVectorize/iv-select-cmp-no-wrap.ll
M llvm/test/Transforms/LoopVectorize/iv-select-cmp-trunc.ll
M llvm/test/Transforms/LoopVectorize/iv-select-cmp.ll
M llvm/test/Transforms/LoopVectorize/select-min-index.ll
Log Message:
-----------
[LoopVectorize] Vectorize select-cmp reduction pattern for increasing integer induction variable (#67812)
Consider the following loop:
```
int rdx = init;
for (int i = 0; i < n; ++i)
rdx = (a[i] > b[i]) ? i : rdx;
```
We can vectorize this loop if `i` is an increasing induction variable.
The final reduced value will be the maximum of `i` that the condition
`a[i] > b[i]` is satisfied, or the start value `init`.
This patch added new RecurKind enums - IFindLastIV and FFindLastIV.
---------
Co-authored-by: Alexey Bataev <5361294+alexey-bataev at users.noreply.github.com>
Commit: 2a825cd2f93b5f83029c36d6c8229f65b6ef2ec7
https://github.com/llvm/llvm-project/commit/2a825cd2f93b5f83029c36d6c8229f65b6ef2ec7
Author: Kazu Hirata <kazu at google.com>
Date: 2024-12-12 (Thu, 12 Dec 2024)
Changed paths:
M clang/include/clang/AST/APValue.h
M clang/include/clang/AST/Decl.h
M clang/include/clang/AST/DeclContextInternals.h
M clang/include/clang/AST/DeclTemplate.h
M clang/include/clang/AST/ExprConcepts.h
M clang/include/clang/AST/ExternalASTSource.h
M clang/include/clang/AST/Redeclarable.h
M clang/include/clang/AST/Type.h
Log Message:
-----------
[AST] Migrate away from PointerUnion::{is,get} (NFC) (#119673)
Note that PointerUnion::{is,get} have been soft deprecated in
PointerUnion.h:
// FIXME: Replace the uses of is(), get() and dyn_cast() with
// isa<T>, cast<T> and the llvm::dyn_cast<T>
I'm not touching PointerUnion::dyn_cast for now because it's a bit
complicated; we could blindly migrate it to dyn_cast_if_present, but
we should probably use dyn_cast when the operand is known to be
non-null.
Commit: e84566ff2b8e9bb67ccc6764d7003871535e550e
https://github.com/llvm/llvm-project/commit/e84566ff2b8e9bb67ccc6764d7003871535e550e
Author: Carlo Cabrera <github at carlo.cab>
Date: 2024-12-12 (Thu, 12 Dec 2024)
Changed paths:
M libc/CMakeLists.txt
Log Message:
-----------
[libc] Fail fast when building standalone (#119426)
Building with the source directory rooted in the libc subdirectory isn't
tested in CI and can lead to subtle build problems (cf. #118871).
Let's fail fast with a helpful error message instead to help users
configure libc correctly.
Co-authored-by: Nick Desaulniers <nickdesaulniers at users.noreply.github.com>
Commit: 08c9bb21482db443a8d5f84e9821abfbce4e9452
https://github.com/llvm/llvm-project/commit/08c9bb21482db443a8d5f84e9821abfbce4e9452
Author: Sudharsan Veeravalli <quic_svs at quicinc.com>
Date: 2024-12-12 (Thu, 12 Dec 2024)
Changed paths:
M llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
Log Message:
-----------
[RISCV] Change func to funct in RISCVInstrInfoXqci.td. NFC (#119669)
Commit: 32403f79f4fcdb74b1576eed19cde7b104191808
https://github.com/llvm/llvm-project/commit/32403f79f4fcdb74b1576eed19cde7b104191808
Author: Tom Eccles <tom.eccles at arm.com>
Date: 2024-12-12 (Thu, 12 Dec 2024)
Changed paths:
M flang/unittests/Runtime/AccessTest.cpp
Log Message:
-----------
[flang][unittests] fix test broken when run as root (#119604)
It is convenient to run tests as root inside of a docker container.
The test (and the library function it is testing) are already
unsupported on Windows so it is safe to use UNIX-isms here.
Commit: ff13f61ec9bc8ae170ef8ab4eb66b00408f302f6
https://github.com/llvm/llvm-project/commit/ff13f61ec9bc8ae170ef8ab4eb66b00408f302f6
Author: Nikita Popov <npopov at redhat.com>
Date: 2024-12-12 (Thu, 12 Dec 2024)
Changed paths:
M llvm/Maintainers.md
Log Message:
-----------
[LLVM] Update TableGen maintainer (#119569)
Update the maintainer for TableGen to jurahul, who has been driving
most of the recent development in this area.
Commit: e3352904309a539eddcf3ddd9fb11ca2aef29d65
https://github.com/llvm/llvm-project/commit/e3352904309a539eddcf3ddd9fb11ca2aef29d65
Author: Nikita Popov <npopov at redhat.com>
Date: 2024-12-12 (Thu, 12 Dec 2024)
Changed paths:
M llvm/Maintainers.md
Log Message:
-----------
[LLVM] Update MC maintainer (#119571)
We currently list Jim Grosbach as the maintainer for the MC layer --
however, he hasn't been involved in LLVM for about ten years.
I'd like to propose MaskRay as the replacement. I think he has done
most of the substantial MC work in recent times.
Commit: 5013c81b781eb95af8e429956d63c8f9c16a4647
https://github.com/llvm/llvm-project/commit/5013c81b781eb95af8e429956d63c8f9c16a4647
Author: Nikita Popov <npopov at redhat.com>
Date: 2024-12-12 (Thu, 12 Dec 2024)
Changed paths:
M llvm/include/llvm/Transforms/Utils/Evaluator.h
M llvm/lib/Transforms/Utils/Evaluator.cpp
M llvm/test/Transforms/GlobalOpt/evaluate-call-errors.ll
M llvm/test/Transforms/GlobalOpt/evaluate-constfold-call.ll
A llvm/test/Transforms/GlobalOpt/evaluate-ret-void-mismatch.ll
Log Message:
-----------
[GlobalOpt][Evaluator] Don't evaluate calls with signature mismatch (#119548)
The global ctor evaluator tries to evalute function calls where the call
function type and function type do not match, by performing bitcasts.
This currently causes a crash when calling a void function with non-void
return type.
I've opted to remove this functionality entirely rather than fixing this
specific case. With opaque pointers, there shouldn't be a legitimate use
case for this anymore, as we don't need to look through pointer type
casts. Doing other bitcasts is very iffy because it ignores ABI
considerations. We should at least leave adjusting the signatures to
make them line up to InstCombine (which also does some iffy things, but
is at least somewhat more constrained).
Fixes https://github.com/llvm/llvm-project/issues/118725.
Commit: 98470c0b2e0eef52e6900bf2d524a390edac9d58
https://github.com/llvm/llvm-project/commit/98470c0b2e0eef52e6900bf2d524a390edac9d58
Author: Timm Baeder <tbaeder at redhat.com>
Date: 2024-12-12 (Thu, 12 Dec 2024)
Changed paths:
M clang/lib/AST/ByteCode/InterpBuiltin.cpp
M clang/test/AST/ByteCode/builtin-functions.cpp
Log Message:
-----------
[clang][bytecode] Handle __builtin_bcmp (#119678)
... the same as `__builtin_memcmp`. Also fix a bug we still had when we
couldn't find a difference in the two inputs after `Size` bytes.
Commit: 5ca26d769deedc931ce19b4a68a68c799f8d7564
https://github.com/llvm/llvm-project/commit/5ca26d769deedc931ce19b4a68a68c799f8d7564
Author: Kerry McLaughlin <kerry.mclaughlin at arm.com>
Date: 2024-12-12 (Thu, 12 Dec 2024)
Changed paths:
M llvm/lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
M llvm/lib/Target/AArch64/AArch64RegisterInfo.cpp
M llvm/lib/Target/AArch64/AArch64RegisterInfo.h
M llvm/lib/Target/AArch64/SMEInstrFormats.td
M llvm/test/CodeGen/AArch64/sme2-intrinsics-int-dots.ll
M llvm/test/CodeGen/AArch64/sme2-intrinsics-vdot.ll
Log Message:
-----------
[AArch64][SME2] Improve register allocation of multi-vector SME intrinsics (#116399)
The FORM_TRANSPOSED_REG_TUPLE pseudos have been created to
improve register allocation for intrinsics which use strided and
contiguous multi-vector registers, avoiding unnecessary copies.
If the operands of the pseudo are copies where the source register is in
the StridedOrContiguous class, the pseudo is used by
getRegAllocationHints
to suggest a contigious multi-vector register which matches the
subregister
sequence used by the operands.
If the operands do not match this pattern, the pseudos are expanded
to a REG_SEQUENCE.
Patch contains changes by Matthew Devereau.
Commit: ceb7214be0287f536b292a41f8a7dc2e1467d72d
https://github.com/llvm/llvm-project/commit/ceb7214be0287f536b292a41f8a7dc2e1467d72d
Author: Kristof Beyls <kristof.beyls at arm.com>
Date: 2024-12-12 (Thu, 12 Dec 2024)
Changed paths:
A bolt/docs/BinaryAnalysis.md
M bolt/include/bolt/Rewrite/RewriteInstance.h
M bolt/include/bolt/Utils/CommandLineOpts.h
M bolt/lib/Rewrite/RewriteInstance.cpp
M bolt/lib/Utils/CommandLineOpts.cpp
M bolt/test/CMakeLists.txt
A bolt/test/binary-analysis/AArch64/Inputs/dummy.txt
A bolt/test/binary-analysis/AArch64/cmdline-args.test
A bolt/test/binary-analysis/AArch64/lit.local.cfg
M bolt/test/lit.cfg.py
M bolt/tools/CMakeLists.txt
A bolt/tools/binary-analysis/CMakeLists.txt
A bolt/tools/binary-analysis/binary-analysis.cpp
Log Message:
-----------
[BOLT] Introduce binary analysis tool based on BOLT (#115330)
This initial commit does not add any specific binary analyses yet, it
merely contains the boilerplate to introduce a new BOLT-based tool.
This basically combines the 4 first patches from the prototype pac-ret
and stack-clash binary analyzer discussed in RFC
https://discourse.llvm.org/t/rfc-bolt-based-binary-analysis-tool-to-verify-correctness-of-security-hardening/78148
and published at
https://github.com/llvm/llvm-project/compare/main...kbeyls:llvm-project:bolt-gadget-scanner-prototype
The introduction of such a BOLT-based binary analysis tool was proposed
and discussed in at least the following places:
- The RFC pointed to above
- EuroLLVM 2024 round table
https://discourse.llvm.org/t/summary-of-bolt-as-a-binary-analysis-tool-round-table-at-eurollvm/78441
The round table showed quite a few people interested in being able to
build a custom binary analysis quickly with a tool like this.
- Also at the US LLVM dev meeting a few weeks ago, I heard interest from
a few people, asking when the tool would be available upstream.
- The presentation "Adding Pointer Authentication ABI support for your
ELF platform"
(https://llvm.swoogo.com/2024devmtg/session/2512720/adding-pointer-authentication-abi-support-for-your-elf-platform)
explicitly mentioned interest to extend the prototype tool to verify
correct implementation of pauthabi.
Commit: 2fae58e9c7becc376454005da69acb3fa993350e
https://github.com/llvm/llvm-project/commit/2fae58e9c7becc376454005da69acb3fa993350e
Author: David Spickett <david.spickett at linaro.org>
Date: 2024-12-12 (Thu, 12 Dec 2024)
Changed paths:
M lldb/unittests/Host/PipeTest.cpp
Log Message:
-----------
[lldb][test] Disable WriteWithTimeout test on Windows
This is still flaky on our Windows on Arm bot:
******************** TEST 'lldb-unit :: Host/./HostTests.exe/8/10' FAILED ********************
Script(shard):
--
GTEST_OUTPUT=json:C:\Users\tcwg\llvm-worker\lldb-aarch64-windows\build\tools\lldb\unittests\Host\.\HostTests.exe-lldb-unit-3616-8-10.json GTEST_SHUFFLE=0 GTEST_TOTAL_SHARDS=10 GTEST_SHARD_INDEX=8 C:\Users\tcwg\llvm-worker\lldb-aarch64-windows\build\tools\lldb\unittests\Host\.\HostTests.exe
--
Script:
--
C:\Users\tcwg\llvm-worker\lldb-aarch64-windows\build\tools\lldb\unittests\Host\.\HostTests.exe --gtest_filter=PipeTest.WriteWithTimeout
--
C:\Users\tcwg\llvm-worker\lldb-aarch64-windows\llvm-project\lldb\unittests\Host\PipeTest.cpp(110): error: Expected: (dur) >= (std::chrono::seconds(2)), actual: 8-byte object <1C-A6 34-77 00-00 00-00> vs 8-byte object <02-00 00-00 00-00 00-00>
C:\Users\tcwg\llvm-worker\lldb-aarch64-windows\llvm-project\lldb\unittests\Host\PipeTest.cpp:110
Expected: (dur) >= (std::chrono::seconds(2)), actual: 8-byte object <1C-A6 34-77 00-00 00-00> vs 8-byte object <02-00 00-00 00-00 00-00>
Commit: 7f4312015291a32d811a0f37e24b4d9736c524f7
https://github.com/llvm/llvm-project/commit/7f4312015291a32d811a0f37e24b4d9736c524f7
Author: Ilya Biryukov <ibiryukov at google.com>
Date: 2024-12-12 (Thu, 12 Dec 2024)
Changed paths:
M clang/unittests/Serialization/LoadSpecLazilyTest.cpp
Log Message:
-----------
[Serialization] Free memory in LoadSpecLazilyTest
Default Clang invocations set DisableFree = true, which causes ASAN to
complain. Override it in tests that are not supposed to leak.
Commit: 5e247d726d7a54cf0acc997bc17b50e7494e6fa3
https://github.com/llvm/llvm-project/commit/5e247d726d7a54cf0acc997bc17b50e7494e6fa3
Author: David Green <david.green at arm.com>
Date: 2024-12-12 (Thu, 12 Dec 2024)
Changed paths:
M llvm/include/llvm/Analysis/PtrUseVisitor.h
M llvm/include/llvm/Transforms/Utils/SSAUpdater.h
M llvm/lib/Transforms/Scalar/SROA.cpp
M llvm/lib/Transforms/Utils/SSAUpdater.cpp
M llvm/test/Transforms/SROA/non-capturing-call-readonly.ll
M llvm/test/Transforms/SROA/readonlynocapture.ll
Log Message:
-----------
[SROA] Optimize reloaded values in allocas that escape into readonly nocapture calls. (#116645)
Given an alloca that potentially has many uses in big complex code and
escapes into a call that is readonly+nocapture, we cannot easily split
up the alloca. There are several optimizations that will attempt to take
a value that is stored and a reload, and replace the load with the
original stored value. Instcombine has some simple heuristics, GVN can
sometimes do it, as can CSE in limited situations. They all suffer from
the same issue with complex code - they start from a load/store and need
to prove no-alias for all code between, which in complex cases might be
a lot to look through. Especially if the ptr is an alloca with many uses
that is over the normal escape capture limits.
The pass that does do well with allocas is SROA, as it has a complete
view of all of the uses. This patch adds a case to SROA where it can
detect allocas that are passed into calls that are no-capture readonly.
It can then optimize the reloaded values inside the alloca slice with
the stored value knowing that it is valid no matter the location of the
loads/stores from the no-escaping nature of the alloca.
Commit: a611d67601528cb18ae26794a1482cff59ca5254
https://github.com/llvm/llvm-project/commit/a611d67601528cb18ae26794a1482cff59ca5254
Author: LiqinWeng <liqin.weng at spacemit.com>
Date: 2024-12-12 (Thu, 12 Dec 2024)
Changed paths:
M llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
M llvm/test/CodeGen/RISCV/rvv/sink-splat-operands.ll
Log Message:
-----------
[RISCV][TTI] Add llvm.fmuladd and llvm.vp.fmuladd into canSplatOperand (#119508)
The first or second operand of fmuladd is a splat operand , it can help
fmuladd fold vv instructions to vf instructions.
Commit: 5b077506de26b1dfce1926895548b86f2106bed9
https://github.com/llvm/llvm-project/commit/5b077506de26b1dfce1926895548b86f2106bed9
Author: Jie Fu <jiefu at tencent.com>
Date: 2024-12-12 (Thu, 12 Dec 2024)
Changed paths:
M llvm/lib/Transforms/Scalar/SROA.cpp
Log Message:
-----------
[Transforms] Silence a warning in SROA.cpp (NFC)
/llvm-project/llvm/lib/Transforms/Scalar/SROA.cpp:5526:48:
error: '&&' within '||' [-Werror,-Wlogical-op-parentheses]
if (!SI->isSimple() || PartitionType && UserTy != PartitionType)
~~ ~~~~~~~~~~~~~~^~~~~~~~~~~~~~~~~~~~~~~~~~
/llvm-project/llvm/lib/Transforms/Scalar/SROA.cpp:5526:48:
note: place parentheses around the '&&' expression to silence this warning
if (!SI->isSimple() || PartitionType && UserTy != PartitionType)
^
( )
1 error generated.
Commit: b604d23febe9ac25d274fd933044aa7846d4397e
https://github.com/llvm/llvm-project/commit/b604d23febe9ac25d274fd933044aa7846d4397e
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-12-12 (Thu, 12 Dec 2024)
Changed paths:
M llvm/lib/Transforms/Vectorize/VectorCombine.cpp
Log Message:
-----------
[VectorCombine] Pull out isa<VectorType> check.
Noticed while investigating a crash in #119559 - we don't account for I being replaced and its Type being reallocated. So hoist the checks to the start of the loop.
Commit: 625ec7ec8983e040c440928bc1b35143a6362eab
https://github.com/llvm/llvm-project/commit/625ec7ec8983e040c440928bc1b35143a6362eab
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-12-12 (Thu, 12 Dec 2024)
Changed paths:
R llvm/test/Transforms/PhaseOrdering/X86/concat-boolmasks.ll
A llvm/test/Transforms/VectorCombine/X86/concat-boolmasks.ll
Log Message:
-----------
[VectorCombine] Move concat-boolmasks.ll tests to be VectorCombine only
Suggested on #119559
Commit: a480d5172215ce8e49b492e5c0295de1f397954d
https://github.com/llvm/llvm-project/commit/a480d5172215ce8e49b492e5c0295de1f397954d
Author: Florian Hahn <flo at fhahn.com>
Date: 2024-12-12 (Thu, 12 Dec 2024)
Changed paths:
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
Log Message:
-----------
[VPlan] Use existing vector trip count VPValue for resume phi (NFC)
Instead of going through getOrAddLiveIn to get a VPValue for the vector
trip count retrieve it directly from VPlan via getVectorTripCount.
Small simplification following 0e70289f373.
Commit: 1d65c35ce16f1bc340649ac8319b34c833e23a1f
https://github.com/llvm/llvm-project/commit/1d65c35ce16f1bc340649ac8319b34c833e23a1f
Author: Mariya Podchishchaeva <mariya.podchishchaeva at intel.com>
Date: 2024-12-12 (Thu, 12 Dec 2024)
Changed paths:
M clang/docs/ReleaseNotes.rst
M clang/lib/Sema/DeclSpec.cpp
M clang/test/AST/ByteCode/complex.cpp
M clang/test/CodeGenCXX/ext-int.cpp
M clang/test/SemaCXX/ext-int.cpp
Log Message:
-----------
[clang] Reject `_Complex _BitInt` (#119402)
The C standard doesn't require support for these types and Codegen for
these types is incorrect ATM.
See https://github.com/llvm/llvm-project/issues/119352
Commit: 9472c5fcc78a1f7ff48d797f91b55246f7c80b1a
https://github.com/llvm/llvm-project/commit/9472c5fcc78a1f7ff48d797f91b55246f7c80b1a
Author: Luke Hutton <luke.hutton at arm.com>
Date: 2024-12-12 (Thu, 12 Dec 2024)
Changed paths:
M mlir/lib/Dialect/Tosa/Transforms/TosaValidation.cpp
M mlir/test/Dialect/Tosa/level_check.mlir
Log Message:
-----------
[TOSA] Make validation pass isValidElementType check more strict (#119671)
The validation pass is used to check alignment of the IR against the
TOSA specification. This commit updates the `isValidElement` check to
more strictly align with the specifications supported element types.
Signed-off-by: Luke Hutton <luke.hutton at arm.com>
Commit: 2be41e7aee1c72177019a219ccd8e0cfccdbb52b
https://github.com/llvm/llvm-project/commit/2be41e7aee1c72177019a219ccd8e0cfccdbb52b
Author: Nikita Popov <npopov at redhat.com>
Date: 2024-12-12 (Thu, 12 Dec 2024)
Changed paths:
M llvm/lib/Transforms/IPO/AlwaysInliner.cpp
A llvm/test/Transforms/Inline/always-inline-bfi.ll
Log Message:
-----------
[AlwaysInline] Fix analysis invalidation (#119566)
This is a followup to #117750. Currently, AlwaysInline only invalidates
analyses at the end, by returning that no analyses are preserved.
However, this means that analyses fetched during inlining may be
outdated. The aforementioned PR exposed this issue.
Instead, bring the logic closer to what the normal inliner does, by
directly invalidating the caller in FAM. This should make sure that we
don't receive any outdated analyses even if they are fetched during
inlining.
Also drop the BFI updating entirely -- there's no point in doing it if
we're going to invalidate everything anyway.
Commit: 0cbdad4bd2396b740742d9ae94cba7d7b8a32cb5
https://github.com/llvm/llvm-project/commit/0cbdad4bd2396b740742d9ae94cba7d7b8a32cb5
Author: Bo Anderson <mail at boanderson.me>
Date: 2024-12-12 (Thu, 12 Dec 2024)
Changed paths:
M clang/lib/Driver/Driver.cpp
M clang/test/Driver/config-file3.c
Log Message:
-----------
[clang][Driver] Support simplified triple versions for config files (#111387)
Currently, the config file system loads the full target triple, e.g.
`arm64-apple-darwin23.6.0.cfg`.
This is however not very useful as this is a moving target. In the case
of macOS, that target moves every ~2 months.
We can improve this by adding fallbacks that simplify the version
component of the triple. This pull request adds support for loading
`arm64-apple-darwin23.cfg` and `arm64-apple-darwin.cfg`. See the
included test for a demonstration on how it works.
Commit: 81825687b4b45e0a6839fd05cad7bedf18205315
https://github.com/llvm/llvm-project/commit/81825687b4b45e0a6839fd05cad7bedf18205315
Author: Jefferson Le Quellec <jefferson.lequellec at codeplay.com>
Date: 2024-12-12 (Thu, 12 Dec 2024)
Changed paths:
M mlir/include/mlir/Conversion/Passes.td
M mlir/lib/Conversion/GPUToLLVMSPV/GPUToLLVMSPV.cpp
M mlir/test/Conversion/GPUToLLVMSPV/gpu-to-llvm-spv.mlir
Log Message:
-----------
[MLIR][GPUToLLVMSPV] Update ConvertGpuOpsToLLVMSPVOps's option (#118818)
## Description
This PR updates the `ConvertGpuOpsToLLVMSPVOps`'s option by replacing
the `index-bitwidth` with a boolean option `use-64bit-index` (similar to
the `ConvertGPUToSPIRV` option).
The reason for this modification is because the
`ConvertGpuOpsToLLVMSPVOps`:
> Generate LLVM operations to be ingested by a SPIR-V backend for gpu
operations
In the context of SPIR-V specifications only two physical addressing
models are allowed: `Physical32` and `Physical64`.
This change guarantees output sanity by preventing invalid or
unsupported index bitwidths from being specified.
Commit: f85579fb510faa0a57500b8fd3642f0269c4a4a1
https://github.com/llvm/llvm-project/commit/f85579fb510faa0a57500b8fd3642f0269c4a4a1
Author: bernhardu <bernhardu at mailbox.org>
Date: 2024-12-12 (Thu, 12 Dec 2024)
Changed paths:
M compiler-rt/lib/interception/interception_win.cpp
M compiler-rt/lib/interception/tests/interception_win_test.cpp
Log Message:
-----------
[win/asan] GetInstructionSize: Fix `83 E4 XX` to return 3. (#119644)
This consolidates the two different lines for x86 and x86_64 into a
single line for both architectures.
And adds a test line.
CC: @zmodem
Commit: 6a9279ca407132eec848eb5c55c2222ce605df81
https://github.com/llvm/llvm-project/commit/6a9279ca407132eec848eb5c55c2222ce605df81
Author: Louis Dionne <ldionne.2 at gmail.com>
Date: 2024-12-12 (Thu, 12 Dec 2024)
Changed paths:
R libcxx/test/benchmarks/ContainerBenchmarks.h
R libcxx/test/benchmarks/algorithms.partition_point.bench.cpp
A libcxx/test/benchmarks/algorithms/algorithms.partition_point.bench.cpp
A libcxx/test/benchmarks/algorithms/lexicographical_compare_three_way.bench.cpp
A libcxx/test/benchmarks/containers/ContainerBenchmarks.h
A libcxx/test/benchmarks/containers/deque.bench.cpp
A libcxx/test/benchmarks/containers/deque_iterator.bench.cpp
A libcxx/test/benchmarks/containers/map.bench.cpp
A libcxx/test/benchmarks/containers/ordered_set.bench.cpp
A libcxx/test/benchmarks/containers/string.bench.cpp
A libcxx/test/benchmarks/containers/unordered_set_operations.bench.cpp
A libcxx/test/benchmarks/containers/vector_operations.bench.cpp
R libcxx/test/benchmarks/deque.bench.cpp
R libcxx/test/benchmarks/deque_iterator.bench.cpp
R libcxx/test/benchmarks/format.bench.cpp
A libcxx/test/benchmarks/format/format.bench.cpp
A libcxx/test/benchmarks/format/format_to.bench.cpp
A libcxx/test/benchmarks/format/format_to_n.bench.cpp
A libcxx/test/benchmarks/format/formatted_size.bench.cpp
A libcxx/test/benchmarks/format/formatter_float.bench.cpp
A libcxx/test/benchmarks/format/formatter_int.bench.cpp
A libcxx/test/benchmarks/format/std_format_spec_string_unicode.bench.cpp
A libcxx/test/benchmarks/format/std_format_spec_string_unicode_escape.bench.cpp
R libcxx/test/benchmarks/format_to.bench.cpp
R libcxx/test/benchmarks/format_to_n.bench.cpp
R libcxx/test/benchmarks/formatted_size.bench.cpp
R libcxx/test/benchmarks/formatter_float.bench.cpp
R libcxx/test/benchmarks/formatter_int.bench.cpp
R libcxx/test/benchmarks/lexicographical_compare_three_way.bench.cpp
R libcxx/test/benchmarks/map.bench.cpp
R libcxx/test/benchmarks/ordered_set.bench.cpp
R libcxx/test/benchmarks/std_format_spec_string_unicode.bench.cpp
R libcxx/test/benchmarks/std_format_spec_string_unicode_escape.bench.cpp
R libcxx/test/benchmarks/string.bench.cpp
R libcxx/test/benchmarks/unordered_set_operations.bench.cpp
R libcxx/test/benchmarks/vector_operations.bench.cpp
Log Message:
-----------
[libc++] Slight reorganization of the benchmarks (#119625)
Move various container benchmarks to the same subdirectory, and regroup
some format-related benchmarks.
Commit: f9734b9df15bc1eea84ef00973c2e5560e70c27d
https://github.com/llvm/llvm-project/commit/f9734b9df15bc1eea84ef00973c2e5560e70c27d
Author: Kareem Ergawy <kareem.ergawy at amd.com>
Date: 2024-12-12 (Thu, 12 Dec 2024)
Changed paths:
M flang/lib/Optimizer/OpenMP/MapsForPrivatizedSymbols.cpp
M llvm/lib/Frontend/OpenMP/OMPIRBuilder.cpp
M llvm/unittests/Frontend/OpenMPIRBuilderTest.cpp
M mlir/include/mlir/Dialect/OpenMP/OpenMPOps.td
M mlir/lib/Target/LLVMIR/Dialect/OpenMP/OpenMPToLLVMIRTranslation.cpp
M mlir/test/Target/LLVMIR/omptarget-byref-bycopy-generation-device.mlir
M mlir/test/Target/LLVMIR/omptarget-declare-target-llvm-device.mlir
A mlir/test/Target/LLVMIR/openmp-target-multiple-private.mlir
A mlir/test/Target/LLVMIR/openmp-target-private-allocatable.mlir
M mlir/test/Target/LLVMIR/openmp-target-private.mlir
M mlir/test/Target/LLVMIR/openmp-target-use-device-nested.mlir
M mlir/test/Target/LLVMIR/openmp-todo.mlir
Log Message:
-----------
[mlir][OpenMP] - MLIR to LLVMIR translation support for delayed privatization of allocatables in `omp.target` ops (#116576)
This PR adds support to translate the `private` clause from MLIR to
LLVMIR when used on allocatables in the context of an `omp.target` op.
This replaces https://github.com/llvm/llvm-project/pull/113208.
Parent PR: https://github.com/llvm/llvm-project/pull/116770. Only the
latest commit is relevant to the PR.
Commit: 86779da52be6c6900a57fbba243f6894b19bb9b1
https://github.com/llvm/llvm-project/commit/86779da52be6c6900a57fbba243f6894b19bb9b1
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-12-12 (Thu, 12 Dec 2024)
Changed paths:
M llvm/lib/Transforms/Vectorize/VectorCombine.cpp
M llvm/test/Transforms/VectorCombine/X86/concat-boolmasks.ll
Log Message:
-----------
[VectorCombine] Fold "(or (zext (bitcast X)), (shl (zext (bitcast Y)), C))" -> "(bitcast (concat X, Y))" MOVMSK bool mask style patterns (#119695)
Mask/Bool vectors are often bitcast to/from scalar integers, in particular when concatenating mask results, often this is due to the difficulties of working with vector of bools on C/C++. On x86 this typically involves the MOVMSK/KMOV instructions.
To concatenate bool masks, these are typically cast to scalars, which are then zero-extended, shifted and OR'd together.
This patch attempts to match these scalar concatenation patterns and convert them to vector shuffles instead. This in turn often assists with further vector combines, depending on the cost model.
Reapplied patch from #119559 - fixed use after free issue.
Fixes #111431
Commit: f4ee5a673f6e593e85306cdf65493b53e62f936e
https://github.com/llvm/llvm-project/commit/f4ee5a673f6e593e85306cdf65493b53e62f936e
Author: Joseph Huber <huberjn at outlook.com>
Date: 2024-12-12 (Thu, 12 Dec 2024)
Changed paths:
M offload/DeviceRTL/include/Synchronization.h
M offload/DeviceRTL/src/Synchronization.cpp
Log Message:
-----------
[OpenMP] Replace AMDGPU fences with generic scoped fences (#119619)
Summary:
This is simpler and more common. I would've replaced the CUDA uses and
made this the same but currently it doesn't codegen these fences fully
and just emits a full system wide barrier as a fallback.
Commit: 34d244a94195dbeb626573c9b2e388dc574f9300
https://github.com/llvm/llvm-project/commit/34d244a94195dbeb626573c9b2e388dc574f9300
Author: Yi Kong <yikong at google.com>
Date: 2024-12-12 (Thu, 12 Dec 2024)
Changed paths:
M compiler-rt/lib/rtsan/rtsan_interceptors_posix.cpp
Log Message:
-----------
Fix rtsan build with musl (#119674)
fd_set is defined by `sys/select.h`. On musl, this header is not
transitively included by the other headers.
Failure message:
```
compiler-rt/lib/rtsan/rtsan_interceptors_posix.cpp:761:37: error: unknown type name 'fd_set'; did you mean 'fd_t'?
761 | INTERCEPTOR(int, pselect, int nfds, fd_set *readfds, fd_set *writefds,
| ^~~~~~
| fd_t
```
Commit: 10ef20f6a629797d81252de143117e2a0bc6556d
https://github.com/llvm/llvm-project/commit/10ef20f6a629797d81252de143117e2a0bc6556d
Author: Nikita Popov <npopov at redhat.com>
Date: 2024-12-12 (Thu, 12 Dec 2024)
Changed paths:
M mlir/CMakeLists.txt
M mlir/cmake/modules/AddMLIR.cmake
M mlir/tools/mlir-cpu-runner/CMakeLists.txt
M mlir/tools/mlir-lsp-server/CMakeLists.txt
M mlir/tools/mlir-opt/CMakeLists.txt
M mlir/tools/mlir-parser-fuzzer/bytecode/CMakeLists.txt
M mlir/tools/mlir-parser-fuzzer/text/CMakeLists.txt
M mlir/tools/mlir-query/CMakeLists.txt
M mlir/tools/mlir-reduce/CMakeLists.txt
M mlir/tools/mlir-rewrite/CMakeLists.txt
M mlir/tools/mlir-translate/CMakeLists.txt
Log Message:
-----------
[mlir] Add support for MLIR_LINK_MLIR_DYLIB (#119408)
While MLIR currently supports building a libMLIR.so, it does not support
actually linking against it for its own tools. When building with LTO,
this means we have to relink the world for every tool, and the resulting
binaries are large.
This adds basic support for MLIR_LINK_MLIR_DYLIB, modelled after how
CLANG_LINK_CLANG_DYLIB is implemented: Libraries that are part of
libMLIR.so should be added via mlir_target_link_libraries instead of
target_link_libraries. This will replace them with libMLIR.so if
MLIR_LINK_MLIR_DYLIB is enabled.
This adds basic support, I think there are two more things that can be
done here:
* C API unit tests should link against libMLIR-C.so. Currently these
still link statically.
* Linking the test libs (not part of libMLIR.so) still pulls in
dependencies statically that should come from libMLIR.so.
Commit: e909c0ccd40e6d6aa2d10e0b60e8b992f3cde35b
https://github.com/llvm/llvm-project/commit/e909c0ccd40e6d6aa2d10e0b60e8b992f3cde35b
Author: Igor Kirillov <igor.kirillov at arm.com>
Date: 2024-12-12 (Thu, 12 Dec 2024)
Changed paths:
M llvm/lib/CodeGen/SelectOptimize.cpp
M llvm/test/CodeGen/AArch64/selectopt-cast.ll
Log Message:
-----------
[SelectOpt] Add support for AShr/LShr operands (#118495)
For conditional increments with sign check conditions like X < 0 or X >= 0,
the compiler may generate code like this:
%cmp = icmp sgt i64 %1, -1
%shift = ashr i64 %1, 63
%j.next = add nsw i64 %j, %shift
%sel = select i1 %cmp ...
, where %cmp is not in computation but in some other implicit or regular
expressions. This patch allows SelectOptimize pass to recognise these
cases.
Commit: 46ec271e039dfea0b8bb543290d27ca18b2e807b
https://github.com/llvm/llvm-project/commit/46ec271e039dfea0b8bb543290d27ca18b2e807b
Author: Jie Fu <jiefu at tencent.com>
Date: 2024-12-12 (Thu, 12 Dec 2024)
Changed paths:
M mlir/lib/Target/LLVMIR/Dialect/OpenMP/OpenMPToLLVMIRTranslation.cpp
Log Message:
-----------
[mlir] Fix -Wunused-variable in OpenMPToLLVMIRTranslation.cpp (NFC)
/llvm-project/mlir/lib/Target/LLVMIR/Dialect/OpenMP/OpenMPToLLVMIRTranslation.cpp:3921:12:
error: unused variable 'varType' [-Werror,-Wunused-variable]
Type varType = mapInfoOp.getVarType();
^
1 error generated.
Commit: e582865aa46b6b46d8c7e8a9244443247f5f173b
https://github.com/llvm/llvm-project/commit/e582865aa46b6b46d8c7e8a9244443247f5f173b
Author: Nikita Popov <npopov at redhat.com>
Date: 2024-12-12 (Thu, 12 Dec 2024)
Changed paths:
M mlir/tools/mlir-opt/CMakeLists.txt
Log Message:
-----------
[mlir] Link MLIRMlirOptMain against test_libs
In 10ef20f6a629797d81252de143117e2a0bc6556d I dropped $test_libs
from $LIBS to handle them separately for the mlir-opt tool.
However, they should still include them in LINK_LIBS for the
MLIRMlirOptMain library.
Commit: bdaa82a7bb14b1016dbee554ef919323a197754d
https://github.com/llvm/llvm-project/commit/bdaa82a7bb14b1016dbee554ef919323a197754d
Author: Pravin Jagtap <Pravin.Jagtap at amd.com>
Date: 2024-12-12 (Thu, 12 Dec 2024)
Changed paths:
M llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
M llvm/test/CodeGen/AMDGPU/av-spill-expansion-with-machine-cp.mir
Log Message:
-----------
[AMDGPU] Mark AGPR tuple implicit in the first instr of AGPR spills. (#115285)
When AGPRs are spilled to stack through VGPRs, the pei only marks the
AGPR tuple as implicit-def. To preserve the liveness, it should also
mark the tuple implicit.
Fixes: SWDEV-462189
Commit: bae383ba6b53b0d8257c83f99ceecdd751d0a378
https://github.com/llvm/llvm-project/commit/bae383ba6b53b0d8257c83f99ceecdd751d0a378
Author: Aaron Puchert <aaron.puchert at sap.com>
Date: 2024-12-12 (Thu, 12 Dec 2024)
Changed paths:
M clang/lib/Driver/ToolChains/CommonArgs.cpp
M clang/lib/Driver/ToolChains/CommonArgs.h
M clang/lib/Driver/ToolChains/FreeBSD.cpp
M clang/lib/Driver/ToolChains/Fuchsia.cpp
M clang/lib/Driver/ToolChains/Gnu.cpp
M clang/lib/Driver/ToolChains/Hexagon.cpp
M clang/lib/Driver/ToolChains/NetBSD.cpp
M clang/lib/Driver/ToolChains/OpenBSD.cpp
M clang/lib/Driver/ToolChains/Solaris.cpp
Log Message:
-----------
[Driver] Cache SanitizerArgs (NFC) (#119442)
The name getSanitizerArgs seems to mislead callers that this is a cheap
function, but it extracts the SanitizerArgs each time it is called.
So we try to reuse it a bit more.
Commit: bb1961ed7779e782f4c28ee38854decf6f53c82f
https://github.com/llvm/llvm-project/commit/bb1961ed7779e782f4c28ee38854decf6f53c82f
Author: Pravin Jagtap <Pravin.Jagtap at amd.com>
Date: 2024-12-12 (Thu, 12 Dec 2024)
Changed paths:
M llvm/lib/Target/AMDGPU/VOP3Instructions.td
Log Message:
-----------
[AMDGPU] Stop using True16 profile for v_bitop3_b16 of gfx950. (#119706)
Commit: 67eb05b2928ea707761bb040e6eb824f4ca9ef3a
https://github.com/llvm/llvm-project/commit/67eb05b2928ea707761bb040e6eb824f4ca9ef3a
Author: Stefan Pintilie <stefanp at ca.ibm.com>
Date: 2024-12-12 (Thu, 12 Dec 2024)
Changed paths:
M llvm/lib/Target/PowerPC/PPCISelLowering.cpp
M llvm/test/CodeGen/PowerPC/aix-cc-abi-mir.ll
M llvm/test/CodeGen/PowerPC/aix-cc-abi.ll
Log Message:
-----------
[PowerPC] Add special handling for arguments that are smaller than pointer size. (#119003)
When arguments are passed in memory instead of registers we currently
load the entire pointer size even though the argument may be smaller.
For exmaple if the pointer size if i32 then we use a load word even if
the argument is only an i8. This patch zeros / extends the bits that are
not required to ensure that we are getting the correct value even if the
load is larger.
Commit: bc28be0a428020ea803c94adb4df48ee4972e9f1
https://github.com/llvm/llvm-project/commit/bc28be0a428020ea803c94adb4df48ee4972e9f1
Author: Peng Huang <shawn.p.huang at gmail.com>
Date: 2024-12-12 (Thu, 12 Dec 2024)
Changed paths:
M clang/lib/Driver/ToolChains/OHOS.cpp
Log Message:
-----------
[Driver][OHOS] Fix lld link issue for OHOS (#118192)
For ohos targets, libclang_rt.builtins.a, clang_rt.crtbegin.o and
clang_rt.crtend.o are installed in
clang/20/lib/${arch}-unknown-linux-ohos. However OHOS toolchain search
them in clang/20/lib/${arch}-linux-ohos folder. It causes link error.
Fix the problem by seaching both folders.
Commit: 6f8a363a483489687597e29b8bda0975e821f188
https://github.com/llvm/llvm-project/commit/6f8a363a483489687597e29b8bda0975e821f188
Author: AidinT <at.aidin at gmail.com>
Date: 2024-12-12 (Thu, 12 Dec 2024)
Changed paths:
M llvm/docs/tutorial/MyFirstLanguageFrontend/LangImpl07.rst
M llvm/examples/Kaleidoscope/Chapter7/toy.cpp
Log Message:
-----------
[Kaleidoscope] Add mem2reg pass to function pass manager (#119707)
Kaleidoscope has switched to new pass manager before (#72324), but both
code and tutorial document have some missing parts.
This pull request fixes the following problems:
1. Adds `PromotePass` to the function pass manager. This pass was
removed during the switch from legacy pass manager to the new pass
manager.
2. Syncs the tutorial with the code.
Commit: 010d0115fc8e3834fc6f747f0841f3b1e467c4da
https://github.com/llvm/llvm-project/commit/010d0115fc8e3834fc6f747f0841f3b1e467c4da
Author: erichkeane <ekeane at nvidia.com>
Date: 2024-12-12 (Thu, 12 Dec 2024)
Changed paths:
M clang/include/clang-c/Index.h
M clang/include/clang/AST/RecursiveASTVisitor.h
M clang/include/clang/AST/StmtOpenACC.h
M clang/include/clang/AST/TextNodeDumper.h
M clang/include/clang/Basic/StmtNodes.td
M clang/include/clang/Serialization/ASTBitCodes.h
M clang/lib/AST/StmtOpenACC.cpp
M clang/lib/AST/StmtPrinter.cpp
M clang/lib/AST/StmtProfile.cpp
M clang/lib/AST/TextNodeDumper.cpp
M clang/lib/CodeGen/CGStmt.cpp
M clang/lib/CodeGen/CodeGenFunction.h
M clang/lib/Parse/ParseOpenACC.cpp
M clang/lib/Sema/SemaExceptionSpec.cpp
M clang/lib/Sema/SemaOpenACC.cpp
M clang/lib/Sema/TreeTransform.h
M clang/lib/Serialization/ASTReaderStmt.cpp
M clang/lib/Serialization/ASTWriterStmt.cpp
M clang/lib/StaticAnalyzer/Core/ExprEngine.cpp
A clang/test/AST/ast-print-openacc-data-construct.cpp
M clang/test/ParserOpenACC/parse-clauses.c
M clang/test/ParserOpenACC/parse-clauses.cpp
M clang/test/ParserOpenACC/parse-constructs.c
M clang/test/SemaOpenACC/combined-construct-collapse-clause.cpp
M clang/test/SemaOpenACC/combined-construct-default-clause.c
M clang/test/SemaOpenACC/combined-construct-if-clause.c
M clang/test/SemaOpenACC/compute-construct-default-clause.c
M clang/test/SemaOpenACC/compute-construct-device_type-clause.c
M clang/test/SemaOpenACC/compute-construct-if-clause.c
A clang/test/SemaOpenACC/data-construct-ast.cpp
A clang/test/SemaOpenACC/data-construct.cpp
M clang/test/SemaOpenACC/loop-construct-collapse-clause.cpp
M clang/tools/libclang/CIndex.cpp
M clang/tools/libclang/CXCursor.cpp
Log Message:
-----------
[OpenACC] Create AST nodes for 'data' constructs
These constructs are all very similar and closely related, so this patch
creates the AST nodes for them, serialization, printing/etc.
Additionally the restrictions are all added as tests/todos in the tests,
as those will have to be implemented once we get those clauses implemented.
Commit: f229ea2ffe9bb8380a4285bd379736aaadaf55ac
https://github.com/llvm/llvm-project/commit/f229ea2ffe9bb8380a4285bd379736aaadaf55ac
Author: Haojian Wu <hokein.wu at gmail.com>
Date: 2024-12-12 (Thu, 12 Dec 2024)
Changed paths:
M clang/docs/ReleaseNotes.rst
M clang/include/clang/Basic/DiagnosticSemaKinds.td
Log Message:
-----------
[clang] Enable the -Wdangling-capture diagnostic by default. (#119685)
We have tested this diagnostics internally, and we don't find see any
issues.
Commit: a8e66d7f17bc648865cebf6b1e58c7a9071c6a84
https://github.com/llvm/llvm-project/commit/a8e66d7f17bc648865cebf6b1e58c7a9071c6a84
Author: iseki <admin at iseki.space>
Date: 2024-12-12 (Thu, 12 Dec 2024)
Changed paths:
M clang/include/clang-c/CXString.h
Log Message:
-----------
[docs] Add a more detailed description in CXString.h. (#119090)
Emmm... Maybe I'm splitting hairs. But I really think the paragraph
should be more detailed. The orginal document makes me confused. Do I
take the ownership of the string data?
Here I don't refer the `clang_disposeString` function, because here's a
`clang_disposeStringSet`.
Co-authored-by: Saleem Abdulrasool <compnerd at compnerd.org>
Commit: 2f8238f849c4836b333082f387d91408234ea73b
https://github.com/llvm/llvm-project/commit/2f8238f849c4836b333082f387d91408234ea73b
Author: Kazu Hirata <kazu at google.com>
Date: 2024-12-12 (Thu, 12 Dec 2024)
Changed paths:
M llvm/lib/DWARFLinker/Parallel/DWARFLinkerCompileUnit.cpp
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
M llvm/unittests/IR/IRBuilderTest.cpp
Log Message:
-----------
[llvm] Migrate away from PointerUnion::{is,get} (NFC) (#119679)
Note that PointerUnion::{is,get} have been soft deprecated in
PointerUnion.h:
// FIXME: Replace the uses of is(), get() and dyn_cast() with
// isa<T>, cast<T> and the llvm::dyn_cast<T>
I'm not touching PointerUnion::dyn_cast for now because it's a bit
complicated; we could blindly migrate it to dyn_cast_if_present, but
we should probably use dyn_cast when the operand is known to be
non-null.
Commit: fda80a4fcad8bab67fc1f522d68012e572866066
https://github.com/llvm/llvm-project/commit/fda80a4fcad8bab67fc1f522d68012e572866066
Author: Kazu Hirata <kazu at google.com>
Date: 2024-12-12 (Thu, 12 Dec 2024)
Changed paths:
M llvm/unittests/ProfileData/MemProfTest.cpp
Log Message:
-----------
[memprof] Use addCallStack in a unit test (NFC) (#119651)
Here IndexedMemProfRecord just needs to reference a CallStackID, so we
can use addCallStack for a real hash-based CallStackId instead of a
fake value like 0x222.
Commit: 6c8f41d3367476d35ac730abf9f980291737193b
https://github.com/llvm/llvm-project/commit/6c8f41d3367476d35ac730abf9f980291737193b
Author: Florian Hahn <flo at fhahn.com>
Date: 2024-12-12 (Thu, 12 Dec 2024)
Changed paths:
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
M llvm/lib/Transforms/Vectorize/VPlan.cpp
M llvm/lib/Transforms/Vectorize/VPlan.h
M llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
M llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
M llvm/lib/Transforms/Vectorize/VPlanUnroll.cpp
M llvm/lib/Transforms/Vectorize/VPlanUtils.cpp
M llvm/lib/Transforms/Vectorize/VPlanVerifier.cpp
M llvm/test/Transforms/LoopVectorize/AArch64/sve-tail-folding-forced.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve-widen-gep.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve2-histcnt-vplan.ll
M llvm/test/Transforms/LoopVectorize/AArch64/synthesize-mask-for-call.ll
M llvm/test/Transforms/LoopVectorize/AArch64/widen-call-with-intrinsic-or-libfunc.ll
M llvm/test/Transforms/LoopVectorize/PowerPC/vplan-force-tail-with-evl.ll
M llvm/test/Transforms/LoopVectorize/RISCV/riscv-vector-reverse.ll
M llvm/test/Transforms/LoopVectorize/RISCV/vplan-vp-intrinsics-reduction.ll
M llvm/test/Transforms/LoopVectorize/RISCV/vplan-vp-select-intrinsics.ll
M llvm/test/Transforms/LoopVectorize/first-order-recurrence-chains-vplan.ll
M llvm/test/Transforms/LoopVectorize/first-order-recurrence-sink-replicate-region.ll
M llvm/test/Transforms/LoopVectorize/icmp-uniforms.ll
M llvm/test/Transforms/LoopVectorize/interleave-and-scalarize-only.ll
M llvm/test/Transforms/LoopVectorize/uncountable-early-exit-vplan.ll
M llvm/test/Transforms/LoopVectorize/vplan-dot-printing.ll
M llvm/test/Transforms/LoopVectorize/vplan-iv-transforms.ll
M llvm/test/Transforms/LoopVectorize/vplan-predicate-switch.ll
M llvm/test/Transforms/LoopVectorize/vplan-printing-before-execute.ll
M llvm/test/Transforms/LoopVectorize/vplan-printing-outer-loop.ll
M llvm/test/Transforms/LoopVectorize/vplan-printing.ll
M llvm/test/Transforms/LoopVectorize/vplan-sink-scalars-and-merge-vf1.ll
M llvm/test/Transforms/LoopVectorize/vplan-sink-scalars-and-merge.ll
M llvm/test/Transforms/LoopVectorize/vplan-unused-interleave-group.ll
M llvm/test/Transforms/PhaseOrdering/AArch64/hoist-runtime-checks.ll
M llvm/test/Transforms/PhaseOrdering/X86/hoist-load-of-baseptr.ll
M llvm/test/Transforms/PhaseOrdering/X86/preserve-access-group.ll
M llvm/unittests/Transforms/Vectorize/VPlanHCFGTest.cpp
M llvm/unittests/Transforms/Vectorize/VPlanTest.cpp
M llvm/unittests/Transforms/Vectorize/VPlanVerifierTest.cpp
Log Message:
-----------
[VPlan] Hook IR blocks into VPlan during skeleton creation (NFC) (#114292)
As a first step to move towards modeling the full skeleton in VPlan,
start by wrapping IR blocks created during legacy skeleton creation in
VPIRBasicBlocks and hook them into the VPlan. This means the skeleton
CFG is represented in VPlan, just before execute. This allows moving
parts of skeleton creation into recipes in the VPBBs gradually.
Note that this allows retiring some manual DT updates, as this will be
handled automatically during VPlan execution.
PR: https://github.com/llvm/llvm-project/pull/114292
Commit: e5371eded9c22ec4854634c9c58df793562f782d
https://github.com/llvm/llvm-project/commit/e5371eded9c22ec4854634c9c58df793562f782d
Author: Sander de Smalen <sander.desmalen at arm.com>
Date: 2024-12-12 (Thu, 12 Dec 2024)
Changed paths:
M compiler-rt/lib/builtins/CMakeLists.txt
Log Message:
-----------
[compiler-rt] Don't build SME routines if __arm_cpu_features is not initialised. (#119703)
According to the conversation
[here](https://github.com/llvm/llvm-project/pull/119414#issuecomment-2536495859),
some platforms don't enable `__arm_cpu_features` with a global
constructor, but rather do so lazily when called from the FMV resolver.
PR #119414 removed the CMake guard to check to see if the targetted
platform is baremetal or supports sys/auxv. Without this check, the
routines rely on `__arm_cpu_features` being initialised when they may
not be, depending on the platform.
This PR simply avoids building the SME routines for those platforms for
now.
Commit: 4aacafd49b74dc168e0d99018b4c8289ce9c923e
https://github.com/llvm/llvm-project/commit/4aacafd49b74dc168e0d99018b4c8289ce9c923e
Author: Clement Courbet <courbet at google.com>
Date: 2024-12-12 (Thu, 12 Dec 2024)
Changed paths:
M clang/include/clang/AST/RecursiveASTVisitor.h
M clang/unittests/AST/ASTContextParentMapTest.cpp
M clang/unittests/Analysis/FlowSensitive/TransferTest.cpp
Log Message:
-----------
[clang][ASTVisitor] Visit `HoldingVar` from `BindingDecl`. (#117858)
Tuple-like types introduce `VarDecl`s in the AST for their "holding
vars", but AST visitors do not visit those. As a result the `VarDecl`
for the holding var is orphaned when trying to retreive its parents.
Fix a `FlowSensitive` test that assumes that only a `BindingDecl` is
introduced with the given name (the matcher now can also reach the
`VarDecl` for the holding var).
Commit: 9c319d5bb40785c969d2af76535ca62448dfafa7
https://github.com/llvm/llvm-project/commit/9c319d5bb40785c969d2af76535ca62448dfafa7
Author: Sander de Smalen <sander.desmalen at arm.com>
Date: 2024-12-12 (Thu, 12 Dec 2024)
Changed paths:
M llvm/lib/Target/AArch64/AArch64Subtarget.cpp
M llvm/test/CodeGen/AArch64/Atomics/aarch64-atomicrmw-lse2_lse128.ll
M llvm/test/CodeGen/AArch64/Atomics/aarch64-atomicrmw-v8_1a.ll
M llvm/test/CodeGen/AArch64/Atomics/aarch64_be-atomicrmw-lse2_lse128.ll
M llvm/test/CodeGen/AArch64/Atomics/aarch64_be-atomicrmw-v8_1a.ll
M llvm/test/CodeGen/AArch64/GlobalISel/arm64-atomic-128.ll
M llvm/test/CodeGen/AArch64/GlobalISel/arm64-atomic.ll
M llvm/test/CodeGen/AArch64/GlobalISel/arm64-pcsections.ll
M llvm/test/CodeGen/AArch64/GlobalISel/combine-udiv.ll
M llvm/test/CodeGen/AArch64/GlobalISel/insert-vector-elt-pr63826.ll
M llvm/test/CodeGen/AArch64/aarch64-addv.ll
M llvm/test/CodeGen/AArch64/aarch64-be-bv.ll
M llvm/test/CodeGen/AArch64/aarch64-bf16-dotprod-intrinsics.ll
M llvm/test/CodeGen/AArch64/aarch64-bif-gen.ll
M llvm/test/CodeGen/AArch64/aarch64-bit-gen.ll
M llvm/test/CodeGen/AArch64/aarch64-combine-add-sub-mul.ll
M llvm/test/CodeGen/AArch64/aarch64-combine-add-zext.ll
M llvm/test/CodeGen/AArch64/aarch64-dup-ext-scalable.ll
M llvm/test/CodeGen/AArch64/aarch64-dup-ext.ll
M llvm/test/CodeGen/AArch64/aarch64-dup-extract-scalable.ll
M llvm/test/CodeGen/AArch64/aarch64-fold-lslfast.ll
M llvm/test/CodeGen/AArch64/aarch64-interleaved-access-w-undef.ll
M llvm/test/CodeGen/AArch64/aarch64-load-ext.ll
M llvm/test/CodeGen/AArch64/aarch64-matrix-umull-smull.ll
M llvm/test/CodeGen/AArch64/aarch64-minmaxv.ll
M llvm/test/CodeGen/AArch64/aarch64-mops-mte.ll
M llvm/test/CodeGen/AArch64/aarch64-mops.ll
M llvm/test/CodeGen/AArch64/aarch64-mull-masks.ll
M llvm/test/CodeGen/AArch64/aarch64-mulv.ll
M llvm/test/CodeGen/AArch64/aarch64-neon-vector-insert-uaddlv.ll
M llvm/test/CodeGen/AArch64/aarch64-scalarize-vec-load-ext.ll
M llvm/test/CodeGen/AArch64/aarch64-sysreg128.ll
M llvm/test/CodeGen/AArch64/aarch64-wide-shuffle.ll
M llvm/test/CodeGen/AArch64/abs.ll
M llvm/test/CodeGen/AArch64/active_lane_mask.ll
M llvm/test/CodeGen/AArch64/adc.ll
M llvm/test/CodeGen/AArch64/add-extract.ll
M llvm/test/CodeGen/AArch64/add.ll
M llvm/test/CodeGen/AArch64/addimm-mulimm.ll
M llvm/test/CodeGen/AArch64/addp-shuffle.ll
M llvm/test/CodeGen/AArch64/addsub_ext.ll
M llvm/test/CodeGen/AArch64/and-mask-removal.ll
M llvm/test/CodeGen/AArch64/andorxor.ll
M llvm/test/CodeGen/AArch64/arm64-abi-varargs.ll
M llvm/test/CodeGen/AArch64/arm64-addp.ll
M llvm/test/CodeGen/AArch64/arm64-addr-type-promotion.ll
M llvm/test/CodeGen/AArch64/arm64-atomic-128.ll
M llvm/test/CodeGen/AArch64/arm64-bitfield-extract.ll
M llvm/test/CodeGen/AArch64/arm64-build-vector.ll
M llvm/test/CodeGen/AArch64/arm64-collect-loh.ll
M llvm/test/CodeGen/AArch64/arm64-dup.ll
M llvm/test/CodeGen/AArch64/arm64-ext.ll
M llvm/test/CodeGen/AArch64/arm64-extract-insert-varidx.ll
M llvm/test/CodeGen/AArch64/arm64-extract_subvector.ll
M llvm/test/CodeGen/AArch64/arm64-fcopysign.ll
M llvm/test/CodeGen/AArch64/arm64-fixed-point-scalar-cvt-dagcombine.ll
M llvm/test/CodeGen/AArch64/arm64-fmax.ll
M llvm/test/CodeGen/AArch64/arm64-fp128.ll
M llvm/test/CodeGen/AArch64/arm64-indexed-vector-ldst.ll
M llvm/test/CodeGen/AArch64/arm64-instruction-mix-remarks.ll
M llvm/test/CodeGen/AArch64/arm64-ld1.ll
M llvm/test/CodeGen/AArch64/arm64-ldxr-stxr.ll
M llvm/test/CodeGen/AArch64/arm64-mul.ll
M llvm/test/CodeGen/AArch64/arm64-neon-2velem-high.ll
M llvm/test/CodeGen/AArch64/arm64-neon-2velem.ll
M llvm/test/CodeGen/AArch64/arm64-neon-3vdiff.ll
M llvm/test/CodeGen/AArch64/arm64-neon-add-pairwise.ll
M llvm/test/CodeGen/AArch64/arm64-neon-copy.ll
M llvm/test/CodeGen/AArch64/arm64-neon-copyPhysReg-tuple.ll
M llvm/test/CodeGen/AArch64/arm64-neon-mul-div.ll
M llvm/test/CodeGen/AArch64/arm64-neon-scalar-by-elem-mul.ll
M llvm/test/CodeGen/AArch64/arm64-neon-select_cc.ll
M llvm/test/CodeGen/AArch64/arm64-neon-simd-ldst-one.ll
M llvm/test/CodeGen/AArch64/arm64-neon-simd-shift.ll
M llvm/test/CodeGen/AArch64/arm64-neon-simd-vget.ll
M llvm/test/CodeGen/AArch64/arm64-neon-v1i1-setcc.ll
M llvm/test/CodeGen/AArch64/arm64-neon-v8.1a.ll
M llvm/test/CodeGen/AArch64/arm64-nvcast.ll
M llvm/test/CodeGen/AArch64/arm64-popcnt.ll
M llvm/test/CodeGen/AArch64/arm64-rev.ll
M llvm/test/CodeGen/AArch64/arm64-shifted-sext.ll
M llvm/test/CodeGen/AArch64/arm64-shrink-wrapping.ll
M llvm/test/CodeGen/AArch64/arm64-stp.ll
M llvm/test/CodeGen/AArch64/arm64-subvector-extend.ll
M llvm/test/CodeGen/AArch64/arm64-tbl.ll
M llvm/test/CodeGen/AArch64/arm64-vadd.ll
M llvm/test/CodeGen/AArch64/arm64-vaddv.ll
M llvm/test/CodeGen/AArch64/arm64-vcvt_f.ll
M llvm/test/CodeGen/AArch64/arm64-vector-insertion.ll
M llvm/test/CodeGen/AArch64/arm64-vmul.ll
M llvm/test/CodeGen/AArch64/arm64-zip.ll
M llvm/test/CodeGen/AArch64/arm64_32-addrs.ll
M llvm/test/CodeGen/AArch64/arm64ec-entry-thunks.ll
M llvm/test/CodeGen/AArch64/arm64ec-exit-thunks.ll
M llvm/test/CodeGen/AArch64/atomic-ops-lse.ll
M llvm/test/CodeGen/AArch64/atomic-ops-msvc.ll
M llvm/test/CodeGen/AArch64/atomic-ops.ll
M llvm/test/CodeGen/AArch64/atomicrmw-fadd.ll
M llvm/test/CodeGen/AArch64/atomicrmw-fmax.ll
M llvm/test/CodeGen/AArch64/atomicrmw-fmin.ll
M llvm/test/CodeGen/AArch64/atomicrmw-fsub.ll
M llvm/test/CodeGen/AArch64/atomicrmw-xchg-fp.ll
M llvm/test/CodeGen/AArch64/bf16-instructions.ll
M llvm/test/CodeGen/AArch64/bf16-select.ll
M llvm/test/CodeGen/AArch64/bf16-shuffle.ll
M llvm/test/CodeGen/AArch64/bf16-v4-instructions.ll
M llvm/test/CodeGen/AArch64/bf16-v8-instructions.ll
M llvm/test/CodeGen/AArch64/bf16-vector-shuffle.ll
M llvm/test/CodeGen/AArch64/bitcast-promote-widen.ll
M llvm/test/CodeGen/AArch64/bitcast.ll
M llvm/test/CodeGen/AArch64/bitfield-insert.ll
M llvm/test/CodeGen/AArch64/bswap.ll
M llvm/test/CodeGen/AArch64/build-one-lane.ll
M llvm/test/CodeGen/AArch64/build-vector-extract.ll
M llvm/test/CodeGen/AArch64/build-vector-two-dup.ll
M llvm/test/CodeGen/AArch64/check-sign-bit-before-extension.ll
M llvm/test/CodeGen/AArch64/cmp-to-cmn.ll
M llvm/test/CodeGen/AArch64/cmpxchg-idioms.ll
M llvm/test/CodeGen/AArch64/combine-andintoload.ll
M llvm/test/CodeGen/AArch64/complex-deinterleaving-f16-add.ll
M llvm/test/CodeGen/AArch64/complex-deinterleaving-f16-mul.ll
M llvm/test/CodeGen/AArch64/complex-deinterleaving-multiuses.ll
M llvm/test/CodeGen/AArch64/complex-deinterleaving-reductions-predicated-scalable.ll
M llvm/test/CodeGen/AArch64/complex-deinterleaving-reductions-scalable.ll
M llvm/test/CodeGen/AArch64/complex-deinterleaving-splat-scalable.ll
M llvm/test/CodeGen/AArch64/complex-deinterleaving-splat.ll
M llvm/test/CodeGen/AArch64/complex-deinterleaving-uniform-cases.ll
M llvm/test/CodeGen/AArch64/concat-vector.ll
M llvm/test/CodeGen/AArch64/concatbinop.ll
M llvm/test/CodeGen/AArch64/cvt-fp-int-fp.ll
M llvm/test/CodeGen/AArch64/dag-numsignbits.ll
M llvm/test/CodeGen/AArch64/dup.ll
M llvm/test/CodeGen/AArch64/duplane-index-patfrags.ll
M llvm/test/CodeGen/AArch64/ext-narrow-index.ll
M llvm/test/CodeGen/AArch64/extbinopload.ll
M llvm/test/CodeGen/AArch64/extract-bits.ll
M llvm/test/CodeGen/AArch64/extract-insert.ll
M llvm/test/CodeGen/AArch64/extract-lowbits.ll
M llvm/test/CodeGen/AArch64/extract-sext-zext.ll
M llvm/test/CodeGen/AArch64/extract-subvec-combine.ll
M llvm/test/CodeGen/AArch64/extract-vector-cmp.ll
M llvm/test/CodeGen/AArch64/extract-vector-elt.ll
M llvm/test/CodeGen/AArch64/f16-instructions.ll
M llvm/test/CodeGen/AArch64/fabs-fp128.ll
M llvm/test/CodeGen/AArch64/fabs.ll
M llvm/test/CodeGen/AArch64/faddp-half.ll
M llvm/test/CodeGen/AArch64/faddp.ll
M llvm/test/CodeGen/AArch64/faddsub.ll
M llvm/test/CodeGen/AArch64/fast-isel-addressing-modes.ll
M llvm/test/CodeGen/AArch64/fast-isel-gep.ll
M llvm/test/CodeGen/AArch64/fast-isel-shift.ll
M llvm/test/CodeGen/AArch64/fcmp.ll
M llvm/test/CodeGen/AArch64/fcopysign-noneon.ll
M llvm/test/CodeGen/AArch64/fcopysign.ll
M llvm/test/CodeGen/AArch64/fcvt.ll
M llvm/test/CodeGen/AArch64/fcvt_combine.ll
M llvm/test/CodeGen/AArch64/fdiv-combine.ll
M llvm/test/CodeGen/AArch64/fdiv.ll
M llvm/test/CodeGen/AArch64/fexplog.ll
M llvm/test/CodeGen/AArch64/fixed-point-conv-vec-pat.ll
M llvm/test/CodeGen/AArch64/fixed-vector-deinterleave.ll
M llvm/test/CodeGen/AArch64/fixed-vector-interleave.ll
M llvm/test/CodeGen/AArch64/fmaximum-legalization.ll
M llvm/test/CodeGen/AArch64/fminimummaximum.ll
M llvm/test/CodeGen/AArch64/fminmax.ll
M llvm/test/CodeGen/AArch64/fmla.ll
M llvm/test/CodeGen/AArch64/fmul.ll
M llvm/test/CodeGen/AArch64/fneg.ll
M llvm/test/CodeGen/AArch64/fold-int-pow2-with-fmul-or-fdiv.ll
M llvm/test/CodeGen/AArch64/fp-conversion-to-tbl.ll
M llvm/test/CodeGen/AArch64/fp-intrinsics-vector.ll
M llvm/test/CodeGen/AArch64/fp-maximumnum-minimumnum.ll
M llvm/test/CodeGen/AArch64/fp16-v8-instructions.ll
M llvm/test/CodeGen/AArch64/fp16-vector-shuffle.ll
M llvm/test/CodeGen/AArch64/fp16_intrinsic_lane.ll
M llvm/test/CodeGen/AArch64/fp8-sve-cvtn.ll
M llvm/test/CodeGen/AArch64/fpclamptosat_vec.ll
M llvm/test/CodeGen/AArch64/fpext.ll
M llvm/test/CodeGen/AArch64/fpmode.ll
M llvm/test/CodeGen/AArch64/fpow.ll
M llvm/test/CodeGen/AArch64/fpowi.ll
M llvm/test/CodeGen/AArch64/fptoi.ll
M llvm/test/CodeGen/AArch64/fptosi-sat-vector.ll
M llvm/test/CodeGen/AArch64/fptoui-sat-vector.ll
M llvm/test/CodeGen/AArch64/fptrunc.ll
M llvm/test/CodeGen/AArch64/freeze.ll
M llvm/test/CodeGen/AArch64/frem-power2.ll
M llvm/test/CodeGen/AArch64/frem.ll
M llvm/test/CodeGen/AArch64/fsincos.ll
M llvm/test/CodeGen/AArch64/fsqrt.ll
M llvm/test/CodeGen/AArch64/funnel-shift.ll
M llvm/test/CodeGen/AArch64/get-active-lane-mask-extract.ll
M llvm/test/CodeGen/AArch64/get_vector_length.ll
M llvm/test/CodeGen/AArch64/half.ll
M llvm/test/CodeGen/AArch64/hoist-and-by-const-from-lshr-in-eqcmp-zero.ll
M llvm/test/CodeGen/AArch64/hoist-and-by-const-from-shl-in-eqcmp-zero.ll
M llvm/test/CodeGen/AArch64/icmp.ll
M llvm/test/CodeGen/AArch64/implicit-def-remat-requires-impdef-check.mir
M llvm/test/CodeGen/AArch64/implicit-def-subreg-to-reg-regression.ll
M llvm/test/CodeGen/AArch64/implicit-def-with-impdef-greedy-assert.mir
M llvm/test/CodeGen/AArch64/insert-extend.ll
M llvm/test/CodeGen/AArch64/insert-subvector.ll
M llvm/test/CodeGen/AArch64/insertextract.ll
M llvm/test/CodeGen/AArch64/insertshuffleload.ll
M llvm/test/CodeGen/AArch64/intrinsic-cttz-elts-sve.ll
M llvm/test/CodeGen/AArch64/intrinsic-vector-match-sve2.ll
M llvm/test/CodeGen/AArch64/itofp-bf16.ll
M llvm/test/CodeGen/AArch64/itofp.ll
M llvm/test/CodeGen/AArch64/ldexp.ll
M llvm/test/CodeGen/AArch64/llrint-conv-fp16.ll
M llvm/test/CodeGen/AArch64/llrint-conv.ll
M llvm/test/CodeGen/AArch64/llround-conv-fp16.ll
M llvm/test/CodeGen/AArch64/llvm.exp10.ll
M llvm/test/CodeGen/AArch64/llvm.frexp.ll
M llvm/test/CodeGen/AArch64/llvm.sincos.ll
M llvm/test/CodeGen/AArch64/load.ll
M llvm/test/CodeGen/AArch64/logic-shift.ll
M llvm/test/CodeGen/AArch64/lrint-conv-fp16.ll
M llvm/test/CodeGen/AArch64/lrint-conv.ll
M llvm/test/CodeGen/AArch64/lround-conv-fp16.ll
M llvm/test/CodeGen/AArch64/lslfast.ll
M llvm/test/CodeGen/AArch64/machine-combiner-copy.ll
M llvm/test/CodeGen/AArch64/machine-licm-sub-loop.ll
M llvm/test/CodeGen/AArch64/memset-inline.ll
M llvm/test/CodeGen/AArch64/memset-vs-memset-inline.ll
M llvm/test/CodeGen/AArch64/misched-detail-resource-booking-01.mir
M llvm/test/CodeGen/AArch64/mla_mls_merge.ll
M llvm/test/CodeGen/AArch64/mul.ll
M llvm/test/CodeGen/AArch64/neon-bitcast.ll
M llvm/test/CodeGen/AArch64/neon-bitwise-instructions.ll
M llvm/test/CodeGen/AArch64/neon-dot-product.ll
M llvm/test/CodeGen/AArch64/neon-extadd-extract.ll
M llvm/test/CodeGen/AArch64/neon-extract.ll
M llvm/test/CodeGen/AArch64/neon-extracttruncate.ll
M llvm/test/CodeGen/AArch64/neon-insert-sve-elt.ll
M llvm/test/CodeGen/AArch64/neon-insextbitcast.ll
M llvm/test/CodeGen/AArch64/neon-luti.ll
M llvm/test/CodeGen/AArch64/neon-partial-reduce-dot-product.ll
M llvm/test/CodeGen/AArch64/neon-perm.ll
M llvm/test/CodeGen/AArch64/neon-reverseshuffle.ll
M llvm/test/CodeGen/AArch64/neon-rshrn.ll
M llvm/test/CodeGen/AArch64/neon-scalar-by-elem-fma.ll
M llvm/test/CodeGen/AArch64/neon-scalarize-histogram.ll
M llvm/test/CodeGen/AArch64/neon-shuffle-vector-tbl.ll
M llvm/test/CodeGen/AArch64/neon-truncstore.ll
M llvm/test/CodeGen/AArch64/neon-vcmla.ll
M llvm/test/CodeGen/AArch64/neon-wide-splat.ll
M llvm/test/CodeGen/AArch64/neon-widen-shuffle.ll
M llvm/test/CodeGen/AArch64/nontemporal-load.ll
M llvm/test/CodeGen/AArch64/nontemporal.ll
M llvm/test/CodeGen/AArch64/phi.ll
M llvm/test/CodeGen/AArch64/popcount.ll
M llvm/test/CodeGen/AArch64/pow.ll
M llvm/test/CodeGen/AArch64/pr-cf624b2.ll
M llvm/test/CodeGen/AArch64/pr58350.ll
M llvm/test/CodeGen/AArch64/pr58431.ll
M llvm/test/CodeGen/AArch64/pr61111.ll
M llvm/test/CodeGen/AArch64/preserve_nonecc_varargs_win64.ll
M llvm/test/CodeGen/AArch64/ptradd.ll
M llvm/test/CodeGen/AArch64/qmovn.ll
M llvm/test/CodeGen/AArch64/rcpc3.ll
M llvm/test/CodeGen/AArch64/reduce-and.ll
M llvm/test/CodeGen/AArch64/reduce-or.ll
M llvm/test/CodeGen/AArch64/reduce-shuffle.ll
M llvm/test/CodeGen/AArch64/reduce-xor.ll
M llvm/test/CodeGen/AArch64/regalloc-last-chance-recolor-with-split.mir
M llvm/test/CodeGen/AArch64/rem.ll
M llvm/test/CodeGen/AArch64/round-fptosi-sat-scalar.ll
M llvm/test/CodeGen/AArch64/select-constant-xor.ll
M llvm/test/CodeGen/AArch64/seqpairspill.mir
M llvm/test/CodeGen/AArch64/setcc_knownbits.ll
M llvm/test/CodeGen/AArch64/sext.ll
M llvm/test/CodeGen/AArch64/shift-amount-mod.ll
M llvm/test/CodeGen/AArch64/shift-by-signext.ll
M llvm/test/CodeGen/AArch64/shift-mod.ll
M llvm/test/CodeGen/AArch64/shift.ll
M llvm/test/CodeGen/AArch64/shift_minsize.ll
M llvm/test/CodeGen/AArch64/shuffle-tbl34.ll
M llvm/test/CodeGen/AArch64/shuffles.ll
M llvm/test/CodeGen/AArch64/shufflevector.ll
M llvm/test/CodeGen/AArch64/sink-and-fold.ll
M llvm/test/CodeGen/AArch64/sme-aarch64-svcount.ll
M llvm/test/CodeGen/AArch64/sme-avoid-coalescing-locally-streaming.ll
M llvm/test/CodeGen/AArch64/sme-intrinsics-loads.ll
M llvm/test/CodeGen/AArch64/sme-intrinsics-stores.ll
M llvm/test/CodeGen/AArch64/sme-pstate-sm-changing-call-disable-coalescing.ll
M llvm/test/CodeGen/AArch64/sme-streaming-body.ll
M llvm/test/CodeGen/AArch64/sme-streaming-compatible-interface.ll
M llvm/test/CodeGen/AArch64/sme2-fp8-intrinsics-cvt.ll
M llvm/test/CodeGen/AArch64/sme2-intrinsics-add-sub-za16.ll
M llvm/test/CodeGen/AArch64/sme2-intrinsics-add.ll
M llvm/test/CodeGen/AArch64/sme2-intrinsics-cvtn.ll
M llvm/test/CodeGen/AArch64/sme2-intrinsics-faminmax.ll
M llvm/test/CodeGen/AArch64/sme2-intrinsics-fmlas.ll
M llvm/test/CodeGen/AArch64/sme2-intrinsics-fp-dots.ll
M llvm/test/CodeGen/AArch64/sme2-intrinsics-fscale.ll
M llvm/test/CodeGen/AArch64/sme2-intrinsics-insert-mova.ll
M llvm/test/CodeGen/AArch64/sme2-intrinsics-luti4.ll
M llvm/test/CodeGen/AArch64/sme2-intrinsics-max.ll
M llvm/test/CodeGen/AArch64/sme2-intrinsics-min.ll
M llvm/test/CodeGen/AArch64/sme2-intrinsics-mlall.ll
M llvm/test/CodeGen/AArch64/sme2-intrinsics-mlals.ll
M llvm/test/CodeGen/AArch64/sme2-intrinsics-rshl.ll
M llvm/test/CodeGen/AArch64/sme2-intrinsics-select-sme-tileslice.ll
M llvm/test/CodeGen/AArch64/sme2-intrinsics-sqdmulh.ll
M llvm/test/CodeGen/AArch64/sme2-intrinsics-sub.ll
M llvm/test/CodeGen/AArch64/sme2-intrinsics-vdot.ll
M llvm/test/CodeGen/AArch64/smul_fix_sat.ll
M llvm/test/CodeGen/AArch64/spill-fold.mir
M llvm/test/CodeGen/AArch64/split-vector-insert.ll
M llvm/test/CodeGen/AArch64/srem-vector-lkk.ll
M llvm/test/CodeGen/AArch64/store.ll
M llvm/test/CodeGen/AArch64/sub.ll
M llvm/test/CodeGen/AArch64/sve-cntp-combine-i32.ll
M llvm/test/CodeGen/AArch64/sve-doublereduct.ll
M llvm/test/CodeGen/AArch64/sve-extract-element.ll
M llvm/test/CodeGen/AArch64/sve-extract-fixed-from-scalable-vector.ll
M llvm/test/CodeGen/AArch64/sve-extract-fixed-vector.ll
M llvm/test/CodeGen/AArch64/sve-extract-scalable-vector.ll
M llvm/test/CodeGen/AArch64/sve-fadda-select.ll
M llvm/test/CodeGen/AArch64/sve-fixed-length-bit-counting.ll
M llvm/test/CodeGen/AArch64/sve-fixed-length-concat.ll
M llvm/test/CodeGen/AArch64/sve-fixed-length-extract-subvector.ll
M llvm/test/CodeGen/AArch64/sve-fixed-length-extract-vector-elt.ll
M llvm/test/CodeGen/AArch64/sve-fixed-length-fp-extend-trunc.ll
M llvm/test/CodeGen/AArch64/sve-fixed-length-fp-reduce.ll
M llvm/test/CodeGen/AArch64/sve-fixed-length-fp-select.ll
M llvm/test/CodeGen/AArch64/sve-fixed-length-fp-to-int.ll
M llvm/test/CodeGen/AArch64/sve-fixed-length-fp128.ll
M llvm/test/CodeGen/AArch64/sve-fixed-length-insert-vector-elt.ll
M llvm/test/CodeGen/AArch64/sve-fixed-length-int-arith.ll
M llvm/test/CodeGen/AArch64/sve-fixed-length-int-div.ll
M llvm/test/CodeGen/AArch64/sve-fixed-length-int-extends.ll
M llvm/test/CodeGen/AArch64/sve-fixed-length-int-minmax.ll
M llvm/test/CodeGen/AArch64/sve-fixed-length-int-mulh.ll
M llvm/test/CodeGen/AArch64/sve-fixed-length-int-reduce.ll
M llvm/test/CodeGen/AArch64/sve-fixed-length-int-rem.ll
M llvm/test/CodeGen/AArch64/sve-fixed-length-int-select.ll
M llvm/test/CodeGen/AArch64/sve-fixed-length-int-to-fp.ll
M llvm/test/CodeGen/AArch64/sve-fixed-length-log-reduce.ll
M llvm/test/CodeGen/AArch64/sve-fixed-length-masked-128bit-loads.ll
M llvm/test/CodeGen/AArch64/sve-fixed-length-masked-loads.ll
M llvm/test/CodeGen/AArch64/sve-fixed-length-no-vscale-range.ll
M llvm/test/CodeGen/AArch64/sve-fixed-length-reshuffle.ll
M llvm/test/CodeGen/AArch64/sve-fixed-length-rev.ll
M llvm/test/CodeGen/AArch64/sve-fixed-length-sdiv-pow2.ll
M llvm/test/CodeGen/AArch64/sve-fixed-length-shuffles.ll
M llvm/test/CodeGen/AArch64/sve-fixed-length-splat-vector.ll
M llvm/test/CodeGen/AArch64/sve-fixed-length-subvector.ll
M llvm/test/CodeGen/AArch64/sve-fixed-length-trunc.ll
M llvm/test/CodeGen/AArch64/sve-fixed-length-vector-shuffle-tbl.ll
M llvm/test/CodeGen/AArch64/sve-fixed-vector-llrint.ll
M llvm/test/CodeGen/AArch64/sve-fixed-vector-lrint.ll
M llvm/test/CodeGen/AArch64/sve-fp-reduce-fadda.ll
M llvm/test/CodeGen/AArch64/sve-fp-reduce.ll
M llvm/test/CodeGen/AArch64/sve-i1-add-reduce.ll
M llvm/test/CodeGen/AArch64/sve-implicit-zero-filling.ll
M llvm/test/CodeGen/AArch64/sve-index-const-step-vector.ll
M llvm/test/CodeGen/AArch64/sve-insert-element.ll
M llvm/test/CodeGen/AArch64/sve-insert-vector.ll
M llvm/test/CodeGen/AArch64/sve-int-reduce.ll
M llvm/test/CodeGen/AArch64/sve-intrinsics-counting-elems-i32.ll
M llvm/test/CodeGen/AArch64/sve-intrinsics-dup-x.ll
M llvm/test/CodeGen/AArch64/sve-intrinsics-fp-reduce.ll
M llvm/test/CodeGen/AArch64/sve-intrinsics-perm-select.ll
M llvm/test/CodeGen/AArch64/sve-intrinsics-reinterpret.ll
M llvm/test/CodeGen/AArch64/sve-intrinsics-shifts.ll
M llvm/test/CodeGen/AArch64/sve-intrinsics-sqdec.ll
M llvm/test/CodeGen/AArch64/sve-intrinsics-sqinc.ll
M llvm/test/CodeGen/AArch64/sve-intrinsics-stN-reg-imm-addr-mode.ll
M llvm/test/CodeGen/AArch64/sve-intrinsics-stN-reg-reg-addr-mode.ll
M llvm/test/CodeGen/AArch64/sve-intrinsics-stores.ll
M llvm/test/CodeGen/AArch64/sve-merging-stores.ll
M llvm/test/CodeGen/AArch64/sve-nontemporal-masked-ldst.ll
M llvm/test/CodeGen/AArch64/sve-pr62151.ll
M llvm/test/CodeGen/AArch64/sve-pred-selectop.ll
M llvm/test/CodeGen/AArch64/sve-select.ll
M llvm/test/CodeGen/AArch64/sve-split-extract-elt.ll
M llvm/test/CodeGen/AArch64/sve-split-fp-reduce.ll
M llvm/test/CodeGen/AArch64/sve-split-int-reduce.ll
M llvm/test/CodeGen/AArch64/sve-stack-frame-layout.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-and-combine.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-bit-counting.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-bitselect.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-build-vector.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-concat.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-ext-loads.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-extract-subvector.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-extract-vector-elt.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fcopysign.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-arith.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-compares.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-extend-trunc.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-fma.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-minmax.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-reduce-fa64.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-reduce.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-rounding.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-select.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-to-int.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-vselect.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-insert-vector-elt.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-arith.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-compares.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-div.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-extends.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-log.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-minmax.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-mla-neon-fa64.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-mul.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-mulh.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-reduce.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-rem.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-select.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-shifts.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-to-fp.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-vselect.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-ld2-alloca.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-limit-duplane.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-loads.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-log-reduce.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-masked-gather-scatter.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-masked-load.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-masked-store.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-permute-rev.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-ptest.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-reductions.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-reshuffle.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-rev.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-sdiv-pow2.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-shuffle.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-splat-vector.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-trunc-stores.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-trunc.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-vector-shuffle.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-test-register-mov.ll
M llvm/test/CodeGen/AArch64/sve-vecreduce-dot.ll
M llvm/test/CodeGen/AArch64/sve-vector-compress.ll
M llvm/test/CodeGen/AArch64/sve-vector-splat.ll
M llvm/test/CodeGen/AArch64/sve-vl-arith.ll
M llvm/test/CodeGen/AArch64/sve2-histcnt.ll
M llvm/test/CodeGen/AArch64/sve2-intrinsics-luti.ll
M llvm/test/CodeGen/AArch64/sve2-intrinsics-perm-tb.ll
M llvm/test/CodeGen/AArch64/sve2p1-intrinsics-bfclamp.ll
M llvm/test/CodeGen/AArch64/sve2p1-intrinsics-fclamp.ll
M llvm/test/CodeGen/AArch64/sve2p1-intrinsics-multivec-stores.ll
M llvm/test/CodeGen/AArch64/sve2p1-intrinsics-sclamp.ll
M llvm/test/CodeGen/AArch64/sve2p1-intrinsics-selx4.ll
M llvm/test/CodeGen/AArch64/sve2p1-intrinsics-stores.ll
M llvm/test/CodeGen/AArch64/sve2p1-intrinsics-uclamp.ll
M llvm/test/CodeGen/AArch64/sve2p1-intrinsics-uzpx4.ll
M llvm/test/CodeGen/AArch64/sve2p1-intrinsics-while-pp.ll
M llvm/test/CodeGen/AArch64/swift-error-unreachable-use.ll
M llvm/test/CodeGen/AArch64/tbl-loops.ll
M llvm/test/CodeGen/AArch64/trunc-to-tbl.ll
M llvm/test/CodeGen/AArch64/uaddlv-vaddlp-combine.ll
M llvm/test/CodeGen/AArch64/umul_fix_sat.ll
M llvm/test/CodeGen/AArch64/urem-vector-lkk.ll
M llvm/test/CodeGen/AArch64/vec-combine-compare-to-bitmask.ll
M llvm/test/CodeGen/AArch64/vec-libcalls.ll
M llvm/test/CodeGen/AArch64/vecreduce-add-legalization.ll
M llvm/test/CodeGen/AArch64/vecreduce-add.ll
M llvm/test/CodeGen/AArch64/vecreduce-and-legalization.ll
M llvm/test/CodeGen/AArch64/vecreduce-bool.ll
M llvm/test/CodeGen/AArch64/vecreduce-fadd-legalization-strict.ll
M llvm/test/CodeGen/AArch64/vecreduce-fadd-legalization.ll
M llvm/test/CodeGen/AArch64/vecreduce-fadd-strict.ll
M llvm/test/CodeGen/AArch64/vecreduce-fadd.ll
M llvm/test/CodeGen/AArch64/vecreduce-fmax-legalization-nan.ll
M llvm/test/CodeGen/AArch64/vecreduce-fmax-legalization.ll
M llvm/test/CodeGen/AArch64/vecreduce-fmaximum.ll
M llvm/test/CodeGen/AArch64/vecreduce-fmin-legalization.ll
M llvm/test/CodeGen/AArch64/vecreduce-fminimum.ll
M llvm/test/CodeGen/AArch64/vecreduce-fmul-legalization-strict.ll
M llvm/test/CodeGen/AArch64/vecreduce-fmul-strict.ll
M llvm/test/CodeGen/AArch64/vecreduce-fmul.ll
M llvm/test/CodeGen/AArch64/vecreduce-umax-legalization.ll
M llvm/test/CodeGen/AArch64/vector-compress.ll
M llvm/test/CodeGen/AArch64/vector-fcopysign.ll
M llvm/test/CodeGen/AArch64/vector-fcvt.ll
M llvm/test/CodeGen/AArch64/vector-llrint.ll
M llvm/test/CodeGen/AArch64/vector-lrint.ll
M llvm/test/CodeGen/AArch64/vldn_shuffle.ll
M llvm/test/CodeGen/AArch64/win64-fpowi.ll
M llvm/test/CodeGen/AArch64/win64_vararg.ll
M llvm/test/CodeGen/AArch64/xtn.ll
M llvm/test/CodeGen/AArch64/zext.ll
Log Message:
-----------
[AArch64] Enable subreg liveness tracking by default.
Internal testing didn't flag up any functional- or performance regressions.
Commit: 60d9e6fba884048e1047a208b61f0dfd8baabaaa
https://github.com/llvm/llvm-project/commit/60d9e6fba884048e1047a208b61f0dfd8baabaaa
Author: Jan Ječmen <JanJecmen at users.noreply.github.com>
Date: 2024-12-12 (Thu, 12 Dec 2024)
Changed paths:
M llvm/lib/Transforms/Scalar/InductiveRangeCheckElimination.cpp
M llvm/test/Transforms/IRCE/low-iterations.ll
A llvm/test/Transforms/IRCE/profitability.ll
Log Message:
-----------
[IRCE] Relax profitability check (#104659)
IRCE currently has two profitability checks:
1. min number of iterations (10 by default)
2. branch is highly biased (> 15/16)
However, it may still be profitable to eliminate range checks even if
the branch isn't as biased. Consider, for example, a loop with 100
iterations, where IRCE currently eliminates all 100 range checks. The
same range checks performed over a loop with 200 iterations aren't
eliminated because the branch is 50-50.
This patch proposes to relax the profitability checks of IRCE. Namely,
instead of the two checks currenly in place, consider IRCE profitable if
the branch probability scaled by the expected number of iterations
(i.e., the estimated number of eliminated checks) is over a threshold.
This covers the minimum number of iterations check (there are at least
as many iterations as eliminated range checks), and changes the bias
check from a percent of iterations to at least a constant threshold of
eliminated checks.
If the number of iterations can't be estimated, the check falls back to
the current 15/16 likelihood check.
Commit: bdd365825d0766b6991c8f5443f8a9f76e75011a
https://github.com/llvm/llvm-project/commit/bdd365825d0766b6991c8f5443f8a9f76e75011a
Author: Benoit Jacob <jacob.benoit.1 at gmail.com>
Date: 2024-12-12 (Thu, 12 Dec 2024)
Changed paths:
M mlir/lib/Conversion/ComplexToStandard/ComplexToStandard.cpp
M mlir/test/Conversion/ComplexToStandard/convert-to-standard.mlir
Log Message:
-----------
[MLIR] Fix `ComplexToStandard` lowering of `complex::MulOp` (#119591)
A complex multiplication should lower simply to the familiar 4 real
multiplications, 1 real addition, 1 real subtraction. No special-casing
of infinite or NaN values should be made, instead the complex numbers
should be thought as just vectors of two reals, naturally bottoming out
on the reals' semantics, IEEE754 or otherwise. That is what nearly
everybody else is doing ("nearly" because at the end of this PR
description we pinpoint the actual source of this in C99 `_Complex`),
and this pattern, by trying to do something different, was generating
much larger code, which was much slower and a departure from the
naturally expected floating-point behavior.
This code had originally been introduced in
https://reviews.llvm.org/D105270, which stated this rationale:
> The lowering handles special cases with NaN or infinity like C++.
I don't think that the C++ standard is a particularly important thing to
follow in this instance. What matters more is what people actually do in
practice with complex numbers, which rarely involves the C++
`std::complex` library type.
But out of curiosity, I checked, and the above statement seems
incorrect. The [current C++
standard](https://www.open-std.org/jtc1/sc22/wg21/docs/papers/2023/n4928.pdf)
library specification for `std::complex` does not say anything about the
implementation of complex multiplication: paragraph `[complex.ops]`
falls back on `[complex.member.ops]` which says:
> Effects: Multiplies the complex value rhs by the complex value *this
and stores the product in *this.
I also checked cppreference which often has useful information in case
something changed in a c++ language revision, but likewise, nothing at
all there:
https://en.cppreference.com/w/cpp/numeric/complex/operator_arith3
Finally, I checked in Compiler Explorer what Clang 19 currently
generates:
https://godbolt.org/z/oY7Ks4j95
That is just the familiar 4 multiplications.... and then there is some
weird check (`fcmp`) and conditionally a call to an external `__mulsc3`.
Googled that, found this StackOverflow answer:
https://stackoverflow.com/a/49438578
Summary: this is not about C++ (this post confirms my reading of the C++
standard not mandating anything about this). This is about C, and it
just happens that this C++ standard library implementation bottoms out
on code shared with the C `_Complex` implementation.
Another nuance missing in that SO answer: this is actually
[implementation-defined
behavior](https://en.cppreference.com/w/c/preprocessor/impl). There are
two modes, controlled by
```c
#pragma STDC CX_LIMITED_RANGE {ON,OFF,DEFAULT}
```
It is implementation-defined which is the default. Clang defaults to
OFF, but that's just Clang. In that mode, the check is required:
https://en.cppreference.com/w/c/language/arithmetic_types#Complex_floating_types
And the specific point in the [C99
standard](https://www.open-std.org/jtc1/sc22/wg14/www/docs/n1256.pdf)
is: `G.5.1 Multiplicative operators`.
But set it to ON and the check is gone:
https://godbolt.org/z/aG8fnbYoP
Summary: the argument has moved from C++ to C --- and even there, to
implementation-defined behavior with a standard opt-out mechanism.
Like with C++, I maintain that the C standard is not a particularly
meaningful thing for MLIR to follow here, because people doing business
with complex numbers tend to lower them to real numbers themselves, or
have their own specialized complex types, either way not relying on
C99's `_Complex` type --- and the very poor performance of the
`CX_LIMITED_RANGE OFF` behavior (default in Clang) is certainly a key
reason why people who care prefer to stay away from `_Complex` and
`std::complex`.
A good example that's relevant to MLIR's space is CUDA's `cuComplex`
type (used in the cuBLAS CGEMM interface). Here is its multiplication
function. The comment about competitiveness is interesting: it's not a
quirk of this particular function, it's the spirit underpinning
numerical code that matters.
https://github.com/tpn/cuda-samples/blob/1bf5cd15c51ce80fc9b387c0ff89a9f535b42bf5/v8.0/include/cuComplex.h#L106-L120
```c
/* This implementation could suffer from intermediate overflow even though
* the final result would be in range. However, various implementations do
* not guard against this (presumably to avoid losing performance), so we
* don't do it either to stay competitive.
*/
__host__ __device__ static __inline__ cuFloatComplex cuCmulf (cuFloatComplex x,
cuFloatComplex y)
{
cuFloatComplex prod;
prod = make_cuFloatComplex ((cuCrealf(x) * cuCrealf(y)) -
(cuCimagf(x) * cuCimagf(y)),
(cuCrealf(x) * cuCimagf(y)) +
(cuCimagf(x) * cuCrealf(y)));
return prod;
}
```
Another instance in CUTLASS:
https://github.com/NVIDIA/cutlass/blob/main/include/cutlass/complex.h#L231-L236
Signed-off-by: Benoit Jacob <jacob.benoit.1 at gmail.com>
Commit: c95af0844d64f15b99fab37c25efb01a8d783847
https://github.com/llvm/llvm-project/commit/c95af0844d64f15b99fab37c25efb01a8d783847
Author: Florian Hahn <flo at fhahn.com>
Date: 2024-12-12 (Thu, 12 Dec 2024)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlan.cpp
Log Message:
-----------
[VPlan] Move ::getVectorLoopRegion out of ifdef (NFC).
Fixes a build failure with assertions disabled after
6c8f41d336747.
Commit: 8eec301fe3ac5fdcb4de4757806661b99c9e6580
https://github.com/llvm/llvm-project/commit/8eec301fe3ac5fdcb4de4757806661b99c9e6580
Author: erichkeane <ekeane at nvidia.com>
Date: 2024-12-12 (Thu, 12 Dec 2024)
Changed paths:
M clang/lib/Sema/SemaOpenACC.cpp
M clang/test/AST/ast-print-openacc-data-construct.cpp
A clang/test/SemaOpenACC/data-construct-device_type-ast.cpp
A clang/test/SemaOpenACC/data-construct-device_type-clause.c
M clang/test/SemaOpenACC/data-construct.cpp
Log Message:
-----------
[OpenACC] Implement 'device_type' for 'data' construct
Semantically this is identical to all other constructs with this tag,
except in this case the 'wait' and 'async' are the only ones allowed
after it. This patch implements that rule using the existing
infrastructure.
Commit: 4a5f82b43be7328d7b7b4cd9912487fd3f284b49
https://github.com/llvm/llvm-project/commit/4a5f82b43be7328d7b7b4cd9912487fd3f284b49
Author: Aleksei Vetrov <vetaleha at gmail.com>
Date: 2024-12-12 (Thu, 12 Dec 2024)
Changed paths:
M llvm/lib/MC/MCParser/AsmParser.cpp
A llvm/test/MC/ELF/debug-hash-file-empty-dwarf.s
M llvm/test/MC/ELF/debug-hash-file.s
Log Message:
-----------
[MC] Fix DWARF file table for files with empty DWARF (#119572)
Update root file in DWARF file/line table as soon as we see the first
"#line" directive.
This was moved from "enabledGenDwarfForAssembly", which is called right
before we emit DWARF information. But if the file is empty or contains
expressions that doesn't need DWARF, it is never called, leaving an
original root file and not the file in the "#line" directive.
Add a test checking for this case.
This is reapply of #119229 with the following fix:
"MCContext::setMCLineTableRootFile" has the effect of adding
".debug_line" section to the output, even if DWARF generation is
disabled. Add a check and a test for this case.
Fixes: #119020
Fixes: #119229
Commit: 6edd867e43cb5eb3bb84561c0490e5ebb9d06d90
https://github.com/llvm/llvm-project/commit/6edd867e43cb5eb3bb84561c0490e5ebb9d06d90
Author: Abhina Sreeskantharajan <Abhina.Sreeskantharajan at ibm.com>
Date: 2024-12-12 (Thu, 12 Dec 2024)
Changed paths:
M clang/lib/Basic/SourceManager.cpp
Log Message:
-----------
[SystemZ][z/OS] Replace assert with updated return statement to check if a file size will grow due to conversion
Commit: 4cce10743d2275710d3d2e0de8013386a9799092
https://github.com/llvm/llvm-project/commit/4cce10743d2275710d3d2e0de8013386a9799092
Author: knickish <knickish at gmail.com>
Date: 2024-12-12 (Thu, 12 Dec 2024)
Changed paths:
M llvm/lib/Target/M68k/Disassembler/M68kDisassembler.cpp
M llvm/lib/Target/M68k/M68kISelDAGToDAG.cpp
M llvm/lib/Target/M68k/M68kInstrAtomics.td
M llvm/test/CodeGen/M68k/Atomics/load-store.ll
M llvm/test/CodeGen/M68k/Atomics/rmw.ll
A llvm/test/CodeGen/M68k/CodeModel/Large/Atomics/cmpxchg.ll
A llvm/test/CodeGen/M68k/CodeModel/Large/Atomics/fence.ll
A llvm/test/CodeGen/M68k/CodeModel/Large/Atomics/load-store.ll
A llvm/test/CodeGen/M68k/CodeModel/Large/Atomics/rmw.ll
A llvm/test/CodeGen/M68k/CodeModel/Large/large-pic.ll
A llvm/test/CodeGen/M68k/CodeModel/Large/large-pie-global-access.ll
A llvm/test/CodeGen/M68k/CodeModel/Large/large-pie.ll
A llvm/test/CodeGen/M68k/CodeModel/Large/large-static.ll
A llvm/test/CodeGen/M68k/CodeModel/Medium/medium-pic.ll
A llvm/test/CodeGen/M68k/CodeModel/Medium/medium-pie-global-access.ll
A llvm/test/CodeGen/M68k/CodeModel/Medium/medium-pie.ll
A llvm/test/CodeGen/M68k/CodeModel/Medium/medium-static.ll
A llvm/test/CodeGen/M68k/CodeModel/Small/small-pic.ll
A llvm/test/CodeGen/M68k/CodeModel/Small/small-pie-global-access.ll
A llvm/test/CodeGen/M68k/CodeModel/Small/small-pie.ll
A llvm/test/CodeGen/M68k/CodeModel/Small/small-static.ll
R llvm/test/CodeGen/M68k/CodeModel/large-pic.ll
R llvm/test/CodeGen/M68k/CodeModel/large-pie-global-access.ll
R llvm/test/CodeGen/M68k/CodeModel/large-pie.ll
R llvm/test/CodeGen/M68k/CodeModel/large-static.ll
R llvm/test/CodeGen/M68k/CodeModel/medium-pic.ll
R llvm/test/CodeGen/M68k/CodeModel/medium-pie-global-access.ll
R llvm/test/CodeGen/M68k/CodeModel/medium-pie.ll
R llvm/test/CodeGen/M68k/CodeModel/medium-static.ll
R llvm/test/CodeGen/M68k/CodeModel/small-pic.ll
R llvm/test/CodeGen/M68k/CodeModel/small-pie-global-access.ll
R llvm/test/CodeGen/M68k/CodeModel/small-pie.ll
R llvm/test/CodeGen/M68k/CodeModel/small-static.ll
A llvm/test/CodeGen/M68k/TLS/tls-arid.ll
M llvm/test/MC/M68k/Atomics/cas.s
Log Message:
-----------
[M68k] Add remaining addressing modes for Atomic operations (#115523)
Had been doing this piece by piece, but makes more sense to do it in a
single PR. Adds support for `ARID`, `PCI`, `PCD`, `AL`, and `ARD`
addressing modes for atomic operations, along with a variety of tests.
The `CodeModel` tests have been rearranged, as some of the new
addressing modes are only exercised under some combinations of
`CodeModel` and relocation mode
Commit: e17d2b585b4d35b9cab0673cf77a35fa933dd030
https://github.com/llvm/llvm-project/commit/e17d2b585b4d35b9cab0673cf77a35fa933dd030
Author: Nick Desaulniers <nickdesaulniers at users.noreply.github.com>
Date: 2024-12-12 (Thu, 12 Dec 2024)
Changed paths:
A libc/docs/headers/arpa/inet.rst
M libc/docs/headers/index.rst
A libc/docs/headers/sys/mman.rst
A libc/utils/docgen/arpa/inet.json
M libc/utils/docgen/docgen.py
M libc/utils/docgen/header.py
A libc/utils/docgen/sys/mman.json
Log Message:
-----------
[libc][docgen] support non-top-level headers (#119621)
such as arpa/inet, sys/*
Commit: 61510b51c33464a6bc15e4cf5b1ee07e2e0ec1c9
https://github.com/llvm/llvm-project/commit/61510b51c33464a6bc15e4cf5b1ee07e2e0ec1c9
Author: Sander de Smalen <sander.desmalen at arm.com>
Date: 2024-12-12 (Thu, 12 Dec 2024)
Changed paths:
M llvm/lib/Target/AArch64/AArch64Subtarget.cpp
M llvm/test/CodeGen/AArch64/Atomics/aarch64-atomicrmw-lse2_lse128.ll
M llvm/test/CodeGen/AArch64/Atomics/aarch64-atomicrmw-v8_1a.ll
M llvm/test/CodeGen/AArch64/Atomics/aarch64_be-atomicrmw-lse2_lse128.ll
M llvm/test/CodeGen/AArch64/Atomics/aarch64_be-atomicrmw-v8_1a.ll
M llvm/test/CodeGen/AArch64/GlobalISel/arm64-atomic-128.ll
M llvm/test/CodeGen/AArch64/GlobalISel/arm64-atomic.ll
M llvm/test/CodeGen/AArch64/GlobalISel/arm64-pcsections.ll
M llvm/test/CodeGen/AArch64/GlobalISel/combine-udiv.ll
M llvm/test/CodeGen/AArch64/GlobalISel/insert-vector-elt-pr63826.ll
M llvm/test/CodeGen/AArch64/aarch64-addv.ll
M llvm/test/CodeGen/AArch64/aarch64-be-bv.ll
M llvm/test/CodeGen/AArch64/aarch64-bf16-dotprod-intrinsics.ll
M llvm/test/CodeGen/AArch64/aarch64-bif-gen.ll
M llvm/test/CodeGen/AArch64/aarch64-bit-gen.ll
M llvm/test/CodeGen/AArch64/aarch64-combine-add-sub-mul.ll
M llvm/test/CodeGen/AArch64/aarch64-combine-add-zext.ll
M llvm/test/CodeGen/AArch64/aarch64-dup-ext-scalable.ll
M llvm/test/CodeGen/AArch64/aarch64-dup-ext.ll
M llvm/test/CodeGen/AArch64/aarch64-dup-extract-scalable.ll
M llvm/test/CodeGen/AArch64/aarch64-fold-lslfast.ll
M llvm/test/CodeGen/AArch64/aarch64-interleaved-access-w-undef.ll
M llvm/test/CodeGen/AArch64/aarch64-load-ext.ll
M llvm/test/CodeGen/AArch64/aarch64-matrix-umull-smull.ll
M llvm/test/CodeGen/AArch64/aarch64-minmaxv.ll
M llvm/test/CodeGen/AArch64/aarch64-mops-mte.ll
M llvm/test/CodeGen/AArch64/aarch64-mops.ll
M llvm/test/CodeGen/AArch64/aarch64-mull-masks.ll
M llvm/test/CodeGen/AArch64/aarch64-mulv.ll
M llvm/test/CodeGen/AArch64/aarch64-neon-vector-insert-uaddlv.ll
M llvm/test/CodeGen/AArch64/aarch64-scalarize-vec-load-ext.ll
M llvm/test/CodeGen/AArch64/aarch64-sysreg128.ll
M llvm/test/CodeGen/AArch64/aarch64-wide-shuffle.ll
M llvm/test/CodeGen/AArch64/abs.ll
M llvm/test/CodeGen/AArch64/active_lane_mask.ll
M llvm/test/CodeGen/AArch64/adc.ll
M llvm/test/CodeGen/AArch64/add-extract.ll
M llvm/test/CodeGen/AArch64/add.ll
M llvm/test/CodeGen/AArch64/addimm-mulimm.ll
M llvm/test/CodeGen/AArch64/addp-shuffle.ll
M llvm/test/CodeGen/AArch64/addsub_ext.ll
M llvm/test/CodeGen/AArch64/and-mask-removal.ll
M llvm/test/CodeGen/AArch64/andorxor.ll
M llvm/test/CodeGen/AArch64/arm64-abi-varargs.ll
M llvm/test/CodeGen/AArch64/arm64-addp.ll
M llvm/test/CodeGen/AArch64/arm64-addr-type-promotion.ll
M llvm/test/CodeGen/AArch64/arm64-atomic-128.ll
M llvm/test/CodeGen/AArch64/arm64-bitfield-extract.ll
M llvm/test/CodeGen/AArch64/arm64-build-vector.ll
M llvm/test/CodeGen/AArch64/arm64-collect-loh.ll
M llvm/test/CodeGen/AArch64/arm64-dup.ll
M llvm/test/CodeGen/AArch64/arm64-ext.ll
M llvm/test/CodeGen/AArch64/arm64-extract-insert-varidx.ll
M llvm/test/CodeGen/AArch64/arm64-extract_subvector.ll
M llvm/test/CodeGen/AArch64/arm64-fcopysign.ll
M llvm/test/CodeGen/AArch64/arm64-fixed-point-scalar-cvt-dagcombine.ll
M llvm/test/CodeGen/AArch64/arm64-fmax.ll
M llvm/test/CodeGen/AArch64/arm64-fp128.ll
M llvm/test/CodeGen/AArch64/arm64-indexed-vector-ldst.ll
M llvm/test/CodeGen/AArch64/arm64-instruction-mix-remarks.ll
M llvm/test/CodeGen/AArch64/arm64-ld1.ll
M llvm/test/CodeGen/AArch64/arm64-ldxr-stxr.ll
M llvm/test/CodeGen/AArch64/arm64-mul.ll
M llvm/test/CodeGen/AArch64/arm64-neon-2velem-high.ll
M llvm/test/CodeGen/AArch64/arm64-neon-2velem.ll
M llvm/test/CodeGen/AArch64/arm64-neon-3vdiff.ll
M llvm/test/CodeGen/AArch64/arm64-neon-add-pairwise.ll
M llvm/test/CodeGen/AArch64/arm64-neon-copy.ll
M llvm/test/CodeGen/AArch64/arm64-neon-copyPhysReg-tuple.ll
M llvm/test/CodeGen/AArch64/arm64-neon-mul-div.ll
M llvm/test/CodeGen/AArch64/arm64-neon-scalar-by-elem-mul.ll
M llvm/test/CodeGen/AArch64/arm64-neon-select_cc.ll
M llvm/test/CodeGen/AArch64/arm64-neon-simd-ldst-one.ll
M llvm/test/CodeGen/AArch64/arm64-neon-simd-shift.ll
M llvm/test/CodeGen/AArch64/arm64-neon-simd-vget.ll
M llvm/test/CodeGen/AArch64/arm64-neon-v1i1-setcc.ll
M llvm/test/CodeGen/AArch64/arm64-neon-v8.1a.ll
M llvm/test/CodeGen/AArch64/arm64-nvcast.ll
M llvm/test/CodeGen/AArch64/arm64-popcnt.ll
M llvm/test/CodeGen/AArch64/arm64-rev.ll
M llvm/test/CodeGen/AArch64/arm64-shifted-sext.ll
M llvm/test/CodeGen/AArch64/arm64-shrink-wrapping.ll
M llvm/test/CodeGen/AArch64/arm64-stp.ll
M llvm/test/CodeGen/AArch64/arm64-subvector-extend.ll
M llvm/test/CodeGen/AArch64/arm64-tbl.ll
M llvm/test/CodeGen/AArch64/arm64-vadd.ll
M llvm/test/CodeGen/AArch64/arm64-vaddv.ll
M llvm/test/CodeGen/AArch64/arm64-vcvt_f.ll
M llvm/test/CodeGen/AArch64/arm64-vector-insertion.ll
M llvm/test/CodeGen/AArch64/arm64-vmul.ll
M llvm/test/CodeGen/AArch64/arm64-zip.ll
M llvm/test/CodeGen/AArch64/arm64_32-addrs.ll
M llvm/test/CodeGen/AArch64/arm64ec-entry-thunks.ll
M llvm/test/CodeGen/AArch64/arm64ec-exit-thunks.ll
M llvm/test/CodeGen/AArch64/atomic-ops-lse.ll
M llvm/test/CodeGen/AArch64/atomic-ops-msvc.ll
M llvm/test/CodeGen/AArch64/atomic-ops.ll
M llvm/test/CodeGen/AArch64/atomicrmw-fadd.ll
M llvm/test/CodeGen/AArch64/atomicrmw-fmax.ll
M llvm/test/CodeGen/AArch64/atomicrmw-fmin.ll
M llvm/test/CodeGen/AArch64/atomicrmw-fsub.ll
M llvm/test/CodeGen/AArch64/atomicrmw-xchg-fp.ll
M llvm/test/CodeGen/AArch64/bf16-instructions.ll
M llvm/test/CodeGen/AArch64/bf16-select.ll
M llvm/test/CodeGen/AArch64/bf16-shuffle.ll
M llvm/test/CodeGen/AArch64/bf16-v4-instructions.ll
M llvm/test/CodeGen/AArch64/bf16-v8-instructions.ll
M llvm/test/CodeGen/AArch64/bf16-vector-shuffle.ll
M llvm/test/CodeGen/AArch64/bitcast-promote-widen.ll
M llvm/test/CodeGen/AArch64/bitcast.ll
M llvm/test/CodeGen/AArch64/bitfield-insert.ll
M llvm/test/CodeGen/AArch64/bswap.ll
M llvm/test/CodeGen/AArch64/build-one-lane.ll
M llvm/test/CodeGen/AArch64/build-vector-extract.ll
M llvm/test/CodeGen/AArch64/build-vector-two-dup.ll
M llvm/test/CodeGen/AArch64/check-sign-bit-before-extension.ll
M llvm/test/CodeGen/AArch64/cmp-to-cmn.ll
M llvm/test/CodeGen/AArch64/cmpxchg-idioms.ll
M llvm/test/CodeGen/AArch64/combine-andintoload.ll
M llvm/test/CodeGen/AArch64/complex-deinterleaving-f16-add.ll
M llvm/test/CodeGen/AArch64/complex-deinterleaving-f16-mul.ll
M llvm/test/CodeGen/AArch64/complex-deinterleaving-multiuses.ll
M llvm/test/CodeGen/AArch64/complex-deinterleaving-reductions-predicated-scalable.ll
M llvm/test/CodeGen/AArch64/complex-deinterleaving-reductions-scalable.ll
M llvm/test/CodeGen/AArch64/complex-deinterleaving-splat-scalable.ll
M llvm/test/CodeGen/AArch64/complex-deinterleaving-splat.ll
M llvm/test/CodeGen/AArch64/complex-deinterleaving-uniform-cases.ll
M llvm/test/CodeGen/AArch64/concat-vector.ll
M llvm/test/CodeGen/AArch64/concatbinop.ll
M llvm/test/CodeGen/AArch64/cvt-fp-int-fp.ll
M llvm/test/CodeGen/AArch64/dag-numsignbits.ll
M llvm/test/CodeGen/AArch64/dup.ll
M llvm/test/CodeGen/AArch64/duplane-index-patfrags.ll
M llvm/test/CodeGen/AArch64/ext-narrow-index.ll
M llvm/test/CodeGen/AArch64/extbinopload.ll
M llvm/test/CodeGen/AArch64/extract-bits.ll
M llvm/test/CodeGen/AArch64/extract-insert.ll
M llvm/test/CodeGen/AArch64/extract-lowbits.ll
M llvm/test/CodeGen/AArch64/extract-sext-zext.ll
M llvm/test/CodeGen/AArch64/extract-subvec-combine.ll
M llvm/test/CodeGen/AArch64/extract-vector-cmp.ll
M llvm/test/CodeGen/AArch64/extract-vector-elt.ll
M llvm/test/CodeGen/AArch64/f16-instructions.ll
M llvm/test/CodeGen/AArch64/fabs-fp128.ll
M llvm/test/CodeGen/AArch64/fabs.ll
M llvm/test/CodeGen/AArch64/faddp-half.ll
M llvm/test/CodeGen/AArch64/faddp.ll
M llvm/test/CodeGen/AArch64/faddsub.ll
M llvm/test/CodeGen/AArch64/fast-isel-addressing-modes.ll
M llvm/test/CodeGen/AArch64/fast-isel-gep.ll
M llvm/test/CodeGen/AArch64/fast-isel-shift.ll
M llvm/test/CodeGen/AArch64/fcmp.ll
M llvm/test/CodeGen/AArch64/fcopysign-noneon.ll
M llvm/test/CodeGen/AArch64/fcopysign.ll
M llvm/test/CodeGen/AArch64/fcvt.ll
M llvm/test/CodeGen/AArch64/fcvt_combine.ll
M llvm/test/CodeGen/AArch64/fdiv-combine.ll
M llvm/test/CodeGen/AArch64/fdiv.ll
M llvm/test/CodeGen/AArch64/fexplog.ll
M llvm/test/CodeGen/AArch64/fixed-point-conv-vec-pat.ll
M llvm/test/CodeGen/AArch64/fixed-vector-deinterleave.ll
M llvm/test/CodeGen/AArch64/fixed-vector-interleave.ll
M llvm/test/CodeGen/AArch64/fmaximum-legalization.ll
M llvm/test/CodeGen/AArch64/fminimummaximum.ll
M llvm/test/CodeGen/AArch64/fminmax.ll
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M llvm/test/CodeGen/AArch64/fp8-sve-cvtn.ll
M llvm/test/CodeGen/AArch64/fpclamptosat_vec.ll
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M llvm/test/CodeGen/AArch64/implicit-def-subreg-to-reg-regression.ll
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M llvm/test/CodeGen/AArch64/insertshuffleload.ll
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M llvm/test/CodeGen/AArch64/intrinsic-vector-match-sve2.ll
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M llvm/test/CodeGen/AArch64/logic-shift.ll
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M llvm/test/CodeGen/AArch64/machine-combiner-copy.ll
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M llvm/test/CodeGen/AArch64/memset-inline.ll
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M llvm/test/CodeGen/AArch64/mla_mls_merge.ll
M llvm/test/CodeGen/AArch64/mul.ll
M llvm/test/CodeGen/AArch64/neon-bitcast.ll
M llvm/test/CodeGen/AArch64/neon-bitwise-instructions.ll
M llvm/test/CodeGen/AArch64/neon-dot-product.ll
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M llvm/test/CodeGen/AArch64/neon-insert-sve-elt.ll
M llvm/test/CodeGen/AArch64/neon-insextbitcast.ll
M llvm/test/CodeGen/AArch64/neon-luti.ll
M llvm/test/CodeGen/AArch64/neon-partial-reduce-dot-product.ll
M llvm/test/CodeGen/AArch64/neon-perm.ll
M llvm/test/CodeGen/AArch64/neon-reverseshuffle.ll
M llvm/test/CodeGen/AArch64/neon-rshrn.ll
M llvm/test/CodeGen/AArch64/neon-scalar-by-elem-fma.ll
M llvm/test/CodeGen/AArch64/neon-scalarize-histogram.ll
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M llvm/test/CodeGen/AArch64/neon-truncstore.ll
M llvm/test/CodeGen/AArch64/neon-vcmla.ll
M llvm/test/CodeGen/AArch64/neon-wide-splat.ll
M llvm/test/CodeGen/AArch64/neon-widen-shuffle.ll
M llvm/test/CodeGen/AArch64/nontemporal-load.ll
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M llvm/test/CodeGen/AArch64/phi.ll
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M llvm/test/CodeGen/AArch64/pow.ll
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M llvm/test/CodeGen/AArch64/rcpc3.ll
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M llvm/test/CodeGen/AArch64/reduce-xor.ll
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M llvm/test/CodeGen/AArch64/rem.ll
M llvm/test/CodeGen/AArch64/round-fptosi-sat-scalar.ll
M llvm/test/CodeGen/AArch64/select-constant-xor.ll
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M llvm/test/CodeGen/AArch64/setcc_knownbits.ll
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M llvm/test/CodeGen/AArch64/shift-amount-mod.ll
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M llvm/test/CodeGen/AArch64/shift_minsize.ll
M llvm/test/CodeGen/AArch64/shuffle-tbl34.ll
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M llvm/test/CodeGen/AArch64/sink-and-fold.ll
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M llvm/test/CodeGen/AArch64/sme-avoid-coalescing-locally-streaming.ll
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M llvm/test/CodeGen/AArch64/sme-intrinsics-stores.ll
M llvm/test/CodeGen/AArch64/sme-pstate-sm-changing-call-disable-coalescing.ll
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M llvm/test/CodeGen/AArch64/sme2-fp8-intrinsics-cvt.ll
M llvm/test/CodeGen/AArch64/sme2-intrinsics-add-sub-za16.ll
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M llvm/test/CodeGen/AArch64/sme2-intrinsics-cvtn.ll
M llvm/test/CodeGen/AArch64/sme2-intrinsics-faminmax.ll
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M llvm/test/CodeGen/AArch64/sme2-intrinsics-select-sme-tileslice.ll
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M llvm/test/CodeGen/AArch64/smul_fix_sat.ll
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M llvm/test/CodeGen/AArch64/split-vector-insert.ll
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M llvm/test/CodeGen/AArch64/sve-doublereduct.ll
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M llvm/test/CodeGen/AArch64/sve-extract-fixed-from-scalable-vector.ll
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M llvm/test/CodeGen/AArch64/sve-vector-compress.ll
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M llvm/test/CodeGen/AArch64/vecreduce-add-legalization.ll
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M llvm/test/CodeGen/AArch64/vecreduce-and-legalization.ll
M llvm/test/CodeGen/AArch64/vecreduce-bool.ll
M llvm/test/CodeGen/AArch64/vecreduce-fadd-legalization-strict.ll
M llvm/test/CodeGen/AArch64/vecreduce-fadd-legalization.ll
M llvm/test/CodeGen/AArch64/vecreduce-fadd-strict.ll
M llvm/test/CodeGen/AArch64/vecreduce-fadd.ll
M llvm/test/CodeGen/AArch64/vecreduce-fmax-legalization-nan.ll
M llvm/test/CodeGen/AArch64/vecreduce-fmax-legalization.ll
M llvm/test/CodeGen/AArch64/vecreduce-fmaximum.ll
M llvm/test/CodeGen/AArch64/vecreduce-fmin-legalization.ll
M llvm/test/CodeGen/AArch64/vecreduce-fminimum.ll
M llvm/test/CodeGen/AArch64/vecreduce-fmul-legalization-strict.ll
M llvm/test/CodeGen/AArch64/vecreduce-fmul-strict.ll
M llvm/test/CodeGen/AArch64/vecreduce-fmul.ll
M llvm/test/CodeGen/AArch64/vecreduce-umax-legalization.ll
M llvm/test/CodeGen/AArch64/vector-compress.ll
M llvm/test/CodeGen/AArch64/vector-fcopysign.ll
M llvm/test/CodeGen/AArch64/vector-fcvt.ll
M llvm/test/CodeGen/AArch64/vector-llrint.ll
M llvm/test/CodeGen/AArch64/vector-lrint.ll
M llvm/test/CodeGen/AArch64/vldn_shuffle.ll
M llvm/test/CodeGen/AArch64/win64-fpowi.ll
M llvm/test/CodeGen/AArch64/win64_vararg.ll
M llvm/test/CodeGen/AArch64/xtn.ll
M llvm/test/CodeGen/AArch64/zext.ll
Log Message:
-----------
Revert "[AArch64] Enable subreg liveness tracking by default."
This reverts commit 9c319d5bb40785c969d2af76535ca62448dfafa7.
Some issues were discovered with the bootstrap builds, which
seem like they were caused by this commit. I'm reverting to investigate.
Commit: 3f136f7dfb41542c76c1b352544009bffbc399d2
https://github.com/llvm/llvm-project/commit/3f136f7dfb41542c76c1b352544009bffbc399d2
Author: Nirvedh Meshram <96096277+nirvedhmeshram at users.noreply.github.com>
Date: 2024-12-12 (Thu, 12 Dec 2024)
Changed paths:
M mlir/lib/Dialect/Tensor/IR/TensorTilingInterfaceImpl.cpp
Log Message:
-----------
[Tensor] Simplify tenor.pad tiling length calculations. (#119039)
The current calculations calculate ending location of the new length and
then subtract the new offset from that location. It is possible to
directly calculate new length. Along with requiring less operations
(which can matter in dynamic case) this also has the advantage that the
values are upper bounded by length rather than source size which is more
friendly for range analysis. I believe the change is already being
tested by
`test/Dialect/Linalg/subtensor-of-padtensor.mlir` and
`test/Dialect/Linalg/tile-and-fuse-tensors.mlir`
---------
Signed-off-by: Nirvedh <nirvedh at gmail.com>
Commit: d99c9994db5e051dc4b71c7bce6e56f8c9c72c1a
https://github.com/llvm/llvm-project/commit/d99c9994db5e051dc4b71c7bce6e56f8c9c72c1a
Author: Michael Maitland <michaeltmaitland at gmail.com>
Date: 2024-12-12 (Thu, 12 Dec 2024)
Changed paths:
M llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp
M llvm/test/CodeGen/RISCV/rvv/vl-opt-instrs.ll
M llvm/test/CodeGen/RISCV/rvv/vl-opt-op-info.mir
Log Message:
-----------
[RISCV][VLOPT] Add support for mask-register logical instructions and set mask instructions (#112231)
We need to adjust getEMULEqualsEEWDivSEWTimesLMUL to account for the
fact that Log2EEW for mask instructions is 0 but their EMUL is
calculated using Log2EEW=3.
Commit: 2e9bfcadbc25e8056ea8f7011786a835c3307a1b
https://github.com/llvm/llvm-project/commit/2e9bfcadbc25e8056ea8f7011786a835c3307a1b
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-12-12 (Thu, 12 Dec 2024)
Changed paths:
M llvm/lib/Target/RISCV/RISCVGISel.td
Log Message:
-----------
[RISCV] Remove unused SDNodeXForm from RISCVGISel.td. NFC
Leftover from when we tried to make i32 legal.
Commit: 77400103da63118e433cbee1feb20146a9fb782c
https://github.com/llvm/llvm-project/commit/77400103da63118e433cbee1feb20146a9fb782c
Author: Nirvedh Meshram <96096277+nirvedhmeshram at users.noreply.github.com>
Date: 2024-12-12 (Thu, 12 Dec 2024)
Changed paths:
M mlir/lib/Dialect/Tensor/IR/TensorTilingInterfaceImpl.cpp
Log Message:
-----------
NfC fix comment in #119039 (#119727)
Missed commiting clang-fomrat in
[#19903](https://github.com/llvm/llvm-project/pull/119039)
Commit: f7e868fe432da733f30379c01076f5f4c9792501
https://github.com/llvm/llvm-project/commit/f7e868fe432da733f30379c01076f5f4c9792501
Author: Ryosuke Niwa <rniwa at webkit.org>
Date: 2024-12-12 (Thu, 12 Dec 2024)
Changed paths:
M clang/lib/StaticAnalyzer/Checkers/WebKit/ASTUtils.cpp
M clang/test/Analysis/Checkers/WebKit/call-args.cpp
Log Message:
-----------
Fix a bug that CXXConstructExpr wasn't recognized by tryToFindPtrOrigin (#119336)
Prior to this PR, only CXXTemporaryObjectExpr, not CXXConstructExpr was
recognized in tryToFindPtrOrigin.
Commit: 9b14ded131aaff617568f1344a7164ba5520d341
https://github.com/llvm/llvm-project/commit/9b14ded131aaff617568f1344a7164ba5520d341
Author: Kazu Hirata <kazu at google.com>
Date: 2024-12-12 (Thu, 12 Dec 2024)
Changed paths:
M llvm/unittests/ProfileData/MemProfTest.cpp
Log Message:
-----------
[memprof] Use return values from addFrame and addCallStack (NFC) (#119676)
Migrating away from Frame::hash and hashCallStack further encapsulates
how the IDs are calculated.
Note that unit tests are the only places where Frame::hash and
hashCallStack are used. The code proper (i.e. llvm/lib) uses
IndexedMemProfData::{addFrame,addCallStack}; they do not directly use
Frame::hash or hashCallStack.
Commit: 357d00d7c7c81768047e9e9668c6f507c6c24cb3
https://github.com/llvm/llvm-project/commit/357d00d7c7c81768047e9e9668c6f507c6c24cb3
Author: Paul Kirth <paulkirth at google.com>
Date: 2024-12-12 (Thu, 12 Dec 2024)
Changed paths:
M clang/lib/Driver/ToolChains/Clang.cpp
M clang/test/Driver/stack-clash-protection.c
Log Message:
-----------
[clang][Driver] Allow `-fstack-clash-protection` for Fuchsia targets (#119633)
Fuchsia uses guard pages for the stack, similar to Linux
and other targets, which are required for stack-clash-protection.
This patch adds Fuchsia to the list of allowed targets.
Commit: 2db2dc8ab917de54a085776b874e93f4fdfd2e8c
https://github.com/llvm/llvm-project/commit/2db2dc8ab917de54a085776b874e93f4fdfd2e8c
Author: Tim Gymnich <tim at gymni.ch>
Date: 2024-12-12 (Thu, 12 Dec 2024)
Changed paths:
M llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
M llvm/lib/CodeGen/GlobalISel/Utils.cpp
M llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
Log Message:
-----------
[GlobalISel][NFC] Fix LLT Propagation (#119587)
Retain LLT type information by creating new LLTs from the original LLT
instead of only using the original scalar size.
This PR prepares for the [LLT FPInfo
RFC](https://discourse.llvm.org/t/rfc-globalisel-adding-fp-type-information-to-llt/83349/24)
where LLTs will carry additional floating point type information in
addition to the scalar size.
Commit: 52db903888eace2e4053a751c8f058ac7c98b49d
https://github.com/llvm/llvm-project/commit/52db903888eace2e4053a751c8f058ac7c98b49d
Author: Nick Desaulniers <ndesaulniers at google.com>
Date: 2024-12-12 (Thu, 12 Dec 2024)
Changed paths:
M libc/utils/docgen/docgen.py
Log Message:
-----------
[libc][docs] fix typo
Fixes: #119621
Commit: 7ece560a50d09686bb384b309b8b05d8f63111e5
https://github.com/llvm/llvm-project/commit/7ece560a50d09686bb384b309b8b05d8f63111e5
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-12-12 (Thu, 12 Dec 2024)
Changed paths:
M llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
M llvm/test/CodeGen/AArch64/Atomics/aarch64-atomicrmw-lse2.ll
M llvm/test/CodeGen/AArch64/Atomics/aarch64-atomicrmw-lse2_lse128.ll
M llvm/test/CodeGen/AArch64/Atomics/aarch64-atomicrmw-outline_atomics.ll
M llvm/test/CodeGen/AArch64/Atomics/aarch64-atomicrmw-rcpc.ll
M llvm/test/CodeGen/AArch64/Atomics/aarch64-atomicrmw-rcpc3.ll
M llvm/test/CodeGen/AArch64/Atomics/aarch64-atomicrmw-v8_1a.ll
M llvm/test/CodeGen/AArch64/Atomics/aarch64-atomicrmw-v8a.ll
M llvm/test/CodeGen/AArch64/GlobalISel/legalize-cmp.mir
M llvm/test/CodeGen/AArch64/GlobalISel/legalize-threeway-cmp.mir
M llvm/test/CodeGen/AArch64/aarch64-minmaxv.ll
M llvm/test/CodeGen/AArch64/icmp.ll
M llvm/test/CodeGen/AArch64/scmp.ll
M llvm/test/CodeGen/AArch64/ucmp.ll
M llvm/test/CodeGen/AArch64/vecreduce-umax-legalization.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/saddsat.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/ssubsat.ll
M llvm/test/CodeGen/AMDGPU/div_i128.ll
M llvm/test/CodeGen/Mips/GlobalISel/legalizer/icmp.mir
M llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/icmp.ll
M llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-addo-subo-rv32.mir
M llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-icmp-rv32.mir
M llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-icmp-rv64.mir
M llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-sat-rv32.mir
M llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-smax-rv32.mir
M llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-smin-rv32.mir
M llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-umax-rv32.mir
M llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-umin-rv32.mir
M llvm/test/CodeGen/X86/isel-select-cmov.ll
Log Message:
-----------
[GISel] Support narrowing G_ICMP with more than 2 parts. (#119335)
This allows us to support i128 G_ICMP on RV32. I'm not sure how to test
the "left over" part of this as RISC-V always widens to a power of 2
before narrowing.
Commit: 85c91afb85be52399e0fc7f082dd1c99932dffaa
https://github.com/llvm/llvm-project/commit/85c91afb85be52399e0fc7f082dd1c99932dffaa
Author: Nirvedh <nirvedh at gmail.com>
Date: 2024-12-12 (Thu, 12 Dec 2024)
Changed paths:
M mlir/lib/Dialect/Tensor/IR/TensorTilingInterfaceImpl.cpp
Log Message:
-----------
[mlir][tensor] fix typo in pad tiling comment
Commit: 33927744db2a910fe1cdeecf9e074d488de2e787
https://github.com/llvm/llvm-project/commit/33927744db2a910fe1cdeecf9e074d488de2e787
Author: Nirvedh <nirvedh at gmail.com>
Date: 2024-12-12 (Thu, 12 Dec 2024)
Changed paths:
M mlir/lib/Dialect/Tensor/IR/TensorTilingInterfaceImpl.cpp
Log Message:
-----------
[mlir][tensor] fix typo in pad tiling comment
Commit: 6cfad635d5aaa01abb82edc386329d8ed25078e1
https://github.com/llvm/llvm-project/commit/6cfad635d5aaa01abb82edc386329d8ed25078e1
Author: erichkeane <ekeane at nvidia.com>
Date: 2024-12-12 (Thu, 12 Dec 2024)
Changed paths:
M clang/include/clang/Basic/OpenACCKinds.h
M clang/lib/Sema/SemaOpenACC.cpp
M clang/test/AST/ast-print-openacc-data-construct.cpp
M clang/test/SemaOpenACC/combined-construct-if-clause.c
M clang/test/SemaOpenACC/compute-construct-if-clause.c
A clang/test/SemaOpenACC/data-construct-if-ast.cpp
A clang/test/SemaOpenACC/data-construct-if-clause.c
M clang/test/SemaOpenACC/data-construct.cpp
Log Message:
-----------
[OpenACC] Implement 'if' clause sema for 'data' constructs
This is another one that has no additional sema work other than enabling
it, so this patch does just that.
Commit: 58f9c4fc0055821d88869aafd49e0424b1070a79
https://github.com/llvm/llvm-project/commit/58f9c4fc0055821d88869aafd49e0424b1070a79
Author: Krzysztof Parzyszek <Krzysztof.Parzyszek at amd.com>
Date: 2024-12-12 (Thu, 12 Dec 2024)
Changed paths:
M flang/include/flang/Parser/dump-parse-tree.h
M flang/include/flang/Parser/parse-tree.h
M flang/lib/Lower/OpenMP/Clauses.cpp
M flang/lib/Parser/openmp-parsers.cpp
M flang/lib/Parser/unparse.cpp
M flang/lib/Semantics/check-omp-structure.cpp
M flang/lib/Semantics/check-omp-structure.h
M flang/test/Parser/OpenMP/in-reduction-clause.f90
M flang/test/Parser/OpenMP/reduction-modifier.f90
A flang/test/Parser/OpenMP/task-reduction-clause.f90
M flang/test/Preprocessing/directive-contin-with-pp.F90
A flang/test/Semantics/OpenMP/in-reduction.f90
M flang/test/Semantics/OpenMP/symbol08.f90
A flang/test/Semantics/OpenMP/task-reduction.f90
M flang/test/Semantics/OpenMP/taskgroup01.f90
M llvm/include/llvm/Frontend/OpenMP/OMP.td
Log Message:
-----------
[flang][OpenMP] Semantic checks for IN_REDUCTION and TASK_REDUCTION (#118841)
Update parsing of these two clauses and add semantic checks for them.
Simplify some code in IsReductionAllowedForType and
CheckReductionOperator.
Commit: 03cbe42627c7a7940b47cc1a2cda0120bc9c6d5e
https://github.com/llvm/llvm-project/commit/03cbe42627c7a7940b47cc1a2cda0120bc9c6d5e
Author: Krzysztof Parzyszek <Krzysztof.Parzyszek at amd.com>
Date: 2024-12-12 (Thu, 12 Dec 2024)
Changed paths:
M flang/examples/FeatureList/FeatureList.cpp
M flang/include/flang/Parser/dump-parse-tree.h
M flang/include/flang/Parser/parse-tree-visitor.h
M flang/include/flang/Parser/parse-tree.h
M flang/include/flang/Semantics/openmp-modifiers.h
M flang/lib/Lower/OpenMP/Clauses.cpp
M flang/lib/Parser/openmp-parsers.cpp
M flang/lib/Parser/unparse.cpp
M flang/lib/Semantics/check-omp-structure.cpp
M flang/lib/Semantics/openmp-modifiers.cpp
M flang/lib/Semantics/resolve-directives.cpp
A flang/test/Parser/OpenMP/linear-clause.f90
M flang/test/Semantics/OpenMP/clause-validity01.f90
M flang/test/Semantics/OpenMP/linear-clause01.f90
A flang/test/Semantics/OpenMP/linear-clause02.f90
M flang/test/Semantics/OpenMP/linear-iter.f90
M llvm/include/llvm/Frontend/OpenMP/ClauseT.h
M llvm/unittests/Frontend/OpenMPDecompositionTest.cpp
Log Message:
-----------
[flang][OpenMP] Rework LINEAR clause (#119278)
The OmpLinearClause class was a variant of two classes, one for when the
linear modifier was present, and one for when it was absent. These two
classes did not follow the conventions for parse tree nodes, (i.e.
tuple/wrapper/union formats), which necessitated specialization of the
parse tree visitor.
The new form of OmpLinearClause is the standard tuple with a list of
modifiers and an object list. The specialization of parse tree visitor
for it has been removed.
Parsing and unparsing of the new form bears additional complexity due to
syntactical differences between OpenMP 5.2 and prior versions: in OpenMP
5.2 the argument list is post-modified, while in the prior versions, the
step modifier was a post-modifier while the linear modifier had an
unusual syntax of `modifier(list)`.
With this change the LINEAR clause is no different from any other
clauses in terms of its structure and use of modifiers. Modifier
validation and all other checks work the same as with other clauses.
Commit: 2546ae4ed09ff69274c184ae7e98f2aa72e7e7f7
https://github.com/llvm/llvm-project/commit/2546ae4ed09ff69274c184ae7e98f2aa72e7e7f7
Author: Han-Kuan Chen <hankuan.chen at sifive.com>
Date: 2024-12-13 (Fri, 13 Dec 2024)
Changed paths:
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
M llvm/test/Transforms/SLPVectorizer/RISCV/revec.ll
Log Message:
-----------
[SLP][REVEC] Fix the number of elements in the mask of a ShuffleVectorInst is not a power of 2. (#119689)
The following shufflevector should not be vectorized when
slp-vectorize-non-power-of-2 is enabled.
shufflevector <8 x float> %1, <8 x float> poison, <3 x i32> <i32 0, i32
1, i32 2>
shufflevector <8 x float> %1, <8 x float> poison, <3 x i32> <i32 4, i32
5, i32 6>
Commit: 139e69b7bcb05e6ff9db0f373d9180deb341a571
https://github.com/llvm/llvm-project/commit/139e69b7bcb05e6ff9db0f373d9180deb341a571
Author: Slava Zakharin <szakharin at nvidia.com>
Date: 2024-12-12 (Thu, 12 Dec 2024)
Changed paths:
M flang/include/flang/Optimizer/HLFIR/HLFIROps.td
M flang/lib/Optimizer/HLFIR/IR/HLFIROps.cpp
M flang/test/HLFIR/shapeof.fir
Log Message:
-----------
[flang] Simple folding for hlfir.shape_of. (#119649)
This folding makes sure there are no hlfir.shape_of users
of hlfir.elemental - this may enable more InlineElementals matches,
because it is looking for exactly two uses of an hlfir.elemental.
Commit: c047a5b3f6e2295dd74f1e8f17f1a023150b246c
https://github.com/llvm/llvm-project/commit/c047a5b3f6e2295dd74f1e8f17f1a023150b246c
Author: Nick Desaulniers <nickdesaulniers at users.noreply.github.com>
Date: 2024-12-12 (Thu, 12 Dec 2024)
Changed paths:
M libc/docs/headers/assert.rst
M libc/docs/headers/ctype.rst
M libc/docs/headers/errno.rst
M libc/docs/headers/fenv.rst
M libc/docs/headers/float.rst
M libc/docs/headers/inttypes.rst
M libc/docs/headers/locale.rst
M libc/docs/headers/signal.rst
M libc/docs/headers/stdlib.rst
M libc/docs/headers/string.rst
M libc/docs/headers/strings.rst
M libc/docs/headers/threads.rst
M libc/docs/headers/uchar.rst
M libc/docs/headers/wchar.rst
M libc/docs/headers/wctype.rst
M libc/utils/docgen/assert.json
M libc/utils/docgen/ctype.json
M libc/utils/docgen/docgen.py
M libc/utils/docgen/errno.json
M libc/utils/docgen/fenv.json
M libc/utils/docgen/float.json
M libc/utils/docgen/inttypes.json
M libc/utils/docgen/locale.json
M libc/utils/docgen/setjmp.json
M libc/utils/docgen/signal.json
M libc/utils/docgen/stdlib.json
M libc/utils/docgen/string.json
M libc/utils/docgen/strings.json
M libc/utils/docgen/threads.json
M libc/utils/docgen/uchar.json
Log Message:
-----------
[libc][docgen] simplify posix links (#119595)
Usually posix functions have individual doc pages, and each header has its own
list of required macro definitions. Use a simpler key of "in-latest-posix" to
signal that the URL convention can be followed.
Add support for a "removed-in-posix-2008" key which will link to the 2004 docs
for functions like bcmp, bcopy, bzero, index, and rindex from strings.h.
I don't want to add all of these links for pthreads.h, so automating this will
make documenting these go much faster.
Commit: f0f8434afac2d30ac143250377fb6433c68fc0a8
https://github.com/llvm/llvm-project/commit/f0f8434afac2d30ac143250377fb6433c68fc0a8
Author: erichkeane <ekeane at nvidia.com>
Date: 2024-12-12 (Thu, 12 Dec 2024)
Changed paths:
M clang/lib/Sema/SemaOpenACC.cpp
M clang/test/AST/ast-print-openacc-data-construct.cpp
M clang/test/ParserOpenACC/parse-clauses.c
A clang/test/SemaOpenACC/data-construct-async-ast.cpp
A clang/test/SemaOpenACC/data-construct-async-clause.c
M clang/test/SemaOpenACC/data-construct-device_type-clause.c
M clang/test/SemaOpenACC/data-construct.cpp
Log Message:
-----------
[OpenACC] Implement sema for 'async' on 'data' constructs
This also is a clause that doesn't have any special rules, so this patch
enables it and adds tests.
Commit: 4e2a9e50f6dd6760b12838517c7f85a0c9032921
https://github.com/llvm/llvm-project/commit/4e2a9e50f6dd6760b12838517c7f85a0c9032921
Author: Petr Hosek <phosek at google.com>
Date: 2024-12-12 (Thu, 12 Dec 2024)
Changed paths:
M libc/config/baremetal/aarch64/entrypoints.txt
M libc/config/baremetal/arm/entrypoints.txt
M libc/config/baremetal/riscv/entrypoints.txt
M libc/src/__support/CMakeLists.txt
A libc/src/__support/freelist_heap.cpp
M libc/src/stdlib/CMakeLists.txt
M libc/src/stdlib/baremetal/CMakeLists.txt
A libc/src/stdlib/baremetal/aligned_alloc.cpp
A libc/src/stdlib/baremetal/calloc.cpp
A libc/src/stdlib/baremetal/free.cpp
A libc/src/stdlib/baremetal/malloc.cpp
A libc/src/stdlib/baremetal/realloc.cpp
R libc/src/stdlib/freelist_malloc.cpp
M libc/test/src/__support/CMakeLists.txt
M libc/test/src/__support/freelist_heap_test.cpp
R libc/test/src/__support/freelist_malloc_test.cpp
Log Message:
-----------
[libc] Breakup freelist_malloc into separate files (#98784)
This better matches the structure we use for the rest of libc.
Commit: b03470b81485281d9f2bdce5e44cc2cac4220d97
https://github.com/llvm/llvm-project/commit/b03470b81485281d9f2bdce5e44cc2cac4220d97
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-12-12 (Thu, 12 Dec 2024)
Changed paths:
M llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
Log Message:
-----------
[RISCV] Use a switch instead of an if/else chain. NFC
Commit: 33b910cde3b305a49c98c6de88dbc22ced9dea61
https://github.com/llvm/llvm-project/commit/33b910cde3b305a49c98c6de88dbc22ced9dea61
Author: Haojian Wu <hokein.wu at gmail.com>
Date: 2024-12-12 (Thu, 12 Dec 2024)
Changed paths:
M clang/docs/ReleaseNotes.rst
M clang/lib/Sema/CheckExprLifetime.cpp
M clang/test/Sema/Inputs/lifetime-analysis.h
M clang/test/Sema/warn-lifetime-analysis-nocfg.cpp
Log Message:
-----------
[clang] Fix the post-filtering heuristic for GSLPointer. (#114044)
The lifetime analyzer processes GSL pointers:
- when encountering a constructor for a `gsl::pointer`, the analyzer
continues traversing the constructor argument, regardless of whether the
parameter has a `lifetimebound` annotation. This aims to catch cases
where a GSL pointer is constructed from a GSL owner, either directly
(e.g., `FooPointer(FooOwner)`) or through a chain of GSL pointers (e.g.,
`FooPointer(FooPointer(FooOwner))`);
- When a temporary object is reported in the callback, the analyzer has
heuristics to exclude non-owner types, aiming to avoid false positives
(like `FooPointer(FooPointer())`).
In the problematic case (discovered in
https://github.com/llvm/llvm-project/pull/112751#issuecomment-2441055471)
of `return foo.get();`:
- When the analyzer reports the local object `foo`, the `Path` is
`[GslPointerInit, Lifetimebound]`.
- The `Path` goes through
[`pathOnlyHandlesGslPointer`](https://github.com/llvm/llvm-project/blob/main/clang/lib/Sema/CheckExprLifetime.cpp#L1136)
and isn’t filtered out by the [[heuristics]](because `foo` is an owner
type), the analyzer treats it as the `FooPointer(FooOwner())` scenario,
thus triggering a diagnostic.
Filtering out base on the object 'foo' is wrong, because the GSLPointer
is constructed from the return result of the `foo.get()`. The patch
fixes this by teaching the heuristic to use the return result (only
`const GSLOwner&` is considered) of the lifetimebound annotated
function.
Commit: 4e828f8d741ff61317bb1e0b67f22e274632b07a
https://github.com/llvm/llvm-project/commit/4e828f8d741ff61317bb1e0b67f22e274632b07a
Author: Florian Hahn <flo at fhahn.com>
Date: 2024-12-12 (Thu, 12 Dec 2024)
Changed paths:
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
Log Message:
-----------
[VPlan] Perform DT expensive input DT verification earlier (NFC).
After 6c8f41d33674, DT adjustments for the skeleton are applied as VPBBs
are executed. Move input DT verification up before starting to execute
any VPBBs to avoid checking DT while the CFG and DT are in an incomplete
state.
This fixes a number of verification failures with expensive checks
enabled, including
https://lab.llvm.org/buildbot/#/builders/16/builds/10584
Commit: afcb7d4a2eab51977497e43ce6539d2b0ca01071
https://github.com/llvm/llvm-project/commit/afcb7d4a2eab51977497e43ce6539d2b0ca01071
Author: erichkeane <ekeane at nvidia.com>
Date: 2024-12-12 (Thu, 12 Dec 2024)
Changed paths:
M clang/lib/Sema/SemaOpenACC.cpp
M clang/test/AST/ast-print-openacc-data-construct.cpp
M clang/test/ParserOpenACC/parse-clauses.c
M clang/test/SemaOpenACC/data-construct-device_type-clause.c
A clang/test/SemaOpenACC/data-construct-wait-ast.cpp
A clang/test/SemaOpenACC/data-construct-wait-clause.c
M clang/test/SemaOpenACC/data-construct.cpp
Log Message:
-----------
[OpenACC] Implement 'wait' sema for data constructs
This is once again simply enabling this for 'data', 'enter data', and
'exit data' (and ensuring we error for 'host_data'). Implementation is
very simply to enable it rather than emit the not-implemented
diagnostic.
Commit: 463e93b95f0887145b51edb81b770eeb4463abc5
https://github.com/llvm/llvm-project/commit/463e93b95f0887145b51edb81b770eeb4463abc5
Author: choikwa <5455710+choikwa at users.noreply.github.com>
Date: 2024-12-12 (Thu, 12 Dec 2024)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPUCodeGenPrepare.cpp
M llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-idiv.ll
M llvm/test/CodeGen/AMDGPU/bypass-div.ll
M llvm/test/CodeGen/AMDGPU/udiv64.ll
M llvm/test/CodeGen/AMDGPU/urem64.ll
Log Message:
-----------
Reapply [AMDGPU] prevent shrinking udiv/urem if either operand exceeds signed max (#119325)
This reverts commit 254d206ee2a337cb38ba347c896f7c6a14c7f218.
+Added a fix in ExpandDivRem24 to disqualify if DivNumBits exceed 24.
Original commit & msg:
ce6e955ac374f2b86cbbb73b2f32174dffd85f25.
Handle signed and unsigned path differently in getDivNumBits. Using
computeKnownBits, this rejects shrinking unsigned div/rem if operands
exceed signed max since we know NumSignBits will be always 0.
Commit: 71418379574d2df5e435f67c4b8d7591bd2038e9
https://github.com/llvm/llvm-project/commit/71418379574d2df5e435f67c4b8d7591bd2038e9
Author: Valentin Clement (バレンタイン クレメン) <clementval at gmail.com>
Date: 2024-12-12 (Thu, 12 Dec 2024)
Changed paths:
M flang/lib/Semantics/resolve-names.cpp
M flang/test/Semantics/modfile55.cuf
Log Message:
-----------
[flang][cuda] Implicitly add DEVICE attribute in device/global functions (#119743)
Variables in global and device function/subroutine that have no CUDA
Fortran data attribute are implicitly DEVICE.
Commit: 186fac33d08b34be494caa58fe63972f69c6d6ab
https://github.com/llvm/llvm-project/commit/186fac33d08b34be494caa58fe63972f69c6d6ab
Author: jimingham <jingham at apple.com>
Date: 2024-12-12 (Thu, 12 Dec 2024)
Changed paths:
M lldb/include/lldb/Target/StackFrameList.h
M lldb/source/Target/StackFrameList.cpp
M lldb/source/Target/Thread.cpp
M lldb/test/API/api/multithreaded/TestMultithreaded.py
A lldb/test/API/api/multithreaded/deep_stack.cpp
A lldb/test/API/api/multithreaded/test_concurrent_unwind.cpp.template
Log Message:
-----------
Convert the StackFrameList mutex to a shared mutex. (#117252)
In fact, there's only one public API in StackFrameList that changes
the list explicitly. The rest only change the list if you happen to
ask for more frames than lldb has currently fetched and that
always adds frames "behind the user's back". So we were
much more prone to deadlocking than we needed to be.
This patch uses a shared_mutex instead, and when we have to add more
frames (in GetFramesUpTo) we switches to exclusive long enough to add
the frames, then goes back to shared.
Most of the work here was actually getting the stack frame list locking
to not
require a recursive mutex (shared mutexes aren't recursive).
I also added a test that has 5 threads progressively asking for more
frames simultaneously to make sure we get back valid frames and don't
deadlock.
Commit: 5048808859eece3aaa680aaecb4a89dfabe9627b
https://github.com/llvm/llvm-project/commit/5048808859eece3aaa680aaecb4a89dfabe9627b
Author: erichkeane <ekeane at nvidia.com>
Date: 2024-12-12 (Thu, 12 Dec 2024)
Changed paths:
M clang/lib/Sema/SemaOpenACC.cpp
M clang/test/AST/ast-print-openacc-data-construct.cpp
M clang/test/SemaOpenACC/combined-construct-default-ast.cpp
M clang/test/SemaOpenACC/combined-construct-default-clause.c
M clang/test/SemaOpenACC/compute-construct-default-clause.c
M clang/test/SemaOpenACC/data-construct-ast.cpp
A clang/test/SemaOpenACC/data-construct-default-ast.cpp
A clang/test/SemaOpenACC/data-construct-default-clause.c
M clang/test/SemaOpenACC/data-construct-if-ast.cpp
M clang/test/SemaOpenACC/data-construct-if-clause.c
M clang/test/SemaOpenACC/data-construct.cpp
Log Message:
-----------
[OpenACC] Implement 'default' Sema for 'data' clause
No additional rules here beyond enabling it, this patch just enables
'default' and adds tests.
Commit: 9b65b1ef25723fcbb61f1ca25a6abbe678bb1770
https://github.com/llvm/llvm-project/commit/9b65b1ef25723fcbb61f1ca25a6abbe678bb1770
Author: knickish <knickish at gmail.com>
Date: 2024-12-12 (Thu, 12 Dec 2024)
Changed paths:
M llvm/test/MC/Disassembler/M68k/control.txt
Log Message:
-----------
[M68k] update dissassmbly test to require atLeastM68020 for BSR32 (#119758)
Fixes test failure reported in #117371. `BSR32` was previously
(incorrectly) allowed for CPUs <M68020, this test was missed while
updating the rest to fit the new model
Commit: 88bcf7283b35b979ace0c6be32736b13f6b771ae
https://github.com/llvm/llvm-project/commit/88bcf7283b35b979ace0c6be32736b13f6b771ae
Author: Nick Desaulniers <nickdesaulniers at users.noreply.github.com>
Date: 2024-12-12 (Thu, 12 Dec 2024)
Changed paths:
R libc/utils/docgen/arpa/inet.json
A libc/utils/docgen/arpa/inet.yaml
R libc/utils/docgen/assert.json
A libc/utils/docgen/assert.yaml
R libc/utils/docgen/ctype.json
A libc/utils/docgen/ctype.yaml
M libc/utils/docgen/docgen.py
R libc/utils/docgen/errno.json
A libc/utils/docgen/errno.yaml
R libc/utils/docgen/fenv.json
A libc/utils/docgen/fenv.yaml
R libc/utils/docgen/float.json
A libc/utils/docgen/float.yaml
M libc/utils/docgen/header.py
R libc/utils/docgen/inttypes.json
A libc/utils/docgen/inttypes.yaml
R libc/utils/docgen/locale.json
A libc/utils/docgen/locale.yaml
R libc/utils/docgen/setjmp.json
A libc/utils/docgen/setjmp.yaml
R libc/utils/docgen/signal.json
A libc/utils/docgen/signal.yaml
R libc/utils/docgen/stdbit.json
A libc/utils/docgen/stdbit.yaml
R libc/utils/docgen/stdlib.json
A libc/utils/docgen/stdlib.yaml
R libc/utils/docgen/string.json
A libc/utils/docgen/string.yaml
R libc/utils/docgen/strings.json
R libc/utils/docgen/sys/mman.json
A libc/utils/docgen/sys/mman.yaml
R libc/utils/docgen/threads.json
A libc/utils/docgen/threads.yaml
R libc/utils/docgen/uchar.json
A libc/utils/docgen/uchar.yaml
R libc/utils/docgen/wchar.json
A libc/utils/docgen/wchar.yaml
R libc/utils/docgen/wctype.json
A libc/utils/docgen/wctype.yaml
Log Message:
-----------
[libc][docs] move docgen from json to yaml (#119744)
That way it can more easily be integrated into hdrgen.
Commit: 379cc44f56e6f220422ce85d2295833f849086e0
https://github.com/llvm/llvm-project/commit/379cc44f56e6f220422ce85d2295833f849086e0
Author: Petr Hosek <phosek at google.com>
Date: 2024-12-12 (Thu, 12 Dec 2024)
Changed paths:
M libc/config/baremetal/aarch64/entrypoints.txt
M libc/config/baremetal/arm/entrypoints.txt
M libc/config/baremetal/riscv/entrypoints.txt
M libc/src/__support/CMakeLists.txt
R libc/src/__support/freelist_heap.cpp
M libc/src/stdlib/CMakeLists.txt
M libc/src/stdlib/baremetal/CMakeLists.txt
R libc/src/stdlib/baremetal/aligned_alloc.cpp
R libc/src/stdlib/baremetal/calloc.cpp
R libc/src/stdlib/baremetal/free.cpp
R libc/src/stdlib/baremetal/malloc.cpp
R libc/src/stdlib/baremetal/realloc.cpp
A libc/src/stdlib/freelist_malloc.cpp
M libc/test/src/__support/CMakeLists.txt
M libc/test/src/__support/freelist_heap_test.cpp
A libc/test/src/__support/freelist_malloc_test.cpp
Log Message:
-----------
Revert "[libc] Breakup freelist_malloc into separate files" (#119749)
Reverts llvm/llvm-project#98784 which broke libc builders.
Commit: 7071cd3885d06bc1ac388db0188468d135b37dfa
https://github.com/llvm/llvm-project/commit/7071cd3885d06bc1ac388db0188468d135b37dfa
Author: Kirill Stoimenov <kstoimenov at google.com>
Date: 2024-12-12 (Thu, 12 Dec 2024)
Changed paths:
M llvm/lib/Transforms/Scalar/SROA.cpp
Log Message:
-----------
Revert "[Transforms] Silence a warning in SROA.cpp (NFC)"
This reverts commit 5b077506de26b1dfce1926895548b86f2106bed9.
Commit: e3676aa21f875c12d878726a1de1663ebf428cc2
https://github.com/llvm/llvm-project/commit/e3676aa21f875c12d878726a1de1663ebf428cc2
Author: Kirill Stoimenov <kstoimenov at google.com>
Date: 2024-12-12 (Thu, 12 Dec 2024)
Changed paths:
M llvm/include/llvm/Analysis/PtrUseVisitor.h
M llvm/include/llvm/Transforms/Utils/SSAUpdater.h
M llvm/lib/Transforms/Scalar/SROA.cpp
M llvm/lib/Transforms/Utils/SSAUpdater.cpp
M llvm/test/Transforms/SROA/non-capturing-call-readonly.ll
M llvm/test/Transforms/SROA/readonlynocapture.ll
Log Message:
-----------
Revert "[SROA] Optimize reloaded values in allocas that escape into readonly nocapture calls. (#116645)"
Causing buffer overflow:
SUMMARY: AddressSanitizer: heap-buffer-overflow llvm/lib/Transforms/Scalar/SROA.cpp:5552:35
This reverts commit 5e247d726d7a54cf0acc997bc17b50e7494e6fa3.
Commit: bd40421ad9ec5ecc164f8208caf3ba5657977e17
https://github.com/llvm/llvm-project/commit/bd40421ad9ec5ecc164f8208caf3ba5657977e17
Author: Joseph Huber <huberjn at outlook.com>
Date: 2024-12-12 (Thu, 12 Dec 2024)
Changed paths:
M libc/hdr/types/CMakeLists.txt
Log Message:
-----------
[libc] Stop installing `sys/types.h` when not requested (#119765)
Summary:
This is installed unconditionally because of the dependency in the
`hdr/` directory. Remove this so it's only used on the systems that need
it.
Commit: 05137cc50726c82b6cd7bdd51ab44b6db2176ce9
https://github.com/llvm/llvm-project/commit/05137cc50726c82b6cd7bdd51ab44b6db2176ce9
Author: Pedro Lobo <pedro.lobo at tecnico.ulisboa.pt>
Date: 2024-12-12 (Thu, 12 Dec 2024)
Changed paths:
M llvm/lib/AsmParser/LLParser.cpp
M llvm/test/Assembler/aggregate-constant-values.ll
M llvm/test/CodeGen/AMDGPU/amdgpu.private-memory.ll
Log Message:
-----------
[AsmParser] Convert empty arrays to `poison` (#119754)
Empty arrays can be converted to `poison` instead of `undef`.
Commit: 81dcbefba3901545d3aef79f7030d45e81e798be
https://github.com/llvm/llvm-project/commit/81dcbefba3901545d3aef79f7030d45e81e798be
Author: Louis Dionne <ldionne.2 at gmail.com>
Date: 2024-12-12 (Thu, 12 Dec 2024)
Changed paths:
A libcxx/test/configs/stdlib-libstdc++.cfg.in
A libcxx/test/configs/stdlib-native.cfg.in
Log Message:
-----------
[libc++] Add testing configurations for libstdc++ and a native stdlib (#98539)
This allows running the test suite against the native Standard Library
on most systems, and against libstdc++ installed at a custom location.
Of course, these configurations don't run 100% clean at the moment. In
particular, running against the native stdlib is almost guaranteed not
to work out-of-the-box, since the test suite generally contains tests
for things that have been implemented on tip-of-trunk but not released
to most major platforms yet. However, having an easy way to run the test
suite against that library is still both useful and interesting.
Commit: d1dff1dc18f6087a89e94866fe474d0be228b7cf
https://github.com/llvm/llvm-project/commit/d1dff1dc18f6087a89e94866fe474d0be228b7cf
Author: Florian Hahn <flo at fhahn.com>
Date: 2024-12-12 (Thu, 12 Dec 2024)
Changed paths:
M llvm/test/Transforms/LoopVectorize/AArch64/fully-unrolled-cost.ll
M llvm/test/Transforms/LoopVectorize/ARM/mve-icmpcost.ll
Log Message:
-----------
[LV] Remove hard-coded VPValue numbers in test check lines. (NFC)
Make tests independent of VPlan value numbers.
Commit: 80cd9e4265a8e3e0a6fc90dfe9815f6958ba0b9a
https://github.com/llvm/llvm-project/commit/80cd9e4265a8e3e0a6fc90dfe9815f6958ba0b9a
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-12-12 (Thu, 12 Dec 2024)
Changed paths:
M llvm/lib/Target/RISCV/RISCVGISel.td
M llvm/lib/Target/RISCV/RISCVInstrInfo.td
M llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
M llvm/lib/Target/RISCV/RISCVInstrInfoZb.td
Log Message:
-----------
[RISCV] Move GIComplexOperandMatcher and GICustomOperandRenderer next to their SelectionDAG equivalents. NFC (#119729)
This makes it easier to see if the SelectionDAG node has an equivalent
without needing to check another file. Putting them in the same file
also helps associate them with the relevant ISA and any additional context
that may be provided by comments.
Naming is a little messy because we inconsistently use camel case and
snake case in the SelectionDAG node names. Thus the GISel node names are
named the same as the SelectionDAG node name with either GI or gi_ as a
prefix.
Commit: ea04148c27264209fb9b732ec8932aa1f4680764
https://github.com/llvm/llvm-project/commit/ea04148c27264209fb9b732ec8932aa1f4680764
Author: Valentin Clement (バレンタイン クレメン) <clementval at gmail.com>
Date: 2024-12-12 (Thu, 12 Dec 2024)
Changed paths:
M flang/lib/Optimizer/Transforms/CUFDeviceGlobal.cpp
M flang/test/Fir/CUDA/cuda-implicit-device-global.f90
Log Message:
-----------
[flang][cuda] Extend implicit global handling to any type descriptor (#119769)
Relax the check to also handle other type descriptor globals.
Commit: 37cd7926b767b3877bfa8079f2f8bcb4cd104b1f
https://github.com/llvm/llvm-project/commit/37cd7926b767b3877bfa8079f2f8bcb4cd104b1f
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2024-12-13 (Fri, 13 Dec 2024)
Changed paths:
M llvm/lib/Target/AMDGPU/VOP3PInstructions.td
Log Message:
-----------
AMDGPU: Fix entry for mac in VGPR->AGPR MFMA table (#119693)
Commit: 37978c466b9c02463885a5de62d16f8ce0ca577f
https://github.com/llvm/llvm-project/commit/37978c466b9c02463885a5de62d16f8ce0ca577f
Author: Valentin Clement (バレンタイン クレメン) <clementval at gmail.com>
Date: 2024-12-12 (Thu, 12 Dec 2024)
Changed paths:
M flang/lib/Optimizer/Transforms/CUFDeviceGlobal.cpp
Log Message:
-----------
[flang][cuda] Remove unused variable
Commit: e605969efe95efd9941cf958d921006d0833889f
https://github.com/llvm/llvm-project/commit/e605969efe95efd9941cf958d921006d0833889f
Author: Soren Lassen <sorenlassen at gmail.com>
Date: 2024-12-13 (Fri, 13 Dec 2024)
Changed paths:
M mlir/unittests/Bytecode/BytecodeTest.cpp
Log Message:
-----------
[MLIR] check resource attr of module in TEST(Bytecode, MultiModuleWithResource) (#119618)
`checkResourceAttribute` accidentally ignored its argument and only
checked `roundTripModule` and not `module`
Commit: 7442be68f7e4bbb9ded915283ea49a005f7ffe8f
https://github.com/llvm/llvm-project/commit/7442be68f7e4bbb9ded915283ea49a005f7ffe8f
Author: Michael Maitland <michaeltmaitland at gmail.com>
Date: 2024-12-12 (Thu, 12 Dec 2024)
Changed paths:
M llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp
M llvm/test/CodeGen/RISCV/rvv/vl-opt-instrs.ll
M llvm/test/CodeGen/RISCV/rvv/vl-opt-op-info.mir
Log Message:
-----------
[RISCV][VLOPT] Add vector mask producing integer instructions to isSupportedInstr and getOperandInfo (#119733)
Commit: 602bbf2fd2ee1dadf0982e05192ee8791b35c657
https://github.com/llvm/llvm-project/commit/602bbf2fd2ee1dadf0982e05192ee8791b35c657
Author: Congcong Cai <congcongcai0907 at 163.com>
Date: 2024-12-13 (Fri, 13 Dec 2024)
Changed paths:
R clang-tools-extra/docs/clang-tidy/checks/clang-analyzer/cplusplus.PureVirtualCall.rst
A clang-tools-extra/docs/clang-tidy/checks/clang-analyzer/cplusplus.SelfAssignment.rst
R clang-tools-extra/docs/clang-tidy/checks/clang-analyzer/optin.osx.OSObjectCStyleCast.rst
R clang-tools-extra/docs/clang-tidy/checks/clang-analyzer/osx.MIG.rst
R clang-tools-extra/docs/clang-tidy/checks/clang-analyzer/osx.OSObjectRetainCount.rst
M clang-tools-extra/docs/clang-tidy/checks/clang-analyzer/security.PutenvStackArray.rst
M clang-tools-extra/docs/clang-tidy/checks/clang-analyzer/security.SetgidSetuidOrder.rst
M clang-tools-extra/docs/clang-tidy/checks/list.rst
Log Message:
-----------
[clang-tidy][NFC][doc] clean out-dated clang-static-analyzer checks (#119580)
Commit: ea6e13586ce22291e9e7a4e382f6b2409b406da9
https://github.com/llvm/llvm-project/commit/ea6e13586ce22291e9e7a4e382f6b2409b406da9
Author: Tom Stellard <tstellar at redhat.com>
Date: 2024-12-12 (Thu, 12 Dec 2024)
Changed paths:
M clang/utils/perf-training/bolt.lit.cfg
M clang/utils/perf-training/lit.cfg
M clang/utils/perf-training/llvm-support/build.test
Log Message:
-----------
[clang][perf-training] Fix profiling with -DCLANG_BOLT=perf (#119117)
This fixes the llvm-support build that generates the profile data, and
wraps the whole `cmake --build` command with perf instead of wrapping
each individual clang invocation. This limits the number of profile
files generated and reduces the time spent running perf2bolt.
Commit: d01c11df04ae45a3d5b08e69bb683c760bbddd54
https://github.com/llvm/llvm-project/commit/d01c11df04ae45a3d5b08e69bb683c760bbddd54
Author: Kazu Hirata <kazu at google.com>
Date: 2024-12-12 (Thu, 12 Dec 2024)
Changed paths:
M clang/include/clang/Basic/FileEntry.h
M clang/include/clang/Basic/IdentifierTable.h
M clang/include/clang/Sema/ParsedAttr.h
M clang/include/clang/Sema/SemaConcept.h
M clang/include/clang/Sema/SemaInternal.h
M clang/include/clang/Sema/Template.h
M clang/lib/APINotes/APINotesManager.cpp
M clang/lib/Analysis/ThreadSafetyCommon.cpp
M clang/lib/Basic/FileManager.cpp
M clang/lib/CodeGen/CGOpenMPRuntime.cpp
M clang/lib/Index/IndexDecl.cpp
Log Message:
-----------
[clang] Migrate away from PointerUnion::{is,get} (NFC) (#119724)
Note that PointerUnion::{is,get} have been soft deprecated in
PointerUnion.h:
// FIXME: Replace the uses of is(), get() and dyn_cast() with
// isa<T>, cast<T> and the llvm::dyn_cast<T>
I'm not touching PointerUnion::dyn_cast for now because it's a bit
complicated; we could blindly migrate it to dyn_cast_if_present, but
we should probably use dyn_cast when the operand is known to be
non-null.
Commit: 88c18da37dfb10d570414bcb92ad075241f1b7c3
https://github.com/llvm/llvm-project/commit/88c18da37dfb10d570414bcb92ad075241f1b7c3
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-12-12 (Thu, 12 Dec 2024)
Changed paths:
M llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
M llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
M llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rvv/render-vlop-rv32.mir
M llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rvv/render-vlop-rv64.mir
M llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rvv/vmclr-rv32.mir
M llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rvv/vmclr-rv64.mir
M llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-crossbb.mir
Log Message:
-----------
[RISCV] Rename suffixes on VCPOP/VMSBF/VMSET/etc pseudos. NFC (#119785)
These are suffixed with B1, B2, B4, B8, B16, B32, or B64 which I think
these were supposed to match the naming of the vbool types from C where
the number should be SEW/LMUL. So the smallest mask is 64 and the
largest is 1. This provides a compact syntax for describing the 7
possible ratios between LMUL and SEW.
We had the instruction names in the opposite order.
Commit: 08379d6430106094aeb24ac02b82ce8e89799e9e
https://github.com/llvm/llvm-project/commit/08379d6430106094aeb24ac02b82ce8e89799e9e
Author: Kazu Hirata <kazu at google.com>
Date: 2024-12-12 (Thu, 12 Dec 2024)
Changed paths:
A llvm/test/Transforms/PGOProfile/memprof_annotate_yaml.test
Log Message:
-----------
[memprof] Test the memprof-use pass with a YAML (#119779)
This patch adds a test to verify that the call site that allocates
cold bytes is annotated as such. The test is the first of its kind
integrating the memprof-use pass and YAML.
Commit: 38eaea73cab3f427edd16d60035cf126f9a99cd0
https://github.com/llvm/llvm-project/commit/38eaea73cab3f427edd16d60035cf126f9a99cd0
Author: pcc <peter at pcc.me.uk>
Date: 2024-12-12 (Thu, 12 Dec 2024)
Changed paths:
M llvm/lib/TargetParser/Host.cpp
M llvm/unittests/TargetParser/Host.cpp
Log Message:
-----------
TargetParser: AArch64: Add part numbers for Apple CPUs.
Part numbers taken from:
https://github.com/AsahiLinux/m1n1/blob/main/src/chickens.c
Reviewers: ahmedbougacha, jroelofs
Reviewed By: jroelofs
Pull Request: https://github.com/llvm/llvm-project/pull/119777
Commit: 768754807f17754fb450ec672779b827ad5df4b4
https://github.com/llvm/llvm-project/commit/768754807f17754fb450ec672779b827ad5df4b4
Author: Matthias Braun <matze at braunis.de>
Date: 2024-12-12 (Thu, 12 Dec 2024)
Changed paths:
M llvm/lib/Transforms/InstCombine/InstCombineInternal.h
M llvm/lib/Transforms/InstCombine/InstCombineVectorOps.cpp
M llvm/lib/Transforms/InstCombine/InstructionCombining.cpp
A llvm/test/Transforms/InstCombine/vec_shuffle-phi-multiuse.ll
Log Message:
-----------
[InstCombine] Optimistically allow multiple shufflevector uses in foldOpPhi (#114278)
We would like to optimize situations of the form that happen after loop
vectorization+SROA:
```
loop:
%phi = phi zeroinitializer, %interleaved
%deinterleave_a = shufflevector %phi, poison ; pick half of the lanes
%deinterleave_b = shufflevector %phi, posion ; pick remaining lanes
... %a = ... %b = ...
%interleaved = shufflevector %a, %b ; interleave lanes of a+b
```
where the interleave and de-interleave shuffle operations cancel each
other out.
This could be handled by `foldOpPhi` but does not currently work because
it does
not proceed when there are multiple uses of the `Phi` operation.
This extends `foldOpPhi` to allow multiple `shufflevector` uses when
they are
shown to simplify for all `Phi` input values.
Commit: 51001f87f1b1136554a73228fac2bde9735b2d06
https://github.com/llvm/llvm-project/commit/51001f87f1b1136554a73228fac2bde9735b2d06
Author: Feng Zou <feng.zou at intel.com>
Date: 2024-12-13 (Fri, 13 Dec 2024)
Changed paths:
M lld/test/ELF/tls-opt.s
M lld/test/ELF/x86-64-tls-ie-local.s
M llvm/lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp
M llvm/lib/Target/X86/MCTargetDesc/X86ELFObjectWriter.cpp
M llvm/lib/Target/X86/MCTargetDesc/X86FixupKinds.h
M llvm/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp
M llvm/lib/Target/X86/MCTargetDesc/X86MachObjectWriter.cpp
M llvm/lib/Target/X86/MCTargetDesc/X86WinCOFFObjectWriter.cpp
M llvm/test/MC/ELF/relocation.s
Log Message:
-----------
[X86][MC] Fix offset for R_X86_64_CODE_6_GOTTPOFF fixup (#119496)
1. Fix the offset for R_X86_64_CODE_6_GOTTPOFF fixup, which is
introduced by #117277. It should be biased with the size of the
immediate field. Related tests are updated.
2. Rename reloc_riprel_6byte_relax to reloc_riprel_4byte_relax_evex as
the number of bytes represents the size of fixup, and "evex" suffix is added
as it's used for APX NDD/NF instructions with EVEX prefix.
3. Remove incorrectly setting R_X86_64_CODE_6_GOTTPOFF relocation type
for APX NDD/NF instructions with GOTPCREL symbol reference modifier.
Commit: 3de5e8b23f5c145b13d930eb5019566d3a6f88d5
https://github.com/llvm/llvm-project/commit/3de5e8b23f5c145b13d930eb5019566d3a6f88d5
Author: Vitaly Buka <vitalybuka at google.com>
Date: 2024-12-12 (Thu, 12 Dec 2024)
Changed paths:
M libcxxabi/CMakeLists.txt
Log Message:
-----------
[libc++abi] Build cxxabi with sanitizers (#119612)
Commit: 6c4e70fcbbb62f38a5aab085634de5faaa5cf729
https://github.com/llvm/llvm-project/commit/6c4e70fcbbb62f38a5aab085634de5faaa5cf729
Author: wanglei <wanglei at loongson.cn>
Date: 2024-12-13 (Fri, 13 Dec 2024)
Changed paths:
M lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_loongarch64.cpp
M lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_loongarch64.h
M lldb/source/Plugins/Process/Utility/CMakeLists.txt
A lldb/source/Plugins/Process/Utility/NativeRegisterContextDBReg_loongarch.cpp
A lldb/source/Plugins/Process/Utility/NativeRegisterContextDBReg_loongarch.h
M lldb/source/Plugins/Process/gdb-remote/GDBRemoteCommunicationServerCommon.cpp
M lldb/source/Target/Process.cpp
Log Message:
-----------
[lldb][Process] Introduce LoongArch64 hw break/watchpoint support
This patch adds support for setting/clearing hardware watchpoints and
breakpoints on LoongArch 64-bit hardware.
Refer to the following document for the hw break/watchpoint:
https://loongson.github.io/LoongArch-Documentation/LoongArch-Vol1-EN.html#control-and-status-registers-related-to-watchpoints
Fix Failed Tests:
lldb-shell :: Subprocess/clone-follow-child-wp.test
lldb-shell :: Subprocess/clone-follow-parent-wp.test
lldb-shell :: Subprocess/fork-follow-child-wp.test
lldb-shell :: Subprocess/fork-follow-parent-wp.test
lldb-shell :: Subprocess/vfork-follow-child-wp.test
lldb-shell :: Subprocess/vfork-follow-parent-wp.test
lldb-shell :: Watchpoint/ExpressionLanguage.test
Depends on: #118043
Reviewed By: SixWeining
Pull Request: https://github.com/llvm/llvm-project/pull/118770
Commit: 7077896a548a22d6a15c59d4b3edbc19d8e44fce
https://github.com/llvm/llvm-project/commit/7077896a548a22d6a15c59d4b3edbc19d8e44fce
Author: Thurston Dang <thurston at google.com>
Date: 2024-12-12 (Thu, 12 Dec 2024)
Changed paths:
M clang/lib/Driver/SanitizerArgs.cpp
Log Message:
-----------
[NFCI][sanitizer] Refactor parseSanitizeTrapArgs (#119797)
parseSanitizeTrapArgs follows the general pattern of "compute the
sanitizer mask based on the default plus opt-in (if supported) minus
opt-out". This patch refactors the functionality into a generalized
function, parseSanitizeArgs, which will be useful for future sanitizer
flag parsing.
Commit: 3b10e31d3a4a1c660c82287d3b9f6515f37a32ca
https://github.com/llvm/llvm-project/commit/3b10e31d3a4a1c660c82287d3b9f6515f37a32ca
Author: hitmoon <zxq_yx_007 at 163.com>
Date: 2024-12-13 (Fri, 13 Dec 2024)
Changed paths:
M clang/lib/Basic/Targets.cpp
M clang/lib/Basic/Targets/OSTargets.h
M clang/lib/Driver/ToolChains/FreeBSD.cpp
M clang/test/Driver/freebsd.c
Log Message:
-----------
[clang][LoongArch] Add FreeBSD targets (#119191)
Add support for freebsd on loongarch
Signed-off-by: xiaoqiang zhao <zxq_yx_007 at 163.com>
Co-authored-by: yu shan wei <mpysw at vip.163.com>
Commit: 5e53a8dadb0019ee87936c1278fa222781257005
https://github.com/llvm/llvm-project/commit/5e53a8dadb0019ee87936c1278fa222781257005
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2024-12-13 (Fri, 13 Dec 2024)
Changed paths:
M llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
A llvm/test/MachineVerifier/AMDGPU/unsupported-subreg-index-aligned-vgpr-check.mir
Log Message:
-----------
AMDGPU: Fix verifier assert with out of bounds subregister indexes (#119799)
The manual check for aligned VGPR classes would assert if a virtual
register used an index not supported by the register class.
Commit: ada517b40c6f90a78ea69b9d2d0997c82065c9fd
https://github.com/llvm/llvm-project/commit/ada517b40c6f90a78ea69b9d2d0997c82065c9fd
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2024-12-13 (Fri, 13 Dec 2024)
Changed paths:
M llvm/lib/CodeGen/MLRegAllocEvictAdvisor.cpp
Log Message:
-----------
[MLGO][NFC] Clang format MLRegAllocEvictAdvisor.cpp
Run clang-format to fix an issue in spacing in a comment.
Commit: 1562b70eaf6e0b95910fa684dfc53bd5ca6252e7
https://github.com/llvm/llvm-project/commit/1562b70eaf6e0b95910fa684dfc53bd5ca6252e7
Author: paperchalice <liujunchang97 at outlook.com>
Date: 2024-12-13 (Fri, 13 Dec 2024)
Changed paths:
M llvm/include/llvm/Analysis/DomTreeUpdater.h
M llvm/include/llvm/Analysis/GenericDomTreeUpdater.h
M llvm/include/llvm/Analysis/GenericDomTreeUpdaterImpl.h
M llvm/include/llvm/CodeGen/MachineBasicBlock.h
M llvm/include/llvm/CodeGen/MachineDomTreeUpdater.h
M llvm/include/llvm/CodeGen/MachineDominators.h
M llvm/include/llvm/CodeGen/MachineSSAContext.h
M llvm/lib/Analysis/DomTreeUpdater.cpp
M llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
M llvm/lib/CodeGen/LazyMachineBlockFrequencyInfo.cpp
M llvm/lib/CodeGen/LiveDebugValues/InstrRefBasedImpl.cpp
M llvm/lib/CodeGen/LiveDebugValues/LiveDebugValues.cpp
M llvm/lib/CodeGen/MachineBasicBlock.cpp
M llvm/lib/CodeGen/MachineDomTreeUpdater.cpp
M llvm/lib/CodeGen/MachineDominanceFrontier.cpp
M llvm/lib/CodeGen/MachineDominators.cpp
M llvm/lib/CodeGen/MachineLICM.cpp
M llvm/lib/CodeGen/MachineLoopInfo.cpp
M llvm/lib/CodeGen/MachineSink.cpp
M llvm/lib/CodeGen/MachineUniformityAnalysis.cpp
M llvm/lib/CodeGen/PHIElimination.cpp
M llvm/lib/CodeGen/XRayInstrumentation.cpp
M llvm/lib/Target/AMDGPU/SILateBranchLowering.cpp
M llvm/lib/Target/AMDGPU/SILowerI1Copies.cpp
M llvm/lib/Target/AMDGPU/SIWholeQuadMode.cpp
M llvm/lib/Target/Hexagon/HexagonFrameLowering.cpp
M llvm/lib/Target/X86/X86FlagsCopyLowering.cpp
M llvm/tools/llvm-reduce/deltas/ReduceInstructionsMIR.cpp
M llvm/unittests/Analysis/DomTreeUpdaterTest.cpp
M llvm/unittests/Target/WebAssembly/WebAssemblyExceptionInfoTest.cpp
Log Message:
-----------
Reapply "[DomTreeUpdater] Move critical edge splitting code to updater" (#119547)
This relands commit #115111.
Use traditional way to update post dominator tree, i.e. break critical
edge splitting into insert, insert, delete sequence.
When splitting critical edges, the post dominator tree may change its
root node, and `setNewRoot` only works in normal dominator tree...
See
https://github.com/llvm/llvm-project/blob/6c7e5827eda26990e872eb7c3f0d7866ee3c3171/llvm/include/llvm/Support/GenericDomTree.h#L684-L687
Commit: 02bcaca5995de283c85acfcca61a39baac315794
https://github.com/llvm/llvm-project/commit/02bcaca5995de283c85acfcca61a39baac315794
Author: Mingming Liu <mingmingl at google.com>
Date: 2024-12-12 (Thu, 12 Dec 2024)
Changed paths:
M clang/docs/LanguageExtensions.rst
Log Message:
-----------
[docs]Fix a typo around '#pragma clang section' (#119791)
Commit: 82204154b7bd1f8c487c94c7ef00399d776b29f0
https://github.com/llvm/llvm-project/commit/82204154b7bd1f8c487c94c7ef00399d776b29f0
Author: Han-Kuan Chen <hankuan.chen at sifive.com>
Date: 2024-12-13 (Fri, 13 Dec 2024)
Changed paths:
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
M llvm/test/Transforms/SLPVectorizer/AArch64/vec3-base.ll
M llvm/test/Transforms/SLPVectorizer/RISCV/reversed-strided-node-with-external-ptr.ll
M llvm/test/Transforms/SLPVectorizer/RISCV/vec3-base.ll
M llvm/test/Transforms/SLPVectorizer/X86/barriercall.ll
M llvm/test/Transforms/SLPVectorizer/X86/bottom-to-top-reorder.ll
M llvm/test/Transforms/SLPVectorizer/X86/extract-scalar-from-undef.ll
M llvm/test/Transforms/SLPVectorizer/X86/extractcost.ll
M llvm/test/Transforms/SLPVectorizer/X86/minbitwidth-drop-wrapping-flags.ll
M llvm/test/Transforms/SLPVectorizer/X86/multi-extracts-bv-combined.ll
M llvm/test/Transforms/SLPVectorizer/X86/vec3-base.ll
M llvm/test/Transforms/SLPVectorizer/alternate-opcode-sindle-bv.ll
M llvm/test/Transforms/SLPVectorizer/resized-alt-shuffle-after-minbw.ll
M llvm/test/Transforms/SLPVectorizer/shuffle-mask-resized.ll
Log Message:
-----------
[SLP] Make getSameOpcode support different instructions if they have same semantics. (#112181)
Commit: 3133acf1fbd1cc57ea8e74288ee9a0acd027d749
https://github.com/llvm/llvm-project/commit/3133acf1fbd1cc57ea8e74288ee9a0acd027d749
Author: Han-Kuan Chen <hankuan.chen at sifive.com>
Date: 2024-12-12 (Thu, 12 Dec 2024)
Changed paths:
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
M llvm/test/Transforms/SLPVectorizer/AArch64/vec3-base.ll
M llvm/test/Transforms/SLPVectorizer/RISCV/reversed-strided-node-with-external-ptr.ll
M llvm/test/Transforms/SLPVectorizer/RISCV/vec3-base.ll
M llvm/test/Transforms/SLPVectorizer/X86/barriercall.ll
M llvm/test/Transforms/SLPVectorizer/X86/bottom-to-top-reorder.ll
M llvm/test/Transforms/SLPVectorizer/X86/extract-scalar-from-undef.ll
M llvm/test/Transforms/SLPVectorizer/X86/extractcost.ll
M llvm/test/Transforms/SLPVectorizer/X86/minbitwidth-drop-wrapping-flags.ll
M llvm/test/Transforms/SLPVectorizer/X86/multi-extracts-bv-combined.ll
M llvm/test/Transforms/SLPVectorizer/X86/vec3-base.ll
M llvm/test/Transforms/SLPVectorizer/alternate-opcode-sindle-bv.ll
M llvm/test/Transforms/SLPVectorizer/resized-alt-shuffle-after-minbw.ll
M llvm/test/Transforms/SLPVectorizer/shuffle-mask-resized.ll
Log Message:
-----------
Revert "[SLP] Make getSameOpcode support different instructions if they have same semantics. (#112181)"
This reverts commit 82204154b7bd1f8c487c94c7ef00399d776b29f0.
Commit: 60325abeb3226b17c28429dfa6e175f25c171ec0
https://github.com/llvm/llvm-project/commit/60325abeb3226b17c28429dfa6e175f25c171ec0
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2024-12-12 (Thu, 12 Dec 2024)
Changed paths:
M llvm/lib/CodeGen/MLRegAllocEvictAdvisor.cpp
Log Message:
-----------
[MLGO] Add Threshold to Prevent Pathological Compile Time Cases (#119807)
This patch adds a threshold flag, -mlregalloc-max-cascade, to prevent
live ranges from being evicted more than is necessary.
After deploying a new regalloc model, we ran into some pathological
cases where the model decided it wanted to ping-pong evictions, taking
up a large amount of compile time. This threshold is mostly a stop gap
while we continue to investigate other solutions and work on
minimizing/constructing test cases.
Commit: 0c94915d34e6934c04140bb908364e54d1bc8ada
https://github.com/llvm/llvm-project/commit/0c94915d34e6934c04140bb908364e54d1bc8ada
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-12-12 (Thu, 12 Dec 2024)
Changed paths:
M llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
M llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
M llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td
M llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
M llvm/test/CodeGen/RISCV/rvv/vl-opt-op-info.mir
M llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-crossbb.mir
Log Message:
-----------
[RISCV] Use _B* suffix for vector mask logic pseudo instructions. (#119787)
Replace LMUL suffixes with _B1, _B2, etc. This matches what we do
for other mask only instructions like VCPOP_M, VFIRST_M, VMSBF_M,
VLM, VSM, etc.
Now all pseudoinstructions that use Log2SEW=0 will be consistently
named.
Commit: 2bf3ef18471a987aea32fd845535b58aedbb3e46
https://github.com/llvm/llvm-project/commit/2bf3ef18471a987aea32fd845535b58aedbb3e46
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2024-12-12 (Thu, 12 Dec 2024)
Changed paths:
M bolt/test/unreadable-profile.test
Log Message:
-----------
[BOLT] Require non root user for unreadable-profile.test (#119816)
This patch adds a requirement for a non root user in
unreadable-profile.test. This test fails if run as a root user (like in
a container without explicitly changing the user), which can lead to
some CI test failures.
Commit: ae89be0797e663b5e699104f58cbb8f5a090080b
https://github.com/llvm/llvm-project/commit/ae89be0797e663b5e699104f58cbb8f5a090080b
Author: Lang Hames <lhames at gmail.com>
Date: 2024-12-13 (Fri, 13 Dec 2024)
Changed paths:
M compiler-rt/lib/orc/macho_tlv.x86-64.S
M compiler-rt/lib/orc/sysv_reenter.arm64.S
Log Message:
-----------
[ORC-RT] Fix comments. NFC.
Fix file name, symbol name, and formatting in comments.
Commit: a1739d2501e813f629268f99a2ab3485aaf02ba1
https://github.com/llvm/llvm-project/commit/a1739d2501e813f629268f99a2ab3485aaf02ba1
Author: Lang Hames <lhames at gmail.com>
Date: 2024-12-13 (Fri, 13 Dec 2024)
Changed paths:
M llvm/include/llvm/ExecutionEngine/JITLink/aarch64.h
Log Message:
-----------
[JITLink][aarch64] Fix comment for trampoline instruction sequence. NFC.
The comment was from a prototype and doesn't reflect the final instruction
sequence.
Commit: 81c680a89622466b279357ca2e1045ef84d2c534
https://github.com/llvm/llvm-project/commit/81c680a89622466b279357ca2e1045ef84d2c534
Author: Lang Hames <lhames at gmail.com>
Date: 2024-12-13 (Fri, 13 Dec 2024)
Changed paths:
M llvm/lib/ExecutionEngine/Orc/JITLinkReentryTrampolines.cpp
Log Message:
-----------
[ORC] Improve JITLinkReentryTrampolines "arch not supported" error message.
"Architecture not supported" becomes
"JITLinkReentryTrampolines: architecture <arch> not supported".
Commit: 1865f0e203d4b23e676fb6ce72cf8797d0f0b80a
https://github.com/llvm/llvm-project/commit/1865f0e203d4b23e676fb6ce72cf8797d0f0b80a
Author: Fangrui Song <i at maskray.me>
Date: 2024-12-12 (Thu, 12 Dec 2024)
Changed paths:
M lld/COFF/PDB.cpp
M lld/COFF/Writer.cpp
Log Message:
-----------
[lld-link] Replace warn(...) with Warn(ctx)
Commit: 7a648554f886fbc043c4f3f58ca88f6c4535f2cf
https://github.com/llvm/llvm-project/commit/7a648554f886fbc043c4f3f58ca88f6c4535f2cf
Author: Akshat Oke <Akshat.Oke at amd.com>
Date: 2024-12-13 (Fri, 13 Dec 2024)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
M llvm/test/CodeGen/AMDGPU/sgpr-regalloc-flags.ll
Log Message:
-----------
[AMDGPU][CodeGen] Do not backtrace invalid -regalloc param (#119687)
No need to generate a stack trace and a GitHub issue prompt on a wrongly
set regalloc option.
Commit: 37d0e2f46e885f47c97b78c21d6b8668cd0ef871
https://github.com/llvm/llvm-project/commit/37d0e2f46e885f47c97b78c21d6b8668cd0ef871
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2024-12-13 (Fri, 13 Dec 2024)
Changed paths:
M clang/test/CodeGenOpenCL/opencl_types.cl
Log Message:
-----------
clang: Fix broken check prefix in test (#119821)
Commit: ea44647a0b49de826191eeb6e05020262b5a81e9
https://github.com/llvm/llvm-project/commit/ea44647a0b49de826191eeb6e05020262b5a81e9
Author: Owen Pan <owenpiano at gmail.com>
Date: 2024-12-12 (Thu, 12 Dec 2024)
Changed paths:
M clang/docs/tools/dump_format_help.py
M clang/docs/tools/dump_format_style.py
Log Message:
-----------
[clang-format] Write in text mode with LF in dump_format_[help|style].py
Commit: 5828aef014ea2b131fb126b328e7828d628ad5ed
https://github.com/llvm/llvm-project/commit/5828aef014ea2b131fb126b328e7828d628ad5ed
Author: Mike Hommey <mh at glandium.org>
Date: 2024-12-12 (Thu, 12 Dec 2024)
Changed paths:
M compiler-rt/lib/sanitizer_common/sanitizer_win.cpp
Log Message:
-----------
[sanitizer_common] Return nullptr from ASan on ERROR_COMMITMENT_LIMIT (#119753)
Followup to #117929
Commit: 28c3bf5c6dad0974f9f15b58afd0935c0c6cb3e4
https://github.com/llvm/llvm-project/commit/28c3bf5c6dad0974f9f15b58afd0935c0c6cb3e4
Author: Younan Zhang <zyn7109 at gmail.com>
Date: 2024-12-13 (Fri, 13 Dec 2024)
Changed paths:
M clang/include/clang/Basic/DiagnosticParseKinds.td
M clang/lib/Parse/ParseExprCXX.cpp
M clang/test/CXX/dcl.decl/dcl.meaning/dcl.fct/p13.cpp
M clang/test/Parser/cxx0x-decl.cpp
M clang/test/Parser/cxx2c-pack-indexing.cpp
M clang/test/SemaCXX/cxx2c-pack-indexing-ext-diags.cpp
Log Message:
-----------
[Clang][Parser] Add a warning to ambiguous uses of T...[N] types (#116332)
`void f(T... [N])` is no longer treated as a function with a parameter
of pack expansion type after the implementation of the pack indexing
feature. This patch introduces a warning to clarify such cases while
maintaining it as a pack indexing type in all language modes.
Closes https://github.com/llvm/llvm-project/issues/115222
Commit: d7a8e09893c43ad1169ff34989c3bec721d8b1a9
https://github.com/llvm/llvm-project/commit/d7a8e09893c43ad1169ff34989c3bec721d8b1a9
Author: Owen Pan <owenpiano at gmail.com>
Date: 2024-12-13 (Fri, 13 Dec 2024)
Changed paths:
M clang/test/Format/docs_updated.test
Log Message:
-----------
[clang-format] Add --strip-trailing-cr to diff in docs_updated.test (#119666)
Fixes #119517.
Commit: e32c428bec2074f954350d225104c299964b4585
https://github.com/llvm/llvm-project/commit/e32c428bec2074f954350d225104c299964b4585
Author: Antonio Frighetto <me at antoniofrighetto.com>
Date: 2024-12-13 (Fri, 13 Dec 2024)
Changed paths:
M llvm/test/Transforms/SimplifyCFG/X86/switch_to_lookup_table.ll
M llvm/test/Transforms/SimplifyCFG/switch-dup-bbs.ll
Log Message:
-----------
[SimplifyCFG] Precommit tests for PR118955 (NFC)
Commit: d26df3225537f3f9dc283f4fb33d191d11802d8c
https://github.com/llvm/llvm-project/commit/d26df3225537f3f9dc283f4fb33d191d11802d8c
Author: Antonio Frighetto <me at antoniofrighetto.com>
Date: 2024-12-13 (Fri, 13 Dec 2024)
Changed paths:
M llvm/lib/Transforms/Utils/SimplifyCFG.cpp
M llvm/test/Transforms/SimplifyCFG/X86/switch_to_lookup_table.ll
M llvm/test/Transforms/SimplifyCFG/switch-dup-bbs.ll
Log Message:
-----------
[SimplifyCFG] Consider preds to switch in `simplifyDuplicateSwitchArms`
Allow a duplicate basic block with multiple predecessors to the
jump table to be simplified, by considering that the same basic
block may appear in more switch cases.
Commit: 1d070988d9172965dee227e5629fa886845b815f
https://github.com/llvm/llvm-project/commit/1d070988d9172965dee227e5629fa886845b815f
Author: Hans Wennborg <hans at hanshq.net>
Date: 2024-12-13 (Fri, 13 Dec 2024)
Changed paths:
M llvm/lib/Target/X86/X86WinEHState.cpp
A llvm/test/CodeGen/WinEH/wineh-musttail-call.ll
Log Message:
-----------
[WinEH] Take musttail calls into account when unlinking eh records (#119702)
Exception handling records are unlinked on function return. However, if
there is a musttail call before the return, that's the de-facto point of
termination and the unlinking instructions must be inserted *before*
that.
Fixes #119255
Commit: 3d6b2d491209018918e4c881a0917bffc54cc0d9
https://github.com/llvm/llvm-project/commit/3d6b2d491209018918e4c881a0917bffc54cc0d9
Author: David Green <david.green at arm.com>
Date: 2024-12-13 (Fri, 13 Dec 2024)
Changed paths:
M llvm/include/llvm/CodeGen/GlobalISel/LegalizationArtifactCombiner.h
M llvm/test/CodeGen/AArch64/GlobalISel/combine-ext-debugloc.mir
M llvm/test/CodeGen/AArch64/GlobalISel/legalize-build-vector.mir
M llvm/test/CodeGen/AArch64/GlobalISel/legalize-concat-vectors.mir
M llvm/test/CodeGen/AArch64/GlobalISel/legalize-inserts.mir
Log Message:
-----------
[GlobalISel] Use replaceRegOrBuildCopy when legalizer-combining anyext(undef). (#119721)
This just avoids the unnecessary creation of some COPY nodes created
from the CSE builder.
Commit: 06789ccb1695214f787cd471a300522973d33375
https://github.com/llvm/llvm-project/commit/06789ccb1695214f787cd471a300522973d33375
Author: Fraser Cormack <fraser at codeplay.com>
Date: 2024-12-13 (Fri, 13 Dec 2024)
Changed paths:
M libclc/clc/include/clc/clcmacro.h
M libclc/clc/include/clc/math/clc_ceil.h
M libclc/clc/include/clc/math/clc_fabs.h
M libclc/clc/include/clc/math/clc_floor.h
M libclc/clc/include/clc/math/clc_rint.h
M libclc/clc/include/clc/math/clc_trunc.h
A libclc/clc/include/clc/math/unary_builtin.inc
M libclc/clc/lib/clspv/SOURCES
R libclc/clc/lib/clspv/dummy.cl
M libclc/clc/lib/generic/SOURCES
A libclc/clc/lib/generic/math/clc_ceil.cl
A libclc/clc/lib/generic/math/clc_fabs.cl
A libclc/clc/lib/generic/math/clc_floor.cl
A libclc/clc/lib/generic/math/clc_rint.cl
A libclc/clc/lib/generic/math/clc_trunc.cl
M libclc/clc/lib/spirv/SOURCES
M libclc/clc/lib/spirv64/SOURCES
M libclc/generic/lib/math/ceil.cl
M libclc/generic/lib/math/fabs.cl
M libclc/generic/lib/math/floor.cl
M libclc/generic/lib/math/rint.cl
M libclc/generic/lib/math/round.cl
M libclc/generic/lib/math/sqrt.cl
M libclc/generic/lib/math/trunc.cl
R libclc/generic/lib/math/unary_builtin.inc
Log Message:
-----------
[libclc] Optimize ceil/fabs/floor/rint/trunc (#119596)
These functions all map to the corresponding LLVM intrinsics, but the
vector intrinsics weren't being generated. The intrinsic mapping from
CLC vector function to vector intrinsic was working correctly, but the
mapping from OpenCL builtin to CLC function was suboptimally recursively
splitting vectors in halves.
For example, with this change, `ceil(float16)` calls `llvm.ceil.v16f32`
directly once optimizations are applied.
Now also, instead of generating LLVM intrinsics through `__asm` we now
call clang elementwise builtins for each CLC builtin. This should be a
more standard way of achieving the same result
The CLC versions of each of these builtins are also now built and
enabled for SPIR-V targets. The LLVM -> SPIR-V translator maps the
intrinsics to the appropriate OpExtInst, so there should be no
difference in semantics, despite the newly introduced indirection from
OpenCL builtin through the CLC builtin to the intrinsic.
The AMDGPU targets make use of the same `_CLC_DEFINE_UNARY_BUILTIN`
macro to override `sqrt`, so those functions also appear more optimal
with this change, calling the vector `llvm.sqrt.vXf32` intrinsics
directly.
Commit: 4c597d42dca13220c19661a021a11e28e2af801b
https://github.com/llvm/llvm-project/commit/4c597d42dca13220c19661a021a11e28e2af801b
Author: Adam Siemieniuk <adam.siemieniuk at intel.com>
Date: 2024-12-13 (Fri, 13 Dec 2024)
Changed paths:
M mlir/lib/Conversion/VectorToXeGPU/VectorToXeGPU.cpp
M mlir/test/Conversion/VectorToXeGPU/load-to-xegpu.mlir
M mlir/test/Conversion/VectorToXeGPU/store-to-xegpu.mlir
M mlir/test/Conversion/VectorToXeGPU/transfer-read-to-xegpu.mlir
M mlir/test/Conversion/VectorToXeGPU/transfer-write-to-xegpu.mlir
Log Message:
-----------
[mlir][xegpu] Support boundary checks only for block instructions (#119380)
Constrains Vector lowering to apply boundary checks only to data
transfers operating on block shapes.
This further aligns lowering with the current Xe instructions'
restrictions.
Commit: ccc8e454044477de9ce71c1b22dd048f189a9601
https://github.com/llvm/llvm-project/commit/ccc8e454044477de9ce71c1b22dd048f189a9601
Author: Haohai Wen <haohai.wen at intel.com>
Date: 2024-12-13 (Fri, 13 Dec 2024)
Changed paths:
M llvm/lib/Transforms/IPO/SampleProfile.cpp
M llvm/test/Transforms/SampleProfile/pseudo-probe-profile.ll
Log Message:
-----------
[PseudoProbe] Fix cleanup for pseudo probe after annotation (#119660)
When using -sample-profile-remove-probe, pseudo probe desc should
also be removed and dwarf discriminator for call instruction should
be restored.
Commit: 1fd3d1d04e6339fff7ef5b8b172ed4954885dde1
https://github.com/llvm/llvm-project/commit/1fd3d1d04e6339fff7ef5b8b172ed4954885dde1
Author: Jonathan Thackray <jonathan.thackray at arm.com>
Date: 2024-12-13 (Fri, 13 Dec 2024)
Changed paths:
M clang/include/clang/Basic/arm_sme.td
M clang/include/clang/Basic/arm_sve_sme_incl.td
A clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_fp8_fdot.c
A clang/test/Sema/aarch64-sme2-intrinsics/acle_sme2_fp8_fdot.c
M llvm/include/llvm/IR/IntrinsicsAArch64.td
M llvm/lib/Target/AArch64/AArch64SMEInstrInfo.td
M llvm/lib/Target/AArch64/SMEInstrFormats.td
A llvm/test/CodeGen/AArch64/sme2-intrinsics-fp8-fdot.ll
Log Message:
-----------
[AArch64] Add intrinsics for SME FP8 FDOT LANE instructions (#118492)
Add support for the following SME 8 bit floating-point dot-product
intrinsics:
* void svdot_lane_za16_mf8_vg1x2_fpm(uint32_t slice, svmfloat8x2_t zn,
svmfloat8_t zm, uint64_t imm_idx, fpm_t fpm);
* void svdot_lane_za16_mf8_vg1x4_fpm(uint32_t slice, svmfloat8x4_t zn,
svmfloat8_t zm, uint64_t imm_idx, fpm_t fpm);
* void svdot_lane_za32_mf8_vg1x2_fpm(uint32_t slice, svmfloat8x2_t zn,
svmfloat8_t zm, uint64_t imm_idx, fpm_t fpm);
* void svdot_lane_za32_mf8_vg1x4_fpm(uint32_t slice, svmfloat8x4_t zn,
svmfloat8_t zm, uint64_t imm_idx, fpm_t fpm);
---------
Co-authored-by: Momchil Velikov <momchil.velikov at arm.com>
Co-authored-by: Marian Lukac <marian.lukac at arm.com>
Co-authored-by: Caroline Concatto <caroline.concatto at arm.com>
Co-authored-by: SpencerAbson <Spencer.Abson at arm.com>
Commit: 7da4b6b7a5beba9ff2589c8ecdc141316acdad12
https://github.com/llvm/llvm-project/commit/7da4b6b7a5beba9ff2589c8ecdc141316acdad12
Author: Congcong Cai <congcongcai0907 at 163.com>
Date: 2024-12-13 (Fri, 13 Dec 2024)
Changed paths:
M clang-tools-extra/docs/clang-tidy/checks/misc/unused-parameters.rst
Log Message:
-----------
[clang-tidy][doc][NFC] format doc for misc-unused-parameters (#119839)
Commit: d6cc140dfdccc7314cc124a7d4aa4d0176299531
https://github.com/llvm/llvm-project/commit/d6cc140dfdccc7314cc124a7d4aa4d0176299531
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2024-12-13 (Fri, 13 Dec 2024)
Changed paths:
A .ci/compute-projects.sh
M .ci/generate-buildkite-pipeline-premerge
Log Message:
-----------
[CI] Refactor common functionality into separate script (#119530)
This patch refactors some common functionality present in the CI scripts
to a separate shell script. This is mainly intended to make it easier to
reuse this functionality inside of a Github Actions pipeline as we make
the switch.
Commit: bc29fc937c6cb4a210f80c93c79fc6ed97c801f8
https://github.com/llvm/llvm-project/commit/bc29fc937c6cb4a210f80c93c79fc6ed97c801f8
Author: Petr Kurapov <petr.a.kurapov at intel.com>
Date: 2024-12-13 (Fri, 13 Dec 2024)
Changed paths:
M mlir/include/mlir/Conversion/GPUCommon/GPUCommonPass.h
M mlir/include/mlir/Dialect/GPU/Transforms/Passes.h
R mlir/include/mlir/Dialect/GPU/Transforms/Utils.h
A mlir/include/mlir/Dialect/GPU/Utils/DistributionUtils.h
A mlir/include/mlir/Dialect/GPU/Utils/GPUUtils.h
M mlir/lib/Dialect/GPU/CMakeLists.txt
M mlir/lib/Dialect/GPU/Transforms/AsyncRegionRewriter.cpp
M mlir/lib/Dialect/GPU/Transforms/KernelOutlining.cpp
M mlir/lib/Dialect/GPU/Transforms/SubgroupReduceLowering.cpp
R mlir/lib/Dialect/GPU/Transforms/Utils.cpp
A mlir/lib/Dialect/GPU/Utils/CMakeLists.txt
A mlir/lib/Dialect/GPU/Utils/DistributionUtils.cpp
A mlir/lib/Dialect/GPU/Utils/Utils.cpp
M mlir/lib/Dialect/Vector/Transforms/CMakeLists.txt
M mlir/lib/Dialect/Vector/Transforms/VectorDistribute.cpp
Log Message:
-----------
[MLIR] Create GPU utils library & move distribution utils (#119264)
Continue the move of `warp_execute_on_lane_0` op to the gpu dialect
(#116994). This patch creates a utils library in GPU and moves generic
helper functions there.
Commit: 05860f9b384b9b8f8bb01fa8984dbc2833669a27
https://github.com/llvm/llvm-project/commit/05860f9b384b9b8f8bb01fa8984dbc2833669a27
Author: Ryosuke Niwa <rniwa at webkit.org>
Date: 2024-12-13 (Fri, 13 Dec 2024)
Changed paths:
M clang/lib/StaticAnalyzer/Checkers/WebKit/ASTUtils.cpp
M clang/lib/StaticAnalyzer/Checkers/WebKit/ASTUtils.h
M clang/lib/StaticAnalyzer/Checkers/WebKit/RawPtrRefCallArgsChecker.cpp
M clang/lib/StaticAnalyzer/Checkers/WebKit/RawPtrRefLocalVarsChecker.cpp
M clang/test/Analysis/Checkers/WebKit/call-args-checked-const-member.cpp
M clang/test/Analysis/Checkers/WebKit/call-args-checked-ptr.cpp
M clang/test/Analysis/Checkers/WebKit/call-args-counted-const-member.cpp
M clang/test/Analysis/Checkers/WebKit/call-args.cpp
M clang/test/Analysis/Checkers/WebKit/local-vars-checked-const-member.cpp
M clang/test/Analysis/Checkers/WebKit/local-vars-counted-const-member.cpp
M clang/test/Analysis/Checkers/WebKit/mock-types.h
Log Message:
-----------
[WebKit checkers] Recognize ensureFoo functions (#119681)
In WebKit, we often write Foo::ensureBar function which lazily
initializes m_bar and returns a raw pointer or a raw reference to m_bar.
Such a return value is safe to use for the duration of a member function
call in Foo so long as m_bar is const so that it never gets unset or
updated with a new value once it's initialized.
This PR adds support for recognizing these types of functions and
treating its return value as a safe origin of a function argument
(including "this") or a local variable.
Commit: 473e2518e850598feae62916ebef4b4dbc88a0ee
https://github.com/llvm/llvm-project/commit/473e2518e850598feae62916ebef4b4dbc88a0ee
Author: GeorgeKA <gkasante at gmail.com>
Date: 2024-12-13 (Fri, 13 Dec 2024)
Changed paths:
M clang/docs/LanguageExtensions.rst
Log Message:
-----------
[clang] Document the return value of __builtin_COLUMN (#118360)
PR for issue #78657
Updated clang/docs/LanguageExtensions.rst to detail the return value of
__builtin_COLUMN for this implementation.
--
Fyi, this is my first contribution, so please bear with me.
There already appears to be a unit test for __builtin_COLUMN in
clang/test/SemaCXX/source_location.cpp.
Commit: 79f41434460d3305c889a6483ea59f1e3ea19b5a
https://github.com/llvm/llvm-project/commit/79f41434460d3305c889a6483ea59f1e3ea19b5a
Author: Matthias Springer <me at m-sp.org>
Date: 2024-12-13 (Fri, 13 Dec 2024)
Changed paths:
M mlir/lib/Transforms/Utils/DialectConversion.cpp
Log Message:
-----------
[mlir][Transforms] Dialect conversion: Move `hasRewrite` to expensive checks (#119848)
The dialect conversion has various checks that detect incorrect API
usage in patterns. One of these checks turned out to be quite expensive
(N*M complexity where N is the number of block rewrites and M is the
total number of rewrites) in NVIDIA-internal workloads: Checking that a
block is not converted multiple times.
This check iterates over the stack of all rewrites, which can be large.
We saw `hasRewrite` being called around 45000 times with an average
rewrite stack size of 500000.
This PR moves the check to `MLIR_ENABLE_EXPENSIVE_PATTERN_API_CHECKS`.
For consistency reasons, the other `hasRewrite`-based check is also
moved there.
Commit: ff939b06a5ef57ac926c53e9f85b955b8bd855aa
https://github.com/llvm/llvm-project/commit/ff939b06a5ef57ac926c53e9f85b955b8bd855aa
Author: Jie Fu <jiefu at tencent.com>
Date: 2024-12-13 (Fri, 13 Dec 2024)
Changed paths:
M mlir/include/mlir/Dialect/GPU/Utils/DistributionUtils.h
Log Message:
-----------
[mlir] Fix the header guard (NFC)
/llvm-project/mlir/include/mlir/Dialect/GPU/Utils/DistributionUtils.h:9:9:
error: 'MLIR_DIALECT_GPU_TRANSFORMS_DISTRIBUTIONUTILS_H_' is used as a header guard here, followed by #define of a different macro [-Werror,-Wheader-guard]
^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
/llvm-project/mlir/include/mlir/Dialect/GPU/Utils/DistributionUtils.h:10:9:
note: 'MLIR_DIALECT_GPU_TRANSFORMS_DISTRIBITIONUTILS_H_' is defined here; did you mean 'MLIR_DIALECT_GPU_TRANSFORMS_DISTRIBUTIONUTILS_H_'?
^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
MLIR_DIALECT_GPU_TRANSFORMS_DISTRIBUTIONUTILS_H_
1 error generated.
Commit: 217e0f39710dec3348c996ecf98a76fd08b69853
https://github.com/llvm/llvm-project/commit/217e0f39710dec3348c996ecf98a76fd08b69853
Author: Florian Hahn <flo at fhahn.com>
Date: 2024-12-13 (Fri, 13 Dec 2024)
Changed paths:
A llvm/include/llvm/Analysis/ScalarEvolutionPatternMatch.h
M llvm/lib/Analysis/ScalarEvolution.cpp
Log Message:
-----------
[SCEV] Add initial pattern matching for SCEV constants. (NFC) (#119389)
Add initial pattern matching for SCEV constants. Follow-up patches will
add additional matchers for various SCEV expressions.
This patch only converts a few instances to use the new matchers to make
sure everything builds as expected for now.
PR: https://github.com/llvm/llvm-project/pull/119389
Commit: 94a77ebe240eb7dff7c5d645fc7f60cce049783f
https://github.com/llvm/llvm-project/commit/94a77ebe240eb7dff7c5d645fc7f60cce049783f
Author: David Green <david.green at arm.com>
Date: 2024-12-13 (Fri, 13 Dec 2024)
Changed paths:
M llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
M llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-hoist-same-hands.mir
Log Message:
-----------
[AArch64][GlobalISel] Guard against no operands in matchHoistLogicOpWithSameOpcodeHands
In case both LeftHandInst and RightHandInst are IMPLICIT_DEF with no input
operands, this patch protects against the post-legalizer-combiner
matchHoistLogicOpWithSameOpcodeHands with no operands. The
prelegalizercombiner-hoist-same-hands.mir test was cleaned up a little in the
process, and has a post-legalizer run line added so that the implicit_def do
not get folded awwy.
Commit: 8820de68ddf02fe3c73def49ec32bbeca54c2754
https://github.com/llvm/llvm-project/commit/8820de68ddf02fe3c73def49ec32bbeca54c2754
Author: Pedro Lobo <pedro.lobo at tecnico.ulisboa.pt>
Date: 2024-12-13 (Fri, 13 Dec 2024)
Changed paths:
M llvm/lib/IR/IntrinsicInst.cpp
Log Message:
-----------
[debug] Use poison instead of undef to set a killed dbg.assign address [NFC] (#119760)
Commit: 30cbd09f4b8f7e94663631f0240d11bb754ea25b
https://github.com/llvm/llvm-project/commit/30cbd09f4b8f7e94663631f0240d11bb754ea25b
Author: Timm Baeder <tbaeder at redhat.com>
Date: 2024-12-13 (Fri, 13 Dec 2024)
Changed paths:
M clang/lib/AST/ByteCode/InterpBuiltin.cpp
M clang/lib/AST/ByteCode/InterpBuiltinBitCast.cpp
M clang/lib/AST/ByteCode/InterpBuiltinBitCast.h
Log Message:
-----------
[clang][bytecode] Fix memcmp/bcmp failures on big-endian hosts (#119851)
See the discussion in
https://github.com/llvm/llvm-project/pull/119678#issuecomment-2539680746
and
https://github.com/llvm/llvm-project/pull/119544#issuecomment-2539678561
Commit: 84b0f0145887bbfe49fd4dc85490b14108a72cee
https://github.com/llvm/llvm-project/commit/84b0f0145887bbfe49fd4dc85490b14108a72cee
Author: VScigolevs <vladimirs.scigolevs at zimperium.com>
Date: 2024-12-13 (Fri, 13 Dec 2024)
Changed paths:
M clang/lib/Sema/SemaAttr.cpp
A clang/test/SemaCXX/msvc-pragma-function-no-builtin-attr.cpp
Log Message:
-----------
[clang-cl] Don't add implicit NoBuiltinAttr to deleted or defaulted functions (#119719)
In Clang `#pragma function` is implemented by adding an implicit
NoBuiltin Attribute to all function definitions after the pragma. This
(wrongly) includes also defaulted or deleted functions, which results in
the error, shown in #116256.
As this attribute has no effect on the deleted or defaulted functions,
this commit fixes the previously mentioned issue by simply not adding
the attribute in such cases.
Fixes #116256
Commit: 8bf19ec444593b3076a446a8eeb5042bbf79dc65
https://github.com/llvm/llvm-project/commit/8bf19ec444593b3076a446a8eeb5042bbf79dc65
Author: macurtis-amd <macurtis at amd.com>
Date: 2024-12-13 (Fri, 13 Dec 2024)
Changed paths:
M clang/unittests/Frontend/CompilerInvocationTest.cpp
Log Message:
-----------
[clang] Fix use of dangling ptr in CommandLineTest (#119798)
If 'GeneratedArgsStorage' ever grows, contained strings may get copied
and data pointers stored in 'GeneratedArgs' may become invalid, pointing
to deallocated memory.
Commit: 716360367fbdabac2c374c19b8746f4de49a5599
https://github.com/llvm/llvm-project/commit/716360367fbdabac2c374c19b8746f4de49a5599
Author: Florian Hahn <flo at fhahn.com>
Date: 2024-12-13 (Fri, 13 Dec 2024)
Changed paths:
M polly/lib/Analysis/ScopBuilder.cpp
M polly/lib/Analysis/ScopDetection.cpp
M polly/lib/Analysis/ScopInfo.cpp
M polly/lib/Support/SCEVAffinator.cpp
M polly/lib/Support/SCEVValidator.cpp
M polly/lib/Support/ScopHelper.cpp
M polly/lib/Support/VirtualInstruction.cpp
Log Message:
-----------
[Polly] Use const SCEV * explicitly in more places. (NFC)
Use const SCEV * explicitly in more places to prepare for
https://github.com/llvm/llvm-project/pull/91961.
Commit: a30e50fcb3119cc1f84f0398d229a929f296188d
https://github.com/llvm/llvm-project/commit/a30e50fcb3119cc1f84f0398d229a929f296188d
Author: Nikita Popov <npopov at redhat.com>
Date: 2024-12-13 (Fri, 13 Dec 2024)
Changed paths:
M clang/test/CodeGen/SystemZ/zos-mixed-ptr-sizes-malloc.c
M llvm/lib/Analysis/BasicAliasAnalysis.cpp
M llvm/test/Analysis/BasicAA/smaller-index-size-overflow.ll
Log Message:
-----------
[BasicAA] Do not decompose past casts with different index width (#119365)
BasicAA currently tries to support addrspacecasts that change the index
width by performing the decomposition in the maximum of all index widths
and then trying to fix this up with in-place sign extends to get correct
overflow behavior if the actual index width is smaller.
However, even in the case where we don't mix different index widths and
just have an index width that is smaller than the maximum, the behavior
is incorrect (see test), because we only perform the index width
adjustment during decomposition and not any of the later logic -- and we
don't do anything at all for variable offsets. I'm sure that the case
where we actually mix different index widths is even more broken than
that.
Fix this by not allowing decomposition through index width changes. If
the pointers have different index widths, fall back to a base object
comparison, ignoring the offsets.
Commit: 07aab4a3cdab3d46caab270845413c5ba4546b50
https://github.com/llvm/llvm-project/commit/07aab4a3cdab3d46caab270845413c5ba4546b50
Author: Nikita Popov <npopov at redhat.com>
Date: 2024-12-13 (Fri, 13 Dec 2024)
Changed paths:
M llvm/include/llvm/IR/DataLayout.h
M llvm/lib/IR/DataLayout.cpp
Log Message:
-----------
[DataLayout] Remove getMaxIndexSizeInBits() API
The last use was removed in #119365, and we should not add more
uses of this concept in the future either.
Commit: a25b2ba782dd5839492b135518f0a58d4a19e1f9
https://github.com/llvm/llvm-project/commit/a25b2ba782dd5839492b135518f0a58d4a19e1f9
Author: Yingwei Zheng <dtcxzyw2333 at gmail.com>
Date: 2024-12-13 (Fri, 13 Dec 2024)
Changed paths:
M llvm/include/llvm/AsmParser/LLParser.h
A llvm/test/Assembler/pr119818.ll
Log Message:
-----------
[AsmParser] Allow comparing ValIDs with different kinds (#119834)
This patch allows comparing `t_[Local|Global]ID` with
`t_[Local|Global]Name`.
Closes https://github.com/llvm/llvm-project/issues/119818.
Commit: 5fd385b3c145270bb9a6388d998a870bf3f79b54
https://github.com/llvm/llvm-project/commit/5fd385b3c145270bb9a6388d998a870bf3f79b54
Author: Nikolas Klauser <nikolasklauser at berlin.de>
Date: 2024-12-13 (Fri, 13 Dec 2024)
Changed paths:
M libcxx/include/string
M libcxx/include/string_view
Log Message:
-----------
[libc++][NFC] Simplify the implementation of string and string_views operator== (#117184)
Commit: 7c9404c279cfa13e24a043e6357cc85bd12f55f1
https://github.com/llvm/llvm-project/commit/7c9404c279cfa13e24a043e6357cc85bd12f55f1
Author: Ivan R. Ivanov <ivanov.i.aa at m.titech.ac.jp>
Date: 2024-12-13 (Fri, 13 Dec 2024)
Changed paths:
M clang/lib/Parse/ParseOpenMP.cpp
M flang/lib/Lower/OpenMP/ClauseProcessor.cpp
M flang/lib/Lower/OpenMP/ClauseProcessor.h
M flang/lib/Lower/OpenMP/OpenMP.cpp
M flang/lib/Parser/openmp-parsers.cpp
M flang/lib/Semantics/check-omp-structure.cpp
A flang/test/Lower/OpenMP/KernelLanguage/bare-clause.f90
A flang/test/Semantics/OpenMP/ompx-bare.f90
M llvm/include/llvm/Frontend/OpenMP/ConstructDecompositionT.h
M llvm/include/llvm/Frontend/OpenMP/OMP.td
M mlir/include/mlir/Dialect/OpenMP/OpenMPClauses.td
M mlir/include/mlir/Dialect/OpenMP/OpenMPOps.td
M mlir/lib/Dialect/OpenMP/IR/OpenMPDialect.cpp
M mlir/lib/Target/LLVMIR/Dialect/OpenMP/OpenMPToLLVMIRTranslation.cpp
Log Message:
-----------
[flang][OpenMP] Add frontend support for ompx_bare clause (#111106)
Commit: a21f9bfe29c2b9f1967952d12a5b7cb8f8b75202
https://github.com/llvm/llvm-project/commit/a21f9bfe29c2b9f1967952d12a5b7cb8f8b75202
Author: Danial Klimkin <dklimkin at google.com>
Date: 2024-12-13 (Fri, 13 Dec 2024)
Changed paths:
M utils/bazel/llvm-project-overlay/mlir/BUILD.bazel
Log Message:
-----------
[bazel]Fix Bazel build past bc29fc937c6cb4a210f80c93c79fc6ed97c801f8 (#119874)
Commit: d098ce0ec9e4dddb494f1f61ff36921dd4ce5f8e
https://github.com/llvm/llvm-project/commit/d098ce0ec9e4dddb494f1f61ff36921dd4ce5f8e
Author: Dmitry Vasilyev <dvassiliev at accesssoftek.com>
Date: 2024-12-13 (Fri, 13 Dec 2024)
Changed paths:
M llvm/lib/Support/Windows/Path.inc
Log Message:
-----------
[llvm][Support][Windows] Refactored remove_directories() w/o CComPtr and atlbase.h (#119843)
This is the update of #118677. This patch fixes building with mingw.
Commit: 12a42a60f9e63fab5699b210248b5b51bd21b6e3
https://github.com/llvm/llvm-project/commit/12a42a60f9e63fab5699b210248b5b51bd21b6e3
Author: VScigolevs <vladimirs.scigolevs at zimperium.com>
Date: 2024-12-13 (Fri, 13 Dec 2024)
Changed paths:
M clang/test/SemaCXX/msvc-pragma-function-no-builtin-attr.cpp
Log Message:
-----------
Fix SemaCXX/msvc-pragma-function-no-builtin-attr.cpp test (#119719)
Fix test failure from #119719
84b0f0145887bbfe49fd4dc85490b14108a72cee
Commit: fb8df8cb658278ceba9ef4b96e0b448aed32c1f6
https://github.com/llvm/llvm-project/commit/fb8df8cb658278ceba9ef4b96e0b448aed32c1f6
Author: Pavel Labath <pavel at labath.sk>
Date: 2024-12-13 (Fri, 13 Dec 2024)
Changed paths:
M lldb/include/lldb/Core/dwarf.h
M lldb/source/Plugins/SymbolFile/DWARF/DIERef.h
M lldb/source/Plugins/SymbolFile/DWARF/DWARFASTParserClang.cpp
M lldb/source/Plugins/SymbolFile/DWARF/DWARFCompileUnit.cpp
M lldb/source/Plugins/SymbolFile/DWARF/DWARFDIE.cpp
M lldb/source/Plugins/SymbolFile/DWARF/DWARFDIE.h
M lldb/source/Plugins/SymbolFile/DWARF/DWARFDebugInfoEntry.cpp
M lldb/source/Plugins/SymbolFile/DWARF/DWARFDebugInfoEntry.h
M lldb/source/Plugins/SymbolFile/DWARF/DWARFUnit.cpp
M lldb/source/Plugins/SymbolFile/DWARF/DWARFUnit.h
M lldb/source/Plugins/SymbolFile/DWARF/SymbolFileDWARF.cpp
Log Message:
-----------
[lldb/DWARF] s/DWARFRangeList/llvm::DWARFAddressRangeVector (#116620)
The main difference is that the llvm class (just a std::vector in
disguise) is not sorted. It turns out this isn't an issue because the
callers either:
- ignore the range list;
- convert it to a different format (which is then sorted);
- or query the minimum value (which is faster than sorting)
The last case is something I want to get rid of in a followup as a part
of removing the assumption that function's entry point is also its
lowest address.
Commit: ea8e328ae2bea9d9a7d556ef4d791fa116f7de18
https://github.com/llvm/llvm-project/commit/ea8e328ae2bea9d9a7d556ef4d791fa116f7de18
Author: Kristóf Umann <dkszelethus at gmail.com>
Date: 2024-12-13 (Fri, 13 Dec 2024)
Changed paths:
M clang/include/clang/StaticAnalyzer/Core/AnalyzerOptions.def
M clang/test/Analysis/analyzer-config.c
M clang/unittests/StaticAnalyzer/Z3CrosscheckOracleTest.cpp
Log Message:
-----------
[analyzer][Z3] Restore the original timeout of 15s (#118291)
Discussion here:
https://discourse.llvm.org/t/analyzer-rfc-taming-z3-query-times/79520/15?u=szelethus
The original patch, #97298 introduced new timeouts backed by thorough
testing and measurements to keep the running time of Z3 within
reasonable limits. The measurements also showed that only certain
reports and certain TUs were responsible for the poor performance of Z3
refutation.
Unfortunately, it seems like that on machines with different
characteristics (slower machines) the current timeouts don't just axe
0.01% of reports, but many more as well. Considering that timeouts are
inherently nondeterministic as a cutoff point, this lead reports sets
being vastly different on the same projects with the same configuration.
The discussion link shows that all configurations introduced in the
patch with their default values lead to severa nondeterminism of the
analyzer. As we, and others use the analyzer as a gating tool for PRs,
we should revert to the original defaults.
We should respect that
* There are still parts of the analyzer that are either proven or
suspected to contain nondeterministic code (like pointer sets),
* A 15s timeout is more likely to hit the same reports every time on a
wider range of machines, but is still inherently nondeterministic, but
an infinite timeout leads to the tool hanging,
* If you measure the performance of the analyzer on your machines, you
can and should achieve some speedup with little or no observable
nondeterminism.
---------
Co-authored-by: Balazs Benics <benicsbalazs at gmail.com>
Commit: 75e6d0eb4d6ad1b58e5eb5c4d25371e6062cee44
https://github.com/llvm/llvm-project/commit/75e6d0eb4d6ad1b58e5eb5c4d25371e6062cee44
Author: Mats Petersson <mats.petersson at arm.com>
Date: 2024-12-13 (Fri, 13 Dec 2024)
Changed paths:
M flang/examples/FlangOmpReport/FlangOmpReportVisitor.cpp
M flang/include/flang/Parser/dump-parse-tree.h
M flang/include/flang/Parser/parse-tree.h
M flang/lib/Lower/OpenMP/OpenMP.cpp
M flang/lib/Parser/openmp-parsers.cpp
M flang/lib/Parser/unparse.cpp
M flang/lib/Semantics/check-omp-structure.cpp
M flang/lib/Semantics/check-omp-structure.h
A flang/test/Lower/OpenMP/Todo/error.f90
A flang/test/Parser/OpenMP/error-unparse.f90
M llvm/include/llvm/Frontend/OpenMP/OMP.td
Log Message:
-----------
[flang][OpenMP]Add support for OpenMP ERROR directive (#119582)
Lowering leads to a TODO, with a test to confirm.
Also testing unparse.
---------
Co-authored-by: Krzysztof Parzyszek <Krzysztof.Parzyszek at amd.com>
Commit: c2172431c72c9b249bf5bdfcc0c239fbfe64fa9b
https://github.com/llvm/llvm-project/commit/c2172431c72c9b249bf5bdfcc0c239fbfe64fa9b
Author: Momchil Velikov <momchil.velikov at arm.com>
Date: 2024-12-13 (Fri, 13 Dec 2024)
Changed paths:
M clang/include/clang/Basic/arm_sve.td
M clang/include/clang/Basic/arm_sve_sme_incl.td
M clang/lib/CodeGen/CGBuiltin.cpp
A clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_fdot.c
M clang/test/Sema/aarch64-sve2-intrinsics/acle_sve2_fp8.c
M clang/utils/TableGen/SveEmitter.cpp
M llvm/include/llvm/IR/IntrinsicsAArch64.td
M llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
M llvm/lib/Target/AArch64/SVEInstrFormats.td
A llvm/test/CodeGen/AArch64/fp8-sve-fdot.ll
Log Message:
-----------
[AArch64] Implements FP8 SVE intrinsics for dot-product (#118125)
This patch adds the following intrinsics:
* 8-bit floating-point dot product to single-precision.
// Only if (__ARM_FEATURE_SVE2 && __ARM_FEATURE_FP8DOT4) ||
__ARM_FEATURE_SSVE_FP8DOT4
svfloat32_t svdot[_f32_mf8]_fpm(svfloat32_t zda, svmfloat8_t zn,
svmfloat8_t zm, fpm_t fpm);
svfloat32_t svdot[_n_f32_mf8]_fpm(svfloat32_t zda, svmfloat8_t zn,
mfloat8_t zm, fpm_t fpm);
* 8-bit floating-point indexed dot product to single-precision.
// Only if (__ARM_FEATURE_SVE2 && __ARM_FEATURE_FP8DOT4) ||
__ARM_FEATURE_SSVE_FP8DOT4
svfloat32_t svdot_lane[_f32_mf8]_fpm(svfloat32_t zda, svmfloat8_t zn,
svmfloat8_t zm,
uint64_t imm0_3, fpm_t fpm);
* 8-bit floating-point dot product to half-precision.
// Only if (__ARM_FEATURE_SVE2 && __ARM_FEATURE_FP8DOT2) ||
__ARM_FEATURE_SSVE_FP8DOT2
svfloat16_t svdot[_f16_mf8]_fpm(svfloat16_t zda, svmfloat8_t zn,
svmfloat8_t zm, fpm_t fpm);
svfloat16_t svdot[_n_f16_mf8]_fpm(svfloat16_t zda, svmfloat8_t zn,
mfloat8_t zm, fpm_t fpm);
* 8-bit floating-point indexed dot product to half-precision.
// Only if (__ARM_FEATURE_SVE2 && __ARM_FEATURE_FP8DOT2) ||
__ARM_FEATURE_SSVE_FP8DOT2
svfloat16_t svdot_lane[_f16_mf8]_fpm(svfloat16_t zda, svmfloat8_t zn,
svmfloat8_t zm,
uint64_t imm0_7, fpm_t fpm);
Commit: 89f1f32bff76c8cf4545ada34663c6a758214cf0
https://github.com/llvm/llvm-project/commit/89f1f32bff76c8cf4545ada34663c6a758214cf0
Author: Durgadoss R <durgadossr at nvidia.com>
Date: 2024-12-13 (Fri, 13 Dec 2024)
Changed paths:
M mlir/include/mlir/Dialect/LLVMIR/NVVMOps.td
A mlir/test/Target/LLVMIR/nvvm/tma_prefetch.mlir
M mlir/test/Target/LLVMIR/nvvmir-invalid.mlir
M mlir/test/Target/LLVMIR/nvvmir.mlir
Log Message:
-----------
[MLIR][NVVM] Refactor tests in nvvmir.mlir (#119731)
* Move the negative tests from nvvmir.mlir to nvvm-invalid.mlir. With
this, all the error-handling tests are moved to the nvvm-invalid.mlir file.
* Move the tma_prefetch tests to a separate file, as there are many
tests, and fix the FileCheck prefix for these.
* Since undef is discouraged, we use an 'i64 0' as the placeholder value
for cache-hint when unused.
Signed-off-by: Durgadoss R <durgadossr at nvidia.com>
Commit: 4a0d53a0b0a58a3c6980a7c551357ac71ba3db10
https://github.com/llvm/llvm-project/commit/4a0d53a0b0a58a3c6980a7c551357ac71ba3db10
Author: Ramkumar Ramachandra <ramkumar.ramachandra at codasip.com>
Date: 2024-12-13 (Fri, 13 Dec 2024)
Changed paths:
M llvm/include/llvm/IR/CmpPredicate.h
M llvm/include/llvm/IR/PatternMatch.h
M llvm/lib/Analysis/IVDescriptors.cpp
M llvm/lib/Analysis/InstructionSimplify.cpp
M llvm/lib/Analysis/OverflowInstAnalysis.cpp
M llvm/lib/Analysis/ValueTracking.cpp
M llvm/lib/CodeGen/CodeGenPrepare.cpp
M llvm/lib/CodeGen/ExpandMemCmp.cpp
M llvm/lib/IR/Instructions.cpp
M llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
M llvm/lib/Target/AMDGPU/AMDGPUCodeGenPrepare.cpp
M llvm/lib/Target/AMDGPU/AMDGPUInstCombineIntrinsic.cpp
M llvm/lib/Target/Hexagon/HexagonLoopIdiomRecognition.cpp
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/lib/Transforms/InstCombine/InstCombineAddSub.cpp
M llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp
M llvm/lib/Transforms/InstCombine/InstCombineCompares.cpp
M llvm/lib/Transforms/InstCombine/InstCombineSelect.cpp
M llvm/lib/Transforms/InstCombine/InstCombineVectorOps.cpp
M llvm/lib/Transforms/InstCombine/InstructionCombining.cpp
M llvm/lib/Transforms/Scalar/CallSiteSplitting.cpp
M llvm/lib/Transforms/Scalar/ConstraintElimination.cpp
M llvm/lib/Transforms/Scalar/DeadStoreElimination.cpp
M llvm/lib/Transforms/Scalar/EarlyCSE.cpp
M llvm/lib/Transforms/Scalar/GuardWidening.cpp
M llvm/lib/Transforms/Scalar/JumpThreading.cpp
M llvm/lib/Transforms/Scalar/LICM.cpp
M llvm/lib/Transforms/Scalar/LoopBoundSplit.cpp
M llvm/lib/Transforms/Scalar/LoopIdiomRecognize.cpp
M llvm/lib/Transforms/Scalar/SimpleLoopUnswitch.cpp
M llvm/lib/Transforms/Utils/LoopPeel.cpp
M llvm/lib/Transforms/Utils/ScalarEvolutionExpander.cpp
M llvm/lib/Transforms/Utils/SimplifyIndVar.cpp
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
M llvm/lib/Transforms/Vectorize/VectorCombine.cpp
M llvm/unittests/IR/PatternMatch.cpp
Log Message:
-----------
PatternMatch: migrate to CmpPredicate (#118534)
With the introduction of CmpPredicate in 51a895a (IR: introduce struct
with CmpInst::Predicate and samesign), PatternMatch is one of the first
key pieces of infrastructure that must be updated to match a CmpInst
respecting samesign information. Implement this change to Cmp-matchers.
This is a preparatory step in migrating the codebase over to
CmpPredicate. Since we no functional changes are desired at this stage,
we have chosen not to migrate CmpPredicate::operator==(CmpPredicate)
calls to use CmpPredicate::getMatching(), as that would have visible
impact on tests that are not yet written: instead, we call
CmpPredicate::operator==(Predicate), preserving the old behavior, while
also inserting a few FIXME comments for follow-ups.
Commit: 7a3504a133437525f3e56f5811e313e4695f932f
https://github.com/llvm/llvm-project/commit/7a3504a133437525f3e56f5811e313e4695f932f
Author: erichkeane <ekeane at nvidia.com>
Date: 2024-12-13 (Fri, 13 Dec 2024)
Changed paths:
M clang/lib/Sema/SemaOpenACC.cpp
A clang/test/SemaOpenACC/data-construct-copy-ast.cpp
A clang/test/SemaOpenACC/data-construct-copy-clause.c
M clang/test/SemaOpenACC/data-construct.cpp
Log Message:
-----------
[OpenACC] Enable 'copy' clause sema for data clause
'copy' is another that is identical in behavior on 'data' as far as
semantic analysis is concerned as the compute constructs, so this patch
adds tests and enables 'copy'.
Commit: 979e9361f0e0426e555c94cb8b1a64c655805765
https://github.com/llvm/llvm-project/commit/979e9361f0e0426e555c94cb8b1a64c655805765
Author: Peng Liu <winner245 at hotmail.com>
Date: 2024-12-13 (Fri, 13 Dec 2024)
Changed paths:
M libcxx/include/__split_buffer
M libcxx/include/deque
Log Message:
-----------
[libc++] Fix improper static_cast in std::deque and __split_buffer (#119106)
This PR addresses the improper use of `static_cast` to `size_t` where
`size_type` is intended. Although the `size_type` member type of STL
containers is usually a synonym of `std::size_t`, there is no guarantee
that they are always equivalent. The C++ standard does not mandate this
equivalence.
In libc++'s implementations of `std::deque`, `std::vector`, and
`__split_buffer`, the `size_type` member type is defined as
`std::allocator_traits<allocator_type>::size_type`, which is either
`allocator_type::size_type` if available or
`std::make_unsigned<difference_type>::type`. While it is true for
`std::allocator` that the `size_type` member type is `std::size_t`, for
user-defined allocator types, they may mismatch. This justifies the need
to replace `static_cast<size_t>` with `static_cast<size_type>` in this
PR.
Commit: 4eec286b51524d385524a9f7cee4b9c4f8153570
https://github.com/llvm/llvm-project/commit/4eec286b51524d385524a9f7cee4b9c4f8153570
Author: lntue <lntue at google.com>
Date: 2024-12-13 (Fri, 13 Dec 2024)
Changed paths:
M libc/src/__support/complex_type.h
M libc/src/__support/macros/properties/complex_types.h
M libc/src/__support/macros/properties/types.h
M libc/test/src/math/CMakeLists.txt
A libc/test/src/math/sqrtf128_test.cpp
M libc/utils/MPFRWrapper/MPFRUtils.cpp
Log Message:
-----------
[libc] Add MPFR testing infra for float128. (#119499)
Commit: 55154d6896e31dd707ac90dd15ed09bec446b4cf
https://github.com/llvm/llvm-project/commit/55154d6896e31dd707ac90dd15ed09bec446b4cf
Author: erichkeane <ekeane at nvidia.com>
Date: 2024-12-13 (Fri, 13 Dec 2024)
Changed paths:
M clang/lib/Sema/SemaOpenACC.cpp
A clang/test/SemaOpenACC/data-construct-no_create-ast.cpp
A clang/test/SemaOpenACC/data-construct-no_create-clause.c
M clang/test/SemaOpenACC/data-construct.cpp
Log Message:
-----------
[OpenACC] Enable 'no_create' sema for data construct
Adds tests and enables the 'no_create' clause semantic analysis for the
'data' constuct, so it will no longer report 'not yet implemented'.
Commit: 62bdb85f9b293180a2cf402fc2fa7c242d01ef3f
https://github.com/llvm/llvm-project/commit/62bdb85f9b293180a2cf402fc2fa7c242d01ef3f
Author: Louis Dionne <ldionne.2 at gmail.com>
Date: 2024-12-13 (Fri, 13 Dec 2024)
Changed paths:
M libcxx/test/std/containers/sequences/vector/vector.cons/assign_iter_iter.pass.cpp
Log Message:
-----------
[libc++][NFC] Fix incorrect comment for vector::assign(iter, iter) test
Commit: 9359625ba99dfbce8d8c27373ade544df16bee34
https://github.com/llvm/llvm-project/commit/9359625ba99dfbce8d8c27373ade544df16bee34
Author: erichkeane <ekeane at nvidia.com>
Date: 2024-12-13 (Fri, 13 Dec 2024)
Changed paths:
M clang/lib/Sema/SemaOpenACC.cpp
A clang/test/SemaOpenACC/data-construct-create-ast.cpp
A clang/test/SemaOpenACC/data-construct-create-clause.c
M clang/test/SemaOpenACC/data-construct.cpp
Log Message:
-----------
[OpenACC] 'create' clause sema for data/enter data constructs
Enable and add tests for 'create' on a data or enter data construct.
Commit: 1cc71197550b92fc23624d81f2474244772bfcfb
https://github.com/llvm/llvm-project/commit/1cc71197550b92fc23624d81f2474244772bfcfb
Author: Congcong Cai <congcongcai0907 at 163.com>
Date: 2024-12-13 (Fri, 13 Dec 2024)
Changed paths:
M clang-tools-extra/docs/clang-tidy/checks/clang-analyzer/security.PutenvStackArray.rst
M clang-tools-extra/docs/clang-tidy/checks/clang-analyzer/security.SetgidSetuidOrder.rst
R clang-tools-extra/docs/clang-tidy/checks/clang-analyzer/valist.CopyToSelf.rst
R clang-tools-extra/docs/clang-tidy/checks/clang-analyzer/valist.Uninitialized.rst
R clang-tools-extra/docs/clang-tidy/checks/clang-analyzer/valist.Unterminated.rst
M clang-tools-extra/docs/clang-tidy/checks/list.rst
Log Message:
-----------
[clang-tidy][NFC][doc] clean out-dated clang-static-analyzer checks documents and update check list (#119887)
The missing part of #119580
Commit: 019948647ebdb9f4d5cfce5a8f4afe9d4eafb14e
https://github.com/llvm/llvm-project/commit/019948647ebdb9f4d5cfce5a8f4afe9d4eafb14e
Author: WANG Rui <wangrui at loongson.cn>
Date: 2024-12-13 (Fri, 13 Dec 2024)
Changed paths:
M llvm/test/CodeGen/LoongArch/sextw-removal.ll
Log Message:
-----------
[LoongArch][NFC] Pre-commit tests for sign-extension removal with vectors
Commit: b2b1eec2b249698337d90a77c000340f0248c9cd
https://github.com/llvm/llvm-project/commit/b2b1eec2b249698337d90a77c000340f0248c9cd
Author: erichkeane <ekeane at nvidia.com>
Date: 2024-12-13 (Fri, 13 Dec 2024)
Changed paths:
M clang/lib/Sema/SemaOpenACC.cpp
M clang/test/AST/ast-print-openacc-data-construct.cpp
M clang/test/SemaOpenACC/data-construct-ast.cpp
M clang/test/SemaOpenACC/data-construct-async-clause.c
A clang/test/SemaOpenACC/data-construct-copyin-ast.cpp
A clang/test/SemaOpenACC/data-construct-copyin-clause.c
M clang/test/SemaOpenACC/data-construct-if-ast.cpp
M clang/test/SemaOpenACC/data-construct-if-clause.c
M clang/test/SemaOpenACC/data-construct-wait-ast.cpp
M clang/test/SemaOpenACC/data-construct-wait-clause.c
M clang/test/SemaOpenACC/data-construct.cpp
Log Message:
-----------
[OpenACC] enable 'copyin' clause sema for 'data'/'enter data'
stop reporting 'copyin' as not implemented on a data/enter data
construct, and enforce sema rules.
Commit: 1da0730ba5994537119ed61205a599cb3929c43a
https://github.com/llvm/llvm-project/commit/1da0730ba5994537119ed61205a599cb3929c43a
Author: erichkeane <ekeane at nvidia.com>
Date: 2024-12-13 (Fri, 13 Dec 2024)
Changed paths:
M clang/lib/Sema/SemaOpenACC.cpp
M clang/test/AST/ast-print-openacc-data-construct.cpp
M clang/test/SemaOpenACC/data-construct-ast.cpp
M clang/test/SemaOpenACC/data-construct-async-clause.c
A clang/test/SemaOpenACC/data-construct-copyout-ast.cpp
A clang/test/SemaOpenACC/data-construct-copyout-clause.c
M clang/test/SemaOpenACC/data-construct-if-ast.cpp
M clang/test/SemaOpenACC/data-construct-if-clause.c
M clang/test/SemaOpenACC/data-construct-wait-ast.cpp
M clang/test/SemaOpenACC/data-construct-wait-clause.c
M clang/test/SemaOpenACC/data-construct.cpp
Log Message:
-----------
[OpenACC] enable 'copyout' clause sema for data constructs
Same as the previous few, this just enables copyout for data constructs
and ensures we have sufficient test coverage.
Commit: fcb1591b46f12b8908a8cdb252611708820102f8
https://github.com/llvm/llvm-project/commit/fcb1591b46f12b8908a8cdb252611708820102f8
Author: Kazu Hirata <kazu at google.com>
Date: 2024-12-13 (Fri, 13 Dec 2024)
Changed paths:
M mlir/lib/IR/AffineMap.cpp
M mlir/lib/IR/Builders.cpp
M mlir/lib/IR/OperationSupport.cpp
M mlir/lib/IR/Region.cpp
M mlir/lib/IR/SymbolTable.cpp
M mlir/lib/IR/TypeRange.cpp
M mlir/lib/IR/Verifier.cpp
Log Message:
-----------
[IR] Migrate away from PointerUnion::{is,get} (NFC) (#119802)
Note that PointerUnion::{is,get} have been soft deprecated in
PointerUnion.h:
// FIXME: Replace the uses of is(), get() and dyn_cast() with
// isa<T>, cast<T> and the llvm::dyn_cast<T>
I'm not touching PointerUnion::dyn_cast for now because it's a bit
complicated; we could blindly migrate it to dyn_cast_if_present, but
we should probably use dyn_cast when the operand is known to be
non-null.
Commit: 331f3cc94b3c66eebf5ec462a8f1ee0d7704dd26
https://github.com/llvm/llvm-project/commit/331f3cc94b3c66eebf5ec462a8f1ee0d7704dd26
Author: erichkeane <ekeane at nvidia.com>
Date: 2024-12-13 (Fri, 13 Dec 2024)
Changed paths:
M clang/lib/Sema/SemaOpenACC.cpp
M clang/test/AST/ast-print-openacc-data-construct.cpp
M clang/test/SemaOpenACC/data-construct-no_create-ast.cpp
A clang/test/SemaOpenACC/data-construct-present-ast.cpp
A clang/test/SemaOpenACC/data-construct-present-clause.c
M clang/test/SemaOpenACC/data-construct.cpp
Log Message:
-----------
[OpenACC] enable 'present' clause for 'data' construct
No additional sema is required once again, so this patch adds testing
and enables the clause.
Commit: 5225f1b4355e4ad9fb0939fded88dc6189be29fd
https://github.com/llvm/llvm-project/commit/5225f1b4355e4ad9fb0939fded88dc6189be29fd
Author: Tibor Dusnoki <tdusnoki at inf.u-szeged.hu>
Date: 2024-12-13 (Fri, 13 Dec 2024)
Changed paths:
A bolt/test/merge-fdata-bat-no-lbr.test
A bolt/test/merge-fdata-lbr-mode.test
A bolt/test/merge-fdata-mixed-bat-no-lbr.test
A bolt/test/merge-fdata-mixed-mode.test
A bolt/test/merge-fdata-no-lbr-mode.test
M bolt/tools/merge-fdata/merge-fdata.cpp
Log Message:
-----------
[BOLT][merge-fdata] Fix basic sample profile aggregation without LBR info (#118481)
When a basic sample profile is gathered without LBR info, the generated
profile contains a "no-lbr" tag in the first line of the fdata file.
This PR fixes merge-fdata to recognize and save this tag to the output
file.
Commit: 754499c1e9410d51a4c41e71388c304de61366a0
https://github.com/llvm/llvm-project/commit/754499c1e9410d51a4c41e71388c304de61366a0
Author: erichkeane <ekeane at nvidia.com>
Date: 2024-12-13 (Fri, 13 Dec 2024)
Changed paths:
M clang/lib/Sema/SemaOpenACC.cpp
M clang/test/AST/ast-print-openacc-data-construct.cpp
A clang/test/SemaOpenACC/data-construct-deviceptr-ast.cpp
A clang/test/SemaOpenACC/data-construct-deviceptr-clause.c
M clang/test/SemaOpenACC/data-construct.cpp
Log Message:
-----------
[OpenACC] Enable 'deviceptr' clause sema on data construct
Another simple implementation, as it uses the same work as the previous
implementation, just enabling it for this construct.
Commit: ce25bd20dc56cef651170f1ee5820758dee415a2
https://github.com/llvm/llvm-project/commit/ce25bd20dc56cef651170f1ee5820758dee415a2
Author: erichkeane <ekeane at nvidia.com>
Date: 2024-12-13 (Fri, 13 Dec 2024)
Changed paths:
M clang/test/SemaOpenACC/data-construct-deviceptr-clause.c
Log Message:
-----------
[OpenACC] Fixup test to be more consistent
Commit: 4a6586140211cc9aed02d9177dba0c01622139f4
https://github.com/llvm/llvm-project/commit/4a6586140211cc9aed02d9177dba0c01622139f4
Author: Chris Apple <cja-private at pm.me>
Date: 2024-12-13 (Fri, 13 Dec 2024)
Changed paths:
M clang/lib/CodeGen/BackendUtil.cpp
M llvm/include/llvm/Transforms/Instrumentation/RealtimeSanitizer.h
M llvm/lib/Passes/PassBuilder.cpp
M llvm/lib/Passes/PassRegistry.def
M llvm/lib/Transforms/Instrumentation/RealtimeSanitizer.cpp
M llvm/test/Instrumentation/RealtimeSanitizer/rtsan.ll
Log Message:
-----------
[rtsan][llvm] Remove function pass, only support module pass (#119739)
Most of the other sanitizers are now only module level passes. This
moves all functionality into the module pass, and removes the function
pass.
Commit: fb02c33605bd988e9c6bb3a18cd7f0c3b1f20d5c
https://github.com/llvm/llvm-project/commit/fb02c33605bd988e9c6bb3a18cd7f0c3b1f20d5c
Author: Dhruv Srivastava <dhruv.srivastava at ibm.com>
Date: 2024-12-13 (Fri, 13 Dec 2024)
Changed paths:
M lldb/source/Plugins/ObjectFile/XCOFF/ObjectFileXCOFF.cpp
M lldb/source/Plugins/ObjectFile/XCOFF/ObjectFileXCOFF.h
Log Message:
-----------
[lldb][AIX] XCOFF clang-format and other minor changes (#119892)
Added some clang-format and other minor changes, Ref:
https://github.com/llvm/llvm-project/pull/116338#discussion_r1884069848
Review Request: @DavidSpickett
Commit: c9070cce09e1aef1c4bf1cb8c0000294b533dcd7
https://github.com/llvm/llvm-project/commit/c9070cce09e1aef1c4bf1cb8c0000294b533dcd7
Author: Sergei Barannikov <barannikov88 at gmail.com>
Date: 2024-12-13 (Fri, 13 Dec 2024)
Changed paths:
M llvm/test/TableGen/MixedCasedMnemonic.td
M llvm/utils/TableGen/Basic/SequenceToOffsetTable.h
M llvm/utils/TableGen/DFAEmitter.cpp
M llvm/utils/TableGen/RegisterInfoEmitter.cpp
Log Message:
-----------
[TableGen] Allow empty terminator in SequenceToOffsetTable (#119751)
Some clients do not want to emit a terminator after each sub-sequence
(they have other means of determining the length of sub-sequences).
This moves `Term` argument from `emit` method to the constructor and
makes it optional. It couldn't be made optional while still on the
`emit` method because if the terminator wasn't specified, it has to be
taken into account in `layout` method as well.
The fact that `layout` method was called is now recorded in a dedicated
member variable, `IsLaidOut`. `Entries != 0` can no longer be used to
reliably check if `layout` method was called because it may be zero for
a different reason: the terminator wasn't specified and all added
sequences (if any) were empty.
This reduces the size of `*LaneMaskLists` and `*SubRegIdxLists` a bit
and resolves the removed TODO.
Commit: c57a8f5b3fa7a7524346595cdc1ddd5eec4a41ae
https://github.com/llvm/llvm-project/commit/c57a8f5b3fa7a7524346595cdc1ddd5eec4a41ae
Author: Krzysztof Parzyszek <Krzysztof.Parzyszek at amd.com>
Date: 2024-12-13 (Fri, 13 Dec 2024)
Changed paths:
M flang/lib/Semantics/check-omp-structure.cpp
Log Message:
-----------
[flang][OpenMP] Remove redundant `Fortran::` from namespaces, NFC
Apply clang-format after the changes.
Commit: 7db20a026b71797975f277a406b604def1da6219
https://github.com/llvm/llvm-project/commit/7db20a026b71797975f277a406b604def1da6219
Author: Brox Chen <guochen2 at amd.com>
Date: 2024-12-13 (Fri, 13 Dec 2024)
Changed paths:
M llvm/test/MC/AMDGPU/gfx11_asm_vop1.s
M llvm/test/MC/AMDGPU/gfx11_asm_vop1_dpp16.s
M llvm/test/MC/AMDGPU/gfx11_asm_vop1_dpp8.s
M llvm/test/MC/AMDGPU/gfx11_asm_vop3_dpp16_from_vop1.s
M llvm/test/MC/AMDGPU/gfx11_asm_vop3_dpp8_from_vop1.s
M llvm/test/MC/AMDGPU/gfx11_asm_vop3_from_vop1.s
M llvm/test/MC/AMDGPU/gfx12_asm_vop1.s
M llvm/test/MC/AMDGPU/gfx12_asm_vop1_dpp16.s
M llvm/test/MC/AMDGPU/gfx12_asm_vop1_dpp8.s
M llvm/test/MC/AMDGPU/gfx12_asm_vop3_from_vop1.s
M llvm/test/MC/AMDGPU/gfx12_asm_vop3_from_vop1_dpp16.s
M llvm/test/MC/AMDGPU/gfx12_asm_vop3_from_vop1_dpp8.s
Log Message:
-----------
[AMDGPU][True16][MC] update vop1 mc test with update script (#119778)
This is a NFC change. Update gfx11/gfx12 vop1 test file with the latest
update_mc_test_script.py.
Changing the runline of gfx12_asm_vop1.s since llvm.cfg cannot be read
by the update script.
This is also preparing for the up-coming true16 change.
Commit: 939c94bbb4731aa1c7dda47b0e4497a82ae6f46a
https://github.com/llvm/llvm-project/commit/939c94bbb4731aa1c7dda47b0e4497a82ae6f46a
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2024-12-13 (Fri, 13 Dec 2024)
Changed paths:
M .github/workflows/containers/github-action-ci/Dockerfile
Log Message:
-----------
[Github] Bump CI container to LLVM 19.1.5 (#119809)
Bump the CI container version to the latest release.
Commit: 0d9fc1743378c73012828698122c46dc580d29eb
https://github.com/llvm/llvm-project/commit/0d9fc1743378c73012828698122c46dc580d29eb
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-12-13 (Fri, 13 Dec 2024)
Changed paths:
M llvm/include/llvm/CodeGen/LowLevelTypeUtils.h
M llvm/include/llvm/CodeGen/TargetLowering.h
M llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
M llvm/lib/CodeGen/GlobalISel/CombinerHelperCasts.cpp
M llvm/lib/CodeGen/GlobalISel/LoadStoreOpt.cpp
M llvm/lib/CodeGen/LowLevelTypeUtils.cpp
M llvm/lib/CodeGen/TargetLoweringBase.cpp
Log Message:
-----------
[GISel] Remove unused DataLayout operand from getApproximateEVTForLLT (#119833)
Commit: 3fcc302af34f648fb7a56557b6a504fcbf49a115
https://github.com/llvm/llvm-project/commit/3fcc302af34f648fb7a56557b6a504fcbf49a115
Author: Adrian Prantl <aprantl at apple.com>
Date: 2024-12-13 (Fri, 13 Dec 2024)
Changed paths:
M lldb/source/Expression/FunctionCaller.cpp
M lldb/source/Expression/UserExpression.cpp
A lldb/test/Shell/Expr/TestExecProgress.test
Log Message:
-----------
[lldb] Add a progress event for executing an expression (#119757)
Expressions can take arbitrary amounts of time to run, so IDEs might
want to be informed about the fact that an expression is currently being
executed.
rdar://141253078
Commit: 003a721c1c9e3a99d6d0c1a6755443b260235537
https://github.com/llvm/llvm-project/commit/003a721c1c9e3a99d6d0c1a6755443b260235537
Author: Ian Wood <ianwood2024 at u.northwestern.edu>
Date: 2024-12-13 (Fri, 13 Dec 2024)
Changed paths:
M llvm/include/llvm/Support/TypeName.h
Log Message:
-----------
[NFC] Don't recompute type name (#119631)
This change uses a local static variable to cache the computed
`StringRef` containing the type's name.
I found that `RelWithDebInfo` builds of MLIR were spending a relatively
large amount of time in `StringRef::find` and I tracked it down to
`getTypeName` which utilizes `StringRef` methods that are defined in a
separate translation unit. This is especially impactful on perf because
`getTypeName` is supposed to be used for debug logging. See an example
here:
https://github.com/llvm/llvm-project/blob/4b825c7417f72ee88ee3e4316d0c01ed463f1241/mlir/include/mlir/IR/Types.h#L294-L300
Commit: 6d69d18437adc79ada8fbc852b3ffb4d797cebb4
https://github.com/llvm/llvm-project/commit/6d69d18437adc79ada8fbc852b3ffb4d797cebb4
Author: erichkeane <ekeane at nvidia.com>
Date: 2024-12-13 (Fri, 13 Dec 2024)
Changed paths:
M clang/lib/Sema/SemaOpenACC.cpp
M clang/test/AST/ast-print-openacc-data-construct.cpp
A clang/test/SemaOpenACC/data-construct-attach-ast.cpp
A clang/test/SemaOpenACC/data-construct-attach-clause.c
M clang/test/SemaOpenACC/data-construct.cpp
Log Message:
-----------
[OpenACC] enable 'attach' clause sema for 'data' and 'enter data'
This is very similar to deviceptr, and is the same implementation as for
combined/compute constructs, so this just enables that, and adds tests.
Commit: bc627a46a858ab1abf7a72a524ef1059b27cfa37
https://github.com/llvm/llvm-project/commit/bc627a46a858ab1abf7a72a524ef1059b27cfa37
Author: Paul Kirth <paulkirth at google.com>
Date: 2024-12-13 (Fri, 13 Dec 2024)
Changed paths:
M clang-tools-extra/test/clang-doc/templates.cpp
Log Message:
-----------
[clang-doc][NFC] Rename CHECK prefix for YAML
We plan to introduce checks for other backends, like markdown.
Reviewers: PeterChou1, petrhosek
Reviewed By: petrhosek
Pull Request: https://github.com/llvm/llvm-project/pull/119810
Commit: b8569528865afec30b91f41cb2e670adea8f95bd
https://github.com/llvm/llvm-project/commit/b8569528865afec30b91f41cb2e670adea8f95bd
Author: Paul Kirth <paulkirth at google.com>
Date: 2024-12-13 (Fri, 13 Dec 2024)
Changed paths:
M clang-tools-extra/test/clang-doc/templates.cpp
Log Message:
-----------
[clang-doc][NFC] Make test resilient to line changes (#119811)
This just reorganizes the test code, so its easy to use @LINE directives
in the test, and avoid needing to update all the line numbers when
making unrelated changes.
Commit: 7d764db9bed1659cfcb2ab18e1d966388c1b5041
https://github.com/llvm/llvm-project/commit/7d764db9bed1659cfcb2ab18e1d966388c1b5041
Author: Paul Kirth <paulkirth at google.com>
Date: 2024-12-13 (Fri, 13 Dec 2024)
Changed paths:
M clang-tools-extra/test/clang-doc/templates.cpp
Log Message:
-----------
[clang-doc][NFC] Avoid unnecessary operations in the template test (#119812)
Commit: 5747ad4392954ebb0046e6397f32256f3cd6fd1e
https://github.com/llvm/llvm-project/commit/5747ad4392954ebb0046e6397f32256f3cd6fd1e
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2024-12-13 (Fri, 13 Dec 2024)
Changed paths:
M .github/workflows/docs.yml
Log Message:
-----------
[Github] Test docs action on workflow changes (#119627)
This patch makes the check docs build workflow run testing on all of the
docs builds when the workflow is changed. This is intended to catch
issues like those that were not caught premerge when adding in the
functionality to download the built docs.
Commit: 52e25912f875dfddef212ec9152ed86057d5d618
https://github.com/llvm/llvm-project/commit/52e25912f875dfddef212ec9152ed86057d5d618
Author: Paul Kirth <paulkirth at google.com>
Date: 2024-12-13 (Fri, 13 Dec 2024)
Changed paths:
M clang-tools-extra/test/clang-doc/templates.cpp
Log Message:
-----------
[clang-doc] Add tests for Markdown output with C++ templates
Reviewers: PeterChou1, petrhosek
Reviewed By: petrhosek
Pull Request: https://github.com/llvm/llvm-project/pull/119813
Commit: e113a72562e8a7e4493a1de0da01776945d0db74
https://github.com/llvm/llvm-project/commit/e113a72562e8a7e4493a1de0da01776945d0db74
Author: Paul Kirth <paulkirth at google.com>
Date: 2024-12-13 (Fri, 13 Dec 2024)
Changed paths:
M clang-tools-extra/test/clang-doc/templates.cpp
Log Message:
-----------
[clang-doc] Precommit test case for functions with templated parameters and return
To address #67549 we need a test case that will show up in the markdown
output for functions.
Reviewers: PeterChou1, petrhosek
Reviewed By: petrhosek
Pull Request: https://github.com/llvm/llvm-project/pull/119814
Commit: 229d78de31467f623e33716a30cb0c6d285d7683
https://github.com/llvm/llvm-project/commit/229d78de31467f623e33716a30cb0c6d285d7683
Author: Paul Kirth <paulkirth at google.com>
Date: 2024-12-13 (Fri, 13 Dec 2024)
Changed paths:
M clang-tools-extra/clang-doc/MDGenerator.cpp
M clang-tools-extra/test/clang-doc/templates.cpp
Log Message:
-----------
[clang-doc] Use QualName in Markdown output
QualName will provide the more useful typename when the type is
templated.
Fixes #67549
Reviewers: petrhosek, PeterChou1
Reviewed By: petrhosek
Pull Request: https://github.com/llvm/llvm-project/pull/119815
Commit: a44915a8e55fae93da17f9ae2ca26f745e1f6f7d
https://github.com/llvm/llvm-project/commit/a44915a8e55fae93da17f9ae2ca26f745e1f6f7d
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2024-12-13 (Fri, 13 Dec 2024)
Changed paths:
A .github/workflows/build-ci-container-windows.yml
A .github/workflows/containers/github-action-ci-windows/Dockerfile
Log Message:
-----------
[Github] Add a windows CI container (#118206)
This patch adds a windows CI container mostly based off of the existing
container used for Buildkite
(https://github.com/google/llvm-premerge-checks/blob/a687e33c37fbdcf67b52805c8cf3a8ed145e3243/containers/buildkite-windows/Dockerfile#L1).
This is intended to be a starting point as we transition to Github
Actions with the eventual plan being to build a custom windows toolchain
similar to what we do on Linux.
Commit: da439d3af47b6004cfed1482b84713fad4b43206
https://github.com/llvm/llvm-project/commit/da439d3af47b6004cfed1482b84713fad4b43206
Author: Han-Kuan Chen <hankuan.chen at sifive.com>
Date: 2024-12-14 (Sat, 14 Dec 2024)
Changed paths:
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
Log Message:
-----------
[SLP] NFC. Refactor getEntryCost and isReverseOrder usage. (#119680)
Users should check whether an input is empty before using
isReverseOrder.
Commit: 27d09e683f59707e82be0500930fbab1c82a29b4
https://github.com/llvm/llvm-project/commit/27d09e683f59707e82be0500930fbab1c82a29b4
Author: vporpo <vporpodas at google.com>
Date: 2024-12-13 (Fri, 13 Dec 2024)
Changed paths:
M llvm/include/llvm/SandboxIR/Instruction.h
Log Message:
-----------
[SandboxIR] Make some instruction constructors private (#119901)
This patch changes the visibility of the constructors of CatchSwitchInst
ResumeInst and SwitchInst to private instead of public. This is similar
to all other Sandbox IR instructions. The constructor is private to
force the user go through the Context create* API.
The issue was exposed by:
https://github.com/llvm/llvm-project/pull/119824
Commit: f01b62ad4881e61dc5d84e1faa984917ac43453c
https://github.com/llvm/llvm-project/commit/f01b62ad4881e61dc5d84e1faa984917ac43453c
Author: Kazu Hirata <kazu at google.com>
Date: 2024-12-13 (Fri, 13 Dec 2024)
Changed paths:
M llvm/lib/CodeGen/GlobalISel/CombinerHelperCasts.cpp
M llvm/lib/CodeGen/GlobalISel/LoadStoreOpt.cpp
Log Message:
-----------
[GlobalISel] Fix warnings
This patch fixes:
llvm/lib/CodeGen/GlobalISel/CombinerHelperCasts.cpp:167:21: error:
unused variable 'DL' [-Werror,-Wunused-variable]
llvm/lib/CodeGen/GlobalISel/LoadStoreOpt.cpp:320:15: error: unused
variable 'DL' [-Werror,-Wunused-variable]
Commit: 668d9688ac8aa97d9156cecabd25bf2a8e82bc9d
https://github.com/llvm/llvm-project/commit/668d9688ac8aa97d9156cecabd25bf2a8e82bc9d
Author: Sudharsan Veeravalli <quic_svs at quicinc.com>
Date: 2024-12-14 (Sat, 14 Dec 2024)
Changed paths:
M clang/test/Driver/print-supported-extensions-riscv.c
M llvm/docs/RISCVUsage.rst
M llvm/docs/ReleaseNotes.md
M llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
M llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
M llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
M llvm/lib/Target/RISCV/RISCVFeatures.td
M llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
M llvm/lib/TargetParser/RISCVISAInfo.cpp
M llvm/test/CodeGen/RISCV/attributes.ll
A llvm/test/MC/RISCV/xqcilsm-aliases-valid.s
A llvm/test/MC/RISCV/xqcilsm-invalid.s
A llvm/test/MC/RISCV/xqcilsm-valid.s
M llvm/unittests/TargetParser/RISCVISAInfoTest.cpp
Log Message:
-----------
[RISCV] Add Qualcomm uC Xqcilsm (Load Store Multiple) extension (#119823)
This extension adds 6 instructions that can do multi-word load/store.
The current spec can be found at:
https://github.com/quic/riscv-unified-db/releases/latest
This patch adds assembler only support.
Commit: 003eb5e80d8c970c2ae7fcbaaebd52b32a61648d
https://github.com/llvm/llvm-project/commit/003eb5e80d8c970c2ae7fcbaaebd52b32a61648d
Author: erichkeane <ekeane at nvidia.com>
Date: 2024-12-13 (Fri, 13 Dec 2024)
Changed paths:
M clang/include/clang/AST/OpenACCClause.h
M clang/include/clang/Basic/OpenACCClauses.def
M clang/lib/AST/OpenACCClause.cpp
M clang/lib/AST/StmtProfile.cpp
M clang/lib/AST/TextNodeDumper.cpp
M clang/lib/Sema/SemaOpenACC.cpp
M clang/lib/Sema/TreeTransform.h
M clang/lib/Serialization/ASTReader.cpp
M clang/lib/Serialization/ASTWriter.cpp
M clang/test/AST/ast-print-openacc-data-construct.cpp
M clang/test/ParserOpenACC/parse-clauses.c
M clang/test/SemaOpenACC/combined-construct-auto_seq_independent-clauses.c
M clang/test/SemaOpenACC/combined-construct-device_type-clause.c
M clang/test/SemaOpenACC/compute-construct-device_type-clause.c
A clang/test/SemaOpenACC/data-construct-finalize-ast.cpp
A clang/test/SemaOpenACC/data-construct-finalize-clause.c
M clang/test/SemaOpenACC/data-construct.cpp
M clang/test/SemaOpenACC/loop-construct-auto_seq_independent-clauses.c
M clang/test/SemaOpenACC/loop-construct-device_type-clause.c
M clang/tools/libclang/CIndex.cpp
Log Message:
-----------
[OpenACC] Implement 'finalize' clause sema
This is a very simple clause as far as sema is concerned. It is only
valid on 'exit data', and doesn't have any rules involving it, so it is
simply applied and passed onto the MLIR.
Commit: 5cac0eb4b4156ed7e2dae2a73af04484cf330ddb
https://github.com/llvm/llvm-project/commit/5cac0eb4b4156ed7e2dae2a73af04484cf330ddb
Author: Ian Wood <ianwood2024 at u.northwestern.edu>
Date: 2024-12-13 (Fri, 13 Dec 2024)
Changed paths:
M llvm/include/llvm/Support/TypeName.h
Log Message:
-----------
[Support] Fix getTypeNameImpl on msvc (#119910)
Updates `Key` to reflect the new name of the function enclosing
`__FUNCSIG__`.
Commit: 3b3394baec18d77e8d5b984882c82f7b3a59f981
https://github.com/llvm/llvm-project/commit/3b3394baec18d77e8d5b984882c82f7b3a59f981
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-12-13 (Fri, 13 Dec 2024)
Changed paths:
M llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
M llvm/test/CodeGen/RISCV/rvv/vmsgeu.ll
Log Message:
-----------
[RISCV] Use Log2SEW=0 for VMNAND/VMSET created for riscv_vmsge(u) intrinsics. (#119767)
These instructions should always be created with Log2SEW=0 and an LMUL
based on SEW=8. This is used by the vsetvli pass to know these
instructions only care about the ratio and not the specific value.
Looks like I fixed riscv_vmsge(u)_mask intrinsics years ago, but forgot
the unmasked intrinsics.
I'm working on an enhancement to our MachineVerifier checks that will
require VMNAND and VMSET to have Log2SEW=0.
Commit: d1f51c67fde6f77b78f78901fb78e3589430a299
https://github.com/llvm/llvm-project/commit/d1f51c67fde6f77b78f78901fb78e3589430a299
Author: Sergei Barannikov <barannikov88 at gmail.com>
Date: 2024-12-13 (Fri, 13 Dec 2024)
Changed paths:
M llvm/utils/TableGen/Common/CodeGenDAGPatterns.cpp
M llvm/utils/TableGen/Common/CodeGenDAGPatterns.h
M llvm/utils/TableGen/DAGISelEmitter.cpp
M llvm/utils/TableGen/DAGISelMatcherGen.cpp
M llvm/utils/TableGen/FastISelEmitter.cpp
M llvm/utils/TableGen/GlobalISelEmitter.cpp
Log Message:
-----------
[TableGen] Add TreePatternNode::children and use it in for loops (NFC) (#119877)
Commit: 9474e09459189fbed30f329a669f9c14979c5367
https://github.com/llvm/llvm-project/commit/9474e09459189fbed30f329a669f9c14979c5367
Author: Louis Dionne <ldionne.2 at gmail.com>
Date: 2024-12-13 (Fri, 13 Dec 2024)
Changed paths:
M libcxx/include/CMakeLists.txt
M libcxx/include/__hash_table
M libcxx/include/__memory/allocator.h
M libcxx/include/__memory/builtin_new_allocator.h
M libcxx/include/__memory/construct_at.h
M libcxx/include/__memory/shared_ptr.h
M libcxx/include/__memory/uninitialized_algorithms.h
A libcxx/include/__new/align_val_t.h
A libcxx/include/__new/allocate.h
A libcxx/include/__new/destroying_delete_t.h
A libcxx/include/__new/exceptions.h
A libcxx/include/__new/global_new_delete.h
A libcxx/include/__new/interference_size.h
A libcxx/include/__new/launder.h
A libcxx/include/__new/new_handler.h
A libcxx/include/__new/nothrow_t.h
A libcxx/include/__new/placement_new_delete.h
M libcxx/include/__utility/small_buffer.h
M libcxx/include/array
M libcxx/include/charconv
M libcxx/include/forward_list
M libcxx/include/future
M libcxx/include/list
M libcxx/include/module.modulemap
M libcxx/include/new
M libcxx/test/libcxx/transitive_includes/cxx03.csv
M libcxx/test/libcxx/transitive_includes/cxx11.csv
M libcxx/test/libcxx/transitive_includes/cxx14.csv
M libcxx/test/libcxx/transitive_includes/cxx23.csv
M libcxx/test/libcxx/transitive_includes/cxx26.csv
M libcxx/test/std/language.support/support.dynamic/alloc.errors/bad.alloc/bad_alloc.pass.cpp
M libcxx/test/std/language.support/support.dynamic/new.delete/new.delete.placement/new_array.pass.cpp
M libcxx/test/std/language.support/support.dynamic/ptr.launder/launder.types.verify.cpp
M libcxx/test/std/utilities/memory/default.allocator/allocator.members/allocate.size.pass.cpp
M libcxxabi/test/cxa_vec_new_overflow_PR41395.pass.cpp
Log Message:
-----------
[libc++] Granularize the <new> header (#119270)
This disentangles the code which previously had a mix of many #ifdefs, a
non-versioned namespace and a versioned namespace. It also makes it
clearer which parts of <new> are implemented on Windows by including <new.h>.
Commit: 2135babe28b038c99d77f15c39b3f7e498fc6694
https://github.com/llvm/llvm-project/commit/2135babe28b038c99d77f15c39b3f7e498fc6694
Author: Louis Dionne <ldionne.2 at gmail.com>
Date: 2024-12-13 (Fri, 13 Dec 2024)
Changed paths:
M libcxx/utils/libcxx/test/format.py
Log Message:
-----------
[libc++] Save benchmark results in a json file (#119761)
When running a benchmark, also save the benchmark results in a JSON
file. That is cheap to do and useful to compare benchmark results
between different runs.
Commit: 64da33a58923e60a5c7854c1a13e14f16d01b1f0
https://github.com/llvm/llvm-project/commit/64da33a58923e60a5c7854c1a13e14f16d01b1f0
Author: Peter Collingbourne <peter at pcc.me.uk>
Date: 2024-12-13 (Fri, 13 Dec 2024)
Changed paths:
M lld/ELF/Config.h
M lld/ELF/Driver.cpp
M lld/ELF/Options.td
M lld/ELF/OutputSections.h
M lld/ELF/SyntheticSections.cpp
M lld/ELF/SyntheticSections.h
M lld/ELF/Writer.cpp
M lld/docs/ld.lld.1
A lld/test/ELF/randomize-section-padding.test
Log Message:
-----------
ELF: Introduce --randomize-section-padding option.
The --randomize-section-padding option randomly inserts padding between
input sections using the given seed. It is intended to be used in A/B
experiments to determine the average effect of a change on program
performance, while controlling for effects such as false sharing in
the cache which may introduce measurement bias. For more details,
see the RFC:
https://discourse.llvm.org/t/rfc-lld-feature-for-controlling-for-code-size-dependent-measurement-bias/83334
Reviewers: smithp35, MaskRay
Reviewed By: MaskRay, smithp35
Pull Request: https://github.com/llvm/llvm-project/pull/117653
Commit: 52e9f2c52cd1d0ffa922761458abc35cd90057ea
https://github.com/llvm/llvm-project/commit/52e9f2c52cd1d0ffa922761458abc35cd90057ea
Author: Djordje Todorovic <56676939+djtodoro at users.noreply.github.com>
Date: 2024-12-13 (Fri, 13 Dec 2024)
Changed paths:
M clang/test/Driver/riscv-cpus.c
M clang/test/Misc/target-invalid-cpu-note/riscv.c
M llvm/docs/ReleaseNotes.md
M llvm/lib/Target/RISCV/RISCVFeatures.td
M llvm/lib/Target/RISCV/RISCVProcessors.td
Log Message:
-----------
[RISCV] Add MIPS P8700 processor (#119882)
The P8700 is a high-performance processor from MIPS designed to meet the
demands of modern workloads, offering exceptional scalability and
efficiency. It builds on MIPS's established architectural strengths
while introducing enhancements that set it apart. For more details, you
can check out the official product page here:
https://mips.com/products/hardware/p8700/.
Scheduling model will be added in a separate commit/PR.
Commit: 8ab6912831277d87838518c5f775f79d14616860
https://github.com/llvm/llvm-project/commit/8ab6912831277d87838518c5f775f79d14616860
Author: Yuxuan Chen <ych at fb.com>
Date: 2024-12-13 (Fri, 13 Dec 2024)
Changed paths:
A clang/test/Interpreter/Inputs/vector
M clang/test/Interpreter/crash.cpp
Log Message:
-----------
[Clang] Interpreter test should not depend on system header (#119903)
https://github.com/llvm/llvm-project/commit/30ad53b92cec0cff9679d559edcc5b933312ba0c
introduced a new test that includes `<vector>` from the system include
path without honoring environment variables that may provide the path to
C++ standard library. This is not supported in some CI systems because
we don't always have the C++ library in the standard location.
The conventional way of doing includes in the test is through `Inputs`
directory and pass it as an include path.
The `vector` file included in this patch has been shortened, but I have
verified that it works with this test. i.e. the clang repl crashes on
this test in the same way if the fix in
https://github.com/llvm/llvm-project/pull/117475 is reverted.
Commit: 9f2dd085ae981740e2986a1b200ca2a7df44953d
https://github.com/llvm/llvm-project/commit/9f2dd085ae981740e2986a1b200ca2a7df44953d
Author: klensy <klensy at users.noreply.github.com>
Date: 2024-12-13 (Fri, 13 Dec 2024)
Changed paths:
M mlir/lib/Interfaces/ValueBoundsOpInterface.cpp
Log Message:
-----------
[mlir] fix copypaste typos in asserts (#119878)
This fixes few copypaste typos
I've also spotted weird `getNumRows() == getNumRows()`: looks like
leftover after refactoring
https://github.com/llvm/llvm-project/blob/ea8e328ae2bea9d9a7d556ef4d791fa116f7de18/mlir/lib/Analysis/Presburger/Simplex.cpp#L107-L111
Co-authored-by: klensy <nightouser at gmail.com>
Commit: e5ab6e960745bfda9204e696a0a99746075f3021
https://github.com/llvm/llvm-project/commit/e5ab6e960745bfda9204e696a0a99746075f3021
Author: lntue <lntue at google.com>
Date: 2024-12-13 (Fri, 13 Dec 2024)
Changed paths:
M libc/docs/talks.rst
Log Message:
-----------
[libc][doc] Add links to LLVM dev meeting talks related to LLVM libc. (#119918)
Commit: 0f776f1df9ec6345f298cc19c33dfea7f98289ec
https://github.com/llvm/llvm-project/commit/0f776f1df9ec6345f298cc19c33dfea7f98289ec
Author: Chris Apple <cja-private at pm.me>
Date: 2024-12-13 (Fri, 13 Dec 2024)
Changed paths:
M clang/lib/CodeGen/BackendUtil.cpp
Log Message:
-----------
[rtsan][clang] NFC: Move rtsan init to addSanitizers (#119904)
Commit: 2244d2e75c50cdd4657ed6c488423790367e1347
https://github.com/llvm/llvm-project/commit/2244d2e75c50cdd4657ed6c488423790367e1347
Author: erichkeane <ekeane at nvidia.com>
Date: 2024-12-13 (Fri, 13 Dec 2024)
Changed paths:
M clang/include/clang/AST/OpenACCClause.h
M clang/include/clang/Basic/OpenACCClauses.def
M clang/lib/AST/OpenACCClause.cpp
M clang/lib/AST/StmtProfile.cpp
M clang/lib/AST/TextNodeDumper.cpp
M clang/lib/Sema/SemaOpenACC.cpp
M clang/lib/Sema/TreeTransform.h
M clang/lib/Serialization/ASTReader.cpp
M clang/lib/Serialization/ASTWriter.cpp
M clang/test/AST/ast-print-openacc-data-construct.cpp
M clang/test/ParserOpenACC/parse-clauses.c
M clang/test/SemaOpenACC/combined-construct-auto_seq_independent-clauses.c
M clang/test/SemaOpenACC/combined-construct-device_type-clause.c
M clang/test/SemaOpenACC/compute-construct-device_type-clause.c
A clang/test/SemaOpenACC/data-construct-if_present-ast.cpp
A clang/test/SemaOpenACC/data-construct-if_present-clause.c
M clang/test/SemaOpenACC/data-construct.cpp
M clang/test/SemaOpenACC/loop-construct-auto_seq_independent-clauses.c
M clang/test/SemaOpenACC/loop-construct-device_type-clause.c
M clang/tools/libclang/CIndex.cpp
Log Message:
-----------
[OpenACC] Implement 'if_present' clause sema
The 'if_present' clause controls the replacement of addresses in the
var-list in current device memory. This clause can only go on
'host_device'. From a Sema perspective, there isn't anything to do
beyond add this to AST and pass it on.
Commit: 2eed88da6a100216bf542e0c16762d336791876b
https://github.com/llvm/llvm-project/commit/2eed88da6a100216bf542e0c16762d336791876b
Author: Momchil Velikov <momchil.velikov at arm.com>
Date: 2024-12-13 (Fri, 13 Dec 2024)
Changed paths:
M clang/include/clang/Basic/arm_sve.td
A clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_fmla.c
M clang/test/Sema/aarch64-sve2-intrinsics/acle_sve2_fp8.c
M llvm/include/llvm/IR/IntrinsicsAArch64.td
M llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
M llvm/lib/Target/AArch64/SVEInstrFormats.td
A llvm/test/CodeGen/AArch64/fp8-sve-fmla.ll
Log Message:
-----------
[AArch64] Implement FP8 SVE intrinsics for fused multiply-add (#118126)
This patch adds the following intrinsics:
* 8-bit floating-point multiply-add long to half-precision (bottom).
// Only if (__ARM_FEATURE_SVE2 && __ARM_FEATURE_FP8FMA) ||
__ARM_FEATURE_SSVE_FP8FMA
svfloat16_t svmlalb[_f16_mf8]_fpm(svfloat16_t zda, svmfloat8_t zn,
svmfloat8_t zm, fpm_t fpm);
svfloat16_t svmlalb[_n_f16_mf8]_fpm(svfloat16_t zda, svmfloat8_t zn,
mfloat8_t zm, fpm_t fpm);
* 8-bit floating-point multiply-add long to half-precision (bottom,
indexed).
// Only if (__ARM_FEATURE_SVE2 && __ARM_FEATURE_FP8FMA) ||
__ARM_FEATURE_SSVE_FP8FMA
svfloat16_t svmlalb_lane[_f16_mf8]_fpm(svfloat16_t zda, svmfloat8_t zn,
svmfloat8_t zm,
uint64_t imm0_15, fpm_t fpm);
* 8-bit floating-point multiply-add long to half-precision (top).
// Only if (__ARM_FEATURE_SVE2 && __ARM_FEATURE_FP8FMA) ||
__ARM_FEATURE_SSVE_FP8FMA
svfloat16_t svmlalt[_f16_mf8]_fpm(svfloat16_t zda, svmfloat8_t zn,
svmfloat8_t zm, fpm_t fpm);
svfloat16_t svmlalt[_n_f16_mf8]_fpm(svfloat16_t zda, svmfloat8_t zn,
mfloat8_t zm, fpm_t fpm);
* 8-bit floating-point multiply-add long to half-precision (top,
indexed).
// Only if (__ARM_FEATURE_SVE2 && __ARM_FEATURE_FP8FMA) ||
__ARM_FEATURE_SSVE_FP8FMA
svfloat16_t svmlalt_lane[_f16_mf8]_fpm(svfloat16_t zda, svmfloat8_t zn,
svmfloat8_t zm,
uint64_t imm0_15, fpm_t fpm);
* 8-bit floating-point multiply-add long long to single-precision
(bottom bottom).
// Only if (__ARM_FEATURE_SVE2 && __ARM_FEATURE_FP8FMA) ||
__ARM_FEATURE_SSVE_FP8FMA
svfloat32_t svmlallbb[_f32_mf8]_fpm(svfloat32_t zda, svmfloat8_t zn,
svmfloat8_t zm, fpm_t fpm);
svfloat32_t svmlallbb[_n_f32_mf8]_fpm(svfloat32_t zda, svmfloat8_t zn,
mfloat8_t zm, fpm_t fpm);
* 8-bit floating-point multiply-add long long to single-precision
(bottom bottom, indexed).
// Only if (__ARM_FEATURE_SVE2 && __ARM_FEATURE_FP8FMA) ||
__ARM_FEATURE_SSVE_FP8FMA
svfloat32_t svmlallbb_lane[_f32_mf8]_fpm(svfloat32_t zda, svmfloat8_t
zn, svmfloat8_t zm,
uint64_t imm0_15, fpm_t fpm);
* 8-bit floating-point multiply-add long long to single-precision
(bottom top).
// Only if (__ARM_FEATURE_SVE2 && __ARM_FEATURE_FP8FMA) ||
__ARM_FEATURE_SSVE_FP8FMA
svfloat32_t svmlallbt[_f32_mf8]_fpm(svfloat32_t zda, svmfloat8_t zn,
svmfloat8_t zm, fpm_t fpm);
svfloat32_t svmlallbt[_n_f32_mf8]_fpm(svfloat32_t zda, svmfloat8_t zn,
mfloat8_t zm, fpm_t fpm);
* 8-bit floating-point multiply-add long long to single-precision
(bottom top, indexed).
// Only if (__ARM_FEATURE_SVE2 && __ARM_FEATURE_FP8FMA) ||
__ARM_FEATURE_SSVE_FP8FMA
svfloat32_t svmlallbt_lane[_f32_mf8]_fpm(svfloat32_t zda, svmfloat8_t
zn, svmfloat8_t zm,
uint64_t imm0_15, fpm_t fpm);
* 8-bit floating-point multiply-add long long to single-precision (top
bottom).
// Only if (__ARM_FEATURE_SVE2 && __ARM_FEATURE_FP8FMA) ||
__ARM_FEATURE_SSVE_FP8FMA
svfloat32_t svmlalltb[_f32_mf8]_fpm(svfloat32_t zda, svmfloat8_t zn,
svmfloat8_t zm, fpm_t fpm);
svfloat32_t svmlalltb[_n_f32_mf8]_fpm(svfloat32_t zda, svmfloat8_t zn,
mfloat8_t zm, fpm_t fpm);
* 8-bit floating-point multiply-add long long to single-precision (top
bottom, indexed).
// Only if (__ARM_FEATURE_SVE2 && __ARM_FEATURE_FP8FMA) ||
__ARM_FEATURE_SSVE_FP8FMA
svfloat32_t svmlalltb_lane[_f32_mf8]_fpm(svfloat32_t zda, svmfloat8_t
zn, svmfloat8_t zm,
uint64_t imm0_15, fpm_t fpm);
* 8-bit floating-point multiply-add long long to single-precision (top
top).
// Only if (__ARM_FEATURE_SVE2 && __ARM_FEATURE_FP8FMA) ||
__ARM_FEATURE_SSVE_FP8FMA
svfloat32_t svmlalltt[_f32_mf8]_fpm(svfloat32_t zda, svmfloat8_t zn,
svmfloat8_t zm, fpm_t fpm);
svfloat32_t svmlalltt[_n_f32_mf8]_fpm(svfloat32_t zda, svmfloat8_t zn,
mfloat8_t zm, fpm_t fpm);
* 8-bit floating-point multiply-add long long to single-precision (top
top, indexed).
// Only if (__ARM_FEATURE_SVE2 && __ARM_FEATURE_FP8FMA) ||
__ARM_FEATURE_SSVE_FP8FMA
svfloat32_t svmlalltt_lane[_f32_mf8]_fpm(svfloat32_t zda, svmfloat8_t
zn, svmfloat8_t zm,
uint64_t imm0_15, fpm_t fpm);
Commit: af5d3afff54e5af61f384a1e95020f0a0374caec
https://github.com/llvm/llvm-project/commit/af5d3afff54e5af61f384a1e95020f0a0374caec
Author: Slava Zakharin <szakharin at nvidia.com>
Date: 2024-12-13 (Fri, 13 Dec 2024)
Changed paths:
M flang/lib/Optimizer/HLFIR/Transforms/OptimizedBufferization.cpp
M flang/test/HLFIR/opt-array-slice-assign.fir
Log Message:
-----------
[flang] Improve disjoint/identical slices recognition in opt-bufferization. (#119780)
The changes are needed to be able to optimize
'x(9,:)=SUM(x(1:8,:),DIM=1)'
without a temporary array. This pattern exists in exchange2.
The patch also fixes an existing problem in Flang with this test:
```
program main
integer :: a(10) = (/1,2,3,4,5,6,7,8,9,10/)
integer :: expected(10) = (/1,10,9,8,7,6,5,4,3,2/)
print *, 'INPUT: ', a
print *, 'EXPECTED: ', expected
call test(a, 10, 2, 10, 9)
print *, 'RESULT: ', a
contains
subroutine test(a, size, x, y, z)
integer :: x, y, z, size
integer :: a(:)
a(x:y:1) = a(z:x-1:-1) + 1
end subroutine test
end program main
```
Commit: a00946fc947d42e67394934bc78b84a37ecc2908
https://github.com/llvm/llvm-project/commit/a00946fc947d42e67394934bc78b84a37ecc2908
Author: Slava Zakharin <szakharin at nvidia.com>
Date: 2024-12-13 (Fri, 13 Dec 2024)
Changed paths:
M flang/include/flang/Optimizer/Builder/HLFIRTools.h
M flang/lib/Optimizer/Builder/HLFIRTools.cpp
M flang/lib/Optimizer/HLFIR/Transforms/SimplifyHLFIRIntrinsics.cpp
M flang/test/HLFIR/simplify-hlfir-intrinsics-sum.fir
Log Message:
-----------
[flang] Simplify hlfir.sum total reductions. (#119482)
I am trying to switch to keeping the reduction value in a temporary
scalar location so that I can use hlfir::genLoopNest easily.
This also allows using omp.loop_nest with worksharing for OpenMP.
Commit: 2daadbdc5e3a6029092963a1c699675320745d70
https://github.com/llvm/llvm-project/commit/2daadbdc5e3a6029092963a1c699675320745d70
Author: Brox Chen <guochen2 at amd.com>
Date: 2024-12-13 (Fri, 13 Dec 2024)
Changed paths:
M llvm/test/MC/AMDGPU/gfx11_asm_vop1.s
M llvm/test/MC/AMDGPU/gfx11_asm_vop1_dpp16.s
M llvm/test/MC/AMDGPU/gfx11_asm_vop1_dpp8.s
M llvm/test/MC/AMDGPU/gfx11_asm_vop3_dpp16_from_vop1.s
M llvm/test/MC/AMDGPU/gfx11_asm_vop3_dpp8_from_vop1.s
M llvm/test/MC/AMDGPU/gfx11_asm_vop3_from_vop1.s
M llvm/test/MC/AMDGPU/gfx12_asm_vop1.s
M llvm/test/MC/AMDGPU/gfx12_asm_vop1_dpp16.s
M llvm/test/MC/AMDGPU/gfx12_asm_vop1_dpp8.s
M llvm/test/MC/AMDGPU/gfx12_asm_vop3_from_vop1.s
M llvm/test/MC/AMDGPU/gfx12_asm_vop3_from_vop1_dpp16.s
M llvm/test/MC/AMDGPU/gfx12_asm_vop3_from_vop1_dpp8.s
Log Message:
-----------
[AMDGPU][true16] [MC] Remove duplication in VOP1 test (#119905)
This is a NFC change. Remove duplicated test line in gfx11/gfx12 vop1
test file with the latest update_mc_test_script.py --unique option
This is also preparing for the up-coming true16 change
Commit: b560b87ba1d85a4262d24386eb7e9a8f7b8086f5
https://github.com/llvm/llvm-project/commit/b560b87ba1d85a4262d24386eb7e9a8f7b8086f5
Author: Maksim Panchenko <maks at fb.com>
Date: 2024-12-13 (Fri, 13 Dec 2024)
Changed paths:
M bolt/lib/Core/BinaryEmitter.cpp
M bolt/lib/Rewrite/RewriteInstance.cpp
Log Message:
-----------
[BOLT] Clean up jump table handling in non-reloc mode. NFCI (#119614)
This change affects non-relocation mode only. Prior to having
CheckLargeFunctions pass, we could have emitted code for functions that
was discarded at the end due to size limitations. Since we didn't know
at the time of emission if the code would be discarded or not, we had to
emit jump tables in separate sections and handle them separately.
However, now we always run CheckLargeFunctions and make sure all emitted
code is used. Thus, we can get rid of the special jump table handling.
Commit: 82459ecf3ebbc697bdde265320d126773111ae0f
https://github.com/llvm/llvm-project/commit/82459ecf3ebbc697bdde265320d126773111ae0f
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-12-13 (Fri, 13 Dec 2024)
Changed paths:
M llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
M llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
M llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
M llvm/test/CodeGen/RISCV/rvv/rvv-peephole-vmerge-to-vmv.mir
Log Message:
-----------
[RISCV] Split OPERAND_SEW operand type for mask only instructions. (#119776)
Mask only instructions like vmand and vmsbf should always have 0 for
their Log2SEW operand. Non-mask instructions should only have
3, 4, 5, or 6 for their Log2SEW operand.
Split the operand type so we can verify these cases separately.
I had to fix the SEW for whole register move to vmv.v.v copy
optimization and update an mir test. The vmv.v.v change isn't
functional since we have already done vsetvli insertion before and
nothing else uses the field after copy expansion. I can split these
changes off if desired.
Commit: 5f72f2c8fd6cf59c9f2066c58559a9a9d2888a9a
https://github.com/llvm/llvm-project/commit/5f72f2c8fd6cf59c9f2066c58559a9a9d2888a9a
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2024-12-14 (Sat, 14 Dec 2024)
Changed paths:
M llvm/lib/Target/AMDGPU/SOPInstructions.td
M llvm/lib/Target/AMDGPU/VOP3Instructions.td
Log Message:
-----------
AMDGPU: Remove large, negative AddedComplexity from minimum/maximum patterns (#119795)
Commit: c4a78b6fe32d72d5c9f3b4a4fa2be206675ccd05
https://github.com/llvm/llvm-project/commit/c4a78b6fe32d72d5c9f3b4a4fa2be206675ccd05
Author: Florian Hahn <flo at fhahn.com>
Date: 2024-12-13 (Fri, 13 Dec 2024)
Changed paths:
M llvm/lib/Transforms/Utils/SimplifyCFG.cpp
M llvm/test/Transforms/SimplifyCFG/hoist-dbgvalue.ll
M llvm/test/Transforms/SimplifyCFG/hoisting-metadata.ll
Log Message:
-----------
[SimplifyCFG] Always allow hoisting if all instructions match. (#97158)
Generalize hoistCommonCodeFromSuccessors's `EqTermsOnly` to
`AllInstsEqOnly` and always allow hoisting if all instructions match.
In that case, all instructions can be hoisted and the
original branch will be replaced and selects for PHIs are added. This
allows preserving metadata in more cases, using the existing hoisting
logic, whereas previously FoldTwoEntryPHINode would drop the metadata.
https://llvm-compile-time-tracker.com/compare.php?from=716360367fbdabac2c374c19b8746f4de49a5599&to=986b2c47df516b31d998c055400e4f62aa76edc6&stat=instructions:u
PR: https://github.com/llvm/llvm-project/pull/97158
Commit: e5e0f23ae8e97eb910cb8ae42373f354eee496c7
https://github.com/llvm/llvm-project/commit/e5e0f23ae8e97eb910cb8ae42373f354eee496c7
Author: Kirill Stoimenov <87100199+kstoimenov at users.noreply.github.com>
Date: 2024-12-13 (Fri, 13 Dec 2024)
Changed paths:
M compiler-rt/lib/ubsan_minimal/ubsan_minimal_handlers.cpp
Log Message:
-----------
[nfc][ubsan-minimal] Refactor error reporting to use a single function (#119920)
This refactoring will allow to make this function weak later on so that
it could be overloaded by a client. See #119242.
Commit: 3273d0bb148795ead4d6e29177bd63346bb6362a
https://github.com/llvm/llvm-project/commit/3273d0bb148795ead4d6e29177bd63346bb6362a
Author: Valentin Clement (バレンタイン クレメン) <clementval at gmail.com>
Date: 2024-12-13 (Fri, 13 Dec 2024)
Changed paths:
M flang/lib/Semantics/resolve-names.cpp
M flang/test/Semantics/modfile55.cuf
Log Message:
-----------
[flang][cuda] Apply implicit data attribute only in device context (#119919)
Fix the condition so the implicit device data attribute is not applied
when the routine has `attribute(host)`
Commit: 3351b3bf8dcb9aebfa6f491fcbe5a00acbcc3291
https://github.com/llvm/llvm-project/commit/3351b3bf8dcb9aebfa6f491fcbe5a00acbcc3291
Author: erichkeane <ekeane at nvidia.com>
Date: 2024-12-13 (Fri, 13 Dec 2024)
Changed paths:
M clang/include/clang/AST/OpenACCClause.h
M clang/include/clang/Basic/OpenACCClauses.def
M clang/include/clang/Sema/SemaOpenACC.h
M clang/lib/AST/OpenACCClause.cpp
M clang/lib/AST/StmtProfile.cpp
M clang/lib/AST/TextNodeDumper.cpp
M clang/lib/Parse/ParseOpenACC.cpp
M clang/lib/Sema/SemaOpenACC.cpp
M clang/lib/Sema/TreeTransform.h
M clang/lib/Serialization/ASTReader.cpp
M clang/lib/Serialization/ASTWriter.cpp
M clang/test/AST/ast-print-openacc-data-construct.cpp
M clang/test/ParserOpenACC/parse-clauses.c
M clang/test/SemaOpenACC/combined-construct-auto_seq_independent-clauses.c
M clang/test/SemaOpenACC/combined-construct-device_type-clause.c
M clang/test/SemaOpenACC/compute-construct-device_type-clause.c
A clang/test/SemaOpenACC/data-construct-detach-ast.cpp
A clang/test/SemaOpenACC/data-construct-detach-clause.c
M clang/test/SemaOpenACC/data-construct.cpp
M clang/test/SemaOpenACC/loop-construct-auto_seq_independent-clauses.c
M clang/test/SemaOpenACC/loop-construct-device_type-clause.c
M clang/tools/libclang/CIndex.cpp
Log Message:
-----------
[OpenACC] implement 'detach' clause sema
This is another new clause specific to 'exit data' that takes a pointer
argument. This patch implements this the same way we do a few other
clauses (like attach) that have the same restrictions.
Commit: ab07c51534b904bab55bcaaf950823fc72719b11
https://github.com/llvm/llvm-project/commit/ab07c51534b904bab55bcaaf950823fc72719b11
Author: Kazu Hirata <kazu at google.com>
Date: 2024-12-13 (Fri, 13 Dec 2024)
Changed paths:
M llvm/unittests/ProfileData/MemProfTest.cpp
Log Message:
-----------
[memprof] Don't use Frame::hash() (NFC) (#119828)
In these tests, we just want to add one instance of
IndexedMemProfRecord to MemProfData.Records and retrieve it from
MemProfReader. There is no particular reason to associate F1.hash()
with the IndexedMemProfRecord instance. A fake value suffices.
While I am at it, I'm switching to try_emplace so that I can move
FakeRecord.
Commit: cd093c2e1bac35dd2c6b914d0b64ce56683cb50a
https://github.com/llvm/llvm-project/commit/cd093c2e1bac35dd2c6b914d0b64ce56683cb50a
Author: Kazu Hirata <kazu at google.com>
Date: 2024-12-13 (Fri, 13 Dec 2024)
Changed paths:
M llvm/include/llvm/ProfileData/InstrProfWriter.h
Log Message:
-----------
[memprof] Make InstrProfwriter::addMemProfRecord and its friends private (NFC) (#119831)
This patch makes the following functions private:
- InstrProfWriter::addMemProfRecord
- InstrProfWriter::addMemProfFrame
- InstrProfWriter::addMemProfCallStack
These days, we add MemProf profile to the writer context via
addMemProfData. We no longer add individual items.
Commit: 5528388e3664c6d7d292f20a739f1bf1c8ef768d
https://github.com/llvm/llvm-project/commit/5528388e3664c6d7d292f20a739f1bf1c8ef768d
Author: Ramkumar Ramachandra <ramkumar.ramachandra at codasip.com>
Date: 2024-12-13 (Fri, 13 Dec 2024)
Changed paths:
M llvm/include/llvm/IR/CmpPredicate.h
M llvm/lib/IR/Instructions.cpp
M llvm/lib/Transforms/Scalar/EarlyCSE.cpp
A llvm/test/Transforms/EarlyCSE/pr119893.ll
Log Message:
-----------
EarlyCSE: fix CmpPredicate duplicate-hashing (#119902)
Strip hash_value() for CmpPredicate, as different callers have different
hashing use-cases. In this case, there is just one caller, namely
EarlyCSE, which calls hash_combine() on a CmpPredicate, which used to
call hash_combine() on a CmpInst::Predicate prior to 4a0d53a
(PatternMatch: migrate to CmpPredicate). This has uncovered a bug where
two icmp instructions differing in just the fact that one of them has
the samesign flag on it are hashed differently, leading to divergent
hashing, and a crash. Fix this crash by dropping samesign information on
icmp instructions before hashing them, preserving the former behavior.
Fixes #119893.
Commit: 537e0e1ff639ed4f8fa4dadbc84f4a6a12e1d20a
https://github.com/llvm/llvm-project/commit/537e0e1ff639ed4f8fa4dadbc84f4a6a12e1d20a
Author: Luke Quinn <quic_lquinn at quicinc.com>
Date: 2024-12-13 (Fri, 13 Dec 2024)
Changed paths:
M llvm/lib/Target/RISCV/RISCVInstrInfo.td
M llvm/test/CodeGen/RISCV/GlobalISel/double-arith.ll
M llvm/test/CodeGen/RISCV/GlobalISel/double-intrinsics.ll
M llvm/test/CodeGen/RISCV/GlobalISel/fp128.ll
M llvm/test/CodeGen/RISCV/GlobalISel/rv64zba.ll
Log Message:
-----------
[RISCV][GISel] Added GISelPredicateCodes to LeadingOnes*Mask (#119886)
Commit: 1345ee4232c90205f152154cfd557c54feb3853d
https://github.com/llvm/llvm-project/commit/1345ee4232c90205f152154cfd557c54feb3853d
Author: Valentin Clement (バレンタイン クレメン) <clementval at gmail.com>
Date: 2024-12-13 (Fri, 13 Dec 2024)
Changed paths:
M flang/lib/Semantics/resolve-names.cpp
M flang/test/Semantics/modfile55.cuf
Log Message:
-----------
[flang][cuda] Do not apply implicit data attribute on dummy arg with VALUE (#119927)
Dummy arguments with the VALUE attribute do not need the implicit data
attribute.
Commit: 71d2fa7988f4ce4647b6ed387cf5b51dafa11e4c
https://github.com/llvm/llvm-project/commit/71d2fa7988f4ce4647b6ed387cf5b51dafa11e4c
Author: Kirill Stoimenov <87100199+kstoimenov at users.noreply.github.com>
Date: 2024-12-13 (Fri, 13 Dec 2024)
Changed paths:
M compiler-rt/lib/ubsan_minimal/ubsan_minimal_handlers.cpp
A compiler-rt/test/ubsan_minimal/TestCases/override-callback.c
Log Message:
-----------
[ubsan-minimal] Switch to weak symbols for callbacks to allow overriding in client code (#119242)
Commit: ecdf0dac565f750376f65f93b5bfd8b08d143116
https://github.com/llvm/llvm-project/commit/ecdf0dac565f750376f65f93b5bfd8b08d143116
Author: Chris White <chriswhiteiodev at gmail.com>
Date: 2024-12-13 (Fri, 13 Dec 2024)
Changed paths:
M llvm/include/llvm/CodeGen/SDPatternMatch.h
M llvm/unittests/CodeGen/SelectionDAGPatternMatchTest.cpp
Log Message:
-----------
[DAG] SDPatternMatch - Add m_ExtractElt and m_InsertElt matchers (#119430)
Resolves #118844
Commit: 9bf79308b893e8998e7efd752835636038c2db4f
https://github.com/llvm/llvm-project/commit/9bf79308b893e8998e7efd752835636038c2db4f
Author: Krzysztof Drewniak <Krzysztof.Drewniak at amd.com>
Date: 2024-12-13 (Fri, 13 Dec 2024)
Changed paths:
M mlir/lib/Dialect/Arith/Transforms/IntRangeOptimizations.cpp
M mlir/test/Dialect/Arith/int-range-narrowing.mlir
Log Message:
-----------
[mlir][Arith] Let integer range narrowing handle negative values (#119642)
Update integer range narrowing to handle negative values.
The previous restriction to only narrowing known-non-negative values
wasn't needed, as both the signed and unsigned ranges represent bounds
on the values of each variable in the program ... except that one might
be more accurate than the other. So, if either the signed or unsigned
interpretetation of the inputs and outputs allows for integer narrowing,
the narrowing is permitted.
This commit also updates the integer optimization rewrites to preserve
the stae of constant-like operations and those that are narrowed so that
rewrites of other operations don't lose that range information.
Commit: d0155789615c2272fbb304e34dc1df4d8d72f7cc
https://github.com/llvm/llvm-project/commit/d0155789615c2272fbb304e34dc1df4d8d72f7cc
Author: alx32 <103613512+alx32 at users.noreply.github.com>
Date: 2024-12-13 (Fri, 13 Dec 2024)
Changed paths:
M llvm/include/llvm/DebugInfo/GSYM/GsymReader.h
M llvm/lib/DebugInfo/GSYM/CallSiteInfo.cpp
M llvm/lib/DebugInfo/GSYM/GsymReader.cpp
A llvm/test/tools/llvm-gsymutil/ARM_AArch64/macho-gsym-merged-callsites-dsym.yaml
Log Message:
-----------
[llvm-gsymutil] Fix dumping of call sites for merged functions (#119759)
Currently, when dumping the contents of a GSYM there are three issues:
- Callsite information is not displayed for merged functions - this is
because of a bug in `CallSiteInfoLoader::buildFunctionMap` where when
enumerating through `Func.MergedFunctions` - we enumerate by value
instead of by reference.
- There is no variable indent for printing callsite info - meaning that
when printing callsites for merged functions, the indent will be
different than the other info of the merged function. To address this we
add configurable indent for printing callsite info
- Callsite info is printed right after merged function info. Meaning
that if the merged function also has call site information, the parent's
callsite info will appear right after the merged function's callsite
info - leading to confusion. To address this we print the callsite info
first, then the merged functions info.
This change addresses all the above 3 issues.
Example of old vs new:
<img width="1074" alt="image"
src="https://github.com/user-attachments/assets/d039ad69-fa79-4abb-9816-eda9cc2eda53"
/>
Commit: f22cff7675f7f64aa52204f4426f5047cc75fbb9
https://github.com/llvm/llvm-project/commit/f22cff7675f7f64aa52204f4426f5047cc75fbb9
Author: Adrian Prantl <aprantl at apple.com>
Date: 2024-12-13 (Fri, 13 Dec 2024)
Changed paths:
M lldb/source/DataFormatters/FormatterSection.cpp
M lldb/test/API/functionalities/data-formatter/embedded-summary/TestEmbeddedTypeSummary.py
M lldb/test/API/functionalities/data-formatter/embedded-summary/main.c
Log Message:
-----------
[lldb] Support zero-padding in formatter sections (#119934)
Commit: d73ef9749e72e59d1d34275e89d4d2fffddd3e8c
https://github.com/llvm/llvm-project/commit/d73ef9749e72e59d1d34275e89d4d2fffddd3e8c
Author: Nico Weber <thakis at chromium.org>
Date: 2024-12-13 (Fri, 13 Dec 2024)
Changed paths:
M lld/COFF/Chunks.cpp
M lld/COFF/Symbols.cpp
M lld/COFF/Symbols.h
M lld/test/COFF/reloc-discarded.s
Log Message:
-----------
[lld/COFF] Demangle symbol name in discarded section relocation error message (#119726)
Commit: 22266bc958abdb1414832fa09a7a3b31166427a6
https://github.com/llvm/llvm-project/commit/22266bc958abdb1414832fa09a7a3b31166427a6
Author: Tom Stellard <tstellar at redhat.com>
Date: 2024-12-13 (Fri, 13 Dec 2024)
Changed paths:
M .github/workflows/build-ci-container.yml
Log Message:
-----------
workflows/build-ci-container: Fix typos in variables (#119943)
This was preventing the containers from being pushed to the registry.
Commit: af20aff35ec37ead88903bc3e44f6a81c5c9ca4e
https://github.com/llvm/llvm-project/commit/af20aff35ec37ead88903bc3e44f6a81c5c9ca4e
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2024-12-13 (Fri, 13 Dec 2024)
Changed paths:
M .github/workflows/build-ci-container-windows.yml
Log Message:
-----------
[Github] Fix windows container push (#119916)
The windows container push was not tested in the pull request and had a
couple of typos that prevented it from functioning. This patch fixes
that so we can actually push the container to GHCR.
Commit: a222d00c667f5582194ba7e50b870312e4b4427b
https://github.com/llvm/llvm-project/commit/a222d00c667f5582194ba7e50b870312e4b4427b
Author: Fangrui Song <i at maskray.me>
Date: 2024-12-13 (Fri, 13 Dec 2024)
Changed paths:
M lld/wasm/Config.h
M lld/wasm/Driver.cpp
Log Message:
-----------
[lld][WebAssembly] Introduce Ctx::arg
and forward it to LinkerDriver's ctor so that some uses of the global
`config` can be dropped. This is similar to how the ELF port
migrates away from the global `config`.
Pull Request: https://github.com/llvm/llvm-project/pull/119829
Commit: e821f642fdc75922b1a020447485acccf3e7fa92
https://github.com/llvm/llvm-project/commit/e821f642fdc75922b1a020447485acccf3e7fa92
Author: Kirill Stoimenov <kstoimenov at google.com>
Date: 2024-12-14 (Sat, 14 Dec 2024)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
M llvm/test/CodeGen/AMDGPU/sgpr-regalloc-flags.ll
Log Message:
-----------
Revert "[AMDGPU][CodeGen] Do not backtrace invalid -regalloc param (#119687)"
Causes bot failure: https://lab.llvm.org/buildbot/#/builders/55/builds/4246/steps/11/logs/stdio
This reverts commit 7a648554f886fbc043c4f3f58ca88f6c4535f2cf.
Commit: 49c2207f21c0922aedb6c70471f8ea068977eb30
https://github.com/llvm/llvm-project/commit/49c2207f21c0922aedb6c70471f8ea068977eb30
Author: Timm Baeder <tbaeder at redhat.com>
Date: 2024-12-14 (Sat, 14 Dec 2024)
Changed paths:
M clang/lib/AST/ByteCode/Integral.h
M clang/lib/AST/ByteCode/Interp.h
M clang/test/AST/ByteCode/shifts.cpp
Log Message:
-----------
[clang][bytecode] Fix some shift edge cases (#119895)
Around shifting negative values.
Commit: a6636ce4d124176856c3913d4bf6c3ceff1f5a1f
https://github.com/llvm/llvm-project/commit/a6636ce4d124176856c3913d4bf6c3ceff1f5a1f
Author: Timm Bäder <tbaeder at redhat.com>
Date: 2024-12-14 (Sat, 14 Dec 2024)
Changed paths:
M clang/lib/AST/ByteCode/Integral.h
M clang/lib/AST/ByteCode/Interp.h
M clang/test/AST/ByteCode/shifts.cpp
Log Message:
-----------
Revert "[clang][bytecode] Fix some shift edge cases (#119895)"
This reverts commit 49c2207f21c0922aedb6c70471f8ea068977eb30.
This breaks on big-endian, again:
https://lab.llvm.org/buildbot/#/builders/154/builds/9018
Commit: 2291e5aa45dc135a5f908032eb31d19ef3570114
https://github.com/llvm/llvm-project/commit/2291e5aa45dc135a5f908032eb31d19ef3570114
Author: Congcong Cai <congcongcai0907 at 163.com>
Date: 2024-12-14 (Sat, 14 Dec 2024)
Changed paths:
M clang-tools-extra/docs/clang-tidy/index.rst
Log Message:
-----------
[clang-tidy][doc] align the title style in clang-tidy/index.rst (#119938)
Uppercase each word in title and toctree
_Originally posted by @nicovank in
https://github.com/llvm/llvm-project/pull/119842#discussion_r1884559775_.
---------
Co-authored-by: Nicolas van Kempen <nvankemp at gmail.com>
Commit: ca79ff07d8ae7a0c2531bfdb1cb623e25e5bd486
https://github.com/llvm/llvm-project/commit/ca79ff07d8ae7a0c2531bfdb1cb623e25e5bd486
Author: Chandler Carruth <chandlerc at gmail.com>
Date: 2024-12-13 (Fri, 13 Dec 2024)
Changed paths:
M clang/include/clang/Basic/Builtins.h
M clang/include/clang/Basic/BuiltinsPPC.def
M clang/include/clang/Basic/TargetInfo.h
M clang/lib/Basic/Builtins.cpp
M clang/lib/Basic/Targets/AArch64.cpp
M clang/lib/Basic/Targets/AArch64.h
M clang/lib/Basic/Targets/AMDGPU.cpp
M clang/lib/Basic/Targets/AMDGPU.h
M clang/lib/Basic/Targets/ARC.h
M clang/lib/Basic/Targets/ARM.cpp
M clang/lib/Basic/Targets/ARM.h
M clang/lib/Basic/Targets/AVR.h
M clang/lib/Basic/Targets/BPF.cpp
M clang/lib/Basic/Targets/BPF.h
M clang/lib/Basic/Targets/CSKY.cpp
M clang/lib/Basic/Targets/CSKY.h
M clang/lib/Basic/Targets/DirectX.h
M clang/lib/Basic/Targets/Hexagon.cpp
M clang/lib/Basic/Targets/Hexagon.h
M clang/lib/Basic/Targets/Lanai.h
M clang/lib/Basic/Targets/LoongArch.cpp
M clang/lib/Basic/Targets/LoongArch.h
M clang/lib/Basic/Targets/M68k.cpp
M clang/lib/Basic/Targets/M68k.h
M clang/lib/Basic/Targets/MSP430.h
M clang/lib/Basic/Targets/Mips.cpp
M clang/lib/Basic/Targets/Mips.h
M clang/lib/Basic/Targets/NVPTX.cpp
M clang/lib/Basic/Targets/NVPTX.h
M clang/lib/Basic/Targets/PNaCl.h
M clang/lib/Basic/Targets/PPC.cpp
M clang/lib/Basic/Targets/PPC.h
M clang/lib/Basic/Targets/RISCV.cpp
M clang/lib/Basic/Targets/RISCV.h
M clang/lib/Basic/Targets/SPIR.cpp
M clang/lib/Basic/Targets/SPIR.h
M clang/lib/Basic/Targets/Sparc.h
M clang/lib/Basic/Targets/SystemZ.cpp
M clang/lib/Basic/Targets/SystemZ.h
M clang/lib/Basic/Targets/TCE.h
M clang/lib/Basic/Targets/VE.cpp
M clang/lib/Basic/Targets/VE.h
M clang/lib/Basic/Targets/WebAssembly.cpp
M clang/lib/Basic/Targets/WebAssembly.h
M clang/lib/Basic/Targets/X86.cpp
M clang/lib/Basic/Targets/X86.h
M clang/lib/Basic/Targets/XCore.cpp
M clang/lib/Basic/Targets/XCore.h
Log Message:
-----------
Revert "Switch builtin strings to use string tables" (#119638)
Reverts llvm/llvm-project#118734
There are currently some specific versions of MSVC that are miscompiling
this code (we think). We don't know why as all the other build bots and
at least some folks' local Windows builds work fine.
This is a candidate revert to help the relevant folks catch their
builders up and have time to debug the issue. However, the expectation
is to roll forward at some point with a workaround if at all possible.
Commit: 7c294eb78009ef252aafa269963f5496d1dedf6f
https://github.com/llvm/llvm-project/commit/7c294eb78009ef252aafa269963f5496d1dedf6f
Author: Kazu Hirata <kazu at google.com>
Date: 2024-12-14 (Sat, 14 Dec 2024)
Changed paths:
M llvm/lib/Transforms/Instrumentation/MemProfiler.cpp
Log Message:
-----------
[memprof] Simplify readMemprof (NFC) (#119930)
This patch essentially replaces:
std::pair<const std::vector<Frame> *, unsigned>
with:
ArrayRef<Frame>
This way, we can store and pass ArrayRef<Frame>, conceptually one
item, instead of the pointer and index.
The only problem is that we don't have an existing hash function for
ArrayRef<Frame>>, so we provide a custom one, namely
CallStackHash.
Commit: 74fb9928443ce3d176911615e6a0297f074736fe
https://github.com/llvm/llvm-project/commit/74fb9928443ce3d176911615e6a0297f074736fe
Author: alx32 <103613512+alx32 at users.noreply.github.com>
Date: 2024-12-14 (Sat, 14 Dec 2024)
Changed paths:
M llvm/test/tools/llvm-gsymutil/ARM_AArch64/macho-gsym-merged-callsites-dsym.yaml
Log Message:
-----------
[llvm-gsymutil] Disable test macho-gsym-merged-callsites-dsym (#119957)
The macho-gsym-merged-callsites-dsym is failing on some hosts.
Disabling for now while we come up with a fix.
Commit: 97c3c32372bb8478c53ab9469585c7c6e531cbd2
https://github.com/llvm/llvm-project/commit/97c3c32372bb8478c53ab9469585c7c6e531cbd2
Author: Sergei Barannikov <barannikov88 at gmail.com>
Date: 2024-12-14 (Sat, 14 Dec 2024)
Changed paths:
M llvm/lib/Target/SystemZ/SystemZInstrInfo.td
M llvm/lib/Target/SystemZ/SystemZOperators.td
M llvm/utils/TableGen/Common/CodeGenDAGPatterns.cpp
Log Message:
-----------
[TableGen][SystemZ] Correctly check the range of a leaf immediate (#119931)
The "Size >= 32" check probably dates back to when TableGen integers
were 32-bit. Delete it and simplify code by using `isInt`/`isUInt`.
Commit: 1911919682c863643787b30286bb67359c7932f4
https://github.com/llvm/llvm-project/commit/1911919682c863643787b30286bb67359c7932f4
Author: Pavel Kosov <kpdev42 at gmail.com>
Date: 2024-12-14 (Sat, 14 Dec 2024)
Changed paths:
M clang/lib/Driver/ToolChains/OHOS.cpp
Log Message:
-----------
Revert "[Driver][OHOS] Fix lld link issue for OHOS (#118192)"
This reverts commit bc28be0a428020ea803c94adb4df48ee4972e9f1.
Some issues were discovered with GN buildbot http://45.33.8.238/linux/155432/step_6.txt
Need to investigate it
Commit: cc54a0ce5674b740c2136d7bd2416ffeb4a230cf
https://github.com/llvm/llvm-project/commit/cc54a0ce5674b740c2136d7bd2416ffeb4a230cf
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-12-14 (Sat, 14 Dec 2024)
Changed paths:
M llvm/lib/Transforms/Vectorize/VectorCombine.cpp
M llvm/test/Transforms/VectorCombine/AMDGPU/as-transition.ll
M llvm/test/Transforms/VectorCombine/X86/load.ll
Log Message:
-----------
[VectorCombine] vectorizeLoadInsert - only fold when inserting into a poison vector (#119906)
We have corresponding poison tests in the "-inseltpoison.ll" sibling test files.
Fixes #119900
Commit: d6b133e5a7f143757736455a2acc7a06266e2c7d
https://github.com/llvm/llvm-project/commit/d6b133e5a7f143757736455a2acc7a06266e2c7d
Author: LLVM GN Syncbot <llvmgnsyncbot at gmail.com>
Date: 2024-12-14 (Sat, 14 Dec 2024)
Changed paths:
M llvm/utils/gn/secondary/lldb/source/Plugins/Process/Utility/BUILD.gn
Log Message:
-----------
[gn build] Port 6c4e70fcbbb6
Commit: b7e75a76449e80d8b6caa1f447d536ffa231783a
https://github.com/llvm/llvm-project/commit/b7e75a76449e80d8b6caa1f447d536ffa231783a
Author: LLVM GN Syncbot <llvmgnsyncbot at gmail.com>
Date: 2024-12-14 (Sat, 14 Dec 2024)
Changed paths:
M llvm/utils/gn/secondary/libcxx/include/BUILD.gn
Log Message:
-----------
[gn build] Port 9474e0945918
Commit: 0ae75eba678a9ab459a382818148ef06afe817b5
https://github.com/llvm/llvm-project/commit/0ae75eba678a9ab459a382818148ef06afe817b5
Author: Aaditya <115080342+easyonaadit at users.noreply.github.com>
Date: 2024-12-14 (Sat, 14 Dec 2024)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
Log Message:
-----------
[AMDGPU] Assert if stack grows downwards. (#119888)
Commit: 10f23d116baa221707d8831d3c34f38f511c408e
https://github.com/llvm/llvm-project/commit/10f23d116baa221707d8831d3c34f38f511c408e
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-12-14 (Sat, 14 Dec 2024)
Changed paths:
M llvm/lib/Target/X86/X86ISelLowering.cpp
Log Message:
-----------
[X86] matchPMADDWD/matchPMADDWD_2 - update to use m_ExtractElt matchers. NFC.
Commit: 6157dbe48c21d900da1c7df11a8072a235f82001
https://github.com/llvm/llvm-project/commit/6157dbe48c21d900da1c7df11a8072a235f82001
Author: Nikolas Klauser <nikolasklauser at berlin.de>
Date: 2024-12-14 (Sat, 14 Dec 2024)
Changed paths:
M libcxx/include/__utility/forward_like.h
M libcxx/include/variant
Log Message:
-----------
[libc++] Introduce __forward_as (#118168)
This allows forwarding an object as a specific type. This is usually
useful when using `deducing this` to avoid calling any functions in a
deriving class.
Commit: 1901da32a4c9318d860a8aa071912da700bfb923
https://github.com/llvm/llvm-project/commit/1901da32a4c9318d860a8aa071912da700bfb923
Author: Nikolas Klauser <nikolasklauser at berlin.de>
Date: 2024-12-14 (Sat, 14 Dec 2024)
Changed paths:
A libcxx/test/std/utilities/meta/derived_from_integral_constant.compile.pass.cpp
Log Message:
-----------
[libc++] Add a test to make sure all the type traits derived from bool_constant
Commit: bca11777bebaf3b61d25fd5874584066e80d57fa
https://github.com/llvm/llvm-project/commit/bca11777bebaf3b61d25fd5874584066e80d57fa
Author: Aviad Cohen <aviadcohen7 at gmail.com>
Date: 2024-12-14 (Sat, 14 Dec 2024)
Changed paths:
M mlir/include/mlir/Dialect/SCF/IR/SCFOps.td
Log Message:
-----------
[nfc][mlir][scf]: Define scf.for lower/upper bounds can be also negative or zero (#117534)
Per the discussion here:
https://github.com/llvm/llvm-project/pull/116748#discussion_r1848680070 , this commit properly declare that lower and upper bounds can be also negative or zero.
Commit: c3276a96d909233b836e839a23a7ad510fae407a
https://github.com/llvm/llvm-project/commit/c3276a96d909233b836e839a23a7ad510fae407a
Author: Nikolas Klauser <nikolasklauser at berlin.de>
Date: 2024-12-14 (Sat, 14 Dec 2024)
Changed paths:
M libcxx/test/std/utilities/meta/derived_from_integral_constant.compile.pass.cpp
Log Message:
-----------
[libc++] Disable deprecation warnings in derived_from_integral_constant.compile.pass.cpp
Commit: a999ab44be8994d39d2469c1b4d025c4e1131197
https://github.com/llvm/llvm-project/commit/a999ab44be8994d39d2469c1b4d025c4e1131197
Author: Aaron Puchert <aaron.puchert at sap.com>
Date: 2024-12-14 (Sat, 14 Dec 2024)
Changed paths:
M clang/lib/Analysis/ThreadSafetyCommon.cpp
M clang/test/SemaCXX/warn-thread-safety-analysis.cpp
Log Message:
-----------
Thread safety analysis: Fix substitution for operator calls (#116487)
For operator calls that go to methods we need to substitute the first
parameter for "this" and the following parameters into the function
parameters, instead of substituting all of them into the parameters.
This revealed an issue about lambdas. An existing test accidentally
worked because the substitution bug was covered by a speciality of
lambdas: a CXXThisExpr in a lambda CXXMethodDecl does not refer to the
implicit this argument of the method, but to a captured "this" from the
context the lambda was created in. This can happen for operator calls,
where it worked due to the substitution bug (we treated the implicit
this argument incorrectly as parameter), and for regular calls (i.e.
obj.operator()(args) instead of obj(args)), where it didn't work.
The correct fix seems to be to clear the self-argument on a lambda call.
Lambdas can only capture "this" inside methods, and calls to the lambda
in that scope cannot substitute anything for "this".
Commit: 9ef73d6017584a5ea425f898754bb5d1e03536bb
https://github.com/llvm/llvm-project/commit/9ef73d6017584a5ea425f898754bb5d1e03536bb
Author: David Green <david.green at arm.com>
Date: 2024-12-14 (Sat, 14 Dec 2024)
Changed paths:
M llvm/lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp
Log Message:
-----------
[AArch64] Fix brackets warning in assert. NFC
Commit: c35108e24488af1db1914ec083439189e6a7fce6
https://github.com/llvm/llvm-project/commit/c35108e24488af1db1914ec083439189e6a7fce6
Author: Kazu Hirata <kazu at google.com>
Date: 2024-12-14 (Sat, 14 Dec 2024)
Changed paths:
M clang/unittests/AST/ASTImporterTest.cpp
Log Message:
-----------
[AST] Migrate away from PointerUnion::get (NFC) (#119949)
Note that PointerUnion::get has been soft deprecated in
PointerUnion.h:
// FIXME: Replace the uses of is(), get() and dyn_cast() with
// isa<T>, cast<T> and the llvm::dyn_cast<T>
Commit: c0849218c43db152259a349aee130eda51057e4e
https://github.com/llvm/llvm-project/commit/c0849218c43db152259a349aee130eda51057e4e
Author: Sergei Barannikov <barannikov88 at gmail.com>
Date: 2024-12-14 (Sat, 14 Dec 2024)
Changed paths:
M llvm/lib/Target/SystemZ/SystemZOperators.td
Log Message:
-----------
[SystemZ] Use the same PatFrag for all "insert imm" fragments (NFC) (#119962)
Commit: 331c2dd8b482e441d8ccddc09f21a02cc9454786
https://github.com/llvm/llvm-project/commit/331c2dd8b482e441d8ccddc09f21a02cc9454786
Author: Alexander Yermolovich <43973793+ayermolo at users.noreply.github.com>
Date: 2024-12-14 (Sat, 14 Dec 2024)
Changed paths:
M bolt/lib/Core/DebugNames.cpp
A bolt/test/X86/dwarf5-debug-names-gnu-push-tls-address.s
Log Message:
-----------
[BOLT][DWARF] Add support for DW_OP_GNU_push_tls_address to .debug_names (#119939)
Added support to BOLT for DW_OP_GNU_push_tls_address. So now
DW_TAG_variable with this OP in DW_AT_location will appear in debug
names acceleration table. Although not in the DWARF 5 spec it is similar
to DW_OP_form_tls_address. Without this support llvm-dwarfdump --verify
--debug-names will report errors.
Commit: 0032c151dcbdbf9cdd8982870c7611e6f08c504b
https://github.com/llvm/llvm-project/commit/0032c151dcbdbf9cdd8982870c7611e6f08c504b
Author: David Green <david.green at arm.com>
Date: 2024-12-14 (Sat, 14 Dec 2024)
Changed paths:
M llvm/include/llvm/Analysis/PtrUseVisitor.h
M llvm/include/llvm/Transforms/Utils/SSAUpdater.h
M llvm/lib/Transforms/Scalar/SROA.cpp
M llvm/lib/Transforms/Utils/SSAUpdater.cpp
M llvm/test/Transforms/SROA/non-capturing-call-readonly.ll
M llvm/test/Transforms/SROA/readonlynocapture.ll
Log Message:
-----------
[SROA] Optimize reloaded values in allocas that escape into readonly nocapture calls. (#116645)
Given an alloca that potentially has many uses in big complex code and
escapes into a call that is readonly+nocapture, we cannot easily split
up the alloca. There are several optimizations that will attempt to take
a value that is stored and a reload, and replace the load with the
original stored value. Instcombine has some simple heuristics, GVN can
sometimes do it, as can CSE in limited situations. They all suffer from
the same issue with complex code - they start from a load/store and need
to prove no-alias for all code between, which in complex cases might be
a lot to look through. Especially if the ptr is an alloca with many uses
that is over the normal escape capture limits.
The pass that does do well with allocas is SROA, as it has a complete
view of all of the uses. This patch adds a case to SROA where it can
detect allocas that are passed into calls that are no-capture readonly.
It can then optimize the reloaded values inside the alloca slice with
the stored value knowing that it is valid no matter the location of the
loads/stores from the no-escaping nature of the alloca.
Commit: e48916f615e0ad2b994b2b785d4fe1b8a98bc322
https://github.com/llvm/llvm-project/commit/e48916f615e0ad2b994b2b785d4fe1b8a98bc322
Author: pzhengqc <55604844+pzhengqc at users.noreply.github.com>
Date: 2024-12-14 (Sat, 14 Dec 2024)
Changed paths:
M llvm/lib/Target/ARM/ARMConstantIslandPass.cpp
A llvm/test/CodeGen/Thumb2/constant-islands-no-split.mir
Log Message:
-----------
[ARM][ConstantIslands] Correct MinNoSplitDisp calculation (#114590)
MinNoSplitDisp was first introduced in D16890 to handle cases where the
ConstantIslands pass fails to converge in the presence of big basic
blocks. However, the computation of the variable seems to be wrong as it
currently computes the offset immediately following UserBB. In other
words, it represents the distance from the beginning of the function to
the end of UserBB. The distance from the beginning of the function does
not seem to be a good indicator of how big the basic block is unless the
basic block is close to the beginning of the function. I think
MinNoSplitDisp should compute the distance between UserOffset and the
end of UserBB instead.
Commit: 9ddcaed3a64c2a187a0cfff4ba8f989c665ae1e5
https://github.com/llvm/llvm-project/commit/9ddcaed3a64c2a187a0cfff4ba8f989c665ae1e5
Author: Davide Italiano <davidino at meta.com>
Date: 2024-12-14 (Sat, 14 Dec 2024)
Changed paths:
R clang/test/Interpreter/Inputs/vector
M clang/test/Interpreter/crash.cpp
Log Message:
-----------
Revert "[Clang] Interpreter test should not depend on system header (#119903)"
This reverts commit 8ab6912831277d87838518c5f775f79d14616860.
Commit: 61ab36a3e226df32855286dd31a2c3859800475d
https://github.com/llvm/llvm-project/commit/61ab36a3e226df32855286dd31a2c3859800475d
Author: Davide Italiano <davidino at meta.com>
Date: 2024-12-14 (Sat, 14 Dec 2024)
Changed paths:
M clang/lib/Interpreter/Interpreter.cpp
R clang/test/Interpreter/crash.cpp
Log Message:
-----------
Revert "[Clang-REPL] Fix crash during `__run_exit_handlers` with dynamic libraries. (#117475)"
This reverts commit 30ad53b92cec0cff9679d559edcc5b933312ba0c as it breaks
systems that don't have a systemwide libc++ or libstdc++ installed. It should
be rewritten to not invoke the system linker. In the meanwhile, reverting
to unblock the bots.
Commit: b5c5c2b26fd4bd0d0d237aaf77a01ca528810707
https://github.com/llvm/llvm-project/commit/b5c5c2b26fd4bd0d0d237aaf77a01ca528810707
Author: Kazu Hirata <kazu at google.com>
Date: 2024-12-14 (Sat, 14 Dec 2024)
Changed paths:
M mlir/include/mlir/Analysis/DataFlow/SparseAnalysis.h
M mlir/lib/Analysis/DataFlow/ConstantPropagationAnalysis.cpp
M mlir/lib/Analysis/DataFlow/IntegerRangeAnalysis.cpp
M mlir/lib/Analysis/DataFlow/SparseAnalysis.cpp
Log Message:
-----------
[DataFlow] Migrate away from PointerUnion::{is,get} (NFC) (#119950)
Note that PointerUnion::{is,get} have been soft deprecated in
PointerUnion.h:
// FIXME: Replace the uses of is(), get() and dyn_cast() with
// isa<T>, cast<T> and the llvm::dyn_cast<T>
I'm not touching PointerUnion::dyn_cast for now because it's a bit
complicated; we could blindly migrate it to dyn_cast_if_present, but
we should probably use dyn_cast when the operand is known to be
non-null.
Commit: 2564f1e1991425cbbfcada52ebaa6191d36fdf53
https://github.com/llvm/llvm-project/commit/2564f1e1991425cbbfcada52ebaa6191d36fdf53
Author: Florian Hahn <flo at fhahn.com>
Date: 2024-12-14 (Sat, 14 Dec 2024)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
M llvm/test/Transforms/LoopVectorize/single_early_exit.ll
M llvm/test/Transforms/LoopVectorize/uncountable-early-exit-vplan.ll
Log Message:
-----------
[VPlan] Simplify Not(Not(A)) -> A.
Follow-up simplification to 5fae408d3a4c073ee4.
Commit: aaadaee7b228d7010ff7076f5002ebb96b5e03dc
https://github.com/llvm/llvm-project/commit/aaadaee7b228d7010ff7076f5002ebb96b5e03dc
Author: Congcong Cai <congcongcai0907 at 163.com>
Date: 2024-12-15 (Sun, 15 Dec 2024)
Changed paths:
M clang-tools-extra/clang-tidy/bugprone/UncheckedOptionalAccessCheck.h
M clang-tools-extra/clang-tidy/cppcoreguidelines/ProTypeMemberInitCheck.cpp
M clang-tools-extra/clang-tidy/cppcoreguidelines/RvalueReferenceParamNotMovedCheck.cpp
M clang-tools-extra/clang-tidy/performance/InefficientVectorOperationCheck.cpp
M clang-tools-extra/clang-tidy/readability/RedundantAccessSpecifiersCheck.h
M clang-tools-extra/clang-tidy/readability/RedundantCastingCheck.cpp
M clang-tools-extra/clang-tidy/utils/RenamerClangTidyCheck.cpp
Log Message:
-----------
[clang-tidy] remove misuse of `getLocalOrGlobal` for non common used options (#119948)
[RFC](https://discourse.llvm.org/t/rfc-global-option-rules-for-clang-tidy/83647)
Commit: 99354f968f64659cbad5c82b0301d851ae54f057
https://github.com/llvm/llvm-project/commit/99354f968f64659cbad5c82b0301d851ae54f057
Author: Richard Dzenis <richard at dzenis.dev>
Date: 2024-12-15 (Sun, 15 Dec 2024)
Changed paths:
M clang/test/SemaCXX/msvc-pragma-function-no-builtin-attr.cpp
Log Message:
-----------
[clang][test] Fix SemaCXX/msvc-pragma-function-no-builtin-attr.cpp for x86 (#119986)
Fix test failure from #119719
84b0f0145887bbfe49fd4dc85490b14108a72cee
Closes #119979
Commit: d33bf2e9df578ff7e44fd22504d6ad5a122b7ee6
https://github.com/llvm/llvm-project/commit/d33bf2e9df578ff7e44fd22504d6ad5a122b7ee6
Author: Hubert Tong <hubert.reinterpretcast at gmail.com>
Date: 2024-12-14 (Sat, 14 Dec 2024)
Changed paths:
M libcxxabi/test/test_demangle.pass.cpp
Log Message:
-----------
NFC: clang-format test_demangle.pass.cpp but keep test "lines"
Add clang-format on/off around test "lines"
Run clang-format without breaking string literals:
clang-format --style='{BasedOnStyle: llvm, BreakStringLiterals: false}'
-i test_demangle.pass.cpp
Add clang-format on/off on fp_literal_cases
Fixups: Split UNSUPPORTED to next line; xfail_cases trailing comma
Replace physical tab
Commit: e2dc0b9b1ec09de2b20387846cd2487362a58322
https://github.com/llvm/llvm-project/commit/e2dc0b9b1ec09de2b20387846cd2487362a58322
Author: Hubert Tong <hubert.reinterpretcast at gmail.com>
Date: 2024-12-14 (Sat, 14 Dec 2024)
Changed paths:
M .git-blame-ignore-revs
Log Message:
-----------
[libc++] Add test_demangle.pass.cpp clang-format to .git-blame-ignore-revs
Commit: 8b02d809d284c8e10b38087431def52c86e3e9e6
https://github.com/llvm/llvm-project/commit/8b02d809d284c8e10b38087431def52c86e3e9e6
Author: Fangrui Song <i at maskray.me>
Date: 2024-12-14 (Sat, 14 Dec 2024)
Changed paths:
M llvm/test/CodeGen/Mips/2008-07-16-SignExtInReg.ll
M llvm/test/CodeGen/Mips/beqzc.ll
M llvm/test/CodeGen/Mips/beqzc1.ll
M llvm/test/CodeGen/Mips/blockaddr.ll
M llvm/test/CodeGen/Mips/brsize3.ll
M llvm/test/CodeGen/Mips/brsize3a.ll
M llvm/test/CodeGen/Mips/ci2.ll
M llvm/test/CodeGen/Mips/const1.ll
M llvm/test/CodeGen/Mips/const4a.ll
M llvm/test/CodeGen/Mips/const6.ll
M llvm/test/CodeGen/Mips/const6a.ll
M llvm/test/CodeGen/Mips/ctlz.ll
M llvm/test/CodeGen/Mips/f16abs.ll
M llvm/test/CodeGen/Mips/fixdfsf.ll
M llvm/test/CodeGen/Mips/fp16instrinsmc.ll
M llvm/test/CodeGen/Mips/fp16mix.ll
M llvm/test/CodeGen/Mips/fpnotneeded.ll
M llvm/test/CodeGen/Mips/funnel-shift-rot.ll
M llvm/test/CodeGen/Mips/funnel-shift.ll
M llvm/test/CodeGen/Mips/helloworld.ll
M llvm/test/CodeGen/Mips/hf16call32.ll
M llvm/test/CodeGen/Mips/hf16call32_body.ll
M llvm/test/CodeGen/Mips/hf1_body.ll
M llvm/test/CodeGen/Mips/hfptrcall.ll
M llvm/test/CodeGen/Mips/i32k.ll
M llvm/test/CodeGen/Mips/l3mc.ll
M llvm/test/CodeGen/Mips/lcb2.ll
M llvm/test/CodeGen/Mips/lcb3c.ll
M llvm/test/CodeGen/Mips/lcb4a.ll
M llvm/test/CodeGen/Mips/lcb5.ll
M llvm/test/CodeGen/Mips/mbrsize4a.ll
M llvm/test/CodeGen/Mips/mips16-hf-attr-2.ll
M llvm/test/CodeGen/Mips/mips16-hf-attr.ll
M llvm/test/CodeGen/Mips/mips16_fpret.ll
M llvm/test/CodeGen/Mips/nomips16.ll
M llvm/test/CodeGen/Mips/powif64_16.ll
M llvm/test/CodeGen/Mips/rotate.ll
M llvm/test/CodeGen/Mips/s2rem.ll
M llvm/test/CodeGen/Mips/sel1c.ll
M llvm/test/CodeGen/Mips/sel2c.ll
M llvm/test/CodeGen/Mips/simplebr.ll
M llvm/test/CodeGen/Mips/small-section-reserve-gp.ll
M llvm/test/CodeGen/Mips/sr1.ll
M llvm/test/CodeGen/Mips/tail16.ll
M llvm/test/CodeGen/Mips/trap1.ll
Log Message:
-----------
[test] Remove redundant -march= in llc -mtriple=
Commit: 8c681a929b8684f5a4ad2ebd4e3e4f20036a9595
https://github.com/llvm/llvm-project/commit/8c681a929b8684f5a4ad2ebd4e3e4f20036a9595
Author: Owen Pan <owenpiano at gmail.com>
Date: 2024-12-14 (Sat, 14 Dec 2024)
Changed paths:
M clang/unittests/Format/FormatTestJS.cpp
Log Message:
-----------
[clang-format][NFC] Add a TypeScript test case
See #108530.
Commit: e04fde193bc2acbaf3ece851479fbd9928c1e280
https://github.com/llvm/llvm-project/commit/e04fde193bc2acbaf3ece851479fbd9928c1e280
Author: Kazu Hirata <kazu at google.com>
Date: 2024-12-14 (Sat, 14 Dec 2024)
Changed paths:
M lld/MachO/Arch/ARM64.cpp
M lld/MachO/ConcatOutputSection.cpp
M lld/MachO/EhFrame.cpp
M lld/MachO/ICF.cpp
M lld/MachO/InputFiles.cpp
M lld/MachO/InputSection.cpp
M lld/MachO/MarkLive.cpp
M lld/MachO/ObjC.cpp
M lld/MachO/Relocations.cpp
M lld/MachO/SyntheticSections.cpp
M lld/MachO/UnwindInfoSection.cpp
Log Message:
-----------
[lld] Migrate away from PointerUnion::{is,get} (NFC) (#119993)
Note that PointerUnion::{is,get} have been soft deprecated in
PointerUnion.h:
// FIXME: Replace the uses of is(), get() and dyn_cast() with
// isa<T>, cast<T> and the llvm::dyn_cast<T>
I'm not touching PointerUnion::dyn_cast for now because it's a bit
complicated; we could blindly migrate it to dyn_cast_if_present, but
we should probably use dyn_cast when the operand is known to be
non-null.
Commit: fe9f2ac8e763d35bf7dea34063b18865ca26a781
https://github.com/llvm/llvm-project/commit/fe9f2ac8e763d35bf7dea34063b18865ca26a781
Author: Fangrui Song <i at maskray.me>
Date: 2024-12-14 (Sat, 14 Dec 2024)
Changed paths:
M llvm/test/MC/ELF/relocation.s
A llvm/test/MC/X86/elf-reloc-got.s
A llvm/test/MC/X86/elf-reloc-size.s
A llvm/test/MC/X86/elf-reloc-tls.s
Log Message:
-----------
[test] Reorganize some R_X86_64_ tests
Commit: 97f43364cc8599bfc64f4f83fb81c7cd0242a1a4
https://github.com/llvm/llvm-project/commit/97f43364cc8599bfc64f4f83fb81c7cd0242a1a4
Author: Amir Ayupov <aaupov at fb.com>
Date: 2024-12-14 (Sat, 14 Dec 2024)
Changed paths:
M bolt/test/merge-fdata-mixed-bat-no-lbr.test
M bolt/test/merge-fdata-mixed-mode.test
M bolt/tools/merge-fdata/merge-fdata.cpp
Log Message:
-----------
[BOLT][NFC] Speedup merge-fdata (#119942)
Eliminate splitting the buffer into lines, and use `std::getline`
directly. Simplify no_lbr and boltedcollection handling as well.
Test Plan: For a large fdata file (200MB), fstream version is ~10%
faster.
Commit: 86526084044167b3c753d32ef8dbf79d57cba0c4
https://github.com/llvm/llvm-project/commit/86526084044167b3c753d32ef8dbf79d57cba0c4
Author: Amir Ayupov <aaupov at fb.com>
Date: 2024-12-14 (Sat, 14 Dec 2024)
Changed paths:
M bolt/test/merge-fdata-lbr-mode.test
M bolt/tools/merge-fdata/merge-fdata.cpp
Log Message:
-----------
[BOLT] Fix counts aggregation in merge-fdata (#119652)
merge-fdata used to consider misprediction count as part of "signature",
or the aggregation key. This prevented it from collapsing profile lines
with different misprediction counts, which resulted in duplicate
`(from, to)` pairs with different misprediction and execution counts.
Fix that by splitting out misprediction count and accumulating it
separately.
Test Plan: updated bolt/test/merge-fdata-lbr-mode.test
Commit: 4c8c1308479166d00b4e1d74ceee7cf0abfe6e72
https://github.com/llvm/llvm-project/commit/4c8c1308479166d00b4e1d74ceee7cf0abfe6e72
Author: David Green <david.green at arm.com>
Date: 2024-12-15 (Sun, 15 Dec 2024)
Changed paths:
M llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
M llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
M llvm/test/CodeGen/AArch64/dup.ll
Log Message:
-----------
[AArch64][GlobalISel] Scalarize i128 shufflevector instructions. (#119980)
This, like other operations, scalarizes shuffle vector operations with
types larger than 64bits. ImplicitDef and Freeze are also handled the
same way, to allow them to legalize. The legalization of
fewerElementsVectorShuffle is adjusted to handled scalarization.
Commit: eb1f9cced9e878362aeac18e120895995f759ee3
https://github.com/llvm/llvm-project/commit/eb1f9cced9e878362aeac18e120895995f759ee3
Author: Alex Rønne Petersen <alex at alexrp.com>
Date: 2024-12-15 (Sun, 15 Dec 2024)
Changed paths:
M libunwind/include/__libunwind_config.h
Log Message:
-----------
[libunwind] Fix compilation for the x32 ABI. (#116608)
This would previously fail the static assertions in `UnwindCursor.hpp`
due to `UnwindCursor`'s size not matching `unw_cursor_t`'s size. As is
done for MIPS N32, this just declares the appropriate size in
`__libunwind_config.h`.
Commit: 6b493baec1ada4ef714197803926c37cd9c56e03
https://github.com/llvm/llvm-project/commit/6b493baec1ada4ef714197803926c37cd9c56e03
Author: Jacek Caban <jacek at codeweavers.com>
Date: 2024-12-15 (Sun, 15 Dec 2024)
Changed paths:
M lld/COFF/Chunks.cpp
M lld/COFF/DLL.cpp
M lld/COFF/Driver.cpp
M lld/COFF/InputFiles.cpp
M lld/COFF/InputFiles.h
M lld/COFF/PDB.cpp
M lld/COFF/SymbolTable.cpp
M lld/COFF/SymbolTable.h
M lld/COFF/Symbols.cpp
Log Message:
-----------
[LLD][COFF] Store reference to SymbolTable instead of COFFLinkerContext in InputFile (NFC) (#119296)
This change prepares for the introduction of separate hybrid namespaces.
Hybrid images will require two `SymbolTable` instances, making it
necessary to associate `InputFile` objects with the relevant one.
Commit: 916bae2d921705c8ce78a4ddec4503c61bc8220c
https://github.com/llvm/llvm-project/commit/916bae2d921705c8ce78a4ddec4503c61bc8220c
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-12-15 (Sun, 15 Dec 2024)
Changed paths:
M llvm/lib/Transforms/Vectorize/VectorCombine.cpp
Log Message:
-----------
[VectorCombine] foldShuffleOfBinops - refactor to make it easier to match icmp/fcmp patterns
NFC refactor to make it easier to also use the fold for icmp/fcmp patterns in a future patch - match the Shuffle with general Instruction operands and avoid explicit use of the BinaryOperator matches as much as possible for the general costing / fold.
Commit: 734a204fbd4b790048c57f79351ad8beeb1000ce
https://github.com/llvm/llvm-project/commit/734a204fbd4b790048c57f79351ad8beeb1000ce
Author: Florian Hahn <flo at fhahn.com>
Date: 2024-12-15 (Sun, 15 Dec 2024)
Changed paths:
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
M llvm/lib/Transforms/Vectorize/VPlan.h
M llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
M llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
Log Message:
-----------
[VPlan] Manage VPWidenIntOrFPInduction debug location via recipe (NFC).
Properly set VPWidenIntOrFpInductionRecipe's debug location in the
recipe and use it, instead of using the debug location of the underlying
IR instruction.
Commit: e1271dd5a7ecf5cee59c8e2684b93501a1aab82d
https://github.com/llvm/llvm-project/commit/e1271dd5a7ecf5cee59c8e2684b93501a1aab82d
Author: Joseph Huber <huberjn at outlook.com>
Date: 2024-12-15 (Sun, 15 Dec 2024)
Changed paths:
M clang-tools-extra/clangd/index/SymbolCollector.cpp
M clang-tools-extra/clangd/unittests/SymbolCollectorTests.cpp
Log Message:
-----------
[clangd] Index reserved symbols from `*intrin.h` system headers (#119735)
Summary:
`clangd` intentionally suppresses indexing symbols from system headers
as these are likely implementation details the user does not want.
Howver, there are plenty of system headers that provide extensions that
we want to index, such as vector intrinsic headers. This patch adds an
extra check for these commonly-named '*intrin.h' headers. This is not
fully inclusive for all symbols the user might want, but it's a good
start.
Fixes: https://github.com/llvm/llvm-project/issues/118684
---------
Co-authored-by: Nathan Ridge <zeratul976 at hotmail.com>
Commit: e85a9f5540f5399b20a32c8d87474e6fc906ad33
https://github.com/llvm/llvm-project/commit/e85a9f5540f5399b20a32c8d87474e6fc906ad33
Author: Jinsong Ji <jinsong.ji at intel.com>
Date: 2024-12-15 (Sun, 15 Dec 2024)
Changed paths:
M libc/shared/rpc.h
M libc/utils/gpu/loader/Loader.h
M libc/utils/gpu/server/rpc_server.cpp
M offload/plugins-nextgen/common/src/RPC.cpp
Log Message:
-----------
libc: Prefix RPC Status code to avoid conflict in windows build (#119991)
Somehow conflict with define in wingdi.h.
Fix build failures:
[ 52%] Building CXX object
projects/offload/plugins-nextgen/common/CMakeFiles/PluginCommon.dir/src/RPC.cpp.obj
In file included from
...llvm\offload\plugins-nextgen\common\src\RPC.cpp:16:
...\llvm\libc\shared\rpc.h(48,3): error: expected identifier
48 | ERROR = 0x1000,
| ^
c:\Program files (x86)\Windows
Kits\10\include\10.0.22000.0\um\wingdi.h(118,29): note: expanded from
macro 'ERROR'
118 | #define ERROR 0
| ^
...\llvm\offload\plugins-nextgen\common\src\RPC.cpp(75,17): error:
expected unqualified-id
75 | return rpc::ERROR;
| ^
c:\Program files (x86)\Windows
Kits\10\include\10.0.22000.0\um\wingdi.h(118,29): note: expanded from
macro 'ERROR'
118 | #define ERROR 0
| ^
2 errors generated.
Commit: 6c98f70b30408916de6ad5cb82081ca7d9b1c39e
https://github.com/llvm/llvm-project/commit/6c98f70b30408916de6ad5cb82081ca7d9b1c39e
Author: Florian Hahn <flo at fhahn.com>
Date: 2024-12-15 (Sun, 15 Dec 2024)
Changed paths:
M llvm/test/Transforms/LoopVectorize/preserve-dbg-loc-and-loop-metadata.ll
Log Message:
-----------
[LV] Add test with missing debug location for pointer IV in vector loop.
Commit: 2067e604a49d49ce054d61a0109ec12a724e3db2
https://github.com/llvm/llvm-project/commit/2067e604a49d49ce054d61a0109ec12a724e3db2
Author: Florian Hahn <flo at fhahn.com>
Date: 2024-12-15 (Sun, 15 Dec 2024)
Changed paths:
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
M llvm/lib/Transforms/Vectorize/VPlan.h
M llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
M llvm/test/Transforms/LoopVectorize/preserve-dbg-loc-and-loop-metadata.ll
Log Message:
-----------
[VPlan] Manage VPWidenPointerInduction debug location via recipe.
Update VPWidenPointerInduction to manage its debug location via recipe.
This makes sure we emit a proper debug location for
VPWidenPointerInductionRecipes.
Commit: 49a5ad8e5714fd404210279303acc97b495d66d0
https://github.com/llvm/llvm-project/commit/49a5ad8e5714fd404210279303acc97b495d66d0
Author: Malte Dehling <mdehling at gmail.com>
Date: 2024-12-15 (Sun, 15 Dec 2024)
Changed paths:
M mlir/docs/Dialects/Transform.md
Log Message:
-----------
[mlir] Add DLTI transform ops section (#118153)
Adds missing _DLTI Transform Operations_ section to the transform
dialect documentation.
Co-authored-by: Malte Dehling <m.dehling at samsung.com>
Commit: b0746c68629c26567cd123d8f9b28e796ef26f47
https://github.com/llvm/llvm-project/commit/b0746c68629c26567cd123d8f9b28e796ef26f47
Author: Kazu Hirata <kazu at google.com>
Date: 2024-12-15 (Sun, 15 Dec 2024)
Changed paths:
M mlir/tools/mlir-tblgen/OpDefinitionsGen.cpp
M mlir/tools/mlir-tblgen/OpPythonBindingGen.cpp
M mlir/tools/mlir-tblgen/RewriterGen.cpp
M mlir/tools/mlir-tblgen/SPIRVUtilsGen.cpp
Log Message:
-----------
[mlir-tblgen] Migrate away from PointerUnion::{is,get} (NFC) (#119994)
Note that PointerUnion::{is,get} have been soft deprecated in
PointerUnion.h:
// FIXME: Replace the uses of is(), get() and dyn_cast() with
// isa<T>, cast<T> and the llvm::dyn_cast<T>
I'm not touching PointerUnion::dyn_cast for now because it's a bit
complicated; we could blindly migrate it to dyn_cast_if_present, but
we should probably use dyn_cast when the operand is known to be
non-null.
Commit: a22578d38c773b3969fc02f80ffd7042dc4ad3e3
https://github.com/llvm/llvm-project/commit/a22578d38c773b3969fc02f80ffd7042dc4ad3e3
Author: Ramkumar Ramachandra <ramkumar.ramachandra at codasip.com>
Date: 2024-12-15 (Sun, 15 Dec 2024)
Changed paths:
M llvm/lib/Transforms/Scalar/ConstraintElimination.cpp
A llvm/test/Transforms/ConstraintElimination/transfer-samesign-facts.ll
Log Message:
-----------
ConstraintElim: teach fact-transfer about samesign (#115893)
When the samesign flag is present on an icmp, we can transfer all the
facts on the unsigned system to the signed system, and vice-versa: we do
this by specializing transferToOtherSystem when samesign is present.
Commit: 0a9810d32599e515236940ce15631cfa8586d403
https://github.com/llvm/llvm-project/commit/0a9810d32599e515236940ce15631cfa8586d403
Author: Jacek Caban <jacek at codeweavers.com>
Date: 2024-12-15 (Sun, 15 Dec 2024)
Changed paths:
M lld/COFF/Driver.cpp
M lld/COFF/Driver.h
M lld/COFF/SymbolTable.cpp
Log Message:
-----------
[LLD][COFF] Factor out LinkerDriver::setMachine (NFC) (#119297)
Commit: d3c485717979add739b90c82b7bc79a1e57f3cd2
https://github.com/llvm/llvm-project/commit/d3c485717979add739b90c82b7bc79a1e57f3cd2
Author: Jacek Caban <jacek at codeweavers.com>
Date: 2024-12-15 (Sun, 15 Dec 2024)
Changed paths:
M lld/COFF/DLL.cpp
M lld/COFF/Driver.cpp
M lld/COFF/InputFiles.cpp
M lld/COFF/SymbolTable.cpp
M lld/COFF/SymbolTable.h
Log Message:
-----------
[LLD][COFF] Store machine type in SymbolTable (NFC) (#119298)
This change prepares for hybrid ARM64X support, which requires two
`SymbolTable` instances: one for native symbols and one for EC symbols.
In such cases, `config.machine` will remain ARM64X, while the
`SymbolTable` instances will store ARM64 and ARM64EC machine types.
Commit: a8206e7b37929f4754806667680ffba0206eef95
https://github.com/llvm/llvm-project/commit/a8206e7b37929f4754806667680ffba0206eef95
Author: Jacek Caban <jacek at codeweavers.com>
Date: 2024-12-15 (Sun, 15 Dec 2024)
Changed paths:
M lld/COFF/COFFLinkerContext.h
M lld/COFF/Driver.cpp
M lld/COFF/InputFiles.cpp
M lld/COFF/InputFiles.h
M lld/COFF/SymbolTable.h
M lld/test/COFF/arm64ec-codemap.test
M lld/test/COFF/arm64ec-entry-thunk.s
M lld/test/COFF/arm64ec-lib.test
M lld/test/COFF/arm64ec-range-thunks.s
A lld/test/COFF/arm64x-symtab.s
Log Message:
-----------
[LLD][COFF] Introduce hybrid symbol table for EC input files on ARM64X (#119294)
On hybrid ARM64X targets, ARM64 and ARM64EC input files operate in
separate namespaces and cannot reference each other. This change
introduces separate `SymbolTable` instances and associates each
`InputFile` with the appropriate table to reflect this behavior.
Commit: 6a865b6d3d44e53adc9342fb2d80a604f5459707
https://github.com/llvm/llvm-project/commit/6a865b6d3d44e53adc9342fb2d80a604f5459707
Author: wldfngrs <wldfngrs at gmail.com>
Date: 2024-12-15 (Sun, 15 Dec 2024)
Changed paths:
M libc/config/linux/x86_64/entrypoints.txt
M libc/docs/headers/math/index.rst
M libc/hdrgen/yaml/math.yaml
M libc/src/math/CMakeLists.txt
A libc/src/math/cosf16.h
M libc/src/math/generic/CMakeLists.txt
A libc/src/math/generic/cosf16.cpp
M libc/src/math/generic/cospif16.cpp
M libc/src/math/generic/sinf16.cpp
M libc/test/src/math/CMakeLists.txt
A libc/test/src/math/cosf16_test.cpp
M libc/test/src/math/smoke/CMakeLists.txt
A libc/test/src/math/smoke/cosf16_test.cpp
Log Message:
-----------
[libc][math][c23] Add cosf16 function (#118785)
Commit: 171056ff5778c40df916c5a4cea84ea6320b965f
https://github.com/llvm/llvm-project/commit/171056ff5778c40df916c5a4cea84ea6320b965f
Author: Fangrui Song <i at maskray.me>
Date: 2024-12-15 (Sun, 15 Dec 2024)
Changed paths:
M llvm/test/CodeGen/M68k/GlobalISel/legalize-add.mir
M llvm/test/CodeGen/M68k/GlobalISel/legalize-and.mir
M llvm/test/CodeGen/M68k/GlobalISel/legalize-load-store.mir
M llvm/test/CodeGen/M68k/GlobalISel/legalize-mul.mir
M llvm/test/CodeGen/M68k/GlobalISel/legalize-sub.mir
M llvm/test/CodeGen/M68k/GlobalISel/legalize-udiv.mir
M llvm/test/CodeGen/MSP430/2009-05-17-Rot.ll
M llvm/test/CodeGen/MSP430/2009-05-17-Shift.ll
M llvm/test/CodeGen/MSP430/2009-05-19-DoubleSplit.ll
M llvm/test/CodeGen/MSP430/2009-10-10-OrImpDef.ll
M llvm/test/CodeGen/MSP430/2009-11-20-NewNode.ll
M llvm/test/CodeGen/MSP430/AddrMode-bis-rx.ll
M llvm/test/CodeGen/MSP430/AddrMode-bis-xr.ll
M llvm/test/CodeGen/MSP430/AddrMode-mov-rx.ll
M llvm/test/CodeGen/MSP430/AddrMode-mov-xr.ll
M llvm/test/CodeGen/MSP430/BranchSelector.ll
M llvm/test/CodeGen/MSP430/DbgValueOtherTargets.test
M llvm/test/CodeGen/MSP430/Inst16mi.ll
M llvm/test/CodeGen/MSP430/Inst16mm.ll
M llvm/test/CodeGen/MSP430/Inst16mr.ll
M llvm/test/CodeGen/MSP430/Inst16ri.ll
M llvm/test/CodeGen/MSP430/Inst16rm.ll
M llvm/test/CodeGen/MSP430/Inst16rr.ll
M llvm/test/CodeGen/MSP430/Inst8mi.ll
M llvm/test/CodeGen/MSP430/Inst8mm.ll
M llvm/test/CodeGen/MSP430/Inst8mr.ll
M llvm/test/CodeGen/MSP430/Inst8ri.ll
M llvm/test/CodeGen/MSP430/Inst8rm.ll
M llvm/test/CodeGen/MSP430/Inst8rr.ll
M llvm/test/CodeGen/MSP430/InstII.ll
M llvm/test/CodeGen/MSP430/bit.ll
M llvm/test/CodeGen/MSP430/flt_rounds.ll
M llvm/test/CodeGen/MSP430/indirectbr.ll
M llvm/test/CodeGen/MSP430/indirectbr2.ll
M llvm/test/CodeGen/MSP430/mult-alt-generic-msp430.ll
M llvm/test/CodeGen/MSP430/select-use-sr.ll
M llvm/test/CodeGen/MSP430/setcc.ll
M llvm/test/CodeGen/MSP430/spill-to-stack.ll
M llvm/test/CodeGen/MSP430/stacksave_restore.ll
M llvm/test/CodeGen/MSP430/umulo-16.ll
Log Message:
-----------
[M68k,MSP430,test] Change llc -march= to -mtriple=
Similar to 806761a7629df268c8aed49657aeccffa6bca449
Commit: 2208c97c1bec2512d4e47b6223db6d95a7037956
https://github.com/llvm/llvm-project/commit/2208c97c1bec2512d4e47b6223db6d95a7037956
Author: Fangrui Song <i at maskray.me>
Date: 2024-12-15 (Sun, 15 Dec 2024)
Changed paths:
M llvm/test/CodeGen/Hexagon/64bit_tstbit.ll
M llvm/test/CodeGen/Hexagon/Atomics.ll
M llvm/test/CodeGen/Hexagon/BranchPredict.ll
M llvm/test/CodeGen/Hexagon/Halide_vec_cast_trunc1.ll
M llvm/test/CodeGen/Hexagon/Halide_vec_cast_trunc2.ll
M llvm/test/CodeGen/Hexagon/M4_mpyri_addi_global.ll
M llvm/test/CodeGen/Hexagon/M4_mpyrr_addi_global.ll
M llvm/test/CodeGen/Hexagon/NVJumpCmp.ll
M llvm/test/CodeGen/Hexagon/P08214.ll
M llvm/test/CodeGen/Hexagon/PR33749.ll
M llvm/test/CodeGen/Hexagon/SUnit-boundary-prob.ll
M llvm/test/CodeGen/Hexagon/V60-VDblNew.ll
M llvm/test/CodeGen/Hexagon/abi-padding-2.ll
M llvm/test/CodeGen/Hexagon/abi-padding.ll
M llvm/test/CodeGen/Hexagon/abs.ll
M llvm/test/CodeGen/Hexagon/absaddr-store.ll
M llvm/test/CodeGen/Hexagon/absimm.ll
M llvm/test/CodeGen/Hexagon/add-use.ll
M llvm/test/CodeGen/Hexagon/add_int_double.ll
M llvm/test/CodeGen/Hexagon/add_mpi_RRR.ll
M llvm/test/CodeGen/Hexagon/addaddi.ll
M llvm/test/CodeGen/Hexagon/addasl-address.ll
M llvm/test/CodeGen/Hexagon/addh-sext-trunc.ll
M llvm/test/CodeGen/Hexagon/addh-shifted.ll
M llvm/test/CodeGen/Hexagon/addh.ll
M llvm/test/CodeGen/Hexagon/addr-calc-opt.ll
M llvm/test/CodeGen/Hexagon/addr-mode-opt.ll
M llvm/test/CodeGen/Hexagon/addrmode-align.ll
M llvm/test/CodeGen/Hexagon/addrmode-globoff.mir
M llvm/test/CodeGen/Hexagon/addrmode-immop.mir
M llvm/test/CodeGen/Hexagon/addrmode-indoff.ll
M llvm/test/CodeGen/Hexagon/addrmode-keepdeadphis.ll
M llvm/test/CodeGen/Hexagon/addrmode-keepdeadphis.mir
M llvm/test/CodeGen/Hexagon/addrmode-no-rdef.mir
M llvm/test/CodeGen/Hexagon/addrmode-offset.ll
M llvm/test/CodeGen/Hexagon/addrmode-opt-assert.mir
M llvm/test/CodeGen/Hexagon/addrmode-rr-to-io.mir
M llvm/test/CodeGen/Hexagon/addsubcarry.ll
M llvm/test/CodeGen/Hexagon/adjust-latency-stackST.ll
M llvm/test/CodeGen/Hexagon/aggr-antidep-tied.ll
M llvm/test/CodeGen/Hexagon/aggr-copy-order.ll
M llvm/test/CodeGen/Hexagon/aggr-licm.ll
M llvm/test/CodeGen/Hexagon/aggressive_licm.ll
M llvm/test/CodeGen/Hexagon/align_Os.ll
M llvm/test/CodeGen/Hexagon/align_test.ll
M llvm/test/CodeGen/Hexagon/alu64.ll
M llvm/test/CodeGen/Hexagon/always-ext.ll
M llvm/test/CodeGen/Hexagon/anti-dep-partial.mir
M llvm/test/CodeGen/Hexagon/args.ll
M llvm/test/CodeGen/Hexagon/ashift-left-right.ll
M llvm/test/CodeGen/Hexagon/asr-rnd.ll
M llvm/test/CodeGen/Hexagon/asr-rnd64.ll
M llvm/test/CodeGen/Hexagon/assert-postinc-ptr-not-value.ll
M llvm/test/CodeGen/Hexagon/atomic-opaque-basic.ll
M llvm/test/CodeGen/Hexagon/atomic-rmw-add.ll
M llvm/test/CodeGen/Hexagon/atomicrmw-cond-sub-clamp.ll
M llvm/test/CodeGen/Hexagon/atomicrmw-uinc-udec-wrap.ll
M llvm/test/CodeGen/Hexagon/autohvx/abs.ll
M llvm/test/CodeGen/Hexagon/autohvx/addi-offset-opt-addr-mode.ll
M llvm/test/CodeGen/Hexagon/autohvx/addi-opt-predicated-def-bug.ll
M llvm/test/CodeGen/Hexagon/autohvx/align-128b.ll
M llvm/test/CodeGen/Hexagon/autohvx/align-64b.ll
M llvm/test/CodeGen/Hexagon/autohvx/align2-128b.ll
M llvm/test/CodeGen/Hexagon/autohvx/align2-64b.ll
M llvm/test/CodeGen/Hexagon/autohvx/arith-float.ll
M llvm/test/CodeGen/Hexagon/autohvx/arith.ll
M llvm/test/CodeGen/Hexagon/autohvx/bitcount-128b.ll
M llvm/test/CodeGen/Hexagon/autohvx/bitcount-64b.ll
M llvm/test/CodeGen/Hexagon/autohvx/bitwise-pred-128b.ll
M llvm/test/CodeGen/Hexagon/autohvx/bitwise-pred-64b.ll
M llvm/test/CodeGen/Hexagon/autohvx/bswap.ll
M llvm/test/CodeGen/Hexagon/autohvx/build-vector-float-type.ll
M llvm/test/CodeGen/Hexagon/autohvx/build-vector-i32-128b.ll
M llvm/test/CodeGen/Hexagon/autohvx/build-vector-i32-64b.ll
M llvm/test/CodeGen/Hexagon/autohvx/build-vector-i32-type.ll
M llvm/test/CodeGen/Hexagon/autohvx/calling-conv.ll
M llvm/test/CodeGen/Hexagon/autohvx/concat-vectors-128b.ll
M llvm/test/CodeGen/Hexagon/autohvx/concat-vectors-64b.ll
M llvm/test/CodeGen/Hexagon/autohvx/contract-128b.ll
M llvm/test/CodeGen/Hexagon/autohvx/contract-64b.ll
M llvm/test/CodeGen/Hexagon/autohvx/conv-fp-fp.ll
M llvm/test/CodeGen/Hexagon/autohvx/conv-fp-int-ieee.ll
M llvm/test/CodeGen/Hexagon/autohvx/ctpop-split.ll
M llvm/test/CodeGen/Hexagon/autohvx/deal-128b.ll
M llvm/test/CodeGen/Hexagon/autohvx/deal-64b.ll
M llvm/test/CodeGen/Hexagon/autohvx/delta-128b.ll
M llvm/test/CodeGen/Hexagon/autohvx/delta-64b.ll
M llvm/test/CodeGen/Hexagon/autohvx/delta2-64b.ll
M llvm/test/CodeGen/Hexagon/autohvx/extract-element.ll
M llvm/test/CodeGen/Hexagon/autohvx/fp-to-int.ll
M llvm/test/CodeGen/Hexagon/autohvx/funnel-128b.ll
M llvm/test/CodeGen/Hexagon/autohvx/hfinsert.ll
M llvm/test/CodeGen/Hexagon/autohvx/hvx-idiom-empty-results.ll
M llvm/test/CodeGen/Hexagon/autohvx/int-to-fp.ll
M llvm/test/CodeGen/Hexagon/autohvx/isel-anyext-inreg.ll
M llvm/test/CodeGen/Hexagon/autohvx/isel-anyext-pair.ll
M llvm/test/CodeGen/Hexagon/autohvx/isel-bitcast-vsplat.ll
M llvm/test/CodeGen/Hexagon/autohvx/isel-bitcast-vsplat2.ll
M llvm/test/CodeGen/Hexagon/autohvx/isel-bool-vector.ll
M llvm/test/CodeGen/Hexagon/autohvx/isel-build-undef.ll
M llvm/test/CodeGen/Hexagon/autohvx/isel-build-vector.ll
M llvm/test/CodeGen/Hexagon/autohvx/isel-concat-multiple.ll
M llvm/test/CodeGen/Hexagon/autohvx/isel-concat-vectors-bool.ll
M llvm/test/CodeGen/Hexagon/autohvx/isel-concat-vectors.ll
M llvm/test/CodeGen/Hexagon/autohvx/isel-const-splat-bitcast.ll
M llvm/test/CodeGen/Hexagon/autohvx/isel-const-splat-imm.ll
M llvm/test/CodeGen/Hexagon/autohvx/isel-const-splat.ll
M llvm/test/CodeGen/Hexagon/autohvx/isel-const-vector.ll
M llvm/test/CodeGen/Hexagon/autohvx/isel-expand-unaligned-loads-noindexed.ll
M llvm/test/CodeGen/Hexagon/autohvx/isel-expand-unaligned-loads.ll
M llvm/test/CodeGen/Hexagon/autohvx/isel-extractelt-illegal-type.ll
M llvm/test/CodeGen/Hexagon/autohvx/isel-hvx-concat-truncate.ll
M llvm/test/CodeGen/Hexagon/autohvx/isel-hvx-pred-bitcast.ll
M llvm/test/CodeGen/Hexagon/autohvx/isel-insert-subvector-v4i8.ll
M llvm/test/CodeGen/Hexagon/autohvx/isel-intrinsics.ll
M llvm/test/CodeGen/Hexagon/autohvx/isel-mstore-fp16.ll
M llvm/test/CodeGen/Hexagon/autohvx/isel-q-legalization-loop.ll
M llvm/test/CodeGen/Hexagon/autohvx/isel-q2v-pair.ll
M llvm/test/CodeGen/Hexagon/autohvx/isel-qfalse.ll
M llvm/test/CodeGen/Hexagon/autohvx/isel-select-const.ll
M llvm/test/CodeGen/Hexagon/autohvx/isel-select-q.ll
M llvm/test/CodeGen/Hexagon/autohvx/isel-setcc-pair-fp.ll
M llvm/test/CodeGen/Hexagon/autohvx/isel-setcc-pair.ll
M llvm/test/CodeGen/Hexagon/autohvx/isel-setcc-v256i1.ll
M llvm/test/CodeGen/Hexagon/autohvx/isel-sext-inreg.ll
M llvm/test/CodeGen/Hexagon/autohvx/isel-shift-byte.ll
M llvm/test/CodeGen/Hexagon/autohvx/isel-shuff-single.ll
M llvm/test/CodeGen/Hexagon/autohvx/isel-shuffle-gather.ll
M llvm/test/CodeGen/Hexagon/autohvx/isel-shuffle-isdisel.ll
M llvm/test/CodeGen/Hexagon/autohvx/isel-shuffle-no-perfect-completion.ll
M llvm/test/CodeGen/Hexagon/autohvx/isel-shuffle-pack.ll
M llvm/test/CodeGen/Hexagon/autohvx/isel-split-masked.ll
M llvm/test/CodeGen/Hexagon/autohvx/isel-store-bitcast-v128i1.ll
M llvm/test/CodeGen/Hexagon/autohvx/isel-truncate-legal.ll
M llvm/test/CodeGen/Hexagon/autohvx/isel-truncate.ll
M llvm/test/CodeGen/Hexagon/autohvx/isel-undef-not-zero.ll
M llvm/test/CodeGen/Hexagon/autohvx/isel-vec-ext.ll
M llvm/test/CodeGen/Hexagon/autohvx/isel-vpackew.ll
M llvm/test/CodeGen/Hexagon/autohvx/isel-vsplat-pair.ll
M llvm/test/CodeGen/Hexagon/autohvx/isel-widen-memop.ll
M llvm/test/CodeGen/Hexagon/autohvx/isel-widen-store.ll
M llvm/test/CodeGen/Hexagon/autohvx/isel-widen-truncate-illegal-elem.ll
M llvm/test/CodeGen/Hexagon/autohvx/isel-widen-truncate-op.ll
M llvm/test/CodeGen/Hexagon/autohvx/isel-widen-truncate-pair.ll
M llvm/test/CodeGen/Hexagon/autohvx/isel-widen-truncate.ll
M llvm/test/CodeGen/Hexagon/autohvx/logical-128b.ll
M llvm/test/CodeGen/Hexagon/autohvx/logical-64b.ll
M llvm/test/CodeGen/Hexagon/autohvx/lower-insert-elt.ll
M llvm/test/CodeGen/Hexagon/autohvx/masked-vmem-basic.ll
M llvm/test/CodeGen/Hexagon/autohvx/minmax-128b.ll
M llvm/test/CodeGen/Hexagon/autohvx/minmax-64b.ll
M llvm/test/CodeGen/Hexagon/autohvx/minmax-float.ll
M llvm/test/CodeGen/Hexagon/autohvx/mulh.ll
M llvm/test/CodeGen/Hexagon/autohvx/non-simple-hvx-type.ll
M llvm/test/CodeGen/Hexagon/autohvx/perfect-single.ll
M llvm/test/CodeGen/Hexagon/autohvx/pred-vmem-128b.ll
M llvm/test/CodeGen/Hexagon/autohvx/pred-vmem-64b.ll
M llvm/test/CodeGen/Hexagon/autohvx/qmul-add-over-32-bit.ll
M llvm/test/CodeGen/Hexagon/autohvx/qmul-chop.ll
M llvm/test/CodeGen/Hexagon/autohvx/qmul.ll
M llvm/test/CodeGen/Hexagon/autohvx/reg-sequence.ll
M llvm/test/CodeGen/Hexagon/autohvx/shift-128b.ll
M llvm/test/CodeGen/Hexagon/autohvx/shift-64b.ll
M llvm/test/CodeGen/Hexagon/autohvx/shuff-128b.ll
M llvm/test/CodeGen/Hexagon/autohvx/shuff-64b.ll
M llvm/test/CodeGen/Hexagon/autohvx/shuff-combos-128b.ll
M llvm/test/CodeGen/Hexagon/autohvx/shuff-combos-64b.ll
M llvm/test/CodeGen/Hexagon/autohvx/shuff-perfect-inverted-pair.ll
M llvm/test/CodeGen/Hexagon/autohvx/shuff-single.ll
M llvm/test/CodeGen/Hexagon/autohvx/shuffle-expanding-128b.ll
M llvm/test/CodeGen/Hexagon/autohvx/shuffle-expanding-64b.ll
M llvm/test/CodeGen/Hexagon/autohvx/shuffle-half-128b.ll
M llvm/test/CodeGen/Hexagon/autohvx/shuffle-half-64b.ll
M llvm/test/CodeGen/Hexagon/autohvx/splat.ll
M llvm/test/CodeGen/Hexagon/autohvx/vdd0.ll
M llvm/test/CodeGen/Hexagon/autohvx/vector-align-addr.ll
M llvm/test/CodeGen/Hexagon/autohvx/vector-align-bad-move.ll
M llvm/test/CodeGen/Hexagon/autohvx/vector-align-bad-move3.ll
M llvm/test/CodeGen/Hexagon/autohvx/vector-align-base-type-mismatch.ll
M llvm/test/CodeGen/Hexagon/autohvx/vector-align-basic.ll
M llvm/test/CodeGen/Hexagon/autohvx/vector-align-interleaved.ll
M llvm/test/CodeGen/Hexagon/autohvx/vector-align-only-phi-use.ll
M llvm/test/CodeGen/Hexagon/autohvx/vector-align-order.ll
M llvm/test/CodeGen/Hexagon/autohvx/vector-align-rescale-nonint.ll
M llvm/test/CodeGen/Hexagon/autohvx/vector-align-scalar-mask.ll
M llvm/test/CodeGen/Hexagon/autohvx/vector-align-store-mask.ll
M llvm/test/CodeGen/Hexagon/autohvx/vector-align-store.ll
M llvm/test/CodeGen/Hexagon/autohvx/vector-align-terminator.ll
M llvm/test/CodeGen/Hexagon/autohvx/vector-align-use-in-different-block.ll
M llvm/test/CodeGen/Hexagon/autohvx/vector-compare-128b.ll
M llvm/test/CodeGen/Hexagon/autohvx/vector-compare-64b.ll
M llvm/test/CodeGen/Hexagon/autohvx/vector-compare-float.ll
M llvm/test/CodeGen/Hexagon/autohvx/vector-load-store-basic.ll
M llvm/test/CodeGen/Hexagon/autohvx/vector-predicate-typecast.ll
M llvm/test/CodeGen/Hexagon/autohvx/vext-128b.ll
M llvm/test/CodeGen/Hexagon/autohvx/vext-64b.ll
M llvm/test/CodeGen/Hexagon/autohvx/vmpy-parts.ll
M llvm/test/CodeGen/Hexagon/autohvx/vmux-order.ll
M llvm/test/CodeGen/Hexagon/autohvx/widen-ext.ll
M llvm/test/CodeGen/Hexagon/autohvx/widen-setcc.ll
M llvm/test/CodeGen/Hexagon/autohvx/widen-trunc.ll
M llvm/test/CodeGen/Hexagon/avoid-predspill-calleesaved.ll
M llvm/test/CodeGen/Hexagon/avoid-predspill.ll
M llvm/test/CodeGen/Hexagon/avoidVectorLowering.ll
M llvm/test/CodeGen/Hexagon/bank-conflict-load.mir
M llvm/test/CodeGen/Hexagon/bank-conflict.mir
M llvm/test/CodeGen/Hexagon/barrier-flag.ll
M llvm/test/CodeGen/Hexagon/base-offset-addr.ll
M llvm/test/CodeGen/Hexagon/base-offset-post.ll
M llvm/test/CodeGen/Hexagon/base-offset-stv4.ll
M llvm/test/CodeGen/Hexagon/bit-addr-align.mir
M llvm/test/CodeGen/Hexagon/bit-bitsplit-at.ll
M llvm/test/CodeGen/Hexagon/bit-bitsplit-regclass.ll
M llvm/test/CodeGen/Hexagon/bit-bitsplit-src.ll
M llvm/test/CodeGen/Hexagon/bit-bitsplit.ll
M llvm/test/CodeGen/Hexagon/bit-cmp0.mir
M llvm/test/CodeGen/Hexagon/bit-eval.ll
M llvm/test/CodeGen/Hexagon/bit-ext-sat.ll
M llvm/test/CodeGen/Hexagon/bit-extract-off.ll
M llvm/test/CodeGen/Hexagon/bit-extract.ll
M llvm/test/CodeGen/Hexagon/bit-extractu-half.ll
M llvm/test/CodeGen/Hexagon/bit-gen-rseq.ll
M llvm/test/CodeGen/Hexagon/bit-has.ll
M llvm/test/CodeGen/Hexagon/bit-loop-rc-mismatch.ll
M llvm/test/CodeGen/Hexagon/bit-loop.ll
M llvm/test/CodeGen/Hexagon/bit-phi.ll
M llvm/test/CodeGen/Hexagon/bit-rie.ll
M llvm/test/CodeGen/Hexagon/bit-skip-byval.ll
M llvm/test/CodeGen/Hexagon/bit-store-upper-sub-hi.mir
M llvm/test/CodeGen/Hexagon/bit-validate-reg.ll
M llvm/test/CodeGen/Hexagon/bit-visit-flowq.ll
M llvm/test/CodeGen/Hexagon/bitcast-i128-to-v128i1.ll
M llvm/test/CodeGen/Hexagon/bitconvert-vector.ll
M llvm/test/CodeGen/Hexagon/bitmanip.ll
M llvm/test/CodeGen/Hexagon/bkfir.ll
M llvm/test/CodeGen/Hexagon/block-addr.ll
M llvm/test/CodeGen/Hexagon/block-address.ll
M llvm/test/CodeGen/Hexagon/block-ranges-nodef.ll
M llvm/test/CodeGen/Hexagon/blockaddr-fpic.ll
M llvm/test/CodeGen/Hexagon/branch-folder-hoist-kills.mir
M llvm/test/CodeGen/Hexagon/branch-non-mbb.ll
M llvm/test/CodeGen/Hexagon/branchfolder-insert-impdef.mir
M llvm/test/CodeGen/Hexagon/branchfolder-keep-impdef.ll
M llvm/test/CodeGen/Hexagon/brcond-setne.ll
M llvm/test/CodeGen/Hexagon/brev_ld.ll
M llvm/test/CodeGen/Hexagon/brev_st.ll
M llvm/test/CodeGen/Hexagon/bss-local.ll
M llvm/test/CodeGen/Hexagon/bug-aa4463-ifconv-vecpred.ll
M llvm/test/CodeGen/Hexagon/bug-allocframe-size.ll
M llvm/test/CodeGen/Hexagon/bug-hcp-tied-kill.ll
M llvm/test/CodeGen/Hexagon/bug14859-iv-cleanup-lpad.ll
M llvm/test/CodeGen/Hexagon/bug14859-split-const-block-addr.ll
M llvm/test/CodeGen/Hexagon/bug17276.ll
M llvm/test/CodeGen/Hexagon/bug17386.ll
M llvm/test/CodeGen/Hexagon/bug18008.ll
M llvm/test/CodeGen/Hexagon/bug18491-optsize.ll
M llvm/test/CodeGen/Hexagon/bug19076.ll
M llvm/test/CodeGen/Hexagon/bug19119.ll
M llvm/test/CodeGen/Hexagon/bug19254-ifconv-vec.ll
M llvm/test/CodeGen/Hexagon/bug27085.ll
M llvm/test/CodeGen/Hexagon/bug31839.ll
M llvm/test/CodeGen/Hexagon/bug6757-endloop.ll
M llvm/test/CodeGen/Hexagon/bug9049.ll
M llvm/test/CodeGen/Hexagon/bug9963.ll
M llvm/test/CodeGen/Hexagon/bugAsmHWloop.ll
M llvm/test/CodeGen/Hexagon/build-vector-shuffle.ll
M llvm/test/CodeGen/Hexagon/build-vector-v4i8-zext.ll
M llvm/test/CodeGen/Hexagon/builtin-expect.ll
M llvm/test/CodeGen/Hexagon/builtin-prefetch-offset.ll
M llvm/test/CodeGen/Hexagon/builtin-prefetch.ll
M llvm/test/CodeGen/Hexagon/call-long1.ll
M llvm/test/CodeGen/Hexagon/call-ret-i1.ll
M llvm/test/CodeGen/Hexagon/call-v4.ll
M llvm/test/CodeGen/Hexagon/callR_noreturn.ll
M llvm/test/CodeGen/Hexagon/calling-conv-2.ll
M llvm/test/CodeGen/Hexagon/calling-conv.ll
M llvm/test/CodeGen/Hexagon/callr-dep-edge.ll
M llvm/test/CodeGen/Hexagon/cext-check.ll
M llvm/test/CodeGen/Hexagon/cext-ice.ll
M llvm/test/CodeGen/Hexagon/cext-opt-basic.mir
M llvm/test/CodeGen/Hexagon/cext-opt-block-addr.mir
M llvm/test/CodeGen/Hexagon/cext-opt-negative-fi.mir
M llvm/test/CodeGen/Hexagon/cext-opt-numops.mir
M llvm/test/CodeGen/Hexagon/cext-opt-range-assert.mir
M llvm/test/CodeGen/Hexagon/cext-opt-range-offset.mir
M llvm/test/CodeGen/Hexagon/cext-opt-shifted-range.mir
M llvm/test/CodeGen/Hexagon/cext-opt-stack-no-rr.mir
M llvm/test/CodeGen/Hexagon/cext-unnamed-global.mir
M llvm/test/CodeGen/Hexagon/cext-valid-packet1.ll
M llvm/test/CodeGen/Hexagon/cext-valid-packet2.ll
M llvm/test/CodeGen/Hexagon/cext.ll
M llvm/test/CodeGen/Hexagon/cexti16.ll
M llvm/test/CodeGen/Hexagon/cfgopt-fall-through.ll
M llvm/test/CodeGen/Hexagon/cfi-late-and-regpressure-init.ll
M llvm/test/CodeGen/Hexagon/cfi-late.ll
M llvm/test/CodeGen/Hexagon/cfi-offset.ll
M llvm/test/CodeGen/Hexagon/cfi_offset.ll
M llvm/test/CodeGen/Hexagon/cfi_offset2.ll
M llvm/test/CodeGen/Hexagon/check-dot-new.ll
M llvm/test/CodeGen/Hexagon/check-subregister-for-latency.ll
M llvm/test/CodeGen/Hexagon/checktabs.ll
M llvm/test/CodeGen/Hexagon/circ-load-isel.ll
M llvm/test/CodeGen/Hexagon/circ_ld.ll
M llvm/test/CodeGen/Hexagon/circ_ldd_bug.ll
M llvm/test/CodeGen/Hexagon/circ_ldw.ll
M llvm/test/CodeGen/Hexagon/circ_new.ll
M llvm/test/CodeGen/Hexagon/circ_pcr_assert.ll
M llvm/test/CodeGen/Hexagon/circ_st.ll
M llvm/test/CodeGen/Hexagon/clr_set_toggle.ll
M llvm/test/CodeGen/Hexagon/cmp-extend.ll
M llvm/test/CodeGen/Hexagon/cmp-promote.ll
M llvm/test/CodeGen/Hexagon/cmp-to-genreg.ll
M llvm/test/CodeGen/Hexagon/cmp-to-predreg.ll
M llvm/test/CodeGen/Hexagon/cmp_pred.ll
M llvm/test/CodeGen/Hexagon/cmp_pred2.ll
M llvm/test/CodeGen/Hexagon/cmp_pred_reg.ll
M llvm/test/CodeGen/Hexagon/cmpb-dec-imm.ll
M llvm/test/CodeGen/Hexagon/cmpb-eq.ll
M llvm/test/CodeGen/Hexagon/cmpb_gtu.ll
M llvm/test/CodeGen/Hexagon/cmpb_pred.ll
M llvm/test/CodeGen/Hexagon/cmpbeq.ll
M llvm/test/CodeGen/Hexagon/cmph-gtu.ll
M llvm/test/CodeGen/Hexagon/cmpy-round.ll
M llvm/test/CodeGen/Hexagon/coalesce_tfri.ll
M llvm/test/CodeGen/Hexagon/coalescing-hvx-across-calls.ll
M llvm/test/CodeGen/Hexagon/combine-imm-ext.ll
M llvm/test/CodeGen/Hexagon/combine-imm-ext2.ll
M llvm/test/CodeGen/Hexagon/combine.ll
M llvm/test/CodeGen/Hexagon/combine_ir.ll
M llvm/test/CodeGen/Hexagon/combine_lh.ll
M llvm/test/CodeGen/Hexagon/combiner-lts.ll
M llvm/test/CodeGen/Hexagon/common-gep-basic.ll
M llvm/test/CodeGen/Hexagon/common-gep-icm.ll
M llvm/test/CodeGen/Hexagon/common-gep-inbounds.ll
M llvm/test/CodeGen/Hexagon/common-global-addr.ll
M llvm/test/CodeGen/Hexagon/concat-vectors-legalize.ll
M llvm/test/CodeGen/Hexagon/const-combine.ll
M llvm/test/CodeGen/Hexagon/const-pool-tf.ll
M llvm/test/CodeGen/Hexagon/constant_compound.ll
M llvm/test/CodeGen/Hexagon/constext-call.ll
M llvm/test/CodeGen/Hexagon/constext-immstore.ll
M llvm/test/CodeGen/Hexagon/constext-replace.ll
M llvm/test/CodeGen/Hexagon/constp-andir-global.mir
M llvm/test/CodeGen/Hexagon/constp-clb.ll
M llvm/test/CodeGen/Hexagon/constp-combine-neg.ll
M llvm/test/CodeGen/Hexagon/constp-ctb.ll
M llvm/test/CodeGen/Hexagon/constp-extract.ll
M llvm/test/CodeGen/Hexagon/constp-rewrite-branches.ll
M llvm/test/CodeGen/Hexagon/constp-rseq.ll
M llvm/test/CodeGen/Hexagon/constp-vsplat.ll
M llvm/test/CodeGen/Hexagon/convert_const_i1_to_i8.ll
M llvm/test/CodeGen/Hexagon/convertdptoint.ll
M llvm/test/CodeGen/Hexagon/convertdptoll.ll
M llvm/test/CodeGen/Hexagon/convertsptoint.ll
M llvm/test/CodeGen/Hexagon/convertsptoll.ll
M llvm/test/CodeGen/Hexagon/copy-to-combine-const64.mir
M llvm/test/CodeGen/Hexagon/copy-to-combine-dbg.ll
M llvm/test/CodeGen/Hexagon/count_0s.ll
M llvm/test/CodeGen/Hexagon/countbits-basic.ll
M llvm/test/CodeGen/Hexagon/csr-func-usedef.ll
M llvm/test/CodeGen/Hexagon/csr_stub_calls_dwarf_frame_info.ll
M llvm/test/CodeGen/Hexagon/ctor.ll
M llvm/test/CodeGen/Hexagon/dadd.ll
M llvm/test/CodeGen/Hexagon/dag-combine-select-or0.ll
M llvm/test/CodeGen/Hexagon/dag-indexed.ll
M llvm/test/CodeGen/Hexagon/dccleana.ll
M llvm/test/CodeGen/Hexagon/dead-store-stack.ll
M llvm/test/CodeGen/Hexagon/dealloc-store.ll
M llvm/test/CodeGen/Hexagon/dealloc_return.ll
M llvm/test/CodeGen/Hexagon/debug-line_table_start.ll
M llvm/test/CodeGen/Hexagon/debug-prologue-loc.ll
M llvm/test/CodeGen/Hexagon/debug-prologue.ll
M llvm/test/CodeGen/Hexagon/def-undef-deps.ll
M llvm/test/CodeGen/Hexagon/default-align.ll
M llvm/test/CodeGen/Hexagon/deflate.ll
M llvm/test/CodeGen/Hexagon/df-min-max.ll
M llvm/test/CodeGen/Hexagon/dfp.ll
M llvm/test/CodeGen/Hexagon/dhry.ll
M llvm/test/CodeGen/Hexagon/dhry_proc8.ll
M llvm/test/CodeGen/Hexagon/dhry_stall.ll
M llvm/test/CodeGen/Hexagon/disable-const64.ll
M llvm/test/CodeGen/Hexagon/dmul.ll
M llvm/test/CodeGen/Hexagon/dont_rotate_pregs_at_O2.ll
M llvm/test/CodeGen/Hexagon/double.ll
M llvm/test/CodeGen/Hexagon/dsub.ll
M llvm/test/CodeGen/Hexagon/duplex-addi-global-imm.mir
M llvm/test/CodeGen/Hexagon/dwarf-discriminator.ll
M llvm/test/CodeGen/Hexagon/early-if-conv-lifetime.mir
M llvm/test/CodeGen/Hexagon/early-if-conversion-bug1.ll
M llvm/test/CodeGen/Hexagon/early-if-debug.mir
M llvm/test/CodeGen/Hexagon/early-if-low8.mir
M llvm/test/CodeGen/Hexagon/early-if-merge-loop.ll
M llvm/test/CodeGen/Hexagon/early-if-phi-i1.ll
M llvm/test/CodeGen/Hexagon/early-if-predicator.mir
M llvm/test/CodeGen/Hexagon/early-if-spare.ll
M llvm/test/CodeGen/Hexagon/early-if-vecpi.ll
M llvm/test/CodeGen/Hexagon/early-if-vecpred.ll
M llvm/test/CodeGen/Hexagon/early-if.ll
M llvm/test/CodeGen/Hexagon/eh_return-r30.ll
M llvm/test/CodeGen/Hexagon/eh_return.ll
M llvm/test/CodeGen/Hexagon/eh_save_restore.ll
M llvm/test/CodeGen/Hexagon/ehabi.ll
M llvm/test/CodeGen/Hexagon/eliminate-pred-spill.ll
M llvm/test/CodeGen/Hexagon/entryBB-isLoopHdr.ll
M llvm/test/CodeGen/Hexagon/expand-condsets-basic.ll
M llvm/test/CodeGen/Hexagon/expand-condsets-copy-lis.ll
M llvm/test/CodeGen/Hexagon/expand-condsets-dead-bad.ll
M llvm/test/CodeGen/Hexagon/expand-condsets-dead-pred.ll
M llvm/test/CodeGen/Hexagon/expand-condsets-dead.ll
M llvm/test/CodeGen/Hexagon/expand-condsets-def-undef.mir
M llvm/test/CodeGen/Hexagon/expand-condsets-extend.ll
M llvm/test/CodeGen/Hexagon/expand-condsets-imm.mir
M llvm/test/CodeGen/Hexagon/expand-condsets-impuse.mir
M llvm/test/CodeGen/Hexagon/expand-condsets-impuse2.mir
M llvm/test/CodeGen/Hexagon/expand-condsets-phys-reg.mir
M llvm/test/CodeGen/Hexagon/expand-condsets-pred-undef.ll
M llvm/test/CodeGen/Hexagon/expand-condsets-pred-undef2.ll
M llvm/test/CodeGen/Hexagon/expand-condsets-rm-reg.mir
M llvm/test/CodeGen/Hexagon/expand-condsets-rm-segment.ll
M llvm/test/CodeGen/Hexagon/expand-condsets-same-inputs.mir
M llvm/test/CodeGen/Hexagon/expand-condsets-undef2.ll
M llvm/test/CodeGen/Hexagon/expand-condsets-undefvni.ll
M llvm/test/CodeGen/Hexagon/expand-condsets.ll
M llvm/test/CodeGen/Hexagon/expand-copyw-undef.mir
M llvm/test/CodeGen/Hexagon/expand-vselect-kill.mir
M llvm/test/CodeGen/Hexagon/expand-vstorerw-undef.ll
M llvm/test/CodeGen/Hexagon/expand-vstorerw-undef2.ll
M llvm/test/CodeGen/Hexagon/expand-wselect.mir
M llvm/test/CodeGen/Hexagon/extload-combine.ll
M llvm/test/CodeGen/Hexagon/extract-basic.ll
M llvm/test/CodeGen/Hexagon/extract_0bits.ll
M llvm/test/CodeGen/Hexagon/extractu_0bits.ll
M llvm/test/CodeGen/Hexagon/fadd.ll
M llvm/test/CodeGen/Hexagon/fcmp.ll
M llvm/test/CodeGen/Hexagon/feature-compound.ll
M llvm/test/CodeGen/Hexagon/feature-memops.ll
M llvm/test/CodeGen/Hexagon/find-loop-instr.ll
M llvm/test/CodeGen/Hexagon/find-loop.ll
M llvm/test/CodeGen/Hexagon/fixed-spill-mutable.ll
M llvm/test/CodeGen/Hexagon/float-amode.ll
M llvm/test/CodeGen/Hexagon/float-bitcast.ll
M llvm/test/CodeGen/Hexagon/float-const64-G0.ll
M llvm/test/CodeGen/Hexagon/float-gen-cmpop.ll
M llvm/test/CodeGen/Hexagon/float.ll
M llvm/test/CodeGen/Hexagon/floatconvert-ieee-rnd-near.ll
M llvm/test/CodeGen/Hexagon/fltnvjump.ll
M llvm/test/CodeGen/Hexagon/fmadd.ll
M llvm/test/CodeGen/Hexagon/fminmax.ll
M llvm/test/CodeGen/Hexagon/fmul-v67.ll
M llvm/test/CodeGen/Hexagon/fmul.ll
M llvm/test/CodeGen/Hexagon/formal-args-i1.ll
M llvm/test/CodeGen/Hexagon/fp16.ll
M llvm/test/CodeGen/Hexagon/fp_latency.ll
M llvm/test/CodeGen/Hexagon/fpelim-basic.ll
M llvm/test/CodeGen/Hexagon/frame-offset-overflow.ll
M llvm/test/CodeGen/Hexagon/fsel.ll
M llvm/test/CodeGen/Hexagon/fsub.ll
M llvm/test/CodeGen/Hexagon/funnel-shift.ll
M llvm/test/CodeGen/Hexagon/fusedandshift.ll
M llvm/test/CodeGen/Hexagon/generate-const-buildvector32.ll
M llvm/test/CodeGen/Hexagon/getBlockAddress.ll
M llvm/test/CodeGen/Hexagon/global-const-gep.ll
M llvm/test/CodeGen/Hexagon/global-ctor-pcrel.ll
M llvm/test/CodeGen/Hexagon/global64bitbug.ll
M llvm/test/CodeGen/Hexagon/gp-plus-offset-load.ll
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M llvm/test/CodeGen/Hexagon/hexagon-verify-implicit-use.ll
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M llvm/test/CodeGen/Hexagon/hidden-relocation.ll
M llvm/test/CodeGen/Hexagon/honor-optsize.ll
M llvm/test/CodeGen/Hexagon/hrc-stack-coloring.ll
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M llvm/test/CodeGen/Hexagon/i128-bitop.ll
M llvm/test/CodeGen/Hexagon/i16_VarArg.ll
M llvm/test/CodeGen/Hexagon/i1_VarArg.ll
M llvm/test/CodeGen/Hexagon/i8_VarArg.ll
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M llvm/test/CodeGen/Hexagon/intrinsics/atomicrmw_bitwise_native.ll
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M llvm/test/CodeGen/Hexagon/invalid-dotnew-attempt.mir
M llvm/test/CodeGen/Hexagon/invalid-memrefs.ll
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M llvm/test/CodeGen/Hexagon/isel-extload-i1.ll
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M llvm/test/CodeGen/Hexagon/isel-splat-vector-crash.ll
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M llvm/test/CodeGen/Hexagon/isel-uaddo-1-i64.ll
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M llvm/test/CodeGen/Hexagon/isel-vselect-v4i8.ll
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M llvm/test/CodeGen/Hexagon/ldst_vector_offset.ll
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M llvm/test/CodeGen/Hexagon/loadi1-v4-G0.ll
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M llvm/test/CodeGen/Hexagon/newify-crash.ll
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M llvm/test/CodeGen/Hexagon/tfr-mux-nvj.ll
M llvm/test/CodeGen/Hexagon/tfr-to-combine.ll
M llvm/test/CodeGen/Hexagon/tied_oper.ll
M llvm/test/CodeGen/Hexagon/tiny_bkfir_artdeps.ll
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M llvm/test/CodeGen/Hexagon/trivialmemaliascheck.ll
M llvm/test/CodeGen/Hexagon/trunc-mpy.ll
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M llvm/test/CodeGen/Hexagon/undo-dag-shift.ll
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M llvm/test/CodeGen/Hexagon/v60small.ll
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M llvm/test/CodeGen/Hexagon/v62-inlasm4.ll
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M llvm/test/CodeGen/Hexagon/v6vec-vshuff.ll
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M llvm/test/CodeGen/Hexagon/vect/vect-illegal-type.ll
M llvm/test/CodeGen/Hexagon/vect/vect-infloop.ll
M llvm/test/CodeGen/Hexagon/vect/vect-insert-extract-elt.ll
M llvm/test/CodeGen/Hexagon/vect/vect-load-1.ll
M llvm/test/CodeGen/Hexagon/vect/vect-load-v4i16.ll
M llvm/test/CodeGen/Hexagon/vect/vect-load.ll
M llvm/test/CodeGen/Hexagon/vect/vect-mul-v2i16.ll
M llvm/test/CodeGen/Hexagon/vect/vect-mul-v2i32.ll
M llvm/test/CodeGen/Hexagon/vect/vect-mul-v4i16.ll
M llvm/test/CodeGen/Hexagon/vect/vect-mul-v4i8.ll
M llvm/test/CodeGen/Hexagon/vect/vect-mul-v8i8.ll
M llvm/test/CodeGen/Hexagon/vect/vect-no-tfrs-1.ll
M llvm/test/CodeGen/Hexagon/vect/vect-no-tfrs.ll
M llvm/test/CodeGen/Hexagon/vect/vect-shift-imm.ll
M llvm/test/CodeGen/Hexagon/vect/vect-shifts.ll
M llvm/test/CodeGen/Hexagon/vect/vect-shuffle.ll
M llvm/test/CodeGen/Hexagon/vect/vect-splat.ll
M llvm/test/CodeGen/Hexagon/vect/vect-store-v2i16.ll
M llvm/test/CodeGen/Hexagon/vect/vect-truncate.ll
M llvm/test/CodeGen/Hexagon/vect/vect-v4i16.ll
M llvm/test/CodeGen/Hexagon/vect/vect-vaddb-1.ll
M llvm/test/CodeGen/Hexagon/vect/vect-vaddb.ll
M llvm/test/CodeGen/Hexagon/vect/vect-vaddh-1.ll
M llvm/test/CodeGen/Hexagon/vect/vect-vaddh.ll
M llvm/test/CodeGen/Hexagon/vect/vect-vaddw.ll
M llvm/test/CodeGen/Hexagon/vect/vect-vaslw.ll
M llvm/test/CodeGen/Hexagon/vect/vect-vshifts.ll
M llvm/test/CodeGen/Hexagon/vect/vect-vsplatb.ll
M llvm/test/CodeGen/Hexagon/vect/vect-vsplath.ll
M llvm/test/CodeGen/Hexagon/vect/vect-vsubb-1.ll
M llvm/test/CodeGen/Hexagon/vect/vect-vsubb.ll
M llvm/test/CodeGen/Hexagon/vect/vect-vsubh-1.ll
M llvm/test/CodeGen/Hexagon/vect/vect-vsubh.ll
M llvm/test/CodeGen/Hexagon/vect/vect-vsubw.ll
M llvm/test/CodeGen/Hexagon/vect/vect-xor.ll
M llvm/test/CodeGen/Hexagon/vect/vect-zeroextend.ll
M llvm/test/CodeGen/Hexagon/vect/vsplat-v8i8.ll
M llvm/test/CodeGen/Hexagon/vect/zext-v4i1.ll
M llvm/test/CodeGen/Hexagon/vect_setcc.ll
M llvm/test/CodeGen/Hexagon/vect_setcc_v2i16.ll
M llvm/test/CodeGen/Hexagon/vector-align.ll
M llvm/test/CodeGen/Hexagon/vector-ext-load.ll
M llvm/test/CodeGen/Hexagon/vector-sint-to-fp.ll
M llvm/test/CodeGen/Hexagon/vector-zext-v4i8.ll
M llvm/test/CodeGen/Hexagon/verify-liveness-at-def.mir
M llvm/test/CodeGen/Hexagon/verify-sink-code.ll
M llvm/test/CodeGen/Hexagon/verify-undef.ll
M llvm/test/CodeGen/Hexagon/vextract-basic.mir
M llvm/test/CodeGen/Hexagon/vgather-opt-addr.ll
M llvm/test/CodeGen/Hexagon/vgather-packetize.mir
M llvm/test/CodeGen/Hexagon/vload-postinc-sel.ll
M llvm/test/CodeGen/Hexagon/vmemu-128.ll
M llvm/test/CodeGen/Hexagon/vmpa-halide-test.ll
M llvm/test/CodeGen/Hexagon/vpack_eo.ll
M llvm/test/CodeGen/Hexagon/vselect-pseudo.ll
M llvm/test/CodeGen/Hexagon/vsplat-ext.ll
M llvm/test/CodeGen/Hexagon/vsplat-isel.ll
M llvm/test/CodeGen/Hexagon/wcsrtomb.ll
M llvm/test/CodeGen/Hexagon/widen-alias.ll
M llvm/test/CodeGen/Hexagon/widen-not-load.ll
M llvm/test/CodeGen/Hexagon/widen-volatile.ll
M llvm/test/CodeGen/Hexagon/zextloadi1.ll
M llvm/test/CodeGen/MIR/Hexagon/addrmode-opt-nonreaching.mir
M llvm/test/CodeGen/MIR/Hexagon/parse-lane-masks.mir
M llvm/test/CodeGen/MIR/Hexagon/target-flags.mir
M llvm/test/MC/Hexagon/extended_relocations.ll
Log Message:
-----------
[Hexagon,test] Change llc -march= to -mtriple=
Similar to 806761a7629df268c8aed49657aeccffa6bca449
-mtriple= specifies the full target triple while -march= merely sets the
architecture part of the default target triple, leaving a target triple which
may not make sense.
Therefore, -march= is error-prone and not recommended for tests without a target
triple. The issue has been benign as we recognize $unknown-apple-darwin as ELF instead
of rejecting it outrightly.
Commit: 5240e0b891fc4bf69d362199f70c94c28a7b9465
https://github.com/llvm/llvm-project/commit/5240e0b891fc4bf69d362199f70c94c28a7b9465
Author: Fangrui Song <i at maskray.me>
Date: 2024-12-15 (Sun, 15 Dec 2024)
Changed paths:
M llvm/test/CodeGen/VE/Packed/vec_fneg.ll
M llvm/test/CodeGen/VE/Packed/vp_add.ll
M llvm/test/CodeGen/VE/Packed/vp_and.ll
M llvm/test/CodeGen/VE/Packed/vp_fadd.ll
M llvm/test/CodeGen/VE/Packed/vp_fdiv.ll
M llvm/test/CodeGen/VE/Packed/vp_fmul.ll
M llvm/test/CodeGen/VE/Packed/vp_fsub.ll
M llvm/test/CodeGen/VE/Packed/vp_mul.ll
M llvm/test/CodeGen/VE/Packed/vp_or.ll
M llvm/test/CodeGen/VE/Packed/vp_sdiv.ll
M llvm/test/CodeGen/VE/Packed/vp_shl.ll
M llvm/test/CodeGen/VE/Packed/vp_sra.ll
M llvm/test/CodeGen/VE/Packed/vp_srl.ll
M llvm/test/CodeGen/VE/Packed/vp_sub.ll
M llvm/test/CodeGen/VE/Packed/vp_udiv.ll
M llvm/test/CodeGen/VE/Packed/vp_xor.ll
M llvm/test/CodeGen/VE/Vector/expand_single_elem_build_vec.ll
M llvm/test/CodeGen/VE/Vector/feature_vpu.ll
M llvm/test/CodeGen/VE/Vector/vec_fma.ll
M llvm/test/CodeGen/VE/Vector/vec_fneg.ll
M llvm/test/CodeGen/VE/Vector/vec_reduce_add.ll
M llvm/test/CodeGen/VE/Vector/vec_reduce_and.ll
M llvm/test/CodeGen/VE/Vector/vec_reduce_or.ll
M llvm/test/CodeGen/VE/Vector/vec_reduce_smax.ll
M llvm/test/CodeGen/VE/Vector/vec_reduce_xor.ll
M llvm/test/CodeGen/VE/Vector/vec_select.ll
M llvm/test/CodeGen/VE/Vector/vp_add.ll
M llvm/test/CodeGen/VE/Vector/vp_and.ll
M llvm/test/CodeGen/VE/Vector/vp_ashr.ll
M llvm/test/CodeGen/VE/Vector/vp_fadd.ll
M llvm/test/CodeGen/VE/Vector/vp_fadd_merge.ll
M llvm/test/CodeGen/VE/Vector/vp_fdiv.ll
M llvm/test/CodeGen/VE/Vector/vp_fdiv_merge.ll
M llvm/test/CodeGen/VE/Vector/vp_fma.ll
M llvm/test/CodeGen/VE/Vector/vp_fma_merge.ll
M llvm/test/CodeGen/VE/Vector/vp_fmul.ll
M llvm/test/CodeGen/VE/Vector/vp_fmul_merge.ll
M llvm/test/CodeGen/VE/Vector/vp_fsub.ll
M llvm/test/CodeGen/VE/Vector/vp_fsub_merge.ll
M llvm/test/CodeGen/VE/Vector/vp_lshr.ll
M llvm/test/CodeGen/VE/Vector/vp_merge.ll
M llvm/test/CodeGen/VE/Vector/vp_mul.ll
M llvm/test/CodeGen/VE/Vector/vp_or.ll
M llvm/test/CodeGen/VE/Vector/vp_reduce_add.ll
M llvm/test/CodeGen/VE/Vector/vp_reduce_and.ll
M llvm/test/CodeGen/VE/Vector/vp_reduce_or.ll
M llvm/test/CodeGen/VE/Vector/vp_reduce_smax.ll
M llvm/test/CodeGen/VE/Vector/vp_reduce_xor.ll
M llvm/test/CodeGen/VE/Vector/vp_sdiv.ll
M llvm/test/CodeGen/VE/Vector/vp_select.ll
M llvm/test/CodeGen/VE/Vector/vp_shl.ll
M llvm/test/CodeGen/VE/Vector/vp_sra.ll
M llvm/test/CodeGen/VE/Vector/vp_srem.ll
M llvm/test/CodeGen/VE/Vector/vp_srl.ll
M llvm/test/CodeGen/VE/Vector/vp_sub.ll
M llvm/test/CodeGen/VE/Vector/vp_udiv.ll
M llvm/test/CodeGen/VE/Vector/vp_urem.ll
M llvm/test/CodeGen/VE/Vector/vp_xor.ll
M llvm/test/CodeGen/VE/null-mctargetstreamer.ll
Log Message:
-----------
[VE,test] Change llc -march= to -mtriple=
Similar to 806761a7629df268c8aed49657aeccffa6bca449
-mtriple= specifies the full target triple while -march= merely sets the
architecture part of the default target triple, leaving a target triple which
may not make sense.
Therefore, -march= is error-prone and not recommended for tests without a target
triple. The issue has been benign as we recognize $ve-apple-darwin as ELF instead
of rejecting it outrightly.
Commit: 9ef1d37ffb5f56a9b949a6307bbb16c2ea0130e3
https://github.com/llvm/llvm-project/commit/9ef1d37ffb5f56a9b949a6307bbb16c2ea0130e3
Author: Fangrui Song <i at maskray.me>
Date: 2024-12-15 (Sun, 15 Dec 2024)
Changed paths:
M llvm/test/CodeGen/AVR/PR31344.ll
M llvm/test/CodeGen/AVR/PR31345.ll
M llvm/test/CodeGen/AVR/PR37143.ll
M llvm/test/CodeGen/AVR/add.ll
M llvm/test/CodeGen/AVR/alloca.ll
M llvm/test/CodeGen/AVR/and.ll
M llvm/test/CodeGen/AVR/atomics/fence.ll
M llvm/test/CodeGen/AVR/atomics/load-store-16-unexpected-register-bug.ll
M llvm/test/CodeGen/AVR/atomics/load16.ll
M llvm/test/CodeGen/AVR/atomics/load32.ll
M llvm/test/CodeGen/AVR/atomics/load64.ll
M llvm/test/CodeGen/AVR/atomics/load8.ll
M llvm/test/CodeGen/AVR/atomics/store.ll
M llvm/test/CodeGen/AVR/atomics/store16.ll
M llvm/test/CodeGen/AVR/atomics/swap.ll
M llvm/test/CodeGen/AVR/avr-rust-issue-123.ll
M llvm/test/CodeGen/AVR/block-address-is-in-progmem-space.ll
M llvm/test/CodeGen/AVR/branch-relaxation-long.ll
M llvm/test/CodeGen/AVR/branch-relaxation.ll
M llvm/test/CodeGen/AVR/brind.ll
M llvm/test/CodeGen/AVR/calling-conv/c/call.ll
M llvm/test/CodeGen/AVR/calling-conv/c/call_aggr.ll
M llvm/test/CodeGen/AVR/calling-conv/c/return.ll
M llvm/test/CodeGen/AVR/calling-conv/c/return_aggr.ll
M llvm/test/CodeGen/AVR/clear-bss.ll
M llvm/test/CodeGen/AVR/cmp.ll
M llvm/test/CodeGen/AVR/copy-data-to-ram.ll
M llvm/test/CodeGen/AVR/ctlz.ll
M llvm/test/CodeGen/AVR/ctpop.ll
M llvm/test/CodeGen/AVR/cttz.ll
M llvm/test/CodeGen/AVR/directmem.ll
M llvm/test/CodeGen/AVR/div.ll
M llvm/test/CodeGen/AVR/dynalloca.ll
M llvm/test/CodeGen/AVR/eor.ll
M llvm/test/CodeGen/AVR/expand-integer-failure.ll
M llvm/test/CodeGen/AVR/features/avr25.ll
M llvm/test/CodeGen/AVR/features/xmega_io.ll
M llvm/test/CodeGen/AVR/frame.ll
M llvm/test/CodeGen/AVR/frmidx-iterator-bug.ll
M llvm/test/CodeGen/AVR/high-pressure-on-ptrregs.ll
M llvm/test/CodeGen/AVR/icall-func-pointer-correct-addr-space.ll
M llvm/test/CodeGen/AVR/impossible-reg-to-reg-copy.ll
M llvm/test/CodeGen/AVR/inline-asm/inline-asm.ll
M llvm/test/CodeGen/AVR/inline-asm/inline-asm2.ll
M llvm/test/CodeGen/AVR/integration/blink.ll
M llvm/test/CodeGen/AVR/interrupts.ll
M llvm/test/CodeGen/AVR/intrinsics/named-reg-alloc.ll
M llvm/test/CodeGen/AVR/intrinsics/named-reg-special.ll
M llvm/test/CodeGen/AVR/intrinsics/stacksave-restore.ll
M llvm/test/CodeGen/AVR/io.ll
M llvm/test/CodeGen/AVR/issue-cannot-select-bswap.ll
M llvm/test/CodeGen/AVR/issue-regalloc-stackframe-folding-earlyclobber.ll
M llvm/test/CodeGen/AVR/large-return-size.ll
M llvm/test/CodeGen/AVR/ldd-immediate-overflow.ll
M llvm/test/CodeGen/AVR/load.ll
M llvm/test/CodeGen/AVR/lower-formal-args-struct-return.ll
M llvm/test/CodeGen/AVR/lower-formal-arguments-assertion.ll
M llvm/test/CodeGen/AVR/no-clear-bss.ll
M llvm/test/CodeGen/AVR/no-copy-data.ll
M llvm/test/CodeGen/AVR/no-print-operand-twice.ll
M llvm/test/CodeGen/AVR/or.ll
M llvm/test/CodeGen/AVR/pre-schedule.ll
M llvm/test/CodeGen/AVR/progmem-extended.ll
M llvm/test/CodeGen/AVR/progmem.ll
M llvm/test/CodeGen/AVR/pseudo/LDDWRdYQ.mir
M llvm/test/CodeGen/AVR/rem.ll
M llvm/test/CodeGen/AVR/runtime-trig.ll
M llvm/test/CodeGen/AVR/rust-avr-bug-112.ll
M llvm/test/CodeGen/AVR/rust-avr-bug-37.ll
M llvm/test/CodeGen/AVR/rust-avr-bug-95.ll
M llvm/test/CodeGen/AVR/rust-avr-bug-99.ll
M llvm/test/CodeGen/AVR/rust-bug-98167.ll
M llvm/test/CodeGen/AVR/select-must-add-unconditional-jump.ll
M llvm/test/CodeGen/AVR/sext.ll
M llvm/test/CodeGen/AVR/shift.ll
M llvm/test/CodeGen/AVR/sign-extension.ll
M llvm/test/CodeGen/AVR/smul-with-overflow.ll
M llvm/test/CodeGen/AVR/software-mul.ll
M llvm/test/CodeGen/AVR/std-immediate-overflow.ll
M llvm/test/CodeGen/AVR/std-ldd-immediate-overflow.ll
M llvm/test/CodeGen/AVR/stdwstk.ll
M llvm/test/CodeGen/AVR/store-undef.ll
M llvm/test/CodeGen/AVR/store.ll
M llvm/test/CodeGen/AVR/sub.ll
M llvm/test/CodeGen/AVR/trunc.ll
M llvm/test/CodeGen/AVR/umul-with-overflow.ll
M llvm/test/CodeGen/AVR/umul.with.overflow.i16-bug.ll
M llvm/test/CodeGen/AVR/unaligned-atomic-ops.ll
M llvm/test/CodeGen/AVR/varargs.ll
M llvm/test/CodeGen/AVR/xor.ll
M llvm/test/CodeGen/AVR/zeroreg.ll
M llvm/test/CodeGen/AVR/zext.ll
Log Message:
-----------
[AVR,test] Change llc -march= to -mtriple=
Similar to 806761a7629df268c8aed49657aeccffa6bca449
-mtriple= specifies the full target triple while -march= merely sets the
architecture part of the default target triple, leaving a target triple which
may not make sense.
Therefore, -march= is error-prone and not recommended for tests without a target
triple. The issue has been benign as we recognize avr-apple-darwin as ELF instead
of rejecting it outrightly.
Commit: 728490257ecc09ada707a0390303bd3c61027a53
https://github.com/llvm/llvm-project/commit/728490257ecc09ada707a0390303bd3c61027a53
Author: Fangrui Song <i at maskray.me>
Date: 2024-12-15 (Sun, 15 Dec 2024)
Changed paths:
M llvm/test/CodeGen/SPARC/2006-01-22-BitConvertLegalize.ll
M llvm/test/CodeGen/SPARC/2007-05-09-JumpTables.ll
M llvm/test/CodeGen/SPARC/2007-07-05-LiveIntervalAssert.ll
M llvm/test/CodeGen/SPARC/2008-10-10-InlineAsmMemoryOperand.ll
M llvm/test/CodeGen/SPARC/2008-10-10-InlineAsmRegOperand.ll
M llvm/test/CodeGen/SPARC/2009-08-28-PIC.ll
M llvm/test/CodeGen/SPARC/2009-08-28-WeakLinkage.ll
M llvm/test/CodeGen/SPARC/2011-01-11-CC.ll
M llvm/test/CodeGen/SPARC/2011-01-11-Call.ll
M llvm/test/CodeGen/SPARC/2011-01-11-FrameAddr.ll
M llvm/test/CodeGen/SPARC/2011-01-19-DelaySlot.ll
M llvm/test/CodeGen/SPARC/2011-01-21-ByValArgs.ll
M llvm/test/CodeGen/SPARC/2011-01-22-SRet.ll
M llvm/test/CodeGen/SPARC/2011-12-03-TailDuplication.ll
M llvm/test/CodeGen/SPARC/2013-05-17-CallFrame.ll
M llvm/test/CodeGen/SPARC/32abi.ll
M llvm/test/CodeGen/SPARC/64abi.ll
M llvm/test/CodeGen/SPARC/64atomics.ll
M llvm/test/CodeGen/SPARC/64bit.ll
M llvm/test/CodeGen/SPARC/64spill.ll
M llvm/test/CodeGen/SPARC/DbgValueOtherTargets.test
M llvm/test/CodeGen/SPARC/LeonCASAInstructionUT.ll
M llvm/test/CodeGen/SPARC/LeonDetectRoundChangePassUT.ll
M llvm/test/CodeGen/SPARC/LeonFixAllFDIVSQRTPassUT.ll
M llvm/test/CodeGen/SPARC/LeonInsertNOPLoadPassUT.ll
M llvm/test/CodeGen/SPARC/LeonItinerariesUT.ll
M llvm/test/CodeGen/SPARC/LeonSMACUMACInstructionUT.ll
M llvm/test/CodeGen/SPARC/alloca-align.ll
M llvm/test/CodeGen/SPARC/atomicrmw-uinc-udec-wrap.ll
M llvm/test/CodeGen/SPARC/atomics.ll
M llvm/test/CodeGen/SPARC/basictest.ll
M llvm/test/CodeGen/SPARC/cast-sret-func.ll
M llvm/test/CodeGen/SPARC/ctpop.ll
M llvm/test/CodeGen/SPARC/cttz.ll
M llvm/test/CodeGen/SPARC/data-align.ll
M llvm/test/CodeGen/SPARC/disable-fsmuld-fmuls.ll
M llvm/test/CodeGen/SPARC/float-constants.ll
M llvm/test/CodeGen/SPARC/float.ll
M llvm/test/CodeGen/SPARC/fp128.ll
M llvm/test/CodeGen/SPARC/inlineasm-bad.ll
M llvm/test/CodeGen/SPARC/inlineasm-v9.ll
M llvm/test/CodeGen/SPARC/inlineasm.ll
M llvm/test/CodeGen/SPARC/leafproc.ll
M llvm/test/CodeGen/SPARC/mult-alt-generic-sparc.ll
M llvm/test/CodeGen/SPARC/multiple-div.ll
M llvm/test/CodeGen/SPARC/parts.ll
M llvm/test/CodeGen/SPARC/private.ll
M llvm/test/CodeGen/SPARC/readcycle.ll
M llvm/test/CodeGen/SPARC/reg64.ll
M llvm/test/CodeGen/SPARC/register-clobber.ll
M llvm/test/CodeGen/SPARC/reserved-regs.ll
M llvm/test/CodeGen/SPARC/salvage-debug-isel.ll
M llvm/test/CodeGen/SPARC/select-mask.ll
M llvm/test/CodeGen/SPARC/setjmp.ll
M llvm/test/CodeGen/SPARC/soft-float.ll
M llvm/test/CodeGen/SPARC/soft-mul-div.ll
M llvm/test/CodeGen/SPARC/spill.ll
M llvm/test/CodeGen/SPARC/sret-secondary.ll
M llvm/test/CodeGen/SPARC/stack-align.ll
M llvm/test/CodeGen/SPARC/tn0009.mir
M llvm/test/CodeGen/SPARC/tn0010.mir
M llvm/test/CodeGen/SPARC/tn0012.mir
M llvm/test/CodeGen/SPARC/tn0013.mir
M llvm/test/CodeGen/SPARC/vector-call.ll
M llvm/test/CodeGen/SPARC/vector-extract-elt.ll
M llvm/test/CodeGen/SPARC/zerostructcall.ll
Log Message:
-----------
[Sparc,test] Change llc -march= to -mtriple=
Similar to 806761a7629df268c8aed49657aeccffa6bca449
-mtriple= specifies the full target triple while -march= merely sets the
architecture part of the default target triple (e.g. Windows, macOS),
leaving a target triple which may not make sense.
Therefore, -march= is error-prone and not recommended for tests without a target
triple. The issue has been benign as we recognize sparc*-apple-darwin as ELF instead
of rejecting it outrightly.
Commit: f1987c74ee5637ec248675a9a7070654167a5260
https://github.com/llvm/llvm-project/commit/f1987c74ee5637ec248675a9a7070654167a5260
Author: Fangrui Song <i at maskray.me>
Date: 2024-12-15 (Sun, 15 Dec 2024)
Changed paths:
M llvm/test/CodeGen/XCore/2008-11-17-Shl64.ll
M llvm/test/CodeGen/XCore/2009-01-08-Crash.ll
M llvm/test/CodeGen/XCore/2009-01-14-Remat-Crash.ll
M llvm/test/CodeGen/XCore/2009-03-27-v2f64-param.ll
M llvm/test/CodeGen/XCore/2009-07-15-store192.ll
M llvm/test/CodeGen/XCore/2010-02-25-LSR-Crash.ll
M llvm/test/CodeGen/XCore/2011-01-31-DAGCombineBug.ll
M llvm/test/CodeGen/XCore/2011-08-01-DynamicAllocBug.ll
M llvm/test/CodeGen/XCore/DbgValueOtherTargets.test
M llvm/test/CodeGen/XCore/addsub64.ll
M llvm/test/CodeGen/XCore/aliases.ll
M llvm/test/CodeGen/XCore/align.ll
M llvm/test/CodeGen/XCore/alignment.ll
M llvm/test/CodeGen/XCore/ashr.ll
M llvm/test/CodeGen/XCore/atomic.ll
M llvm/test/CodeGen/XCore/basictest.ll
M llvm/test/CodeGen/XCore/bigstructret.ll
M llvm/test/CodeGen/XCore/bitrev.ll
M llvm/test/CodeGen/XCore/byVal.ll
M llvm/test/CodeGen/XCore/call.ll
M llvm/test/CodeGen/XCore/constants.ll
M llvm/test/CodeGen/XCore/events.ll
M llvm/test/CodeGen/XCore/exception.ll
M llvm/test/CodeGen/XCore/fneg.ll
M llvm/test/CodeGen/XCore/getid.ll
M llvm/test/CodeGen/XCore/globals.ll
M llvm/test/CodeGen/XCore/indirectbr.ll
M llvm/test/CodeGen/XCore/inline-asm.ll
M llvm/test/CodeGen/XCore/inlineasm-output-template.ll
M llvm/test/CodeGen/XCore/ladd_lsub_combine.ll
M llvm/test/CodeGen/XCore/licm-ldwcp.ll
M llvm/test/CodeGen/XCore/linkage.ll
M llvm/test/CodeGen/XCore/llvm-intrinsics.ll
M llvm/test/CodeGen/XCore/load.ll
M llvm/test/CodeGen/XCore/memcpy.ll
M llvm/test/CodeGen/XCore/misc-intrinsics.ll
M llvm/test/CodeGen/XCore/mkmsk.ll
M llvm/test/CodeGen/XCore/mul64.ll
M llvm/test/CodeGen/XCore/offset_folding.ll
M llvm/test/CodeGen/XCore/private.ll
M llvm/test/CodeGen/XCore/ps-intrinsics.ll
M llvm/test/CodeGen/XCore/resources.ll
M llvm/test/CodeGen/XCore/resources_combine.ll
M llvm/test/CodeGen/XCore/section-name.ll
M llvm/test/CodeGen/XCore/sext.ll
M llvm/test/CodeGen/XCore/shedulingPreference.ll
M llvm/test/CodeGen/XCore/sr-intrinsics.ll
M llvm/test/CodeGen/XCore/store.ll
M llvm/test/CodeGen/XCore/switch.ll
M llvm/test/CodeGen/XCore/switch_long.ll
M llvm/test/CodeGen/XCore/tls.ll
M llvm/test/CodeGen/XCore/trampoline.ll
M llvm/test/CodeGen/XCore/trap.ll
M llvm/test/CodeGen/XCore/unaligned_load.ll
M llvm/test/CodeGen/XCore/unaligned_store.ll
M llvm/test/CodeGen/XCore/unaligned_store_combine.ll
M llvm/test/CodeGen/XCore/varargs.ll
M llvm/test/CodeGen/XCore/zext.ll
M llvm/test/CodeGen/XCore/zextfree.ll
Log Message:
-----------
[XCore,test] Change llc -march= to -mtriple=
Similar to 806761a7629df268c8aed49657aeccffa6bca449
-mtriple= specifies the full target triple while -march= merely sets the
architecture part of the default target triple (e.g. Windows, macOS),
leaving a target triple which may not make sense.
Therefore, -march= is error-prone and not recommended for tests without a target
triple. The issue has been benign as we recognize xcore-apple-darwin as ELF instead
of rejecting it outrightly.
Commit: b279f6b098d3849f7f1c1f539b108307d5f8ae2d
https://github.com/llvm/llvm-project/commit/b279f6b098d3849f7f1c1f539b108307d5f8ae2d
Author: Fangrui Song <i at maskray.me>
Date: 2024-12-15 (Sun, 15 Dec 2024)
Changed paths:
M llvm/test/CodeGen/MIR/NVPTX/expected-floating-point-literal.mir
M llvm/test/CodeGen/MIR/NVPTX/floating-point-immediate-operands.mir
M llvm/test/CodeGen/MIR/NVPTX/floating-point-invalid-type-error.mir
M llvm/test/CodeGen/NVPTX/APIntLoadStore.ll
M llvm/test/CodeGen/NVPTX/APIntParam.ll
M llvm/test/CodeGen/NVPTX/APIntSextParam.ll
M llvm/test/CodeGen/NVPTX/APIntZextParam.ll
M llvm/test/CodeGen/NVPTX/access-non-generic.ll
M llvm/test/CodeGen/NVPTX/activemask.ll
M llvm/test/CodeGen/NVPTX/add-sub-128bit.ll
M llvm/test/CodeGen/NVPTX/addr-mode.ll
M llvm/test/CodeGen/NVPTX/addrspacecast-gvar.ll
M llvm/test/CodeGen/NVPTX/addrspacecast.ll
M llvm/test/CodeGen/NVPTX/aggr-param.ll
M llvm/test/CodeGen/NVPTX/aggregate-return.ll
M llvm/test/CodeGen/NVPTX/alias-errors.ll
M llvm/test/CodeGen/NVPTX/alias.ll
M llvm/test/CodeGen/NVPTX/annotations.ll
M llvm/test/CodeGen/NVPTX/anonymous-fn-param.ll
M llvm/test/CodeGen/NVPTX/arg-lowering.ll
M llvm/test/CodeGen/NVPTX/arithmetic-fp-sm20.ll
M llvm/test/CodeGen/NVPTX/arithmetic-int.ll
M llvm/test/CodeGen/NVPTX/async-copy.ll
M llvm/test/CodeGen/NVPTX/atomicrmw-expand.ll
M llvm/test/CodeGen/NVPTX/atomics-sm60.ll
M llvm/test/CodeGen/NVPTX/atomics-sm70.ll
M llvm/test/CodeGen/NVPTX/atomics-sm90.ll
M llvm/test/CodeGen/NVPTX/atomics-with-scope.ll
M llvm/test/CodeGen/NVPTX/atomics.ll
M llvm/test/CodeGen/NVPTX/barrier.ll
M llvm/test/CodeGen/NVPTX/bf16-instructions.ll
M llvm/test/CodeGen/NVPTX/bf16.ll
M llvm/test/CodeGen/NVPTX/bf16x2-instructions-approx.ll
M llvm/test/CodeGen/NVPTX/bf16x2-instructions.ll
M llvm/test/CodeGen/NVPTX/bfe.ll
M llvm/test/CodeGen/NVPTX/boolean-patterns.ll
M llvm/test/CodeGen/NVPTX/branch-fold.ll
M llvm/test/CodeGen/NVPTX/branch-fold.mir
M llvm/test/CodeGen/NVPTX/brkpt.ll
M llvm/test/CodeGen/NVPTX/bswap.ll
M llvm/test/CodeGen/NVPTX/bug17709.ll
M llvm/test/CodeGen/NVPTX/bug21465.ll
M llvm/test/CodeGen/NVPTX/bug22246.ll
M llvm/test/CodeGen/NVPTX/bug22322.ll
M llvm/test/CodeGen/NVPTX/bug26185-2.ll
M llvm/test/CodeGen/NVPTX/bug26185.ll
M llvm/test/CodeGen/NVPTX/bug52623.ll
M llvm/test/CodeGen/NVPTX/bypass-div.ll
M llvm/test/CodeGen/NVPTX/call-with-alloca-buffer.ll
M llvm/test/CodeGen/NVPTX/call_bitcast_byval.ll
M llvm/test/CodeGen/NVPTX/callchain.ll
M llvm/test/CodeGen/NVPTX/calling-conv.ll
M llvm/test/CodeGen/NVPTX/calls-with-phi.ll
M llvm/test/CodeGen/NVPTX/cluster-dim.ll
M llvm/test/CodeGen/NVPTX/cmpxchg.ll
M llvm/test/CodeGen/NVPTX/combine-min-max.ll
M llvm/test/CodeGen/NVPTX/common-linkage.ll
M llvm/test/CodeGen/NVPTX/compare-int.ll
M llvm/test/CodeGen/NVPTX/compute-ptx-value-vts.ll
M llvm/test/CodeGen/NVPTX/constant-vectors.ll
M llvm/test/CodeGen/NVPTX/convert-fp.ll
M llvm/test/CodeGen/NVPTX/convert-int-sm20.ll
M llvm/test/CodeGen/NVPTX/convert-sm80.ll
M llvm/test/CodeGen/NVPTX/convert-sm89.ll
M llvm/test/CodeGen/NVPTX/copysign.ll
M llvm/test/CodeGen/NVPTX/cp-async-bulk-tensor-g2s.ll
M llvm/test/CodeGen/NVPTX/cp-async-bulk-tensor-prefetch.ll
M llvm/test/CodeGen/NVPTX/cp-async-bulk-tensor-reduce.ll
M llvm/test/CodeGen/NVPTX/cp-async-bulk-tensor-s2g.ll
M llvm/test/CodeGen/NVPTX/ctlz.ll
M llvm/test/CodeGen/NVPTX/ctpop.ll
M llvm/test/CodeGen/NVPTX/cttz.ll
M llvm/test/CodeGen/NVPTX/dag-cse.ll
M llvm/test/CodeGen/NVPTX/demote-vars.ll
M llvm/test/CodeGen/NVPTX/disable-opt.ll
M llvm/test/CodeGen/NVPTX/div-ri.ll
M llvm/test/CodeGen/NVPTX/div.ll
M llvm/test/CodeGen/NVPTX/divrem-combine.ll
M llvm/test/CodeGen/NVPTX/dot-product.ll
M llvm/test/CodeGen/NVPTX/dynamic-stackalloc-regression.ll
M llvm/test/CodeGen/NVPTX/dynamic_stackalloc.ll
M llvm/test/CodeGen/NVPTX/elect.ll
M llvm/test/CodeGen/NVPTX/empty-type.ll
M llvm/test/CodeGen/NVPTX/envreg.ll
M llvm/test/CodeGen/NVPTX/extloadv.ll
M llvm/test/CodeGen/NVPTX/extractelement.ll
M llvm/test/CodeGen/NVPTX/f16-ex2.ll
M llvm/test/CodeGen/NVPTX/fast-math.ll
M llvm/test/CodeGen/NVPTX/fcos-no-fast-math.ll
M llvm/test/CodeGen/NVPTX/fence-proxy-tensormap.ll
M llvm/test/CodeGen/NVPTX/fence-sm-90.ll
M llvm/test/CodeGen/NVPTX/fence.ll
M llvm/test/CodeGen/NVPTX/filetype-null.ll
M llvm/test/CodeGen/NVPTX/fma-assoc.ll
M llvm/test/CodeGen/NVPTX/fma-disable.ll
M llvm/test/CodeGen/NVPTX/fma-relu-contract.ll
M llvm/test/CodeGen/NVPTX/fma-relu-fma-intrinsic.ll
M llvm/test/CodeGen/NVPTX/fma-relu-instruction-flag.ll
M llvm/test/CodeGen/NVPTX/fma.ll
M llvm/test/CodeGen/NVPTX/fminimum-fmaximum.ll
M llvm/test/CodeGen/NVPTX/fns.ll
M llvm/test/CodeGen/NVPTX/fp-contract.ll
M llvm/test/CodeGen/NVPTX/fp-literals.ll
M llvm/test/CodeGen/NVPTX/fp16.ll
M llvm/test/CodeGen/NVPTX/fsin-no-fast-math.ll
M llvm/test/CodeGen/NVPTX/function-align.ll
M llvm/test/CodeGen/NVPTX/funnel-shift-clamp.ll
M llvm/test/CodeGen/NVPTX/generic-to-nvvm.ll
M llvm/test/CodeGen/NVPTX/global-addrspace.ll
M llvm/test/CodeGen/NVPTX/global-ctor-empty.ll
M llvm/test/CodeGen/NVPTX/global-ctor.ll
M llvm/test/CodeGen/NVPTX/global-dtor.ll
M llvm/test/CodeGen/NVPTX/global-incomplete-init.ll
M llvm/test/CodeGen/NVPTX/global-ordering.ll
M llvm/test/CodeGen/NVPTX/global-visibility.ll
M llvm/test/CodeGen/NVPTX/globals_init.ll
M llvm/test/CodeGen/NVPTX/gvar-init.ll
M llvm/test/CodeGen/NVPTX/half.ll
M llvm/test/CodeGen/NVPTX/i1-array-global.ll
M llvm/test/CodeGen/NVPTX/i1-ext-load.ll
M llvm/test/CodeGen/NVPTX/i1-global.ll
M llvm/test/CodeGen/NVPTX/i1-icmp.ll
M llvm/test/CodeGen/NVPTX/i1-int-to-fp.ll
M llvm/test/CodeGen/NVPTX/i1-load-lower.ll
M llvm/test/CodeGen/NVPTX/i1-param.ll
M llvm/test/CodeGen/NVPTX/i128-global.ll
M llvm/test/CodeGen/NVPTX/i128-param.ll
M llvm/test/CodeGen/NVPTX/i128-retval.ll
M llvm/test/CodeGen/NVPTX/i128-struct.ll
M llvm/test/CodeGen/NVPTX/i8-param.ll
M llvm/test/CodeGen/NVPTX/idioms.ll
M llvm/test/CodeGen/NVPTX/imad.ll
M llvm/test/CodeGen/NVPTX/indirect_byval.ll
M llvm/test/CodeGen/NVPTX/inline-asm-b128-test1.ll
M llvm/test/CodeGen/NVPTX/inline-asm-b128-test2.ll
M llvm/test/CodeGen/NVPTX/inline-asm-b128-test3.ll
M llvm/test/CodeGen/NVPTX/inline-asm.ll
M llvm/test/CodeGen/NVPTX/inlineasm-output-template.ll
M llvm/test/CodeGen/NVPTX/intrinsic-old.ll
M llvm/test/CodeGen/NVPTX/intrinsics-sm90.ll
M llvm/test/CodeGen/NVPTX/intrinsics.ll
M llvm/test/CodeGen/NVPTX/isspacep.ll
M llvm/test/CodeGen/NVPTX/kernel-param-align.ll
M llvm/test/CodeGen/NVPTX/ld-addrspace.ll
M llvm/test/CodeGen/NVPTX/ld-generic.ll
M llvm/test/CodeGen/NVPTX/ld-st-addrrspace.py
M llvm/test/CodeGen/NVPTX/ldg-invariant.ll
M llvm/test/CodeGen/NVPTX/ldparam-v4.ll
M llvm/test/CodeGen/NVPTX/ldu-i8.ll
M llvm/test/CodeGen/NVPTX/ldu-ldg.ll
M llvm/test/CodeGen/NVPTX/ldu-reg-plus-offset.ll
M llvm/test/CodeGen/NVPTX/load-sext-i1.ll
M llvm/test/CodeGen/NVPTX/load-store-sm-70.ll
M llvm/test/CodeGen/NVPTX/load-store-sm-90.ll
M llvm/test/CodeGen/NVPTX/load-store.ll
M llvm/test/CodeGen/NVPTX/load-with-non-coherent-cache.ll
M llvm/test/CodeGen/NVPTX/local-stack-frame.ll
M llvm/test/CodeGen/NVPTX/lower-aggr-copies.ll
M llvm/test/CodeGen/NVPTX/lower-alloca.ll
M llvm/test/CodeGen/NVPTX/lower-kernel-ptr-arg.ll
M llvm/test/CodeGen/NVPTX/machine-sink.ll
M llvm/test/CodeGen/NVPTX/managed.ll
M llvm/test/CodeGen/NVPTX/match.ll
M llvm/test/CodeGen/NVPTX/math-intrins-sm53-ptx42.ll
M llvm/test/CodeGen/NVPTX/math-intrins-sm80-ptx70-autoupgrade.ll
M llvm/test/CodeGen/NVPTX/math-intrins-sm80-ptx70.ll
M llvm/test/CodeGen/NVPTX/math-intrins-sm86-ptx72-autoupgrade.ll
M llvm/test/CodeGen/NVPTX/math-intrins-sm86-ptx72.ll
M llvm/test/CodeGen/NVPTX/max-align.ll
M llvm/test/CodeGen/NVPTX/maxclusterrank.ll
M llvm/test/CodeGen/NVPTX/mbarrier.ll
M llvm/test/CodeGen/NVPTX/minmax-negative.ll
M llvm/test/CodeGen/NVPTX/misaligned-vector-ldst.ll
M llvm/test/CodeGen/NVPTX/misched_func_call.ll
M llvm/test/CodeGen/NVPTX/mma-no-sink-after-laneid-check.ll
M llvm/test/CodeGen/NVPTX/module-inline-asm.ll
M llvm/test/CodeGen/NVPTX/mulwide.ll
M llvm/test/CodeGen/NVPTX/named-barriers.ll
M llvm/test/CodeGen/NVPTX/nanosleep.ll
M llvm/test/CodeGen/NVPTX/no-extra-parens.ll
M llvm/test/CodeGen/NVPTX/nofunc.ll
M llvm/test/CodeGen/NVPTX/noreturn.ll
M llvm/test/CodeGen/NVPTX/nounroll.ll
M llvm/test/CodeGen/NVPTX/nvcl-param-align.ll
M llvm/test/CodeGen/NVPTX/nvvm-reflect-arch-O0.ll
M llvm/test/CodeGen/NVPTX/packed-aggr.ll
M llvm/test/CodeGen/NVPTX/param-align.ll
M llvm/test/CodeGen/NVPTX/param-load-store.ll
M llvm/test/CodeGen/NVPTX/param-overalign.ll
M llvm/test/CodeGen/NVPTX/pass-name.ll
M llvm/test/CodeGen/NVPTX/pow2_mask_cmp.ll
M llvm/test/CodeGen/NVPTX/pr13291-i1-store.ll
M llvm/test/CodeGen/NVPTX/pr16278.ll
M llvm/test/CodeGen/NVPTX/pr17529.ll
M llvm/test/CodeGen/NVPTX/proxy-reg-erasure-ptx.ll
M llvm/test/CodeGen/NVPTX/proxy-reg-erasure.mir
M llvm/test/CodeGen/NVPTX/rcp-opt.ll
M llvm/test/CodeGen/NVPTX/read-global-variable-constant.ll
M llvm/test/CodeGen/NVPTX/redux-sync.ll
M llvm/test/CodeGen/NVPTX/refl1.ll
M llvm/test/CodeGen/NVPTX/reg-copy.ll
M llvm/test/CodeGen/NVPTX/reg-types.ll
M llvm/test/CodeGen/NVPTX/rotate_64.ll
M llvm/test/CodeGen/NVPTX/rsqrt-opt.ll
M llvm/test/CodeGen/NVPTX/rsqrt.ll
M llvm/test/CodeGen/NVPTX/sched1.ll
M llvm/test/CodeGen/NVPTX/sched2.ll
M llvm/test/CodeGen/NVPTX/setmaxnreg.ll
M llvm/test/CodeGen/NVPTX/sext-in-reg.ll
M llvm/test/CodeGen/NVPTX/sext-params.ll
M llvm/test/CodeGen/NVPTX/sext-setcc.ll
M llvm/test/CodeGen/NVPTX/shfl-p.ll
M llvm/test/CodeGen/NVPTX/shfl-sync-p.ll
M llvm/test/CodeGen/NVPTX/shfl-sync.ll
M llvm/test/CodeGen/NVPTX/shfl.ll
M llvm/test/CodeGen/NVPTX/shift-parts.ll
M llvm/test/CodeGen/NVPTX/short-ptr.ll
M llvm/test/CodeGen/NVPTX/shuffle-vec-undef-init.ll
M llvm/test/CodeGen/NVPTX/simple-call.ll
M llvm/test/CodeGen/NVPTX/sm-version.ll
M llvm/test/CodeGen/NVPTX/sqrt-approx.ll
M llvm/test/CodeGen/NVPTX/st-addrspace.ll
M llvm/test/CodeGen/NVPTX/st-generic.ll
M llvm/test/CodeGen/NVPTX/st-param-imm.ll
M llvm/test/CodeGen/NVPTX/stacksaverestore.ll
M llvm/test/CodeGen/NVPTX/store-undef.ll
M llvm/test/CodeGen/NVPTX/surf-read-cuda.ll
M llvm/test/CodeGen/NVPTX/surf-write-cuda.ll
M llvm/test/CodeGen/NVPTX/symbol-naming.ll
M llvm/test/CodeGen/NVPTX/tex-read-cuda.ll
M llvm/test/CodeGen/NVPTX/texsurf-queries.ll
M llvm/test/CodeGen/NVPTX/tid-range.ll
M llvm/test/CodeGen/NVPTX/unaligned-param-load-store.ll
M llvm/test/CodeGen/NVPTX/unreachable.ll
M llvm/test/CodeGen/NVPTX/variadics-backend.ll
M llvm/test/CodeGen/NVPTX/vec-param-load.ll
M llvm/test/CodeGen/NVPTX/vec8.ll
M llvm/test/CodeGen/NVPTX/vector-args.ll
M llvm/test/CodeGen/NVPTX/vector-call.ll
M llvm/test/CodeGen/NVPTX/vector-compare.ll
M llvm/test/CodeGen/NVPTX/vector-global.ll
M llvm/test/CodeGen/NVPTX/vector-loads.ll
M llvm/test/CodeGen/NVPTX/vector-returns.ll
M llvm/test/CodeGen/NVPTX/vector-select.ll
M llvm/test/CodeGen/NVPTX/vector-stores.ll
M llvm/test/CodeGen/NVPTX/vote.ll
M llvm/test/CodeGen/NVPTX/weak-global.ll
M llvm/test/CodeGen/NVPTX/weak-linkage.ll
M llvm/test/CodeGen/NVPTX/wmma-ptx60-sm70.py
M llvm/test/CodeGen/NVPTX/wmma-ptx61-sm70.py
M llvm/test/CodeGen/NVPTX/wmma-ptx63-sm72.py
M llvm/test/CodeGen/NVPTX/wmma-ptx63-sm75.py
M llvm/test/CodeGen/NVPTX/wmma-ptx64-sm70.py
M llvm/test/CodeGen/NVPTX/wmma-ptx65-sm75.py
M llvm/test/CodeGen/NVPTX/wmma-ptx71-sm80.py
M llvm/test/CodeGen/NVPTX/zeroext-32bit.ll
Log Message:
-----------
[NVPTX,test] Change llc -march= to -mtriple=
Similar to 806761a7629df268c8aed49657aeccffa6bca449
-mtriple= specifies the full target triple while -march= merely sets the
architecture part of the default target triple (e.g. Windows, macOS),
leaving a target triple which may not make sense.
Therefore, -march= is error-prone and not recommended for tests without
a target triple. The issue has been benign as we recognize
nvptx{,64}-apple-darwin as ELF instead of rejecting it outrightly.
Commit: e64650d702f23674f5a7995a0bb6bd56a604b291
https://github.com/llvm/llvm-project/commit/e64650d702f23674f5a7995a0bb6bd56a604b291
Author: Florian Hahn <flo at fhahn.com>
Date: 2024-12-15 (Sun, 15 Dec 2024)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
M llvm/test/Transforms/LoopVectorize/AArch64/sve-widen-gep.ll
Log Message:
-----------
[VPlan] Get types and step from VPWidenPointerInductionRecipe (NFC).
Use information directly from operands instead of going through
IVDescriptor.
Commit: 9afaf9c6c89efb22bccab39677e8dff47da91a00
https://github.com/llvm/llvm-project/commit/9afaf9c6c89efb22bccab39677e8dff47da91a00
Author: Fangrui Song <i at maskray.me>
Date: 2024-12-15 (Sun, 15 Dec 2024)
Changed paths:
M llvm/test/CodeGen/AMDGPU/GlobalISel/mmra.ll
M llvm/test/CodeGen/AMDGPU/bf16-conversions.ll
M llvm/test/CodeGen/AMDGPU/bitreverse-inline-immediates.ll
M llvm/test/CodeGen/AMDGPU/invalid-inline-asm-constraint-crash.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.bitop3.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.read.tr.gfx950.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.gfx950.bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.gfx950.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.prng.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.atomic.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.atomic.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.buffer.prefetch.data.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.prefetch.data.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.smfmac.gfx950.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.atomic.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.atomic.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.update.dpp.gfx90a.ll
M llvm/test/CodeGen/AMDGPU/llvm.set.rounding.ll
M llvm/test/CodeGen/AMDGPU/load-store-opt-addc0.mir
M llvm/test/CodeGen/AMDGPU/mai-hazards-mfma-scale.gfx950.mir
M llvm/test/CodeGen/AMDGPU/mmra.ll
M llvm/test/CodeGen/AMDGPU/v_swap_b16.ll
M llvm/test/MachineVerifier/AMDGPU/fix-illegal-vector-copies.mir
Log Message:
-----------
[AMDGPU,test] Change llc -march= to -mtriple=
Follow-up to 806761a7629df268c8aed49657aeccffa6bca449
Commit: c5037db4acd95790a0ca5061c8fa79c5c291607e
https://github.com/llvm/llvm-project/commit/c5037db4acd95790a0ca5061c8fa79c5c291607e
Author: Fangrui Song <i at maskray.me>
Date: 2024-12-15 (Sun, 15 Dec 2024)
Changed paths:
M llvm/test/CodeGen/BPF/32-bit-subreg-alu.ll
M llvm/test/CodeGen/BPF/32-bit-subreg-cond-select.ll
M llvm/test/CodeGen/BPF/32-bit-subreg-load-store.ll
M llvm/test/CodeGen/BPF/32-bit-subreg-peephole-phi-1.ll
M llvm/test/CodeGen/BPF/32-bit-subreg-peephole-phi-2.ll
M llvm/test/CodeGen/BPF/32-bit-subreg-peephole-phi-3.ll
M llvm/test/CodeGen/BPF/32-bit-subreg-peephole.ll
M llvm/test/CodeGen/BPF/32-bit-subreg-zext.ll
M llvm/test/CodeGen/BPF/BTF/array-1d-char.ll
M llvm/test/CodeGen/BPF/BTF/array-1d-int.ll
M llvm/test/CodeGen/BPF/BTF/array-2d-int.ll
M llvm/test/CodeGen/BPF/BTF/array-size-0.ll
M llvm/test/CodeGen/BPF/BTF/array-typedef.ll
M llvm/test/CodeGen/BPF/BTF/atomics.ll
M llvm/test/CodeGen/BPF/BTF/char-no-debuginfo.ll
M llvm/test/CodeGen/BPF/BTF/char.ll
M llvm/test/CodeGen/BPF/BTF/double.ll
M llvm/test/CodeGen/BPF/BTF/empty-btf.ll
M llvm/test/CodeGen/BPF/BTF/enum-basic.ll
M llvm/test/CodeGen/BPF/BTF/extern-builtin.ll
M llvm/test/CodeGen/BPF/BTF/extern-func-arg.ll
M llvm/test/CodeGen/BPF/BTF/extern-func-ptr.ll
M llvm/test/CodeGen/BPF/BTF/extern-global-var.ll
M llvm/test/CodeGen/BPF/BTF/extern-var-func-weak-section.ll
M llvm/test/CodeGen/BPF/BTF/extern-var-func-weak.ll
M llvm/test/CodeGen/BPF/BTF/extern-var-func.ll
M llvm/test/CodeGen/BPF/BTF/extern-var-func2.ll
M llvm/test/CodeGen/BPF/BTF/extern-var-section.ll
M llvm/test/CodeGen/BPF/BTF/extern-var-struct-weak.ll
M llvm/test/CodeGen/BPF/BTF/extern-var-struct.ll
M llvm/test/CodeGen/BPF/BTF/extern-var-weak-section.ll
M llvm/test/CodeGen/BPF/BTF/filename.ll
M llvm/test/CodeGen/BPF/BTF/float.ll
M llvm/test/CodeGen/BPF/BTF/func-func-ptr.ll
M llvm/test/CodeGen/BPF/BTF/func-non-void.ll
M llvm/test/CodeGen/BPF/BTF/func-source.ll
M llvm/test/CodeGen/BPF/BTF/func-typedef.ll
M llvm/test/CodeGen/BPF/BTF/func-unused-arg.ll
M llvm/test/CodeGen/BPF/BTF/func-void.ll
M llvm/test/CodeGen/BPF/BTF/fwd-no-define.ll
M llvm/test/CodeGen/BPF/BTF/fwd-with-define.ll
M llvm/test/CodeGen/BPF/BTF/global-var-bss-and-data.ll
M llvm/test/CodeGen/BPF/BTF/global-var-inited.ll
M llvm/test/CodeGen/BPF/BTF/global-var-sec-readonly.ll
M llvm/test/CodeGen/BPF/BTF/global-var-sec.ll
M llvm/test/CodeGen/BPF/BTF/incomplete-debuginfo.ll
M llvm/test/CodeGen/BPF/BTF/int.ll
M llvm/test/CodeGen/BPF/BTF/local-var-readonly-1.ll
M llvm/test/CodeGen/BPF/BTF/local-var-readonly-2.ll
M llvm/test/CodeGen/BPF/BTF/local-var.ll
M llvm/test/CodeGen/BPF/BTF/longlong.ll
M llvm/test/CodeGen/BPF/BTF/map-def-2.ll
M llvm/test/CodeGen/BPF/BTF/map-def-3.ll
M llvm/test/CodeGen/BPF/BTF/map-def.ll
M llvm/test/CodeGen/BPF/BTF/pruning-const.ll
M llvm/test/CodeGen/BPF/BTF/pruning-dup-ptr-struct.ll
M llvm/test/CodeGen/BPF/BTF/pruning-multi-derived-type.ll
M llvm/test/CodeGen/BPF/BTF/pruning-typedef.ll
M llvm/test/CodeGen/BPF/BTF/ptr-const-void.ll
M llvm/test/CodeGen/BPF/BTF/ptr-func-1.ll
M llvm/test/CodeGen/BPF/BTF/ptr-func-2.ll
M llvm/test/CodeGen/BPF/BTF/ptr-func-3.ll
M llvm/test/CodeGen/BPF/BTF/ptr-int.ll
M llvm/test/CodeGen/BPF/BTF/ptr-prune-type.ll
M llvm/test/CodeGen/BPF/BTF/ptr-void.ll
M llvm/test/CodeGen/BPF/BTF/ptr-volatile-const-void.ll
M llvm/test/CodeGen/BPF/BTF/ptr-volatile-void.ll
M llvm/test/CodeGen/BPF/BTF/restrict-ptr.ll
M llvm/test/CodeGen/BPF/BTF/short.ll
M llvm/test/CodeGen/BPF/BTF/static-func.ll
M llvm/test/CodeGen/BPF/BTF/static-var-derived-type.ll
M llvm/test/CodeGen/BPF/BTF/static-var-inited-sec.ll
M llvm/test/CodeGen/BPF/BTF/static-var-inited.ll
M llvm/test/CodeGen/BPF/BTF/static-var-readonly-sec.ll
M llvm/test/CodeGen/BPF/BTF/static-var-readonly.ll
M llvm/test/CodeGen/BPF/BTF/static-var-sec.ll
M llvm/test/CodeGen/BPF/BTF/static-var-zerolen-array.ll
M llvm/test/CodeGen/BPF/BTF/static-var.ll
M llvm/test/CodeGen/BPF/BTF/struct-anon-2.ll
M llvm/test/CodeGen/BPF/BTF/struct-anon.ll
M llvm/test/CodeGen/BPF/BTF/struct-basic.ll
M llvm/test/CodeGen/BPF/BTF/struct-bitfield-typedef.ll
M llvm/test/CodeGen/BPF/BTF/struct-enum.ll
M llvm/test/CodeGen/BPF/BTF/tag-1.ll
M llvm/test/CodeGen/BPF/BTF/tag-2.ll
M llvm/test/CodeGen/BPF/BTF/tag-extern-func.ll
M llvm/test/CodeGen/BPF/BTF/tag-typedef.ll
M llvm/test/CodeGen/BPF/BTF/type-tag-fixup-fwd.ll
M llvm/test/CodeGen/BPF/BTF/type-tag-fixup-resolved.ll
M llvm/test/CodeGen/BPF/BTF/type-tag-var.ll
M llvm/test/CodeGen/BPF/BTF/uchar.ll
M llvm/test/CodeGen/BPF/BTF/uint.ll
M llvm/test/CodeGen/BPF/BTF/ulonglong.ll
M llvm/test/CodeGen/BPF/BTF/union-array-typedef.ll
M llvm/test/CodeGen/BPF/BTF/ushort.ll
M llvm/test/CodeGen/BPF/BTF/weak-global-2.ll
M llvm/test/CodeGen/BPF/BTF/weak-global-3.ll
M llvm/test/CodeGen/BPF/BTF/weak-global.ll
M llvm/test/CodeGen/BPF/CORE/field-reloc-st-imm.ll
M llvm/test/CodeGen/BPF/CORE/simplifypatable-nullptr.ll
M llvm/test/CodeGen/BPF/addr-space-cast.ll
M llvm/test/CodeGen/BPF/addr-space-globals.ll
M llvm/test/CodeGen/BPF/addr-space-globals2.ll
M llvm/test/CodeGen/BPF/alu8.ll
M llvm/test/CodeGen/BPF/atomics.ll
M llvm/test/CodeGen/BPF/atomics_2.ll
M llvm/test/CodeGen/BPF/atomics_mem_order_v1.ll
M llvm/test/CodeGen/BPF/atomics_mem_order_v3.ll
M llvm/test/CodeGen/BPF/atomics_sub64_relaxed_v1.ll
M llvm/test/CodeGen/BPF/basictest.ll
M llvm/test/CodeGen/BPF/bpf-fastcall-1.ll
M llvm/test/CodeGen/BPF/bpf-fastcall-2.ll
M llvm/test/CodeGen/BPF/bpf-fastcall-3.ll
M llvm/test/CodeGen/BPF/bpf-fastcall-4.ll
M llvm/test/CodeGen/BPF/bpf-fastcall-5.ll
M llvm/test/CodeGen/BPF/bpf-fastcall-regmask-1.ll
M llvm/test/CodeGen/BPF/bswap.ll
M llvm/test/CodeGen/BPF/byval.ll
M llvm/test/CodeGen/BPF/callx.ll
M llvm/test/CodeGen/BPF/cc_args.ll
M llvm/test/CodeGen/BPF/cc_args_be.ll
M llvm/test/CodeGen/BPF/cc_ret.ll
M llvm/test/CodeGen/BPF/cmp.ll
M llvm/test/CodeGen/BPF/cttz-ctlz.ll
M llvm/test/CodeGen/BPF/dwarfdump.ll
M llvm/test/CodeGen/BPF/ex1.ll
M llvm/test/CodeGen/BPF/fi_ri.ll
M llvm/test/CodeGen/BPF/gotol.ll
M llvm/test/CodeGen/BPF/i128.ll
M llvm/test/CodeGen/BPF/inline_asm.ll
M llvm/test/CodeGen/BPF/inlineasm-wreg.ll
M llvm/test/CodeGen/BPF/intrinsics.ll
M llvm/test/CodeGen/BPF/is_trunc_free.ll
M llvm/test/CodeGen/BPF/is_zext_free.ll
M llvm/test/CodeGen/BPF/ldsx.ll
M llvm/test/CodeGen/BPF/load.ll
M llvm/test/CodeGen/BPF/loops.ll
M llvm/test/CodeGen/BPF/many_args1.ll
M llvm/test/CodeGen/BPF/many_args2.ll
M llvm/test/CodeGen/BPF/mem_offset.ll
M llvm/test/CodeGen/BPF/mem_offset_be.ll
M llvm/test/CodeGen/BPF/memcmp.ll
M llvm/test/CodeGen/BPF/memcpy-expand-in-order.ll
M llvm/test/CodeGen/BPF/movsx.ll
M llvm/test/CodeGen/BPF/no-merge-attr.ll
M llvm/test/CodeGen/BPF/optnone-1.ll
M llvm/test/CodeGen/BPF/optnone-2.ll
M llvm/test/CodeGen/BPF/remove_truncate_1.ll
M llvm/test/CodeGen/BPF/remove_truncate_2.ll
M llvm/test/CodeGen/BPF/remove_truncate_3.ll
M llvm/test/CodeGen/BPF/remove_truncate_4.ll
M llvm/test/CodeGen/BPF/remove_truncate_5.ll
M llvm/test/CodeGen/BPF/remove_truncate_6.ll
M llvm/test/CodeGen/BPF/remove_truncate_7.ll
M llvm/test/CodeGen/BPF/remove_truncate_8.ll
M llvm/test/CodeGen/BPF/remove_truncate_9.ll
M llvm/test/CodeGen/BPF/rodata_1.ll
M llvm/test/CodeGen/BPF/rodata_2.ll
M llvm/test/CodeGen/BPF/rodata_3.ll
M llvm/test/CodeGen/BPF/rodata_4.ll
M llvm/test/CodeGen/BPF/rodata_5.ll
M llvm/test/CodeGen/BPF/rodata_6.ll
M llvm/test/CodeGen/BPF/rodata_7.ll
M llvm/test/CodeGen/BPF/sdiv_smod.ll
M llvm/test/CodeGen/BPF/sdiv_to_mul.ll
M llvm/test/CodeGen/BPF/select_ri.ll
M llvm/test/CodeGen/BPF/selectiondag-bug.ll
M llvm/test/CodeGen/BPF/setcc.ll
M llvm/test/CodeGen/BPF/shifts.ll
M llvm/test/CodeGen/BPF/sockex2.ll
M llvm/test/CodeGen/BPF/spill-alu32.ll
M llvm/test/CodeGen/BPF/store_imm.ll
M llvm/test/CodeGen/BPF/struct-arg.ll
M llvm/test/CodeGen/BPF/struct_ret1.ll
M llvm/test/CodeGen/BPF/struct_ret2.ll
M llvm/test/CodeGen/BPF/undef.ll
M llvm/test/CodeGen/BPF/vararg1.ll
M llvm/test/CodeGen/BPF/warn-call.ll
M llvm/test/CodeGen/BPF/warn-stack.ll
M llvm/test/CodeGen/BPF/xadd.ll
M llvm/test/CodeGen/BPF/xadd_legal.ll
M llvm/test/CodeGen/BPF/xaddd_v1.ll
Log Message:
-----------
[BPF,test] Change llc -march= to -mtriple=
Similar to 806761a7629df268c8aed49657aeccffa6bca449
-mtriple= specifies the full target triple while -march= merely sets the
architecture part of the default target triple (e.g. Windows, macOS),
leaving a target triple which may not make sense.
Therefore, -march= is error-prone and not recommended for tests without
a target triple. The issue has been benign as we recognize
bpf*-apple-darwin as ELF instead of rejecting it outrightly.
Commit: 50046221b8e913ec6506eb96ce4c0cd267a5cc99
https://github.com/llvm/llvm-project/commit/50046221b8e913ec6506eb96ce4c0cd267a5cc99
Author: Nico Weber <thakis at chromium.org>
Date: 2024-12-15 (Sun, 15 Dec 2024)
Changed paths:
M clang/lib/Driver/ToolChains/CommonArgs.cpp
M clang/lib/Driver/ToolChains/CommonArgs.h
M clang/lib/Driver/ToolChains/FreeBSD.cpp
M clang/lib/Driver/ToolChains/Fuchsia.cpp
M clang/lib/Driver/ToolChains/Gnu.cpp
M clang/lib/Driver/ToolChains/Hexagon.cpp
M clang/lib/Driver/ToolChains/NetBSD.cpp
M clang/lib/Driver/ToolChains/OpenBSD.cpp
M clang/lib/Driver/ToolChains/Solaris.cpp
Log Message:
-----------
Revert "[Driver] Cache SanitizerArgs (NFC) (#119442)"
This reverts commit bae383ba6b53b0d8257c83f99ceecdd751d0a378.
Prerequisite to reverting #119071.
Commit: 1464b8ec8a675fd11dc7280db1c56aac03771b0a
https://github.com/llvm/llvm-project/commit/1464b8ec8a675fd11dc7280db1c56aac03771b0a
Author: Nico Weber <thakis at chromium.org>
Date: 2024-12-15 (Sun, 15 Dec 2024)
Changed paths:
M clang/lib/Driver/ToolChains/CommonArgs.cpp
M clang/test/Driver/sanitizer-ld.c
M compiler-rt/lib/msan/msan_interceptors.cpp
M compiler-rt/lib/sanitizer_common/sanitizer_common_interceptors.inc
M compiler-rt/lib/sanitizer_common/sanitizer_platform_interceptors.h
R compiler-rt/test/msan/Linux/dn_expand.cpp
A compiler-rt/test/sanitizer_common/TestCases/Linux/b64.cpp
A compiler-rt/test/sanitizer_common/TestCases/Linux/dn_expand.cpp
Log Message:
-----------
Revert "Move interceptors for libresolv functions to MSan (#119071)"
This reverts commit f5f965058a5f9b835382f96bd4041bc7e608ece0.
Breaks a test on some bots, see
https://github.com/llvm/llvm-project/pull/119071#issuecomment-2544000926
Commit: 40a4cbb0f200e5e0bafbd58d55c2da6daab9515d
https://github.com/llvm/llvm-project/commit/40a4cbb0f200e5e0bafbd58d55c2da6daab9515d
Author: Fangrui Song <i at maskray.me>
Date: 2024-12-15 (Sun, 15 Dec 2024)
Changed paths:
M llvm/test/CodeGen/MIR/X86/basic-block-liveins.mir
M llvm/test/CodeGen/MIR/X86/basic-block-not-at-start-of-line-error.mir
M llvm/test/CodeGen/MIR/X86/block-address-operands.mir
M llvm/test/CodeGen/MIR/X86/callee-saved-info.mir
M llvm/test/CodeGen/MIR/X86/cfi-def-cfa-offset.mir
M llvm/test/CodeGen/MIR/X86/cfi-def-cfa-register.mir
M llvm/test/CodeGen/MIR/X86/cfi-offset.mir
M llvm/test/CodeGen/MIR/X86/constant-pool-item-redefinition-error.mir
M llvm/test/CodeGen/MIR/X86/constant-pool.mir
M llvm/test/CodeGen/MIR/X86/constant-value-error.mir
M llvm/test/CodeGen/MIR/X86/copyIRflags.mir
M llvm/test/CodeGen/MIR/X86/dead-register-flag.mir
M llvm/test/CodeGen/MIR/X86/def-register-already-tied-error.mir
M llvm/test/CodeGen/MIR/X86/duplicate-memory-operand-flag.mir
M llvm/test/CodeGen/MIR/X86/duplicate-register-flag-error.mir
M llvm/test/CodeGen/MIR/X86/early-clobber-register-flag.mir
M llvm/test/CodeGen/MIR/X86/exception-function-state.mir
M llvm/test/CodeGen/MIR/X86/expected-align-in-memory-operand.mir
M llvm/test/CodeGen/MIR/X86/expected-alignment-after-align-in-memory-operand.mir
M llvm/test/CodeGen/MIR/X86/expected-basic-block-at-start-of-body.mir
M llvm/test/CodeGen/MIR/X86/expected-block-reference-in-blockaddress.mir
M llvm/test/CodeGen/MIR/X86/expected-comma-after-cfi-register.mir
M llvm/test/CodeGen/MIR/X86/expected-comma-after-memory-operand.mir
M llvm/test/CodeGen/MIR/X86/expected-different-implicit-operand.mir
M llvm/test/CodeGen/MIR/X86/expected-different-implicit-register-flag.mir
M llvm/test/CodeGen/MIR/X86/expected-function-reference-after-blockaddress.mir
M llvm/test/CodeGen/MIR/X86/expected-global-value-after-blockaddress.mir
M llvm/test/CodeGen/MIR/X86/expected-integer-after-offset-sign.mir
M llvm/test/CodeGen/MIR/X86/expected-integer-after-tied-def.mir
M llvm/test/CodeGen/MIR/X86/expected-integer-in-successor-weight.mir
M llvm/test/CodeGen/MIR/X86/expected-load-or-store-in-memory-operand.mir
M llvm/test/CodeGen/MIR/X86/expected-machine-operand.mir
M llvm/test/CodeGen/MIR/X86/expected-metadata-node-after-debug-location.mir
M llvm/test/CodeGen/MIR/X86/expected-metadata-node-after-exclaim.mir
M llvm/test/CodeGen/MIR/X86/expected-metadata-node-in-stack-object.mir
M llvm/test/CodeGen/MIR/X86/expected-named-register-in-allocation-hint.mir
M llvm/test/CodeGen/MIR/X86/expected-named-register-in-callee-saved-register.mir
M llvm/test/CodeGen/MIR/X86/expected-named-register-in-functions-livein.mir
M llvm/test/CodeGen/MIR/X86/expected-named-register-livein.mir
M llvm/test/CodeGen/MIR/X86/expected-newline-at-end-of-list.mir
M llvm/test/CodeGen/MIR/X86/expected-number-after-bb.mir
M llvm/test/CodeGen/MIR/X86/expected-offset-after-cfi-operand.mir
M llvm/test/CodeGen/MIR/X86/expected-pointer-value-in-memory-operand.mir
M llvm/test/CodeGen/MIR/X86/expected-positive-alignment-after-align.mir
M llvm/test/CodeGen/MIR/X86/expected-power-of-2-after-align.mir
M llvm/test/CodeGen/MIR/X86/expected-register-after-cfi-operand.mir
M llvm/test/CodeGen/MIR/X86/expected-register-after-flags.mir
M llvm/test/CodeGen/MIR/X86/expected-size-integer-after-memory-operation.mir
M llvm/test/CodeGen/MIR/X86/expected-size-integer-after-memory-operation2.mir
M llvm/test/CodeGen/MIR/X86/expected-stack-object-function-context.mir
M llvm/test/CodeGen/MIR/X86/expected-stack-object.mir
M llvm/test/CodeGen/MIR/X86/expected-subregister-after-colon.mir
M llvm/test/CodeGen/MIR/X86/expected-target-flag-name.mir
M llvm/test/CodeGen/MIR/X86/expected-tied-def-after-lparen.mir
M llvm/test/CodeGen/MIR/X86/expected-value-in-memory-operand.mir
M llvm/test/CodeGen/MIR/X86/expected-virtual-register-in-functions-livein.mir
M llvm/test/CodeGen/MIR/X86/external-symbol-operands.mir
M llvm/test/CodeGen/MIR/X86/fastmath.mir
M llvm/test/CodeGen/MIR/X86/frame-info-save-restore-points.mir
M llvm/test/CodeGen/MIR/X86/frame-info-stack-references.mir
M llvm/test/CodeGen/MIR/X86/frame-setup-instruction-flag.mir
M llvm/test/CodeGen/MIR/X86/function-liveins.mir
M llvm/test/CodeGen/MIR/X86/generic-instr-type.mir
M llvm/test/CodeGen/MIR/X86/global-value-operands.mir
M llvm/test/CodeGen/MIR/X86/immediate-operands.mir
M llvm/test/CodeGen/MIR/X86/implicit-register-flag.mir
M llvm/test/CodeGen/MIR/X86/inline-asm-registers.mir
M llvm/test/CodeGen/MIR/X86/instr-cfi-type.mir
M llvm/test/CodeGen/MIR/X86/instr-heap-alloc-operands.mir
M llvm/test/CodeGen/MIR/X86/instr-pcsections.mir
M llvm/test/CodeGen/MIR/X86/instr-symbols-and-mcsymbol-operands.mir
M llvm/test/CodeGen/MIR/X86/instructions-debug-location.mir
M llvm/test/CodeGen/MIR/X86/invalid-constant-pool-item.mir
M llvm/test/CodeGen/MIR/X86/invalid-metadata-node-type.mir
M llvm/test/CodeGen/MIR/X86/invalid-target-flag-name.mir
M llvm/test/CodeGen/MIR/X86/invalid-tied-def-index-error.mir
M llvm/test/CodeGen/MIR/X86/jump-table-info.mir
M llvm/test/CodeGen/MIR/X86/jump-table-redefinition-error.mir
M llvm/test/CodeGen/MIR/X86/killed-register-flag.mir
M llvm/test/CodeGen/MIR/X86/large-cfi-offset-number-error.mir
M llvm/test/CodeGen/MIR/X86/large-immediate-operand-error.mir
M llvm/test/CodeGen/MIR/X86/large-index-number-error.mir
M llvm/test/CodeGen/MIR/X86/large-offset-number-error.mir
M llvm/test/CodeGen/MIR/X86/large-size-in-memory-operand-error.mir
M llvm/test/CodeGen/MIR/X86/liveout-register-mask.mir
M llvm/test/CodeGen/MIR/X86/load-with-max-alignment.mir
M llvm/test/CodeGen/MIR/X86/machine-basic-block-operands.mir
M llvm/test/CodeGen/MIR/X86/machine-instructions.mir
M llvm/test/CodeGen/MIR/X86/machine-verifier-address.mir
M llvm/test/CodeGen/MIR/X86/machine-verifier.mir
M llvm/test/CodeGen/MIR/X86/memory-operands.mir
M llvm/test/CodeGen/MIR/X86/metadata-operands.mir
M llvm/test/CodeGen/MIR/X86/mircanon-flags.mir
M llvm/test/CodeGen/MIR/X86/missing-closing-quote.mir
M llvm/test/CodeGen/MIR/X86/missing-comma.mir
M llvm/test/CodeGen/MIR/X86/missing-implicit-operand.mir
M llvm/test/CodeGen/MIR/X86/named-registers.mir
M llvm/test/CodeGen/MIR/X86/newline-handling.mir
M llvm/test/CodeGen/MIR/X86/null-register-operands.mir
M llvm/test/CodeGen/MIR/X86/register-mask-operands.mir
M llvm/test/CodeGen/MIR/X86/register-operand-class-invalid0.mir
M llvm/test/CodeGen/MIR/X86/register-operand-class-invalid1.mir
M llvm/test/CodeGen/MIR/X86/register-operand-class.mir
M llvm/test/CodeGen/MIR/X86/register-operands-target-flag-error.mir
M llvm/test/CodeGen/MIR/X86/renamable-register-flag.mir
M llvm/test/CodeGen/MIR/X86/simple-register-allocation-hints.mir
M llvm/test/CodeGen/MIR/X86/spill-slot-fixed-stack-object-aliased.mir
M llvm/test/CodeGen/MIR/X86/spill-slot-fixed-stack-object-immutable.mir
M llvm/test/CodeGen/MIR/X86/spill-slot-fixed-stack-objects.mir
M llvm/test/CodeGen/MIR/X86/stack-object-debug-info.mir
M llvm/test/CodeGen/MIR/X86/stack-object-invalid-name.mir
M llvm/test/CodeGen/MIR/X86/stack-object-operand-name-mismatch-error.mir
M llvm/test/CodeGen/MIR/X86/stack-object-redefinition-error.mir
M llvm/test/CodeGen/MIR/X86/stack-objects.mir
M llvm/test/CodeGen/MIR/X86/standalone-register-error.mir
M llvm/test/CodeGen/MIR/X86/subreg-on-physreg.mir
M llvm/test/CodeGen/MIR/X86/subregister-index-operands.mir
M llvm/test/CodeGen/MIR/X86/subregister-operands.mir
M llvm/test/CodeGen/MIR/X86/successor-basic-blocks-weights.mir
M llvm/test/CodeGen/MIR/X86/successor-basic-blocks.mir
M llvm/test/CodeGen/MIR/X86/tied-def-operand-invalid.mir
M llvm/test/CodeGen/MIR/X86/tied-physical-regs-match.mir
M llvm/test/CodeGen/MIR/X86/undef-register-flag.mir
M llvm/test/CodeGen/MIR/X86/undefined-fixed-stack-object.mir
M llvm/test/CodeGen/MIR/X86/undefined-global-value.mir
M llvm/test/CodeGen/MIR/X86/undefined-ir-block-in-blockaddress.mir
M llvm/test/CodeGen/MIR/X86/undefined-ir-block-slot-in-blockaddress.mir
M llvm/test/CodeGen/MIR/X86/undefined-jump-table-id.mir
M llvm/test/CodeGen/MIR/X86/undefined-named-global-value.mir
M llvm/test/CodeGen/MIR/X86/undefined-register-class.mir
M llvm/test/CodeGen/MIR/X86/undefined-stack-object.mir
M llvm/test/CodeGen/MIR/X86/undefined-value-in-memory-operand.mir
M llvm/test/CodeGen/MIR/X86/undefined-virtual-register.mir
M llvm/test/CodeGen/MIR/X86/unexpected-type-phys.mir
M llvm/test/CodeGen/MIR/X86/unknown-instruction.mir
M llvm/test/CodeGen/MIR/X86/unknown-machine-basic-block.mir
M llvm/test/CodeGen/MIR/X86/unknown-metadata-keyword.mir
M llvm/test/CodeGen/MIR/X86/unknown-metadata-node.mir
M llvm/test/CodeGen/MIR/X86/unknown-named-machine-basic-block.mir
M llvm/test/CodeGen/MIR/X86/unknown-register.mir
M llvm/test/CodeGen/MIR/X86/unknown-subregister-index-op.mir
M llvm/test/CodeGen/MIR/X86/unknown-subregister-index.mir
M llvm/test/CodeGen/MIR/X86/unrecognized-character.mir
M llvm/test/CodeGen/MIR/X86/variable-sized-stack-object-size-error.mir
M llvm/test/CodeGen/MIR/X86/variable-sized-stack-objects.mir
M llvm/test/CodeGen/MIR/X86/virtual-register-redefinition-error.mir
M llvm/test/CodeGen/MIR/X86/virtual-registers.mir
M llvm/test/DebugInfo/MIR/InstrRef/instr-ref-roundtrip.mir
M llvm/test/DebugInfo/MIR/InstrRef/livedebugvalues_illegal_locs.mir
M llvm/test/DebugInfo/MIR/InstrRef/livedebugvalues_instrref_tolocs.mir
M llvm/test/DebugInfo/MIR/InstrRef/livedebugvalues_recover_clobbers.mir
M llvm/test/DebugInfo/MIR/InstrRef/livedebugvalues_stackslot_subregs.mir
M llvm/test/DebugInfo/MIR/InstrRef/livedebugvalues_subreg_substitutions.mir
M llvm/test/DebugInfo/MIR/InstrRef/memory-operand-tracking.mir
M llvm/test/DebugInfo/MIR/InstrRef/no-duplicates.mir
M llvm/test/DebugInfo/MIR/InstrRef/no-metainstrs.mir
M llvm/test/DebugInfo/MIR/InstrRef/out-of-scope-blocks.mir
M llvm/test/DebugInfo/MIR/InstrRef/pretty-print.mir
M llvm/test/DebugInfo/MIR/InstrRef/single-assign-propagation.mir
M llvm/test/DebugInfo/MIR/InstrRef/substitusions-roundtrip.mir
M llvm/test/DebugInfo/MIR/X86/dbginfo-entryvals.mir
M llvm/test/DebugInfo/MIR/X86/live-debug-values-restore.mir
M llvm/test/DebugInfo/MIR/X86/livedebugvalues-ignores-metaInstructions.mir
M llvm/test/DebugInfo/MIR/X86/livedebugvalues_basic_diamond.mir
M llvm/test/DebugInfo/MIR/X86/livedebugvalues_basic_diamond_match_clobber.mir
M llvm/test/DebugInfo/MIR/X86/livedebugvalues_basic_diamond_match_move.mir
M llvm/test/DebugInfo/MIR/X86/livedebugvalues_basic_diamond_one_clobber.mir
M llvm/test/DebugInfo/MIR/X86/livedebugvalues_basic_diamond_one_move.mir
M llvm/test/DebugInfo/MIR/X86/livedebugvalues_basic_loop.mir
M llvm/test/DebugInfo/MIR/X86/livedebugvalues_bb_to_bb.mir
M llvm/test/DebugInfo/MIR/X86/livedebugvalues_bb_to_bb_clobbered.mir
M llvm/test/DebugInfo/MIR/X86/livedebugvalues_bb_to_bb_move_to_clobber.mir
M llvm/test/DebugInfo/MIR/X86/livedebugvalues_load_in_loop.mir
M llvm/test/DebugInfo/MIR/X86/livedebugvalues_loop_break.mir
M llvm/test/DebugInfo/MIR/X86/livedebugvalues_loop_break_clobbered.mir
M llvm/test/DebugInfo/MIR/X86/livedebugvalues_loop_clobbered.mir
M llvm/test/DebugInfo/MIR/X86/livedebugvalues_loop_diamond.mir
M llvm/test/DebugInfo/MIR/X86/livedebugvalues_loop_diamond_clobber.mir
M llvm/test/DebugInfo/MIR/X86/livedebugvalues_loop_diamond_move.mir
M llvm/test/DebugInfo/MIR/X86/livedebugvalues_loop_early_clobber.mir
M llvm/test/DebugInfo/MIR/X86/livedebugvalues_loop_terminated.mir
M llvm/test/DebugInfo/MIR/X86/livedebugvalues_loop_two_backedge.mir
M llvm/test/DebugInfo/MIR/X86/livedebugvalues_loop_two_backedge_clobbered.mir
M llvm/test/DebugInfo/MIR/X86/livedebugvalues_loop_within_loop.mir
M llvm/test/DebugInfo/MIR/X86/livedebugvalues_loop_within_loop_clobbered.mir
M llvm/test/DebugInfo/MIR/X86/livedebugvalues_loop_within_loop_moved.mir
M llvm/test/DebugInfo/MIR/X86/livedebugvalues_loop_within_loop_outer_moved.mir
M llvm/test/DebugInfo/MIR/X86/livedebugvalues_many_loop_heads.mir
M llvm/test/DebugInfo/MIR/X86/multiple-param-dbg-value-entry.mir
M llvm/test/DebugInfo/MIR/X86/no-cfi-loc.mir
Log Message:
-----------
[MIR,test] Change llc -march=x86-64 to -mtriple=x86_64
Similar to 806761a7629df268c8aed49657aeccffa6bca449
-mtriple= specifies the full target triple while -march= merely sets the
architecture part of the default target triple (e.g. Windows, macOS).
Therefore, -march= is error-prone and not recommended for tests without
a target triple. The issue has been benign as these MIR tests do not
utilize object file format specific detail, but it's good to change
these tests to neighbor files that use -mtriple=x86_64
Commit: e339f0a9daf2e61bd24414c99e49e0170c9a486e
https://github.com/llvm/llvm-project/commit/e339f0a9daf2e61bd24414c99e49e0170c9a486e
Author: Fangrui Song <i at maskray.me>
Date: 2024-12-15 (Sun, 15 Dec 2024)
Changed paths:
M llvm/test/CodeGen/MIR/X86/dbg-value-list.mir
M llvm/test/DebugInfo/MIR/X86/backup-entry-values-usage.mir
M llvm/test/DebugInfo/MIR/X86/complex-entryvalue.mir
M llvm/test/DebugInfo/MIR/X86/entry-value-of-modified-param.mir
M llvm/test/DebugInfo/MIR/X86/entry-value-of-modified-param2.mir
M llvm/test/DebugInfo/MIR/X86/entry-values-diamond-bbs.mir
M llvm/test/DebugInfo/MIR/X86/kill-entry-value-after-diamond-bbs.mir
M llvm/test/DebugInfo/MIR/X86/kill-entry-value-after-diamond-bbs2.mir
M llvm/test/DebugInfo/MIR/X86/live-debug-values-3preds.mir
M llvm/test/DebugInfo/MIR/X86/live-debug-values-spill.mir
M llvm/test/DebugInfo/MIR/X86/live-debug-values.mir
M llvm/test/DebugInfo/MIR/X86/livedebugvalues-limit.mir
M llvm/test/DebugInfo/MIR/X86/piece-entryval.mir
M llvm/test/DebugInfo/MIR/X86/propagate-entry-value-cross-bbs.mir
M llvm/test/DebugInfo/MIR/X86/remove-entry-value-from-loop.mir
Log Message:
-----------
[test] Remove redundant -march=x86-64 when target triple is specified in IR
Commit: 6e8718c3e32225c579a3a974be003c7f38c32a05
https://github.com/llvm/llvm-project/commit/6e8718c3e32225c579a3a974be003c7f38c32a05
Author: Fangrui Song <i at maskray.me>
Date: 2024-12-15 (Sun, 15 Dec 2024)
Changed paths:
M llvm/test/CodeGen/ARC/addrmode.ll
M llvm/test/CodeGen/ARC/alu.ll
M llvm/test/CodeGen/ARC/brcc.ll
M llvm/test/CodeGen/ARC/call.ll
M llvm/test/CodeGen/ARC/intrinsics.ll
M llvm/test/CodeGen/ARC/ldst.ll
Log Message:
-----------
[ARC,test] Change llc -march= to -mtriple=
Similar to 806761a7629df268c8aed49657aeccffa6bca449
-mtriple= specifies the full target triple while -march= merely sets the
architecture part of the default target triple (e.g. Windows, macOS),
leaving a target triple which may not make sense.
Therefore, -march= is error-prone and not recommended for tests without
a target triple. The issue has been benign as we recognize
arc-apple-darwin as ELF instead of rejecting it outrightly.
Commit: 133352feb30605ec51b15f77826ed3a2fbf8db56
https://github.com/llvm/llvm-project/commit/133352feb30605ec51b15f77826ed3a2fbf8db56
Author: Fangrui Song <i at maskray.me>
Date: 2024-12-15 (Sun, 15 Dec 2024)
Changed paths:
M llvm/test/CodeGen/AArch64/stack-tagging-ex-2.ll
M llvm/test/CodeGen/Hexagon/autohvx/float-cost.ll
M llvm/test/CodeGen/Hexagon/autohvx/interleave.ll
M llvm/test/CodeGen/Hexagon/autohvx/maximize-bandwidth.ll
M llvm/test/CodeGen/Hexagon/bug15515-shuffle.ll
M llvm/test/CodeGen/Hexagon/const-pool-tf.ll
M llvm/test/CodeGen/Hexagon/glob-align-volatile.ll
M llvm/test/CodeGen/Hexagon/loop-idiom/pmpy-infinite-loop.ll
M llvm/test/CodeGen/Hexagon/loop-idiom/pmpy-long-loop.ll
M llvm/test/CodeGen/Hexagon/loop-idiom/pmpy-mod.ll
M llvm/test/CodeGen/Hexagon/loop-idiom/pmpy-shiftconv-fail.ll
M llvm/test/CodeGen/Hexagon/vcombine_zero_diff_ptrs.ll
M llvm/test/CodeGen/Lanai/delay_filler.ll
M llvm/test/CodeGen/Lanai/lowering-128.ll
M llvm/test/CodeGen/NVPTX/surf-read.ll
M llvm/test/CodeGen/NVPTX/surf-write.ll
M llvm/test/CodeGen/NVPTX/tex-read.ll
M llvm/test/CodeGen/PowerPC/ppc64le-aggregates.ll
M llvm/test/CodeGen/Thumb2/bug-subw.ll
M llvm/test/DebugInfo/NVPTX/debug-ptx-symbols.ll
M llvm/test/DebugInfo/X86/instr-ref-flag.ll
M llvm/test/DebugInfo/X86/no-entry-values-with-O0.ll
M llvm/test/DebugInfo/X86/single-dbg_value.ll
M llvm/test/Transforms/LoadStoreVectorizer/NVPTX/propagate-invariance-metadata.ll
M llvm/test/Transforms/StraightLineStrengthReduce/NVPTX/reassociate-geps-and-slsr.ll
M llvm/test/Transforms/StraightLineStrengthReduce/NVPTX/speculative-slsr.ll
Log Message:
-----------
[test] Remove redundant -march= when target triple is specified in IR
Commit: 43045051d4114f2490bf0e6b01a7969d5c27ee04
https://github.com/llvm/llvm-project/commit/43045051d4114f2490bf0e6b01a7969d5c27ee04
Author: Florian Hahn <flo at fhahn.com>
Date: 2024-12-15 (Sun, 15 Dec 2024)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
M llvm/test/Transforms/LoopVectorize/PowerPC/vplan-force-tail-with-evl.ll
M llvm/test/Transforms/LoopVectorize/first-order-recurrence-sink-replicate-region.ll
M llvm/test/Transforms/LoopVectorize/icmp-uniforms.ll
M llvm/test/Transforms/LoopVectorize/vplan-iv-transforms.ll
M llvm/test/Transforms/LoopVectorize/vplan-printing.ll
M llvm/test/Transforms/LoopVectorize/vplan-sink-scalars-and-merge.ll
Log Message:
-----------
[VPlan] Modernize VPWidenIntOrFpInductionRecipe printing (NFC).
Modernize VPWidenIntOrFpInductionRecipe printing by including the result
VPValue and all operand VPValues, similar to VPScalarIVStepsRecipe and
VPDerivedIVRecipe.
Commit: 8d550aa0f027eb2cf32850f3905dc1db22317587
https://github.com/llvm/llvm-project/commit/8d550aa0f027eb2cf32850f3905dc1db22317587
Author: Fangrui Song <i at maskray.me>
Date: 2024-12-15 (Sun, 15 Dec 2024)
Changed paths:
M llvm/test/CodeGen/X86/stack-frame-layout-remarks.ll
Log Message:
-----------
[test] Replace -march=x86 -mcpu=i386 with -mtriple
Commit: cd12922235f14a78eeed25fabf364950d02cb786
https://github.com/llvm/llvm-project/commit/cd12922235f14a78eeed25fabf364950d02cb786
Author: Fangrui Song <i at maskray.me>
Date: 2024-12-15 (Sun, 15 Dec 2024)
Changed paths:
M llvm/test/Analysis/CostModel/X86/scalarize.ll
M llvm/test/CodeGen/MIR/X86/fixed-stack-memory-operands.mir
M llvm/test/CodeGen/MIR/X86/fixed-stack-object-redefinition-error.mir
M llvm/test/CodeGen/MIR/X86/fixed-stack-objects.mir
M llvm/test/CodeGen/MIR/X86/stack-object-operands.mir
M llvm/test/CodeGen/X86/2006-10-02-BoolRetCrash.ll
M llvm/test/MachineVerifier/test_copy_physregs_x86.mir
M llvm/test/MachineVerifier/verify-regops.mir
M llvm/test/Transforms/NaryReassociate/NVPTX/nary-slsr.ll
Log Message:
-----------
[test] Change llc -march= to -mtriple=
Similar to 806761a7629df268c8aed49657aeccffa6bca449
-march= is error-prone when running on a host whose OS is different.
Commit: 7168de5ca7a09b929006bd0fb5c3d9510c0ba058
https://github.com/llvm/llvm-project/commit/7168de5ca7a09b929006bd0fb5c3d9510c0ba058
Author: Jacek Caban <jacek at codeweavers.com>
Date: 2024-12-15 (Sun, 15 Dec 2024)
Changed paths:
M lld/COFF/COFFLinkerContext.h
M lld/COFF/Driver.cpp
M lld/COFF/InputFiles.cpp
M lld/COFF/InputFiles.h
M lld/COFF/SymbolTable.h
M lld/test/COFF/arm64ec-codemap.test
M lld/test/COFF/arm64ec-entry-thunk.s
M lld/test/COFF/arm64ec-lib.test
M lld/test/COFF/arm64ec-range-thunks.s
R lld/test/COFF/arm64x-symtab.s
Log Message:
-----------
Revert "[LLD][COFF] Introduce hybrid symbol table for EC input files on ARM64X (#119294)"
This reverts commit a8206e7b37929f4754806667680ffba0206eef95 due to sanitizer failures.
Commit: e86910337f98e57f5b9253f7d80d5b916eb1d97e
https://github.com/llvm/llvm-project/commit/e86910337f98e57f5b9253f7d80d5b916eb1d97e
Author: Ryosuke Niwa <rniwa at webkit.org>
Date: 2024-12-15 (Sun, 15 Dec 2024)
Changed paths:
M clang/lib/StaticAnalyzer/Checkers/WebKit/UncountedLambdaCapturesChecker.cpp
M clang/test/Analysis/Checkers/WebKit/uncounted-lambda-captures.cpp
Log Message:
-----------
[webkit.UncountedLambdaCapturesChecker] Add a fallback for checking lambda captures (#119800)
Commit: 938cdd60d4938e32a7f4f1620e3d9c11aabc4af5
https://github.com/llvm/llvm-project/commit/938cdd60d4938e32a7f4f1620e3d9c11aabc4af5
Author: Oleksandr "Alex" Zinenko <git at ozinenko.com>
Date: 2024-12-15 (Sun, 15 Dec 2024)
Changed paths:
M mlir/lib/Dialect/Transform/Transforms/CheckUses.cpp
M mlir/test/Dialect/Transform/check-use-after-free.mlir
Log Message:
-----------
correctly check uses of pattern descriptor transform ops (#118791)
In the transform dialect use-after-free chcker pass, account for pattern
descriptor operations that intentionally have no declared side effects.
They are not destroying any handles.
Closes #118761.
Commit: 1c352e66e7bac03a654cbd4c13c3bec6ed346048
https://github.com/llvm/llvm-project/commit/1c352e66e7bac03a654cbd4c13c3bec6ed346048
Author: Oleksandr "Alex" Zinenko <git at ozinenko.com>
Date: 2024-12-15 (Sun, 15 Dec 2024)
Changed paths:
M mlir/include/mlir/Dialect/Transform/IR/TransformOps.td
M mlir/lib/Dialect/Transform/IR/TransformOps.cpp
M mlir/test/Dialect/Transform/test-interpreter.mlir
Log Message:
-----------
make transform.split_handle accept any handle kind (#118752)
It can now split value and parameter handles in addition to operation
handles. This is a generally useful functionality.
Commit: d072ca1a496cc3f4ad0adf6f7d43f76406a704d6
https://github.com/llvm/llvm-project/commit/d072ca1a496cc3f4ad0adf6f7d43f76406a704d6
Author: Oleksandr "Alex" Zinenko <git at ozinenko.com>
Date: 2024-12-15 (Sun, 15 Dec 2024)
Changed paths:
M mlir/include/mlir/Dialect/Func/IR/FuncOps.td
M mlir/lib/Dialect/Func/Extensions/InlinerExtension.cpp
M mlir/test/Transforms/inlining.mlir
Log Message:
-----------
[mlir] add noinline attribute to func.func/call (#119970)
This allows for inlining to be somewhat controlled by the user instead
of always inlining everything. External heuristics may be used to place
`no_inline` attributes on invidiual calls or functions to prevent
inlining.
Commit: 8345a95a404cb490918201274da877b8ca2edf51
https://github.com/llvm/llvm-project/commit/8345a95a404cb490918201274da877b8ca2edf51
Author: William Moses <gh at wsmoses.com>
Date: 2024-12-15 (Sun, 15 Dec 2024)
Changed paths:
M mlir/include/mlir-c/Dialect/LLVM.h
M mlir/lib/CAPI/Dialect/LLVM.cpp
Log Message:
-----------
MLIR-C: Add accessor for LLVM array type (#119998)
Commit: 646ad49eacea19cfd656145cd41ae5ef99029a97
https://github.com/llvm/llvm-project/commit/646ad49eacea19cfd656145cd41ae5ef99029a97
Author: Lang Hames <lhames at gmail.com>
Date: 2024-12-16 (Mon, 16 Dec 2024)
Changed paths:
M llvm/tools/llvm-jitlink/llvm-jitlink.cpp
Log Message:
-----------
[llvm-jitlink] Avoid some SymbolStringPtr copies.
Commit: 8daf4f16fa08b5d876e98108721dd1743a360326
https://github.com/llvm/llvm-project/commit/8daf4f16fa08b5d876e98108721dd1743a360326
Author: Lang Hames <lhames at gmail.com>
Date: 2024-12-15 (Sun, 15 Dec 2024)
Changed paths:
M compiler-rt/lib/orc/CMakeLists.txt
A compiler-rt/lib/orc/sysv_reenter.x86-64.S
M compiler-rt/test/orc/TestCases/Generic/lazy-link.ll
M llvm/include/llvm/ExecutionEngine/JITLink/x86_64.h
M llvm/lib/ExecutionEngine/JITLink/x86_64.cpp
M llvm/lib/ExecutionEngine/Orc/JITLinkReentryTrampolines.cpp
Log Message:
-----------
[ORC][ORC-RT] Add ORC-RT based lazy compilation support for x86-64.
Adds support for the ORC-RT based lazy compilation scheme that was introduced
in 570ecdcf8b4.
Commit: f86f4574bbab9cb8c998f9e6560c68696c45f90f
https://github.com/llvm/llvm-project/commit/f86f4574bbab9cb8c998f9e6560c68696c45f90f
Author: Maksim Panchenko <maks at fb.com>
Date: 2024-12-15 (Sun, 15 Dec 2024)
Changed paths:
M bolt/test/X86/linux-static-keys.s
Log Message:
-----------
[BOLT][Linux] Fix static keys test case (#119771)
The key address in the static keys jump table was incorrectly encoded as
an absolute value instead of PC-relative causing incorrect
interpretation of the "likely" property of the key.
Commit: ca60ee2b8c57034175f590f0aff5978a066569a0
https://github.com/llvm/llvm-project/commit/ca60ee2b8c57034175f590f0aff5978a066569a0
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-12-15 (Sun, 15 Dec 2024)
Changed paths:
M llvm/lib/CodeGen/MachineVerifier.cpp
M llvm/test/MachineVerifier/test_abd_su.mir
Log Message:
-----------
[GISel] Remove unnecessary MachineVerifier checks for G_ABDS/G_ABDU. (#120014)
These are declared to use a single type index for all operands in
GenericOpcodes.td and the verifier knows how to check that all operands
with the same type index match.
Commit: 73eecb70c2abb1c6149647ec213cb9312c398569
https://github.com/llvm/llvm-project/commit/73eecb70c2abb1c6149647ec213cb9312c398569
Author: Sergei Barannikov <barannikov88 at gmail.com>
Date: 2024-12-16 (Mon, 16 Dec 2024)
Changed paths:
M llvm/utils/TableGen/Common/CodeGenTarget.cpp
M llvm/utils/TableGen/Common/CodeGenTarget.h
M llvm/utils/TableGen/GlobalISelEmitter.cpp
Log Message:
-----------
[TableGen][GISel] Don't use std::optional with pointers (NFC) (#120026)
Pointers already have a well-defined null value.
Commit: bb18e49edb2c4bbb7dd70ee0b5946598822a4e2a
https://github.com/llvm/llvm-project/commit/bb18e49edb2c4bbb7dd70ee0b5946598822a4e2a
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2024-12-16 (Mon, 16 Dec 2024)
Changed paths:
M llvm/include/llvm/IR/DiagnosticInfo.h
M llvm/lib/CodeGen/RegAllocBase.cpp
M llvm/lib/CodeGen/RegAllocFast.cpp
M llvm/lib/IR/DiagnosticInfo.cpp
M llvm/test/CodeGen/AArch64/arm64-anyregcc-crash.ll
M llvm/test/CodeGen/AMDGPU/illegal-eviction-assert.mir
M llvm/test/CodeGen/AMDGPU/issue48473.mir
A llvm/test/CodeGen/AMDGPU/ran-out-of-registers-error-all-regs-reserved.ll
A llvm/test/CodeGen/AMDGPU/ran-out-of-registers-errors.ll
M llvm/test/CodeGen/AMDGPU/remaining-virtual-register-operands.ll
M llvm/test/CodeGen/PowerPC/ppc64-anyregcc-crash.ll
M llvm/test/CodeGen/X86/anyregcc-crash.ll
Log Message:
-----------
RegAlloc: Use DiagnosticInfo to report register allocation failures (#119492)
Improve the non-fatal cases to use DiagnosticInfo, which will now
provide a location. The allocators attempt to report different errors
if it happens to see inline assembly is involved (this detection is
quite unreliable) using srcloc instead of dbgloc. For now, leave this
behavior unchanged. I think reporting the full location and context
function would be more useful.
Commit: 61f99a1c75e9dc84b70d6f2a660e99c1ac182e5b
https://github.com/llvm/llvm-project/commit/61f99a1c75e9dc84b70d6f2a660e99c1ac182e5b
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2024-12-16 (Mon, 16 Dec 2024)
Changed paths:
M llvm/include/llvm/CodeGen/MachineFunction.h
M llvm/lib/CodeGen/MachineFunction.cpp
M llvm/lib/CodeGen/RegAllocBase.cpp
M llvm/lib/CodeGen/RegAllocBase.h
M llvm/lib/CodeGen/RegAllocFast.cpp
M llvm/lib/CodeGen/VirtRegMap.cpp
M llvm/test/CodeGen/AMDGPU/alloc-all-regs-reserved-in-class.mir
M llvm/test/CodeGen/AMDGPU/ran-out-of-registers-error-all-regs-reserved.ll
M llvm/test/CodeGen/AMDGPU/ran-out-of-registers-errors.ll
M llvm/test/CodeGen/AMDGPU/regalloc-illegal-eviction-assert.ll
Log Message:
-----------
RegAlloc: Do not fatal error if there are no registers in the alloc order (#119640)
Try to use DiagnosticInfo if every register in the class is reserved
by forcing assignment to a reserved register. Also reduces the number
of redundant errors emitted, particularly with fast.
This is still broken in the case of undef uses. There are additional
complications in greedy and fast, so leave it for a separate fix.
Commit: 818bffcb1c454da8ec778327bde3d974dfe44550
https://github.com/llvm/llvm-project/commit/818bffcb1c454da8ec778327bde3d974dfe44550
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2024-12-16 (Mon, 16 Dec 2024)
Changed paths:
M llvm/lib/CodeGen/RegAllocFast.cpp
M llvm/lib/CodeGen/RegAllocGreedy.cpp
M llvm/test/CodeGen/AMDGPU/ran-out-of-registers-error-all-regs-reserved.ll
Log Message:
-----------
RegAlloc: Fix failure on undef use when all registers are reserved (#119647)
Greedy and fast would hit different assertions on undef uses if all
registers in a class were reserved.
Commit: 58cd17d960462c63c3a964efe539ae15774a6c66
https://github.com/llvm/llvm-project/commit/58cd17d960462c63c3a964efe539ae15774a6c66
Author: Lang Hames <lhames at gmail.com>
Date: 2024-12-16 (Mon, 16 Dec 2024)
Changed paths:
M llvm/include/llvm/ExecutionEngine/Orc/Core.h
Log Message:
-----------
[ORC] Add comments to ResourceManager to clarify locking rules.
Commit: 4914b188998deb50402405567d5a98186bf0a155
https://github.com/llvm/llvm-project/commit/4914b188998deb50402405567d5a98186bf0a155
Author: Lang Hames <lhames at gmail.com>
Date: 2024-12-16 (Mon, 16 Dec 2024)
Changed paths:
M llvm/include/llvm/ExecutionEngine/Orc/LazyObjectLinkingLayer.h
Log Message:
-----------
[ORC] Fix / add comments for LazyObjectLinkingLayer. NFC.
Also remove some redundant namespace qualification.
Commit: f8ad6e0cdae3cbc1618b19c3c7b41021070c0e94
https://github.com/llvm/llvm-project/commit/f8ad6e0cdae3cbc1618b19c3c7b41021070c0e94
Author: Luke Lau <luke at igalia.com>
Date: 2024-12-16 (Mon, 16 Dec 2024)
Changed paths:
M llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp
Log Message:
-----------
[RISCV][VLOPT] Get MachineInstr from MachineOperand in getOperandInfo. NFC (#119838)
IICU MI should be MO's parent, so just use MachineOperand::getParent().
Commit: 4746395bd75bc234dfd026bad672613b99e87e7a
https://github.com/llvm/llvm-project/commit/4746395bd75bc234dfd026bad672613b99e87e7a
Author: Luke Lau <luke at igalia.com>
Date: 2024-12-16 (Mon, 16 Dec 2024)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
M llvm/test/Transforms/LoopVectorize/AArch64/clamped-trip-count.ll
M llvm/test/Transforms/LoopVectorize/AArch64/divs-with-scalable-vfs.ll
M llvm/test/Transforms/LoopVectorize/AArch64/outer_loop_prefer_scalable.ll
M llvm/test/Transforms/LoopVectorize/AArch64/scalable-avoid-scalarization.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve-inductions-unusual-types.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve-tail-folding.ll
M llvm/test/Transforms/LoopVectorize/RISCV/blocks-with-dead-instructions.ll
M llvm/test/Transforms/LoopVectorize/RISCV/dead-ops-cost.ll
M llvm/test/Transforms/LoopVectorize/RISCV/induction-costs.ll
M llvm/test/Transforms/LoopVectorize/RISCV/mask-index-type.ll
M llvm/test/Transforms/LoopVectorize/RISCV/masked_gather_scatter.ll
M llvm/test/Transforms/LoopVectorize/RISCV/pr87378-vpinstruction-or-drop-poison-generating-flags.ll
M llvm/test/Transforms/LoopVectorize/RISCV/strided-accesses.ll
M llvm/test/Transforms/LoopVectorize/RISCV/uniform-load-store.ll
M llvm/test/Transforms/LoopVectorize/RISCV/vectorize-force-tail-with-evl-cond-reduction.ll
M llvm/test/Transforms/LoopVectorize/RISCV/vectorize-force-tail-with-evl-interleave.ll
M llvm/test/Transforms/LoopVectorize/outer_loop_scalable.ll
Log Message:
-----------
[VPlan] Omit zero add in VPWidenIntOrFpInductionRecipe (#119668)
I'm not sure if getStepVector was used for other things in the past
where StartIdx was non-zero, but nowadays VPWidenIntOrFpInductionRecipe
is the only user of it, and just passes zero to it. I presume
InstCombine was already catching this so hopefully removing this won't
affect codegen.
Commit: 9571d2023bee35f7c0e60a931ce5a4074d034635
https://github.com/llvm/llvm-project/commit/9571d2023bee35f7c0e60a931ce5a4074d034635
Author: Pengcheng Wang <wangpengcheng.pp at bytedance.com>
Date: 2024-12-16 (Mon, 16 Dec 2024)
Changed paths:
M llvm/lib/Target/RISCV/RISCVProcessors.td
M llvm/lib/Target/RISCV/RISCVSubtarget.cpp
M llvm/lib/Target/RISCV/RISCVSubtarget.h
Log Message:
-----------
[RISCV] Add tune info for postra scheduling direction (#115864)
The results differ on different platforms so it is really hard to
determine a common default value.
Tune info for postra scheduling direction is added and CPUs can
set their own preferable postra scheduling direction.
Commit: de1a423c2356d2040cab74e657ed024bf9ce8517
https://github.com/llvm/llvm-project/commit/de1a423c2356d2040cab74e657ed024bf9ce8517
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-12-15 (Sun, 15 Dec 2024)
Changed paths:
M llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
M llvm/test/CodeGen/AArch64/GlobalISel/legalize-threeway-cmp.mir
M llvm/test/CodeGen/AArch64/scmp.ll
M llvm/test/CodeGen/AArch64/ucmp.ll
M llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-threeway-cmp-rv32.mir
M llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-threeway-cmp-rv64.mir
M llvm/test/CodeGen/RISCV/GlobalISel/scmp.ll
M llvm/test/CodeGen/RISCV/GlobalISel/ucmp.ll
Log Message:
-----------
[GISel][RISCV][AArch64] Support legalizing G_SCMP/G_UCMP to sub(isgt,islt). (#119265)
Convert the LLT to EVT and call
TargetLowering::shouldExpandCmpUsingSelects to determine if we should do
this.
We don't have a getSetccResultType, so I'm boolean extending the
compares to the result type and using that. If the compares legalize to
the same type, these extends will get removed. Unfortunately, if the
compares legalize to a different type, we end up with truncates or
extends that might not be optimally placed.
Commit: e4fb30205f1df5156328b234ff2a2866b7035fef
https://github.com/llvm/llvm-project/commit/e4fb30205f1df5156328b234ff2a2866b7035fef
Author: hev <wangrui at loongson.cn>
Date: 2024-12-16 (Mon, 16 Dec 2024)
Changed paths:
M llvm/lib/Target/LoongArch/LoongArchOptWInstrs.cpp
M llvm/test/CodeGen/LoongArch/sextw-removal.ll
Log Message:
-----------
[LoongArch] Adds support for vectors in OptWInstrs (#118935)
Commit: f420d26e9dd7ff6aed435f86e7d6768501a29741
https://github.com/llvm/llvm-project/commit/f420d26e9dd7ff6aed435f86e7d6768501a29741
Author: Lang Hames <lhames at gmail.com>
Date: 2024-12-16 (Mon, 16 Dec 2024)
Changed paths:
M llvm/include/llvm/ExecutionEngine/Orc/ObjectLinkingLayer.h
M llvm/lib/ExecutionEngine/Orc/ObjectLinkingLayer.cpp
Log Message:
-----------
[ORC] Make ObjectLinkingLayerJITLinkContext a private nested class.
This class is an implementation detail, so doesn't need a publicly accessible
name.
Commit: 9ba7e2da009d7128c81e16f5a8e60c9abcb0e83d
https://github.com/llvm/llvm-project/commit/9ba7e2da009d7128c81e16f5a8e60c9abcb0e83d
Author: David Green <david.green at arm.com>
Date: 2024-12-16 (Mon, 16 Dec 2024)
Changed paths:
M llvm/include/llvm/CodeGen/GlobalISel/LegalizationArtifactCombiner.h
M llvm/test/CodeGen/AArch64/GlobalISel/legalize-ext.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-and.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-merge-values.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-or.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-phi.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-shuffle-vector.s16.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-xor.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-zext.mir
Log Message:
-----------
[GlobalISel] Use replaceRegOrBuildCopy when legalizer-combining s/zext(undef) (#119850)
Similar to #119721, this helps remove some of the COPYs created by the
CSE builder.
Commit: b446c208a5f0e2ad7193cc23e70642d207db4d13
https://github.com/llvm/llvm-project/commit/b446c208a5f0e2ad7193cc23e70642d207db4d13
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2024-12-16 (Mon, 16 Dec 2024)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPULibCalls.cpp
M llvm/lib/Target/AMDGPU/AMDGPULibFunc.cpp
M llvm/lib/Target/AMDGPU/AMDGPULibFunc.h
A llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-image-function-signatures.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-ldexp.ll
Log Message:
-----------
AMDGPU: Verify function type matches when matching libcalls (#119043)
Previously this would recognize a call to a mangled ldexp(float, float)
as a candidate to replace with the intrinsic. We need to verify the second
parameter is in fact an integer.
Fixes: SWDEV-501389
Commit: 1100d6a995fe392b3885b8d2bd5afed2bd57e80c
https://github.com/llvm/llvm-project/commit/1100d6a995fe392b3885b8d2bd5afed2bd57e80c
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2024-12-16 (Mon, 16 Dec 2024)
Changed paths:
M clang/test/CodeGenOpenCL/opencl_types.cl
M llvm/lib/Target/AMDGPU/AMDGPULibFunc.cpp
M llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-image-function-signatures.ll
Log Message:
-----------
AMDGPU: Fix libcall recognition of image array types (#119832)
Add tests with get_image_width as a sample for all of the non-extension
image types. The transform doesn't do anything, but this runs through
all the mangled libfunc parsing and shows it does not crash. It would
probably be smarter to check for exact match of the types, rather than
checking the prefix.
Commit: 6dc24f6a2fcf0a199e007dc127ca5a4901a3a24e
https://github.com/llvm/llvm-project/commit/6dc24f6a2fcf0a199e007dc127ca5a4901a3a24e
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-12-15 (Sun, 15 Dec 2024)
Changed paths:
M llvm/lib/CodeGen/MachineVerifier.cpp
M llvm/test/MachineVerifier/test_uscmp.mir
Log Message:
-----------
[GISel] Improve MachineVerifier for G_SCMP/UCMP. (#120017)
-Ensure destination type is at least 2 bits.
-Remove unnecessary check that both sources are the same type. The
verifier already handles this generically.
Commit: 8476ba71f20a6c260c8b55822ce02db45f8252be
https://github.com/llvm/llvm-project/commit/8476ba71f20a6c260c8b55822ce02db45f8252be
Author: Kazu Hirata <kazu at google.com>
Date: 2024-12-15 (Sun, 15 Dec 2024)
Changed paths:
M llvm/test/Transforms/PGOProfile/memprof_match_hot_cold_new_calls.ll
Log Message:
-----------
[memprof] YAMLify one test (NFC) (#119955)
This patch replaces the raw binary profile with a YAML profile.
I've trimmed the profile by removing all MemProfRecords except the one
for _Z3foov.
This patch demonstrates that we can see !memprof generated even with a
YAML profile.
Commit: 62cd735db36c1ba41ba627c8336dfa643ff703af
https://github.com/llvm/llvm-project/commit/62cd735db36c1ba41ba627c8336dfa643ff703af
Author: Yuhao Gu <49391101+yhgu2000 at users.noreply.github.com>
Date: 2024-12-16 (Mon, 16 Dec 2024)
Changed paths:
Log Message:
-----------
[docs] remove some out-of-date content in LLVM Programmer's Manual. (#119565)
Remove the part about implicit conversion from an iterator to a pointer.
This part of the manual was written 14 years ago, in:
https://github.com/llvm/llvm-project/commit/37027c30ec526afe3bb571df6f8701bf0d322f22
There do exist a type casting operator in `ilist` then:
https://github.com/llvm/llvm-project/blob/37027c30ec526afe3bb571df6f8701bf0d322f22/llvm/include/llvm/ADT/ilist.h#L192-L194
But it has been remove since 2016:
https://github.com/llvm/llvm-project/commit/f197b1f78f854d8513ef617b8cfc61860f7b4b84
So I think it makes sense to remove this part to avoid mislead new
contributors.
Commit: 115872902b9b056d42e24273f93a2be7c93d2f54
https://github.com/llvm/llvm-project/commit/115872902b9b056d42e24273f93a2be7c93d2f54
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-12-15 (Sun, 15 Dec 2024)
Changed paths:
M llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
M llvm/test/CodeGen/RISCV/GlobalISel/double-arith.ll
M llvm/test/CodeGen/RISCV/GlobalISel/double-convert.ll
M llvm/test/CodeGen/RISCV/GlobalISel/double-fcmp.ll
M llvm/test/CodeGen/RISCV/GlobalISel/float-arith.ll
M llvm/test/CodeGen/RISCV/GlobalISel/float-convert.ll
M llvm/test/CodeGen/RISCV/GlobalISel/float-fcmp.ll
M llvm/test/CodeGen/RISCV/GlobalISel/float-intrinsics.ll
M llvm/test/CodeGen/RISCV/GlobalISel/fp128.ll
M llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-addo-subo-rv64.mir
M llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-icmp-rv64.mir
M llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-sat-rv64.mir
M llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-umax-rv64.mir
M llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-umin-rv64.mir
M llvm/test/CodeGen/RISCV/GlobalISel/rv64zbb.ll
M llvm/test/CodeGen/RISCV/GlobalISel/ucmp.ll
Log Message:
-----------
[GISel][RISCV] Use isSExtCheaperThanZExt when widening G_ICMP. (#120032)
Sign extending i32->i64 is more efficient than zero extend for RV64.
Commit: 54dac27c57d05d3f5c33bd4ec878bcb0a9c7cb71
https://github.com/llvm/llvm-project/commit/54dac27c57d05d3f5c33bd4ec878bcb0a9c7cb71
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-12-15 (Sun, 15 Dec 2024)
Changed paths:
M llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
M llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-umax-rv64.mir
M llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-umin-rv64.mir
M llvm/test/CodeGen/RISCV/GlobalISel/rv64zbb.ll
Log Message:
-----------
[GISel][RISCV] Use isSExtCheaperThanZExt when widening G_UMAX/G_UMIN. (#120041)
Similar to what we do for unsigned comparisons after #120032.
Commit: f65a21a4ecc2e712c700c59842b6b9a1d2a9a060
https://github.com/llvm/llvm-project/commit/f65a21a4ecc2e712c700c59842b6b9a1d2a9a060
Author: Daniil Kovalev <dkovalev at accesssoftek.com>
Date: 2024-12-16 (Mon, 16 Dec 2024)
Changed paths:
M clang/lib/CodeGen/CodeGenModule.cpp
M clang/test/CodeGen/ptrauth-module-flags.c
M llvm/include/llvm/CodeGen/MachineModuleInfoImpls.h
M llvm/include/llvm/CodeGen/TargetLoweringObjectFileImpl.h
M llvm/include/llvm/Target/TargetLoweringObjectFile.h
M llvm/lib/CodeGen/AsmPrinter/DwarfCFIException.cpp
M llvm/lib/CodeGen/MachineModuleInfoImpls.cpp
M llvm/lib/CodeGen/TargetLoweringObjectFileImpl.cpp
M llvm/lib/Target/AArch64/AArch64TargetObjectFile.cpp
M llvm/lib/Target/AArch64/AArch64TargetObjectFile.h
M llvm/lib/Target/AArch64/MCTargetDesc/AArch64TargetStreamer.cpp
M llvm/lib/Target/AArch64/MCTargetDesc/AArch64TargetStreamer.h
M llvm/lib/Target/TargetLoweringObjectFile.cpp
A llvm/test/CodeGen/AArch64/ptrauth-sign-personality.ll
Log Message:
-----------
[PAC][ELF][AArch64] Support signed personality function pointer (#119361)
Re-apply #113148 after revert in #119331
If function pointer signing is enabled, sign personality function
pointer stored in `.DW.ref.__gxx_personality_v0` section with IA key,
0x7EAD = `ptrauth_string_discriminator("personality")` constant
discriminator and address diversity enabled.
Commit: a3db5910b434d746c9c0585a092100ff7abcd1a0
https://github.com/llvm/llvm-project/commit/a3db5910b434d746c9c0585a092100ff7abcd1a0
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2024-12-16 (Mon, 16 Dec 2024)
Changed paths:
M llvm/lib/CodeGen/RegAllocBase.cpp
Log Message:
-----------
RegAllocBase: Avoid using temporary DiagnosticInfo (#120046)
Commit: 003fb2aeb49dc7440cab7e009bd264f8f42fc8dc
https://github.com/llvm/llvm-project/commit/003fb2aeb49dc7440cab7e009bd264f8f42fc8dc
Author: Yingwei Zheng <dtcxzyw2333 at gmail.com>
Date: 2024-12-16 (Mon, 16 Dec 2024)
Changed paths:
M llvm/lib/Transforms/Scalar/ConstraintElimination.cpp
A llvm/test/Transforms/ConstraintElimination/sub-nsw.ll
Log Message:
-----------
[ConstraintElim] Decompose `sub nsw` (#118219)
Closes https://github.com/llvm/llvm-project/issues/118211.
Commit: b4c1f0cc492f1597397dcf0b06b816fa0a2135f1
https://github.com/llvm/llvm-project/commit/b4c1f0cc492f1597397dcf0b06b816fa0a2135f1
Author: David Spickett <david.spickett at linaro.org>
Date: 2024-12-16 (Mon, 16 Dec 2024)
Changed paths:
M lldb/test/API/CMakeLists.txt
Log Message:
-----------
[lldb][test] Prefer gmake to make and warn for potentially non-GNU make (#119573)
System make on FreeBSD is missing some GNU make features so out of the
box you get a lot of:
```
make: "<...>/Makefile.rules" line 569: Invalid line type
```
To solve this, you can install gmake which is a port of GNU make.
However because we prefer 'make', gmake won't be used unless you set
LLDB_TEST_MAKE.
To fix that, prefer 'gmake'. Also check (as best we can) that the make
we found is GNU make. This won't be perfect but it's better than the
cryptic error shown above.
```
-- Found make: /usr/bin/make
CMake Warning at /home/ec2-user/llvm-project/lldb/test/API/CMakeLists.txt:63 (message):
'make' tool /usr/bin/make may not be GNU make compatible. Some tests may
fail to build. Provide a GNU compatible 'make' tool by setting
LLDB_TEST_MAKE.
```
When a make isn't found at all, the warning message will show the names
we tried:
```
-- Did not find one of: gmake make
CMake Warning at /home/ec2-user/llvm-project/lldb/test/API/CMakeLists.txt:69 (message):
Many LLDB API tests require a 'make' tool. Please provide it in Path or
pass via LLDB_TEST_MAKE.
```
Commit: a35db2880a488b62a16f269972ad885fd58033f7
https://github.com/llvm/llvm-project/commit/a35db2880a488b62a16f269972ad885fd58033f7
Author: David Green <david.green at arm.com>
Date: 2024-12-16 (Mon, 16 Dec 2024)
Changed paths:
M llvm/include/llvm/CodeGen/GlobalISel/GIMatchTableExecutorImpl.h
M llvm/include/llvm/CodeGen/GlobalISel/LegalizationArtifactCombiner.h
M llvm/lib/CodeGen/BranchFolding.cpp
M llvm/lib/CodeGen/GlobalISel/CSEInfo.cpp
M llvm/lib/CodeGen/MIRCanonicalizerPass.cpp
M llvm/lib/CodeGen/MachineCombiner.cpp
M llvm/lib/CodeGen/MachineLateInstrsCleanup.cpp
M llvm/lib/CodeGen/MachineOutliner.cpp
M llvm/lib/CodeGen/MachinePipeliner.cpp
M llvm/lib/CodeGen/ModuloSchedule.cpp
M llvm/lib/CodeGen/ScheduleDAGInstrs.cpp
M llvm/lib/CodeGen/SelectionDAG/FastISel.cpp
M llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
M llvm/lib/Target/AArch64/AArch64PBQPRegAlloc.cpp
M llvm/lib/Target/ARM/ARMISelLowering.cpp
M llvm/lib/Target/ARM/Thumb2ITBlockPass.cpp
Log Message:
-----------
[NFC] Remove some unnecessary semicolons
All inside LLVM_DEBUG, some of which have been cleaned up by adding block
scopes to allow them to format more nicely.
Commit: a24645463bd8a758005f4e5fdcd78971f87e3ba1
https://github.com/llvm/llvm-project/commit/a24645463bd8a758005f4e5fdcd78971f87e3ba1
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2024-12-16 (Mon, 16 Dec 2024)
Changed paths:
M .ci/monolithic-linux.sh
M .ci/monolithic-windows.sh
Log Message:
-----------
[CI] Only upload test results if buildkite-agent is present (#119954)
This patch modifies the monolithic shell scrips to only run if the
buildkite-agent application is present. This allows for running the
scripts to completion outside of buildkite (eg inside of a GHA
pipeline).
Commit: 2503a6659621e27e6b4c5946c3acff7a5b9dadca
https://github.com/llvm/llvm-project/commit/2503a6659621e27e6b4c5946c3acff7a5b9dadca
Author: Timm Bäder <tbaeder at redhat.com>
Date: 2024-12-16 (Mon, 16 Dec 2024)
Changed paths:
M clang/lib/AST/ByteCode/Integral.h
M clang/lib/AST/ByteCode/Interp.h
M clang/test/AST/ByteCode/shifts.cpp
Log Message:
-----------
Reapply "[clang][bytecode] Fix some shift edge cases (#119895)"
This reverts commit a6636ce4d124176856c3913d4bf6c3ceff1f5a1f.
This original commit failed on hosts with signed wchar_t. Care for
this in the test.
Commit: 92a4f4dda5796049b6dbeb5ed89384380bff97d9
https://github.com/llvm/llvm-project/commit/92a4f4dda5796049b6dbeb5ed89384380bff97d9
Author: Vadim D. <vvd170501 at gmail.com>
Date: 2024-12-16 (Mon, 16 Dec 2024)
Changed paths:
M clang/lib/Tooling/Inclusions/Stdlib/StdSpecialSymbolMap.inc
M clang/lib/Tooling/Inclusions/Stdlib/StdSymbolMap.inc
Log Message:
-----------
[Tooling/Inclusion] Update std symbol mapping (#118174)
This adds new symbols to the generated mapping and removes special
mappings for missing symbols introduced in #113612, as these symbols are
now included in the generated mapping.
Commit: e0fb3acd8a0b2a9340b9b2ae370c84c98f1a5cc2
https://github.com/llvm/llvm-project/commit/e0fb3acd8a0b2a9340b9b2ae370c84c98f1a5cc2
Author: Sander de Smalen <sander.desmalen at arm.com>
Date: 2024-12-16 (Mon, 16 Dec 2024)
Changed paths:
M compiler-rt/lib/builtins/aarch64/sme-abi.S
M compiler-rt/lib/builtins/aarch64/sme-libc-mem-routines.S
Log Message:
-----------
[compiler-rt][AArch64] Allow platform-specific mangling of SME routines. (#119864)
Support platform-specific mangling to avoid the compiler emitting a call
to a function that is mangled differently than the definition in the
runtime library.
Commit: ace87ec04cd588e5fbe393c3b642bd759a7abadb
https://github.com/llvm/llvm-project/commit/ace87ec04cd588e5fbe393c3b642bd759a7abadb
Author: Juan Manuel Martinez Caamaño <jmartinezcaamao at gmail.com>
Date: 2024-12-16 (Mon, 16 Dec 2024)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
M llvm/test/CodeGen/AMDGPU/gfx12_scalar_subword_loads.ll
Log Message:
-----------
[AMDGPU][AMDGPURegBankInfo] Map S_BUFFER_LOAD_XXX to its corresponding BUFFER_LOAD_XXX (#117574)
In one test code generation diverged between GISEL and DAG
For example, this intrinsic
> %ld = call i8 @llvm.amdgcn.s.buffer.load.u8(<4 x i32> %src, i32
%offset, i32 0)
would be lowered into these two cases:
* `buffer_load_u8 v2, v2, s[0:3], null offen`
* `buffer_load_b32 v2, v2, s[0:3], null offen`
This patch fixes this issue.
Commit: 978de2d6664a74864471d62244700c216fdc6741
https://github.com/llvm/llvm-project/commit/978de2d6664a74864471d62244700c216fdc6741
Author: Vyacheslav Levytskyy <vyacheslav.levytskyy at intel.com>
Date: 2024-12-16 (Mon, 16 Dec 2024)
Changed paths:
M llvm/docs/SPIRVUsage.rst
M llvm/lib/Target/SPIRV/MCTargetDesc/SPIRVMCCodeEmitter.cpp
M llvm/lib/Target/SPIRV/SPIRVBuiltins.cpp
M llvm/lib/Target/SPIRV/SPIRVBuiltins.h
M llvm/lib/Target/SPIRV/SPIRVCommandLine.cpp
M llvm/lib/Target/SPIRV/SPIRVEmitIntrinsics.cpp
M llvm/lib/Target/SPIRV/SPIRVGlobalRegistry.cpp
M llvm/lib/Target/SPIRV/SPIRVInstrInfo.td
M llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
M llvm/lib/Target/SPIRV/SPIRVLegalizerInfo.cpp
M llvm/lib/Target/SPIRV/SPIRVModuleAnalysis.cpp
M llvm/lib/Target/SPIRV/SPIRVPostLegalizer.cpp
M llvm/lib/Target/SPIRV/SPIRVPreLegalizer.cpp
M llvm/lib/Target/SPIRV/SPIRVSymbolicOperands.td
A llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_float_controls2/exec_mode_float_control_empty.ll
A llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_float_controls2/exec_mode_float_control_intel.ll
M llvm/test/CodeGen/SPIRV/instructions/integer-casts.ll
A llvm/test/CodeGen/SPIRV/llvm-intrinsics/constrained-arithmetic.ll
Log Message:
-----------
[SPIR-V] Add saturation and float rounding mode decorations, a subset of arithmetic constrained floating-point intrinsics, and SPV_INTEL_float_controls2 extension (#119862)
This PR adds the following features:
* saturation and float rounding mode decorations,
* arithmetic constrained floating-point intrinsics (strict_fadd,
strict_fsub, strict_fmul, strict_fdiv, strict_frem, strict_fma and
strict_fldexp),
* and SPV_INTEL_float_controls2 extension,
* using recent improvements of emit-intrinsics step, this PR also
simplifies pre- and post-legalizer steps and improves instruction
selection.
Commit: 95e509a98993e84ef987accb2ed7109c3810281e
https://github.com/llvm/llvm-project/commit/95e509a98993e84ef987accb2ed7109c3810281e
Author: Florian Hahn <flo at fhahn.com>
Date: 2024-12-16 (Mon, 16 Dec 2024)
Changed paths:
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
M llvm/lib/Transforms/Vectorize/VPlan.cpp
M llvm/lib/Transforms/Vectorize/VPlan.h
M llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
M llvm/test/Transforms/LoopVectorize/vplan-printing.ll
Log Message:
-----------
[VPlan] Add VPWidenInduction recipe as common base class (NFC). (#120008)
This helps to simplify some existing code and new code
(https://github.com/llvm/llvm-project/pull/112145)
PR: https://github.com/llvm/llvm-project/pull/120008
Commit: aff3e68d6f10dd3087c29a09865683b9d35a362e
https://github.com/llvm/llvm-project/commit/aff3e68d6f10dd3087c29a09865683b9d35a362e
Author: Shao-Ce SUN <sunshaoce at outlook.com>
Date: 2024-12-16 (Mon, 16 Dec 2024)
Changed paths:
M llvm/lib/MC/TargetRegistry.cpp
M llvm/test/tools/llc/invalid-target.ll
M llvm/tools/llc/llc.cpp
Log Message:
-----------
[LLVM][tools] Remove unnecessary newline from error message (#120037)
The previous missing a newline:
```shell
$ llc --mattr=help
llc: error: unable to get target for 'unknown', see --version and --triple.$
```
Commit: 3b17d041dd775e033cca499f2a25548c8c22bb86
https://github.com/llvm/llvm-project/commit/3b17d041dd775e033cca499f2a25548c8c22bb86
Author: Benjamin Maxwell <benjamin.maxwell at arm.com>
Date: 2024-12-16 (Mon, 16 Dec 2024)
Changed paths:
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
A llvm/test/CodeGen/AArch64/sve-load-store-strict-align.ll
A llvm/test/CodeGen/AArch64/sve-unaligned-load-store-strict-align.ll
Log Message:
-----------
[AArch64][SVE] Don't require 16-byte aligned SVE loads/stores with +strict-align (#119732)
Instead, allow any alignment >= the element size (in bytes). This is all
that is needed for (predicated) vector loads even if unaligned accesses
are disabled.
See:
https://developer.arm.com/documentation/ddi0602/2024-09/Shared-Pseudocode/aarch64-functions-memory?lang=en#impl-aarch64.Mem.read.3
Specifically:
```
// Check alignment on size of element accessed, not overall access size.
constant integer alignment = if accdesc.ispair then size DIV 2 else size;
```
The `size` passed to `Mem` by SVE load/store instructions is the element
size.
Commit: 9455ea740d8ef91f73e0c7d4e1fc04a705d37ad8
https://github.com/llvm/llvm-project/commit/9455ea740d8ef91f73e0c7d4e1fc04a705d37ad8
Author: Dmitry Chestnykh <dm.chestnykh at gmail.com>
Date: 2024-12-16 (Mon, 16 Dec 2024)
Changed paths:
M llvm/lib/Target/ARM/ARMInstrInfo.td
M llvm/lib/Target/ARM/ARMInstrThumb2.td
A llvm/test/MC/ARM/idiv-2op.s
M llvm/test/MC/ARM/idiv.s
Log Message:
-----------
[ARM][Thumb2] Allow 2-operand variants of `[us]div` (#119976)
Fixes #119963
Commit: e31c70d9fa9ba4e61ecf0b34fbc6da2785e60eb6
https://github.com/llvm/llvm-project/commit/e31c70d9fa9ba4e61ecf0b34fbc6da2785e60eb6
Author: Oliver Stannard <oliver.stannard at arm.com>
Date: 2024-12-16 (Mon, 16 Dec 2024)
Changed paths:
M llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
Log Message:
-----------
[AArch64] Add immediate range checks for more MTE instructions (#119216)
This would have turned the bug fixed in #117146 from a miscompilation
into an assertion failure.
Commit: 0dbdc23e78ac1f34a5b563f2db73f9ca64714fac
https://github.com/llvm/llvm-project/commit/0dbdc23e78ac1f34a5b563f2db73f9ca64714fac
Author: Pavel Labath <pavel at labath.sk>
Date: 2024-12-16 (Mon, 16 Dec 2024)
Changed paths:
M lldb/include/lldb/Core/Progress.h
M lldb/source/Core/Progress.cpp
M lldb/source/Plugins/SymbolFile/DWARF/ManualDWARFIndex.cpp
M lldb/unittests/Core/ProgressReportTest.cpp
Log Message:
-----------
[lldb] Add ability to rate-limit progress reports (#119377)
For high-frequency multithreaded progress reports, the contention of
taking the progress mutex and the overhead of generating event can
significantly slow down the operation whose progress we are reporting.
This patch adds an (optional) capability to rate-limit them. It's
optional because this approach has one drawback: if the progress
reporting has a pattern where it generates a burst of activity and then
blocks (without reporting anything) for a large amount of time, it can
appear as if less progress was made that it actually was (because we
only reported the first event from the burst and dropped the other
ones).
I've also made a small refactor of the Progress class to better
distinguish between const (don't need protection), atomic (are used on
the hot path) and other (need mutex protection) members.
Commit: 360f0a6a89ea721f2c29321fb0e116809b1568d8
https://github.com/llvm/llvm-project/commit/360f0a6a89ea721f2c29321fb0e116809b1568d8
Author: Florian Mayer <fmayer at google.com>
Date: 2024-12-16 (Mon, 16 Dec 2024)
Changed paths:
A .ci/compute-projects.sh
M .ci/generate-buildkite-pipeline-premerge
M .ci/monolithic-linux.sh
M .ci/monolithic-windows.sh
M .git-blame-ignore-revs
A .github/workflows/build-ci-container-windows.yml
M .github/workflows/build-ci-container.yml
A .github/workflows/containers/github-action-ci-windows/Dockerfile
M .github/workflows/containers/github-action-ci/Dockerfile
M .github/workflows/docs.yml
A bolt/docs/BinaryAnalysis.md
M bolt/include/bolt/Core/DIEBuilder.h
M bolt/include/bolt/Core/DebugNames.h
M bolt/include/bolt/Rewrite/RewriteInstance.h
M bolt/include/bolt/Utils/CommandLineOpts.h
M bolt/lib/Core/BinaryEmitter.cpp
M bolt/lib/Core/DIEBuilder.cpp
M bolt/lib/Core/DebugNames.cpp
M bolt/lib/Rewrite/RewriteInstance.cpp
M bolt/lib/Utils/CommandLineOpts.cpp
M bolt/test/CMakeLists.txt
A bolt/test/X86/dwarf5-debug-names-abstract-origin-linkage-name-only.s
A bolt/test/X86/dwarf5-debug-names-abstract-origin-specification.s
A bolt/test/X86/dwarf5-debug-names-gnu-push-tls-address.s
M bolt/test/X86/linux-static-keys.s
A bolt/test/binary-analysis/AArch64/Inputs/dummy.txt
A bolt/test/binary-analysis/AArch64/cmdline-args.test
A bolt/test/binary-analysis/AArch64/lit.local.cfg
M bolt/test/lit.cfg.py
A bolt/test/merge-fdata-bat-no-lbr.test
A bolt/test/merge-fdata-lbr-mode.test
A bolt/test/merge-fdata-mixed-bat-no-lbr.test
A bolt/test/merge-fdata-mixed-mode.test
A bolt/test/merge-fdata-no-lbr-mode.test
M bolt/test/unreadable-profile.test
M bolt/tools/CMakeLists.txt
A bolt/tools/binary-analysis/CMakeLists.txt
A bolt/tools/binary-analysis/binary-analysis.cpp
M bolt/tools/merge-fdata/merge-fdata.cpp
M clang-tools-extra/clang-doc/MDGenerator.cpp
M clang-tools-extra/clang-tidy/bugprone/OptionalValueConversionCheck.cpp
M clang-tools-extra/clang-tidy/bugprone/UncheckedOptionalAccessCheck.h
M clang-tools-extra/clang-tidy/cppcoreguidelines/ProTypeMemberInitCheck.cpp
M clang-tools-extra/clang-tidy/cppcoreguidelines/RvalueReferenceParamNotMovedCheck.cpp
M clang-tools-extra/clang-tidy/modernize/CMakeLists.txt
M clang-tools-extra/clang-tidy/modernize/ModernizeTidyModule.cpp
A clang-tools-extra/clang-tidy/modernize/UseIntegerSignComparisonCheck.cpp
A clang-tools-extra/clang-tidy/modernize/UseIntegerSignComparisonCheck.h
M clang-tools-extra/clang-tidy/performance/InefficientVectorOperationCheck.cpp
M clang-tools-extra/clang-tidy/readability/RedundantAccessSpecifiersCheck.h
M clang-tools-extra/clang-tidy/readability/RedundantCastingCheck.cpp
M clang-tools-extra/clang-tidy/utils/RenamerClangTidyCheck.cpp
M clang-tools-extra/clangd/CompileCommands.cpp
M clang-tools-extra/clangd/index/SymbolCollector.cpp
M clang-tools-extra/clangd/unittests/SymbolCollectorTests.cpp
M clang-tools-extra/docs/ReleaseNotes.rst
R clang-tools-extra/docs/clang-tidy/checks/clang-analyzer/cplusplus.PureVirtualCall.rst
A clang-tools-extra/docs/clang-tidy/checks/clang-analyzer/cplusplus.SelfAssignment.rst
R clang-tools-extra/docs/clang-tidy/checks/clang-analyzer/optin.osx.OSObjectCStyleCast.rst
R clang-tools-extra/docs/clang-tidy/checks/clang-analyzer/osx.MIG.rst
R clang-tools-extra/docs/clang-tidy/checks/clang-analyzer/osx.OSObjectRetainCount.rst
M clang-tools-extra/docs/clang-tidy/checks/clang-analyzer/security.PutenvStackArray.rst
M clang-tools-extra/docs/clang-tidy/checks/clang-analyzer/security.SetgidSetuidOrder.rst
R clang-tools-extra/docs/clang-tidy/checks/clang-analyzer/valist.CopyToSelf.rst
R clang-tools-extra/docs/clang-tidy/checks/clang-analyzer/valist.Uninitialized.rst
R clang-tools-extra/docs/clang-tidy/checks/clang-analyzer/valist.Unterminated.rst
M clang-tools-extra/docs/clang-tidy/checks/list.rst
M clang-tools-extra/docs/clang-tidy/checks/misc/unused-parameters.rst
A clang-tools-extra/docs/clang-tidy/checks/modernize/use-integer-sign-comparison.rst
M clang-tools-extra/docs/clang-tidy/index.rst
M clang-tools-extra/test/clang-doc/templates.cpp
A clang-tools-extra/test/clang-tidy/checkers/bugprone/optional-value-conversion-construct-from-std.cpp
A clang-tools-extra/test/clang-tidy/checkers/modernize/use-integer-sign-comparison.cpp
M clang/docs/LanguageExtensions.rst
M clang/docs/ReleaseNotes.rst
M clang/docs/tools/dump_format_help.py
M clang/docs/tools/dump_format_style.py
M clang/include/clang-c/CXString.h
M clang/include/clang-c/Index.h
M clang/include/clang/AST/APValue.h
M clang/include/clang/AST/Attr.h
M clang/include/clang/AST/Decl.h
M clang/include/clang/AST/DeclBase.h
M clang/include/clang/AST/DeclCXX.h
M clang/include/clang/AST/DeclContextInternals.h
M clang/include/clang/AST/DeclTemplate.h
M clang/include/clang/AST/ExprCXX.h
M clang/include/clang/AST/ExprConcepts.h
M clang/include/clang/AST/ExprObjC.h
M clang/include/clang/AST/ExternalASTSource.h
M clang/include/clang/AST/OpenACCClause.h
M clang/include/clang/AST/RecursiveASTVisitor.h
M clang/include/clang/AST/Redeclarable.h
M clang/include/clang/AST/StmtOpenACC.h
M clang/include/clang/AST/TemplateBase.h
M clang/include/clang/AST/TextNodeDumper.h
M clang/include/clang/AST/Type.h
M clang/include/clang/Basic/Builtins.h
M clang/include/clang/Basic/BuiltinsPPC.def
M clang/include/clang/Basic/DiagnosticParseKinds.td
M clang/include/clang/Basic/DiagnosticSemaKinds.td
M clang/include/clang/Basic/FileEntry.h
M clang/include/clang/Basic/IdentifierTable.h
M clang/include/clang/Basic/OpenACCClauses.def
M clang/include/clang/Basic/OpenACCKinds.h
M clang/include/clang/Basic/StmtNodes.td
M clang/include/clang/Basic/TargetInfo.h
M clang/include/clang/Basic/arm_sme.td
M clang/include/clang/Basic/arm_sve.td
M clang/include/clang/Basic/arm_sve_sme_incl.td
M clang/include/clang/Lex/PreprocessingRecord.h
M clang/include/clang/Lex/Preprocessor.h
M clang/include/clang/Sema/ParsedAttr.h
M clang/include/clang/Sema/SemaConcept.h
M clang/include/clang/Sema/SemaInternal.h
M clang/include/clang/Sema/SemaOpenACC.h
M clang/include/clang/Sema/Template.h
M clang/include/clang/Serialization/ASTBitCodes.h
M clang/include/clang/StaticAnalyzer/Core/AnalyzerOptions.def
M clang/include/module.modulemap
M clang/lib/APINotes/APINotesManager.cpp
M clang/lib/AST/ByteCode/BitcastBuffer.h
M clang/lib/AST/ByteCode/Integral.h
M clang/lib/AST/ByteCode/Interp.h
M clang/lib/AST/ByteCode/InterpBuiltin.cpp
M clang/lib/AST/ByteCode/InterpBuiltinBitCast.cpp
M clang/lib/AST/ByteCode/InterpBuiltinBitCast.h
M clang/lib/AST/OpenACCClause.cpp
M clang/lib/AST/StmtOpenACC.cpp
M clang/lib/AST/StmtPrinter.cpp
M clang/lib/AST/StmtProfile.cpp
M clang/lib/AST/TextNodeDumper.cpp
M clang/lib/Analysis/PathDiagnostic.cpp
M clang/lib/Analysis/ThreadSafetyCommon.cpp
M clang/lib/Analysis/UnsafeBufferUsage.cpp
M clang/lib/Basic/Builtins.cpp
M clang/lib/Basic/FileManager.cpp
M clang/lib/Basic/SourceManager.cpp
M clang/lib/Basic/Targets.cpp
M clang/lib/Basic/Targets/AArch64.cpp
M clang/lib/Basic/Targets/AArch64.h
M clang/lib/Basic/Targets/AMDGPU.cpp
M clang/lib/Basic/Targets/AMDGPU.h
M clang/lib/Basic/Targets/ARC.h
M clang/lib/Basic/Targets/ARM.cpp
M clang/lib/Basic/Targets/ARM.h
M clang/lib/Basic/Targets/AVR.h
M clang/lib/Basic/Targets/BPF.cpp
M clang/lib/Basic/Targets/BPF.h
M clang/lib/Basic/Targets/CSKY.cpp
M clang/lib/Basic/Targets/CSKY.h
M clang/lib/Basic/Targets/DirectX.h
M clang/lib/Basic/Targets/Hexagon.cpp
M clang/lib/Basic/Targets/Hexagon.h
M clang/lib/Basic/Targets/Lanai.h
M clang/lib/Basic/Targets/LoongArch.cpp
M clang/lib/Basic/Targets/LoongArch.h
M clang/lib/Basic/Targets/M68k.cpp
M clang/lib/Basic/Targets/M68k.h
M clang/lib/Basic/Targets/MSP430.h
M clang/lib/Basic/Targets/Mips.cpp
M clang/lib/Basic/Targets/Mips.h
M clang/lib/Basic/Targets/NVPTX.cpp
M clang/lib/Basic/Targets/NVPTX.h
M clang/lib/Basic/Targets/OSTargets.h
M clang/lib/Basic/Targets/PNaCl.h
M clang/lib/Basic/Targets/PPC.cpp
M clang/lib/Basic/Targets/PPC.h
M clang/lib/Basic/Targets/RISCV.cpp
M clang/lib/Basic/Targets/RISCV.h
M clang/lib/Basic/Targets/SPIR.cpp
M clang/lib/Basic/Targets/SPIR.h
M clang/lib/Basic/Targets/Sparc.h
M clang/lib/Basic/Targets/SystemZ.cpp
M clang/lib/Basic/Targets/SystemZ.h
M clang/lib/Basic/Targets/TCE.h
M clang/lib/Basic/Targets/VE.cpp
M clang/lib/Basic/Targets/VE.h
M clang/lib/Basic/Targets/WebAssembly.cpp
M clang/lib/Basic/Targets/WebAssembly.h
M clang/lib/Basic/Targets/X86.cpp
M clang/lib/Basic/Targets/X86.h
M clang/lib/Basic/Targets/XCore.cpp
M clang/lib/Basic/Targets/XCore.h
M clang/lib/CodeGen/BackendUtil.cpp
M clang/lib/CodeGen/CGBuiltin.cpp
M clang/lib/CodeGen/CGOpenMPRuntime.cpp
M clang/lib/CodeGen/CGStmt.cpp
M clang/lib/CodeGen/CodeGenFunction.h
M clang/lib/CodeGen/CodeGenModule.cpp
M clang/lib/Driver/Driver.cpp
M clang/lib/Driver/DriverOptions.cpp
M clang/lib/Driver/SanitizerArgs.cpp
M clang/lib/Driver/ToolChains/Clang.cpp
M clang/lib/Driver/ToolChains/CommonArgs.cpp
M clang/lib/Driver/ToolChains/Darwin.cpp
M clang/lib/Driver/ToolChains/FreeBSD.cpp
M clang/lib/Driver/ToolChains/MSVC.cpp
M clang/lib/Frontend/CompilerInvocation.cpp
M clang/lib/Index/FileIndexRecord.cpp
M clang/lib/Index/IndexDecl.cpp
M clang/lib/Interpreter/Interpreter.cpp
M clang/lib/Parse/ParseExprCXX.cpp
M clang/lib/Parse/ParseOpenACC.cpp
M clang/lib/Parse/ParseOpenMP.cpp
M clang/lib/Sema/CheckExprLifetime.cpp
M clang/lib/Sema/DeclSpec.cpp
M clang/lib/Sema/SemaAttr.cpp
M clang/lib/Sema/SemaDeclCXX.cpp
M clang/lib/Sema/SemaExceptionSpec.cpp
M clang/lib/Sema/SemaOpenACC.cpp
M clang/lib/Sema/TreeTransform.h
M clang/lib/Serialization/ASTReader.cpp
M clang/lib/Serialization/ASTReaderStmt.cpp
M clang/lib/Serialization/ASTWriter.cpp
M clang/lib/Serialization/ASTWriterStmt.cpp
M clang/lib/StaticAnalyzer/Checkers/WebKit/ASTUtils.cpp
M clang/lib/StaticAnalyzer/Checkers/WebKit/ASTUtils.h
M clang/lib/StaticAnalyzer/Checkers/WebKit/RawPtrRefCallArgsChecker.cpp
M clang/lib/StaticAnalyzer/Checkers/WebKit/RawPtrRefLocalVarsChecker.cpp
M clang/lib/StaticAnalyzer/Checkers/WebKit/UncountedLambdaCapturesChecker.cpp
M clang/lib/StaticAnalyzer/Core/ExprEngine.cpp
M clang/lib/Tooling/Inclusions/Stdlib/StdSpecialSymbolMap.inc
M clang/lib/Tooling/Inclusions/Stdlib/StdSymbolMap.inc
M clang/test/AST/ByteCode/builtin-functions.cpp
M clang/test/AST/ByteCode/complex.cpp
M clang/test/AST/ByteCode/shifts.cpp
A clang/test/AST/ast-print-openacc-data-construct.cpp
M clang/test/Analysis/Checkers/WebKit/call-args-checked-const-member.cpp
M clang/test/Analysis/Checkers/WebKit/call-args-checked-ptr.cpp
M clang/test/Analysis/Checkers/WebKit/call-args-counted-const-member.cpp
M clang/test/Analysis/Checkers/WebKit/call-args.cpp
M clang/test/Analysis/Checkers/WebKit/local-vars-checked-const-member.cpp
M clang/test/Analysis/Checkers/WebKit/local-vars-counted-const-member.cpp
M clang/test/Analysis/Checkers/WebKit/mock-types.h
M clang/test/Analysis/Checkers/WebKit/uncounted-lambda-captures.cpp
M clang/test/Analysis/analyzer-config.c
M clang/test/CXX/dcl.decl/dcl.meaning/dcl.fct/p13.cpp
M clang/test/CodeGen/AArch64/cpu-supports.c
M clang/test/CodeGen/AArch64/fmv-dependencies.c
A clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_cvtn.c
A clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_fdot.c
A clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_fmla.c
M clang/test/CodeGen/AArch64/mixed-target-attributes.c
A clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_fp8_fdot.c
M clang/test/CodeGen/SystemZ/zos-mixed-ptr-sizes-malloc.c
M clang/test/CodeGen/attr-target-clones-aarch64.c
M clang/test/CodeGen/attr-target-version.c
M clang/test/CodeGen/ptrauth-module-flags.c
M clang/test/CodeGenCXX/attr-target-clones-aarch64.cpp
M clang/test/CodeGenCXX/attr-target-version.cpp
M clang/test/CodeGenCXX/ext-int.cpp
M clang/test/CodeGenCXX/fmv-namespace.cpp
M clang/test/CodeGenOpenCL/opencl_types.cl
M clang/test/Driver/config-file3.c
M clang/test/Driver/freebsd.c
M clang/test/Driver/fsanitize.c
M clang/test/Driver/fveclib.c
M clang/test/Driver/print-supported-extensions-riscv.c
M clang/test/Driver/riscv-cpus.c
M clang/test/Driver/sanitizer-ld.c
M clang/test/Driver/stack-clash-protection.c
M clang/test/Driver/sysroot.c
M clang/test/Format/docs_updated.test
R clang/test/Interpreter/crash.cpp
M clang/test/Misc/target-invalid-cpu-note/riscv.c
A clang/test/Modules/initializer-list-recognition-through-export-and-linkage-issue-118218.cpp
M clang/test/Parser/cxx0x-decl.cpp
M clang/test/Parser/cxx2c-pack-indexing.cpp
M clang/test/ParserOpenACC/parse-clauses.c
M clang/test/ParserOpenACC/parse-clauses.cpp
M clang/test/ParserOpenACC/parse-constructs.c
M clang/test/Sema/Inputs/lifetime-analysis.h
A clang/test/Sema/aarch64-sme2-intrinsics/acle_sme2_fp8_fdot.c
M clang/test/Sema/aarch64-sve2-intrinsics/acle_sve2_fp8.c
M clang/test/Sema/warn-lifetime-analysis-nocfg.cpp
M clang/test/SemaCXX/cxx2c-pack-indexing-ext-diags.cpp
M clang/test/SemaCXX/ext-int.cpp
A clang/test/SemaCXX/msvc-pragma-function-no-builtin-attr.cpp
M clang/test/SemaCXX/warn-thread-safety-analysis.cpp
M clang/test/SemaCXX/warn-unsafe-buffer-usage-array.cpp
M clang/test/SemaCXX/warn-unsafe-buffer-usage-field-attr.cpp
M clang/test/SemaCXX/warn-unsafe-buffer-usage-fixits-parm-unsupported.cpp
M clang/test/SemaCXX/warn-unsafe-buffer-usage.cpp
M clang/test/SemaOpenACC/combined-construct-auto_seq_independent-clauses.c
M clang/test/SemaOpenACC/combined-construct-collapse-clause.cpp
M clang/test/SemaOpenACC/combined-construct-default-ast.cpp
M clang/test/SemaOpenACC/combined-construct-default-clause.c
M clang/test/SemaOpenACC/combined-construct-device_type-clause.c
M clang/test/SemaOpenACC/combined-construct-if-clause.c
M clang/test/SemaOpenACC/compute-construct-default-clause.c
M clang/test/SemaOpenACC/compute-construct-device_type-clause.c
M clang/test/SemaOpenACC/compute-construct-if-clause.c
A clang/test/SemaOpenACC/data-construct-ast.cpp
A clang/test/SemaOpenACC/data-construct-async-ast.cpp
A clang/test/SemaOpenACC/data-construct-async-clause.c
A clang/test/SemaOpenACC/data-construct-attach-ast.cpp
A clang/test/SemaOpenACC/data-construct-attach-clause.c
A clang/test/SemaOpenACC/data-construct-copy-ast.cpp
A clang/test/SemaOpenACC/data-construct-copy-clause.c
A clang/test/SemaOpenACC/data-construct-copyin-ast.cpp
A clang/test/SemaOpenACC/data-construct-copyin-clause.c
A clang/test/SemaOpenACC/data-construct-copyout-ast.cpp
A clang/test/SemaOpenACC/data-construct-copyout-clause.c
A clang/test/SemaOpenACC/data-construct-create-ast.cpp
A clang/test/SemaOpenACC/data-construct-create-clause.c
A clang/test/SemaOpenACC/data-construct-default-ast.cpp
A clang/test/SemaOpenACC/data-construct-default-clause.c
A clang/test/SemaOpenACC/data-construct-detach-ast.cpp
A clang/test/SemaOpenACC/data-construct-detach-clause.c
A clang/test/SemaOpenACC/data-construct-device_type-ast.cpp
A clang/test/SemaOpenACC/data-construct-device_type-clause.c
A clang/test/SemaOpenACC/data-construct-deviceptr-ast.cpp
A clang/test/SemaOpenACC/data-construct-deviceptr-clause.c
A clang/test/SemaOpenACC/data-construct-finalize-ast.cpp
A clang/test/SemaOpenACC/data-construct-finalize-clause.c
A clang/test/SemaOpenACC/data-construct-if-ast.cpp
A clang/test/SemaOpenACC/data-construct-if-clause.c
A clang/test/SemaOpenACC/data-construct-if_present-ast.cpp
A clang/test/SemaOpenACC/data-construct-if_present-clause.c
A clang/test/SemaOpenACC/data-construct-no_create-ast.cpp
A clang/test/SemaOpenACC/data-construct-no_create-clause.c
A clang/test/SemaOpenACC/data-construct-present-ast.cpp
A clang/test/SemaOpenACC/data-construct-present-clause.c
A clang/test/SemaOpenACC/data-construct-wait-ast.cpp
A clang/test/SemaOpenACC/data-construct-wait-clause.c
A clang/test/SemaOpenACC/data-construct.cpp
M clang/test/SemaOpenACC/loop-construct-auto_seq_independent-clauses.c
M clang/test/SemaOpenACC/loop-construct-collapse-clause.cpp
M clang/test/SemaOpenACC/loop-construct-device_type-clause.c
M clang/tools/clang-installapi/Options.cpp
M clang/tools/clang-linker-wrapper/ClangLinkerWrapper.cpp
M clang/tools/clang-nvlink-wrapper/ClangNVLinkWrapper.cpp
M clang/tools/clang-scan-deps/ClangScanDeps.cpp
M clang/tools/clang-sycl-linker/ClangSYCLLinker.cpp
M clang/tools/libclang/CIndex.cpp
M clang/tools/libclang/CIndexCXX.cpp
M clang/tools/libclang/CXCursor.cpp
M clang/unittests/AST/ASTContextParentMapTest.cpp
M clang/unittests/AST/ASTImporterTest.cpp
M clang/unittests/Analysis/FlowSensitive/TransferTest.cpp
M clang/unittests/Format/FormatTestJS.cpp
M clang/unittests/Frontend/CompilerInvocationTest.cpp
M clang/unittests/Serialization/LoadSpecLazilyTest.cpp
M clang/unittests/StaticAnalyzer/Z3CrosscheckOracleTest.cpp
M clang/utils/TableGen/ClangAttrEmitter.cpp
M clang/utils/TableGen/ClangDiagnosticsEmitter.cpp
M clang/utils/TableGen/SveEmitter.cpp
M clang/utils/perf-training/bolt.lit.cfg
M clang/utils/perf-training/lit.cfg
M clang/utils/perf-training/llvm-support/build.test
M compiler-rt/lib/builtins/CMakeLists.txt
A compiler-rt/lib/builtins/aarch64/sme-abi-assert.c
R compiler-rt/lib/builtins/aarch64/sme-abi-init.c
M compiler-rt/lib/builtins/aarch64/sme-abi.S
M compiler-rt/lib/builtins/aarch64/sme-libc-mem-routines.S
M compiler-rt/lib/builtins/cpu_model/aarch64.c
A compiler-rt/lib/builtins/cpu_model/aarch64/fmv/baremetal.inc
M compiler-rt/lib/interception/interception_win.cpp
M compiler-rt/lib/interception/tests/interception_win_test.cpp
M compiler-rt/lib/msan/msan_interceptors.cpp
M compiler-rt/lib/orc/CMakeLists.txt
M compiler-rt/lib/orc/macho_tlv.x86-64.S
M compiler-rt/lib/orc/sysv_reenter.arm64.S
A compiler-rt/lib/orc/sysv_reenter.x86-64.S
M compiler-rt/lib/rtsan/rtsan_interceptors_posix.cpp
M compiler-rt/lib/sanitizer_common/sanitizer_common_interceptors.inc
M compiler-rt/lib/sanitizer_common/sanitizer_platform_interceptors.h
M compiler-rt/lib/sanitizer_common/sanitizer_win.cpp
M compiler-rt/lib/ubsan_minimal/ubsan_minimal_handlers.cpp
R compiler-rt/test/msan/Linux/dn_expand.cpp
M compiler-rt/test/orc/TestCases/Generic/lazy-link.ll
A compiler-rt/test/sanitizer_common/TestCases/Linux/b64.cpp
A compiler-rt/test/sanitizer_common/TestCases/Linux/dn_expand.cpp
A compiler-rt/test/ubsan_minimal/TestCases/override-callback.c
M flang/examples/FeatureList/FeatureList.cpp
M flang/examples/FlangOmpReport/FlangOmpReportVisitor.cpp
M flang/include/flang/Common/Fortran-consts.h
M flang/include/flang/Optimizer/Builder/HLFIRTools.h
M flang/include/flang/Optimizer/HLFIR/HLFIROps.td
M flang/include/flang/Parser/dump-parse-tree.h
M flang/include/flang/Parser/parse-tree-visitor.h
M flang/include/flang/Parser/parse-tree.h
M flang/include/flang/Semantics/openmp-modifiers.h
M flang/lib/Lower/OpenMP/ClauseProcessor.cpp
M flang/lib/Lower/OpenMP/ClauseProcessor.h
M flang/lib/Lower/OpenMP/Clauses.cpp
M flang/lib/Lower/OpenMP/DataSharingProcessor.cpp
M flang/lib/Lower/OpenMP/DataSharingProcessor.h
M flang/lib/Lower/OpenMP/OpenMP.cpp
M flang/lib/Optimizer/Builder/HLFIRTools.cpp
M flang/lib/Optimizer/HLFIR/IR/HLFIROps.cpp
M flang/lib/Optimizer/HLFIR/Transforms/OptimizedBufferization.cpp
M flang/lib/Optimizer/HLFIR/Transforms/SimplifyHLFIRIntrinsics.cpp
M flang/lib/Optimizer/OpenMP/MapsForPrivatizedSymbols.cpp
M flang/lib/Optimizer/Transforms/CUFDeviceGlobal.cpp
M flang/lib/Parser/openmp-parsers.cpp
M flang/lib/Parser/unparse.cpp
M flang/lib/Semantics/check-omp-structure.cpp
M flang/lib/Semantics/check-omp-structure.h
M flang/lib/Semantics/openmp-modifiers.cpp
M flang/lib/Semantics/resolve-directives.cpp
M flang/lib/Semantics/resolve-names.cpp
M flang/test/Driver/fveclib.f90
M flang/test/Fir/CUDA/cuda-implicit-device-global.f90
M flang/test/HLFIR/opt-array-slice-assign.fir
M flang/test/HLFIR/shapeof.fir
A flang/test/HLFIR/simplify-hlfir-intrinsics-cshift.fir
M flang/test/HLFIR/simplify-hlfir-intrinsics-sum.fir
A flang/test/Lower/OpenMP/KernelLanguage/bare-clause.f90
A flang/test/Lower/OpenMP/Todo/atomic-compare-fail.f90
A flang/test/Lower/OpenMP/Todo/error.f90
M flang/test/Parser/OpenMP/atomic-unparse.f90
A flang/test/Parser/OpenMP/error-unparse.f90
M flang/test/Parser/OpenMP/in-reduction-clause.f90
A flang/test/Parser/OpenMP/linear-clause.f90
M flang/test/Parser/OpenMP/reduction-modifier.f90
A flang/test/Parser/OpenMP/task-reduction-clause.f90
M flang/test/Preprocessing/directive-contin-with-pp.F90
M flang/test/Semantics/OpenMP/atomic-compare.f90
M flang/test/Semantics/OpenMP/atomic01.f90
M flang/test/Semantics/OpenMP/atomic05.f90
M flang/test/Semantics/OpenMP/clause-validity01.f90
A flang/test/Semantics/OpenMP/in-reduction.f90
M flang/test/Semantics/OpenMP/linear-clause01.f90
A flang/test/Semantics/OpenMP/linear-clause02.f90
M flang/test/Semantics/OpenMP/linear-iter.f90
A flang/test/Semantics/OpenMP/ompx-bare.f90
M flang/test/Semantics/OpenMP/symbol08.f90
A flang/test/Semantics/OpenMP/task-reduction.f90
M flang/test/Semantics/OpenMP/taskgroup01.f90
M flang/test/Semantics/modfile55.cuf
M flang/unittests/Runtime/AccessTest.cpp
M libc/CMakeLists.txt
M libc/config/linux/aarch64/headers.txt
M libc/config/linux/arm/headers.txt
M libc/config/linux/riscv/headers.txt
M libc/config/linux/x86_64/entrypoints.txt
M libc/config/linux/x86_64/headers.txt
A libc/docs/headers/arpa/inet.rst
M libc/docs/headers/assert.rst
M libc/docs/headers/ctype.rst
M libc/docs/headers/errno.rst
M libc/docs/headers/fenv.rst
M libc/docs/headers/float.rst
M libc/docs/headers/index.rst
M libc/docs/headers/inttypes.rst
M libc/docs/headers/locale.rst
M libc/docs/headers/math/index.rst
M libc/docs/headers/signal.rst
M libc/docs/headers/stdlib.rst
M libc/docs/headers/string.rst
M libc/docs/headers/strings.rst
A libc/docs/headers/sys/mman.rst
M libc/docs/headers/threads.rst
M libc/docs/headers/uchar.rst
M libc/docs/headers/wchar.rst
M libc/docs/headers/wctype.rst
M libc/docs/talks.rst
M libc/hdr/types/CMakeLists.txt
A libc/hdrgen/yaml/complex.yaml
M libc/hdrgen/yaml/math.yaml
M libc/shared/rpc.h
M libc/src/__support/complex_type.h
M libc/src/__support/macros/properties/complex_types.h
M libc/src/__support/macros/properties/types.h
M libc/src/math/CMakeLists.txt
A libc/src/math/cosf16.h
M libc/src/math/generic/CMakeLists.txt
A libc/src/math/generic/cosf16.cpp
M libc/src/math/generic/cospif16.cpp
M libc/src/math/generic/sinf16.cpp
M libc/test/src/math/CMakeLists.txt
A libc/test/src/math/cosf16_test.cpp
M libc/test/src/math/smoke/CMakeLists.txt
A libc/test/src/math/smoke/cosf16_test.cpp
A libc/test/src/math/sqrtf128_test.cpp
M libc/test/src/strings/CMakeLists.txt
M libc/test/src/strings/index_test.cpp
M libc/test/src/strings/rindex_test.cpp
M libc/utils/MPFRWrapper/MPFRUtils.cpp
A libc/utils/docgen/arpa/inet.yaml
R libc/utils/docgen/assert.json
A libc/utils/docgen/assert.yaml
R libc/utils/docgen/ctype.json
A libc/utils/docgen/ctype.yaml
M libc/utils/docgen/docgen.py
R libc/utils/docgen/errno.json
A libc/utils/docgen/errno.yaml
R libc/utils/docgen/fenv.json
A libc/utils/docgen/fenv.yaml
R libc/utils/docgen/float.json
A libc/utils/docgen/float.yaml
M libc/utils/docgen/header.py
R libc/utils/docgen/inttypes.json
A libc/utils/docgen/inttypes.yaml
R libc/utils/docgen/locale.json
A libc/utils/docgen/locale.yaml
R libc/utils/docgen/setjmp.json
A libc/utils/docgen/setjmp.yaml
R libc/utils/docgen/signal.json
A libc/utils/docgen/signal.yaml
R libc/utils/docgen/stdbit.json
A libc/utils/docgen/stdbit.yaml
R libc/utils/docgen/stdlib.json
A libc/utils/docgen/stdlib.yaml
R libc/utils/docgen/string.json
A libc/utils/docgen/string.yaml
R libc/utils/docgen/strings.json
A libc/utils/docgen/sys/mman.yaml
R libc/utils/docgen/threads.json
A libc/utils/docgen/threads.yaml
R libc/utils/docgen/uchar.json
A libc/utils/docgen/uchar.yaml
R libc/utils/docgen/wchar.json
A libc/utils/docgen/wchar.yaml
R libc/utils/docgen/wctype.json
A libc/utils/docgen/wctype.yaml
M libc/utils/gpu/loader/Loader.h
M libc/utils/gpu/server/rpc_server.cpp
M libclc/clc/include/clc/clcmacro.h
M libclc/clc/include/clc/math/clc_ceil.h
M libclc/clc/include/clc/math/clc_fabs.h
M libclc/clc/include/clc/math/clc_floor.h
M libclc/clc/include/clc/math/clc_rint.h
M libclc/clc/include/clc/math/clc_trunc.h
A libclc/clc/include/clc/math/unary_builtin.inc
M libclc/clc/lib/clspv/SOURCES
R libclc/clc/lib/clspv/dummy.cl
M libclc/clc/lib/generic/SOURCES
A libclc/clc/lib/generic/math/clc_ceil.cl
A libclc/clc/lib/generic/math/clc_fabs.cl
A libclc/clc/lib/generic/math/clc_floor.cl
A libclc/clc/lib/generic/math/clc_rint.cl
A libclc/clc/lib/generic/math/clc_trunc.cl
M libclc/clc/lib/spirv/SOURCES
M libclc/clc/lib/spirv64/SOURCES
M libclc/generic/lib/math/ceil.cl
M libclc/generic/lib/math/fabs.cl
M libclc/generic/lib/math/floor.cl
M libclc/generic/lib/math/rint.cl
M libclc/generic/lib/math/round.cl
M libclc/generic/lib/math/sqrt.cl
M libclc/generic/lib/math/trunc.cl
R libclc/generic/lib/math/unary_builtin.inc
M libcxx/include/CMakeLists.txt
M libcxx/include/__hash_table
M libcxx/include/__memory/allocator.h
M libcxx/include/__memory/builtin_new_allocator.h
M libcxx/include/__memory/construct_at.h
M libcxx/include/__memory/shared_ptr.h
M libcxx/include/__memory/uninitialized_algorithms.h
A libcxx/include/__new/align_val_t.h
A libcxx/include/__new/allocate.h
A libcxx/include/__new/destroying_delete_t.h
A libcxx/include/__new/exceptions.h
A libcxx/include/__new/global_new_delete.h
A libcxx/include/__new/interference_size.h
A libcxx/include/__new/launder.h
A libcxx/include/__new/new_handler.h
A libcxx/include/__new/nothrow_t.h
A libcxx/include/__new/placement_new_delete.h
M libcxx/include/__split_buffer
M libcxx/include/__utility/forward_like.h
M libcxx/include/__utility/small_buffer.h
M libcxx/include/array
M libcxx/include/charconv
M libcxx/include/deque
M libcxx/include/experimental/iterator
M libcxx/include/experimental/memory
M libcxx/include/experimental/propagate_const
M libcxx/include/experimental/simd
M libcxx/include/experimental/type_traits
M libcxx/include/experimental/utility
M libcxx/include/ext/hash_map
M libcxx/include/ext/hash_set
M libcxx/include/flat_map
M libcxx/include/forward_list
M libcxx/include/future
M libcxx/include/list
M libcxx/include/module.modulemap
M libcxx/include/new
M libcxx/include/string
M libcxx/include/string_view
M libcxx/include/variant
R libcxx/test/benchmarks/ContainerBenchmarks.h
R libcxx/test/benchmarks/algorithms.partition_point.bench.cpp
A libcxx/test/benchmarks/algorithms/algorithms.partition_point.bench.cpp
A libcxx/test/benchmarks/algorithms/lexicographical_compare_three_way.bench.cpp
A libcxx/test/benchmarks/containers/ContainerBenchmarks.h
A libcxx/test/benchmarks/containers/deque.bench.cpp
A libcxx/test/benchmarks/containers/deque_iterator.bench.cpp
A libcxx/test/benchmarks/containers/map.bench.cpp
A libcxx/test/benchmarks/containers/ordered_set.bench.cpp
A libcxx/test/benchmarks/containers/string.bench.cpp
A libcxx/test/benchmarks/containers/unordered_set_operations.bench.cpp
A libcxx/test/benchmarks/containers/vector_operations.bench.cpp
R libcxx/test/benchmarks/deque.bench.cpp
R libcxx/test/benchmarks/deque_iterator.bench.cpp
R libcxx/test/benchmarks/format.bench.cpp
A libcxx/test/benchmarks/format/format.bench.cpp
A libcxx/test/benchmarks/format/format_to.bench.cpp
A libcxx/test/benchmarks/format/format_to_n.bench.cpp
A libcxx/test/benchmarks/format/formatted_size.bench.cpp
A libcxx/test/benchmarks/format/formatter_float.bench.cpp
A libcxx/test/benchmarks/format/formatter_int.bench.cpp
A libcxx/test/benchmarks/format/std_format_spec_string_unicode.bench.cpp
A libcxx/test/benchmarks/format/std_format_spec_string_unicode_escape.bench.cpp
R libcxx/test/benchmarks/format_to.bench.cpp
R libcxx/test/benchmarks/format_to_n.bench.cpp
R libcxx/test/benchmarks/formatted_size.bench.cpp
R libcxx/test/benchmarks/formatter_float.bench.cpp
R libcxx/test/benchmarks/formatter_int.bench.cpp
R libcxx/test/benchmarks/lexicographical_compare_three_way.bench.cpp
R libcxx/test/benchmarks/map.bench.cpp
R libcxx/test/benchmarks/ordered_set.bench.cpp
R libcxx/test/benchmarks/std_format_spec_string_unicode.bench.cpp
R libcxx/test/benchmarks/std_format_spec_string_unicode_escape.bench.cpp
R libcxx/test/benchmarks/string.bench.cpp
R libcxx/test/benchmarks/unordered_set_operations.bench.cpp
R libcxx/test/benchmarks/vector_operations.bench.cpp
A libcxx/test/configs/stdlib-libstdc++.cfg.in
A libcxx/test/configs/stdlib-native.cfg.in
M libcxx/test/libcxx/feature_test_macro/version_header.sh.py
M libcxx/test/libcxx/transitive_includes/cxx03.csv
M libcxx/test/libcxx/transitive_includes/cxx11.csv
M libcxx/test/libcxx/transitive_includes/cxx14.csv
M libcxx/test/libcxx/transitive_includes/cxx17.csv
M libcxx/test/libcxx/transitive_includes/cxx20.csv
M libcxx/test/libcxx/transitive_includes/cxx23.csv
M libcxx/test/libcxx/transitive_includes/cxx26.csv
M libcxx/test/std/containers/sequences/vector/vector.cons/assign_iter_iter.pass.cpp
M libcxx/test/std/language.support/support.dynamic/alloc.errors/bad.alloc/bad_alloc.pass.cpp
M libcxx/test/std/language.support/support.dynamic/new.delete/new.delete.placement/new_array.pass.cpp
M libcxx/test/std/language.support/support.dynamic/ptr.launder/launder.types.verify.cpp
M libcxx/test/std/utilities/memory/default.allocator/allocator.members/allocate.size.pass.cpp
A libcxx/test/std/utilities/meta/derived_from_integral_constant.compile.pass.cpp
M libcxx/utils/generate_feature_test_macro_components.py
M libcxx/utils/libcxx/test/format.py
M libcxxabi/CMakeLists.txt
M libcxxabi/src/private_typeinfo.cpp
M libcxxabi/test/cxa_vec_new_overflow_PR41395.pass.cpp
M libcxxabi/test/test_demangle.pass.cpp
M libunwind/CMakeLists.txt
M libunwind/include/__libunwind_config.h
M lld/COFF/Chunks.cpp
M lld/COFF/DLL.cpp
M lld/COFF/Driver.cpp
M lld/COFF/Driver.h
M lld/COFF/DriverUtils.cpp
M lld/COFF/InputFiles.cpp
M lld/COFF/InputFiles.h
M lld/COFF/PDB.cpp
M lld/COFF/SymbolTable.cpp
M lld/COFF/SymbolTable.h
M lld/COFF/Symbols.cpp
M lld/COFF/Symbols.h
M lld/COFF/Writer.cpp
M lld/ELF/Config.h
M lld/ELF/Driver.cpp
M lld/ELF/DriverUtils.cpp
M lld/ELF/InputFiles.cpp
M lld/ELF/Options.td
M lld/ELF/OutputSections.h
M lld/ELF/SyntheticSections.cpp
M lld/ELF/SyntheticSections.h
M lld/ELF/Writer.cpp
M lld/MachO/Arch/ARM64.cpp
M lld/MachO/ConcatOutputSection.cpp
M lld/MachO/DriverUtils.cpp
M lld/MachO/EhFrame.cpp
M lld/MachO/ICF.cpp
M lld/MachO/InputFiles.cpp
M lld/MachO/InputSection.cpp
M lld/MachO/MarkLive.cpp
M lld/MachO/ObjC.cpp
M lld/MachO/Relocations.cpp
M lld/MachO/SyntheticSections.cpp
M lld/MachO/UnwindInfoSection.cpp
M lld/MinGW/Driver.cpp
M lld/docs/ld.lld.1
M lld/test/COFF/reloc-discarded.s
M lld/test/ELF/lto/internalize-exportdyn.ll
A lld/test/ELF/randomize-section-padding.test
M lld/test/ELF/tls-opt.s
M lld/test/ELF/x86-64-tls-ie-local.s
M lld/wasm/Config.h
M lld/wasm/Driver.cpp
M lldb/include/lldb/Core/Progress.h
M lldb/include/lldb/Core/dwarf.h
M lldb/include/lldb/Target/StackFrameList.h
M lldb/source/Core/Progress.cpp
M lldb/source/DataFormatters/FormatterBytecode.cpp
M lldb/source/DataFormatters/FormatterSection.cpp
M lldb/source/Expression/FunctionCaller.cpp
M lldb/source/Expression/UserExpression.cpp
M lldb/source/Plugins/ObjectFile/XCOFF/ObjectFileXCOFF.cpp
M lldb/source/Plugins/ObjectFile/XCOFF/ObjectFileXCOFF.h
M lldb/source/Plugins/Platform/MacOSX/PlatformDarwin.cpp
M lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_loongarch64.cpp
M lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_loongarch64.h
M lldb/source/Plugins/Process/Utility/CMakeLists.txt
A lldb/source/Plugins/Process/Utility/NativeRegisterContextDBReg.cpp
A lldb/source/Plugins/Process/Utility/NativeRegisterContextDBReg.h
M lldb/source/Plugins/Process/Utility/NativeRegisterContextDBReg_arm64.cpp
M lldb/source/Plugins/Process/Utility/NativeRegisterContextDBReg_arm64.h
A lldb/source/Plugins/Process/Utility/NativeRegisterContextDBReg_loongarch.cpp
A lldb/source/Plugins/Process/Utility/NativeRegisterContextDBReg_loongarch.h
M lldb/source/Plugins/Process/gdb-remote/GDBRemoteCommunicationServerCommon.cpp
M lldb/source/Plugins/SymbolFile/DWARF/DIERef.h
M lldb/source/Plugins/SymbolFile/DWARF/DWARFASTParserClang.cpp
M lldb/source/Plugins/SymbolFile/DWARF/DWARFCompileUnit.cpp
M lldb/source/Plugins/SymbolFile/DWARF/DWARFDIE.cpp
M lldb/source/Plugins/SymbolFile/DWARF/DWARFDIE.h
M lldb/source/Plugins/SymbolFile/DWARF/DWARFDebugInfoEntry.cpp
M lldb/source/Plugins/SymbolFile/DWARF/DWARFDebugInfoEntry.h
M lldb/source/Plugins/SymbolFile/DWARF/DWARFUnit.cpp
M lldb/source/Plugins/SymbolFile/DWARF/DWARFUnit.h
M lldb/source/Plugins/SymbolFile/DWARF/ManualDWARFIndex.cpp
M lldb/source/Plugins/SymbolFile/DWARF/SymbolFileDWARF.cpp
M lldb/source/Target/Process.cpp
M lldb/source/Target/StackFrameList.cpp
M lldb/source/Target/Thread.cpp
M lldb/test/API/CMakeLists.txt
M lldb/test/API/api/multithreaded/TestMultithreaded.py
A lldb/test/API/api/multithreaded/deep_stack.cpp
A lldb/test/API/api/multithreaded/test_concurrent_unwind.cpp.template
M lldb/test/API/functionalities/data-formatter/embedded-summary/TestEmbeddedTypeSummary.py
M lldb/test/API/functionalities/data-formatter/embedded-summary/main.c
A lldb/test/Shell/Expr/TestExecProgress.test
M lldb/tools/driver/Driver.cpp
M lldb/tools/lldb-dap/lldb-dap.cpp
M lldb/tools/lldb-server/lldb-gdbserver.cpp
M lldb/unittests/Core/ProgressReportTest.cpp
M lldb/unittests/DataFormatter/FormatterBytecodeTest.cpp
M lldb/unittests/Host/PipeTest.cpp
M llvm/Maintainers.md
M llvm/docs/RISCVUsage.rst
M llvm/docs/ReleaseNotes.md
M llvm/docs/SPIRVUsage.rst
M llvm/docs/Security.rst
M llvm/docs/UndefinedBehavior.rst
M llvm/docs/Vectorizers.rst
M llvm/docs/tutorial/MyFirstLanguageFrontend/LangImpl07.rst
A llvm/docs/vplan-early-exit.dot
A llvm/docs/vplan-early-exit.png
M llvm/examples/Kaleidoscope/Chapter7/toy.cpp
A llvm/include/llvm/ADT/StringTable.h
M llvm/include/llvm/Analysis/DomTreeUpdater.h
M llvm/include/llvm/Analysis/GenericDomTreeUpdater.h
M llvm/include/llvm/Analysis/GenericDomTreeUpdaterImpl.h
M llvm/include/llvm/Analysis/IVDescriptors.h
M llvm/include/llvm/Analysis/PtrUseVisitor.h
A llvm/include/llvm/Analysis/ScalarEvolutionPatternMatch.h
M llvm/include/llvm/Analysis/TargetLibraryInfo.h
M llvm/include/llvm/AsmParser/LLParser.h
M llvm/include/llvm/CodeGen/GlobalISel/GIMatchTableExecutorImpl.h
M llvm/include/llvm/CodeGen/GlobalISel/LegalizationArtifactCombiner.h
M llvm/include/llvm/CodeGen/LowLevelTypeUtils.h
M llvm/include/llvm/CodeGen/MachineBasicBlock.h
M llvm/include/llvm/CodeGen/MachineDomTreeUpdater.h
M llvm/include/llvm/CodeGen/MachineDominators.h
M llvm/include/llvm/CodeGen/MachineFunction.h
M llvm/include/llvm/CodeGen/MachineModuleInfoImpls.h
M llvm/include/llvm/CodeGen/MachineSSAContext.h
M llvm/include/llvm/CodeGen/MachineScheduler.h
M llvm/include/llvm/CodeGen/SDNodeProperties.td
M llvm/include/llvm/CodeGen/SDPatternMatch.h
M llvm/include/llvm/CodeGen/TargetLowering.h
M llvm/include/llvm/CodeGen/TargetLoweringObjectFileImpl.h
M llvm/include/llvm/CodeGen/TargetRegisterInfo.h
M llvm/include/llvm/DebugInfo/DWARF/DWARFTypePrinter.h
M llvm/include/llvm/DebugInfo/GSYM/GsymReader.h
M llvm/include/llvm/ExecutionEngine/JITLink/aarch64.h
M llvm/include/llvm/ExecutionEngine/JITLink/x86_64.h
M llvm/include/llvm/ExecutionEngine/Orc/Core.h
M llvm/include/llvm/ExecutionEngine/Orc/LazyObjectLinkingLayer.h
M llvm/include/llvm/ExecutionEngine/Orc/ObjectLinkingLayer.h
M llvm/include/llvm/Frontend/OpenMP/ClauseT.h
M llvm/include/llvm/Frontend/OpenMP/ConstructDecompositionT.h
M llvm/include/llvm/Frontend/OpenMP/OMP.td
M llvm/include/llvm/IR/CmpPredicate.h
M llvm/include/llvm/IR/DataLayout.h
M llvm/include/llvm/IR/DiagnosticInfo.h
M llvm/include/llvm/IR/IntrinsicsAArch64.td
M llvm/include/llvm/IR/NVVMIntrinsicFlags.h
M llvm/include/llvm/IR/PatternMatch.h
M llvm/include/llvm/Option/OptTable.h
M llvm/include/llvm/Option/Option.h
M llvm/include/llvm/ProfileData/InstrProfReader.h
M llvm/include/llvm/ProfileData/InstrProfWriter.h
M llvm/include/llvm/ProfileData/MemProf.h
A llvm/include/llvm/ProfileData/MemProfYAML.h
M llvm/include/llvm/SandboxIR/Instruction.h
M llvm/include/llvm/SandboxIR/Type.h
M llvm/include/llvm/Support/AutoConvert.h
M llvm/include/llvm/Support/Memory.h
M llvm/include/llvm/Support/TypeName.h
M llvm/include/llvm/Target/TargetLoweringObjectFile.h
M llvm/include/llvm/Target/TargetSelectionDAG.td
M llvm/include/llvm/TargetParser/AArch64TargetParser.h
M llvm/include/llvm/Transforms/Instrumentation/RealtimeSanitizer.h
M llvm/include/llvm/Transforms/Utils/Evaluator.h
M llvm/include/llvm/Transforms/Utils/ExtraPassManager.h
M llvm/include/llvm/Transforms/Utils/LoopUtils.h
M llvm/include/llvm/Transforms/Utils/SSAUpdater.h
M llvm/include/llvm/Transforms/Vectorize/LoopVectorizationLegality.h
M llvm/include/module.modulemap
M llvm/lib/Analysis/BasicAliasAnalysis.cpp
M llvm/lib/Analysis/DomTreeUpdater.cpp
M llvm/lib/Analysis/IVDescriptors.cpp
M llvm/lib/Analysis/InstructionSimplify.cpp
M llvm/lib/Analysis/OverflowInstAnalysis.cpp
M llvm/lib/Analysis/ScalarEvolution.cpp
M llvm/lib/Analysis/TargetLibraryInfo.cpp
M llvm/lib/Analysis/ValueTracking.cpp
M llvm/lib/AsmParser/LLParser.cpp
M llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
M llvm/lib/CodeGen/AsmPrinter/AsmPrinterInlineAsm.cpp
M llvm/lib/CodeGen/AsmPrinter/DwarfCFIException.cpp
M llvm/lib/CodeGen/BranchFolding.cpp
M llvm/lib/CodeGen/CodeGenPrepare.cpp
M llvm/lib/CodeGen/ExpandMemCmp.cpp
M llvm/lib/CodeGen/GlobalISel/CSEInfo.cpp
M llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
M llvm/lib/CodeGen/GlobalISel/CombinerHelperCasts.cpp
M llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
M llvm/lib/CodeGen/GlobalISel/LoadStoreOpt.cpp
M llvm/lib/CodeGen/GlobalISel/Utils.cpp
M llvm/lib/CodeGen/LazyMachineBlockFrequencyInfo.cpp
M llvm/lib/CodeGen/LiveDebugValues/InstrRefBasedImpl.cpp
M llvm/lib/CodeGen/LiveDebugValues/LiveDebugValues.cpp
M llvm/lib/CodeGen/LowLevelTypeUtils.cpp
M llvm/lib/CodeGen/MIRCanonicalizerPass.cpp
M llvm/lib/CodeGen/MLRegAllocEvictAdvisor.cpp
M llvm/lib/CodeGen/MachineBasicBlock.cpp
M llvm/lib/CodeGen/MachineCombiner.cpp
M llvm/lib/CodeGen/MachineDomTreeUpdater.cpp
M llvm/lib/CodeGen/MachineDominanceFrontier.cpp
M llvm/lib/CodeGen/MachineDominators.cpp
M llvm/lib/CodeGen/MachineFunction.cpp
M llvm/lib/CodeGen/MachineLICM.cpp
M llvm/lib/CodeGen/MachineLateInstrsCleanup.cpp
M llvm/lib/CodeGen/MachineLoopInfo.cpp
M llvm/lib/CodeGen/MachineModuleInfoImpls.cpp
M llvm/lib/CodeGen/MachineOutliner.cpp
M llvm/lib/CodeGen/MachinePipeliner.cpp
M llvm/lib/CodeGen/MachineScheduler.cpp
M llvm/lib/CodeGen/MachineSink.cpp
M llvm/lib/CodeGen/MachineUniformityAnalysis.cpp
M llvm/lib/CodeGen/MachineVerifier.cpp
M llvm/lib/CodeGen/ModuloSchedule.cpp
M llvm/lib/CodeGen/PHIElimination.cpp
M llvm/lib/CodeGen/RegAllocBase.cpp
M llvm/lib/CodeGen/RegAllocBase.h
M llvm/lib/CodeGen/RegAllocFast.cpp
M llvm/lib/CodeGen/RegAllocGreedy.cpp
M llvm/lib/CodeGen/ScheduleDAGInstrs.cpp
M llvm/lib/CodeGen/SelectOptimize.cpp
M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
M llvm/lib/CodeGen/SelectionDAG/FastISel.cpp
M llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
M llvm/lib/CodeGen/TargetLoweringBase.cpp
M llvm/lib/CodeGen/TargetLoweringObjectFileImpl.cpp
M llvm/lib/CodeGen/VLIWMachineScheduler.cpp
M llvm/lib/CodeGen/VirtRegMap.cpp
M llvm/lib/CodeGen/XRayInstrumentation.cpp
M llvm/lib/DWARFLinker/Parallel/DWARFLinkerCompileUnit.cpp
M llvm/lib/DebugInfo/GSYM/CallSiteInfo.cpp
M llvm/lib/DebugInfo/GSYM/GsymReader.cpp
M llvm/lib/ExecutionEngine/JITLink/COFFDirectiveParser.cpp
M llvm/lib/ExecutionEngine/JITLink/x86_64.cpp
M llvm/lib/ExecutionEngine/Orc/JITLinkReentryTrampolines.cpp
M llvm/lib/ExecutionEngine/Orc/ObjectLinkingLayer.cpp
M llvm/lib/Frontend/OpenMP/OMPIRBuilder.cpp
M llvm/lib/IR/DataLayout.cpp
M llvm/lib/IR/DiagnosticInfo.cpp
M llvm/lib/IR/Instructions.cpp
M llvm/lib/IR/IntrinsicInst.cpp
M llvm/lib/MC/MCParser/AsmParser.cpp
M llvm/lib/MC/TargetRegistry.cpp
M llvm/lib/Option/OptTable.cpp
M llvm/lib/Option/Option.cpp
M llvm/lib/Passes/PassBuilder.cpp
M llvm/lib/Passes/PassRegistry.def
M llvm/lib/ProfileData/MemProfReader.cpp
M llvm/lib/SandboxIR/Type.cpp
M llvm/lib/Support/AutoConvert.cpp
M llvm/lib/Support/MemoryBuffer.cpp
M llvm/lib/Support/Windows/Path.inc
M llvm/lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp
M llvm/lib/Target/AArch64/AArch64Features.td
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
M llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
M llvm/lib/Target/AArch64/AArch64PBQPRegAlloc.cpp
M llvm/lib/Target/AArch64/AArch64RegisterInfo.cpp
M llvm/lib/Target/AArch64/AArch64RegisterInfo.h
M llvm/lib/Target/AArch64/AArch64SMEInstrInfo.td
M llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
M llvm/lib/Target/AArch64/AArch64TargetObjectFile.cpp
M llvm/lib/Target/AArch64/AArch64TargetObjectFile.h
M llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
M llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
M llvm/lib/Target/AArch64/MCTargetDesc/AArch64TargetStreamer.cpp
M llvm/lib/Target/AArch64/MCTargetDesc/AArch64TargetStreamer.h
M llvm/lib/Target/AArch64/SMEInstrFormats.td
M llvm/lib/Target/AArch64/SVEInstrFormats.td
M llvm/lib/Target/AMDGPU/AMDGPUAttributor.cpp
M llvm/lib/Target/AMDGPU/AMDGPUCodeGenPrepare.cpp
M llvm/lib/Target/AMDGPU/AMDGPUInstCombineIntrinsic.cpp
M llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
M llvm/lib/Target/AMDGPU/AMDGPULibCalls.cpp
M llvm/lib/Target/AMDGPU/AMDGPULibFunc.cpp
M llvm/lib/Target/AMDGPU/AMDGPULibFunc.h
M llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
M llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
M llvm/lib/Target/AMDGPU/BUFInstructions.td
M llvm/lib/Target/AMDGPU/FLATInstructions.td
M llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp
M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
M llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
M llvm/lib/Target/AMDGPU/SIInstrInfo.td
M llvm/lib/Target/AMDGPU/SILateBranchLowering.cpp
M llvm/lib/Target/AMDGPU/SILowerI1Copies.cpp
M llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
M llvm/lib/Target/AMDGPU/SIWholeQuadMode.cpp
M llvm/lib/Target/AMDGPU/SOPInstructions.td
M llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
M llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h
M llvm/lib/Target/AMDGPU/VOP3Instructions.td
M llvm/lib/Target/AMDGPU/VOP3PInstructions.td
M llvm/lib/Target/AMDGPU/VOPInstructions.td
M llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
M llvm/lib/Target/ARM/ARMConstantIslandPass.cpp
M llvm/lib/Target/ARM/ARMISelLowering.cpp
M llvm/lib/Target/ARM/ARMInstrInfo.td
M llvm/lib/Target/ARM/ARMInstrMVE.td
M llvm/lib/Target/ARM/ARMInstrThumb.td
M llvm/lib/Target/ARM/ARMInstrThumb2.td
M llvm/lib/Target/ARM/Thumb2ITBlockPass.cpp
M llvm/lib/Target/AVR/AVRInstrInfo.td
M llvm/lib/Target/Hexagon/HexagonFrameLowering.cpp
M llvm/lib/Target/Hexagon/HexagonLoopIdiomRecognition.cpp
M llvm/lib/Target/Hexagon/HexagonRegisterInfo.cpp
M llvm/lib/Target/LoongArch/LoongArchOptWInstrs.cpp
M llvm/lib/Target/M68k/Disassembler/M68kDisassembler.cpp
M llvm/lib/Target/M68k/M68kISelDAGToDAG.cpp
M llvm/lib/Target/M68k/M68kInstrAtomics.td
M llvm/lib/Target/M68k/M68kInstrControl.td
M llvm/lib/Target/M68k/M68kInstrInfo.td
M llvm/lib/Target/M68k/MCTargetDesc/M68kAsmBackend.cpp
M llvm/lib/Target/NVPTX/NVPTXInstrInfo.td
M llvm/lib/Target/PowerPC/PPCISelLowering.cpp
M llvm/lib/Target/PowerPC/PPCInstrInfo.td
M llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
M llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
M llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
M llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
M llvm/lib/Target/RISCV/RISCVFeatures.td
M llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
M llvm/lib/Target/RISCV/RISCVGISel.td
M llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
M llvm/lib/Target/RISCV/RISCVInstrInfo.td
M llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
M llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td
M llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
M llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
M llvm/lib/Target/RISCV/RISCVInstrInfoZb.td
M llvm/lib/Target/RISCV/RISCVProcessors.td
M llvm/lib/Target/RISCV/RISCVSubtarget.cpp
M llvm/lib/Target/RISCV/RISCVSubtarget.h
M llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
M llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
M llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp
M llvm/lib/Target/SPIRV/MCTargetDesc/SPIRVMCCodeEmitter.cpp
M llvm/lib/Target/SPIRV/SPIRVBuiltins.cpp
M llvm/lib/Target/SPIRV/SPIRVBuiltins.h
M llvm/lib/Target/SPIRV/SPIRVCommandLine.cpp
M llvm/lib/Target/SPIRV/SPIRVEmitIntrinsics.cpp
M llvm/lib/Target/SPIRV/SPIRVGlobalRegistry.cpp
M llvm/lib/Target/SPIRV/SPIRVInstrInfo.td
M llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
M llvm/lib/Target/SPIRV/SPIRVLegalizerInfo.cpp
M llvm/lib/Target/SPIRV/SPIRVModuleAnalysis.cpp
M llvm/lib/Target/SPIRV/SPIRVPostLegalizer.cpp
M llvm/lib/Target/SPIRV/SPIRVPreLegalizer.cpp
M llvm/lib/Target/SPIRV/SPIRVSymbolicOperands.td
M llvm/lib/Target/SystemZ/SystemZInstrInfo.td
M llvm/lib/Target/SystemZ/SystemZOperators.td
M llvm/lib/Target/TargetLoweringObjectFile.cpp
M llvm/lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp
M llvm/lib/Target/X86/MCTargetDesc/X86ELFObjectWriter.cpp
M llvm/lib/Target/X86/MCTargetDesc/X86FixupKinds.h
M llvm/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp
M llvm/lib/Target/X86/MCTargetDesc/X86MachObjectWriter.cpp
M llvm/lib/Target/X86/MCTargetDesc/X86WinCOFFObjectWriter.cpp
M llvm/lib/Target/X86/X86FlagsCopyLowering.cpp
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/lib/Target/X86/X86InstrFragments.td
M llvm/lib/Target/X86/X86RegisterInfo.cpp
M llvm/lib/Target/X86/X86WinEHState.cpp
M llvm/lib/Target/Xtensa/XtensaISelLowering.cpp
M llvm/lib/Target/Xtensa/XtensaISelLowering.h
M llvm/lib/Target/Xtensa/XtensaMachineFunctionInfo.h
M llvm/lib/TargetParser/AArch64TargetParser.cpp
M llvm/lib/TargetParser/Host.cpp
M llvm/lib/TargetParser/RISCVISAInfo.cpp
M llvm/lib/ToolDrivers/llvm-dlltool/DlltoolDriver.cpp
M llvm/lib/ToolDrivers/llvm-lib/LibDriver.cpp
M llvm/lib/Transforms/IPO/AlwaysInliner.cpp
M llvm/lib/Transforms/IPO/SampleProfile.cpp
M llvm/lib/Transforms/InstCombine/InstCombineAddSub.cpp
M llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp
M llvm/lib/Transforms/InstCombine/InstCombineCompares.cpp
M llvm/lib/Transforms/InstCombine/InstCombineInternal.h
M llvm/lib/Transforms/InstCombine/InstCombineSelect.cpp
M llvm/lib/Transforms/InstCombine/InstCombineVectorOps.cpp
M llvm/lib/Transforms/InstCombine/InstructionCombining.cpp
M llvm/lib/Transforms/Instrumentation/MemProfiler.cpp
M llvm/lib/Transforms/Instrumentation/RealtimeSanitizer.cpp
M llvm/lib/Transforms/Scalar/CallSiteSplitting.cpp
M llvm/lib/Transforms/Scalar/ConstraintElimination.cpp
M llvm/lib/Transforms/Scalar/DeadStoreElimination.cpp
M llvm/lib/Transforms/Scalar/EarlyCSE.cpp
M llvm/lib/Transforms/Scalar/GuardWidening.cpp
M llvm/lib/Transforms/Scalar/InductiveRangeCheckElimination.cpp
M llvm/lib/Transforms/Scalar/JumpThreading.cpp
M llvm/lib/Transforms/Scalar/LICM.cpp
M llvm/lib/Transforms/Scalar/LoopBoundSplit.cpp
M llvm/lib/Transforms/Scalar/LoopIdiomRecognize.cpp
M llvm/lib/Transforms/Scalar/SROA.cpp
M llvm/lib/Transforms/Scalar/SimpleLoopUnswitch.cpp
M llvm/lib/Transforms/Utils/Evaluator.cpp
M llvm/lib/Transforms/Utils/LoopPeel.cpp
M llvm/lib/Transforms/Utils/LoopUtils.cpp
M llvm/lib/Transforms/Utils/SSAUpdater.cpp
M llvm/lib/Transforms/Utils/ScalarEvolutionExpander.cpp
M llvm/lib/Transforms/Utils/SimplifyCFG.cpp
M llvm/lib/Transforms/Utils/SimplifyIndVar.cpp
M llvm/lib/Transforms/Utils/SimplifyLibCalls.cpp
M llvm/lib/Transforms/Vectorize/LoopVectorizationLegality.cpp
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
M llvm/lib/Transforms/Vectorize/VPlan.cpp
M llvm/lib/Transforms/Vectorize/VPlan.h
M llvm/lib/Transforms/Vectorize/VPlanAnalysis.cpp
M llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
M llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
M llvm/lib/Transforms/Vectorize/VPlanTransforms.h
M llvm/lib/Transforms/Vectorize/VPlanUnroll.cpp
M llvm/lib/Transforms/Vectorize/VPlanUtils.cpp
M llvm/lib/Transforms/Vectorize/VPlanVerifier.cpp
M llvm/lib/Transforms/Vectorize/VectorCombine.cpp
M llvm/test/Analysis/BasicAA/smaller-index-size-overflow.ll
M llvm/test/Analysis/CostModel/RISCV/rvv-extractelement.ll
M llvm/test/Analysis/CostModel/RISCV/rvv-insertelement.ll
M llvm/test/Analysis/CostModel/X86/scalarize.ll
M llvm/test/Assembler/aggregate-constant-values.ll
A llvm/test/Assembler/pr119818.ll
M llvm/test/CodeGen/AArch64/Atomics/aarch64-atomicrmw-lse2.ll
M llvm/test/CodeGen/AArch64/Atomics/aarch64-atomicrmw-lse2_lse128.ll
M llvm/test/CodeGen/AArch64/Atomics/aarch64-atomicrmw-outline_atomics.ll
M llvm/test/CodeGen/AArch64/Atomics/aarch64-atomicrmw-rcpc.ll
M llvm/test/CodeGen/AArch64/Atomics/aarch64-atomicrmw-rcpc3.ll
M llvm/test/CodeGen/AArch64/Atomics/aarch64-atomicrmw-v8_1a.ll
M llvm/test/CodeGen/AArch64/Atomics/aarch64-atomicrmw-v8a.ll
M llvm/test/CodeGen/AArch64/GlobalISel/combine-ext-debugloc.mir
M llvm/test/CodeGen/AArch64/GlobalISel/legalize-build-vector.mir
M llvm/test/CodeGen/AArch64/GlobalISel/legalize-cmp.mir
M llvm/test/CodeGen/AArch64/GlobalISel/legalize-concat-vectors.mir
M llvm/test/CodeGen/AArch64/GlobalISel/legalize-ext.mir
M llvm/test/CodeGen/AArch64/GlobalISel/legalize-inserts.mir
M llvm/test/CodeGen/AArch64/GlobalISel/legalize-threeway-cmp.mir
M llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-hoist-same-hands.mir
M llvm/test/CodeGen/AArch64/aarch64-minmaxv.ll
M llvm/test/CodeGen/AArch64/arm64-anyregcc-crash.ll
M llvm/test/CodeGen/AArch64/dag-combine-setcc.ll
M llvm/test/CodeGen/AArch64/dump-schedule-trace.mir
M llvm/test/CodeGen/AArch64/dup.ll
M llvm/test/CodeGen/AArch64/force-enable-intervals.mir
A llvm/test/CodeGen/AArch64/fp8-sve-cvtn.ll
A llvm/test/CodeGen/AArch64/fp8-sve-fdot.ll
A llvm/test/CodeGen/AArch64/fp8-sve-fmla.ll
M llvm/test/CodeGen/AArch64/icmp.ll
M llvm/test/CodeGen/AArch64/illegal-floating-point-vector-compares.ll
M llvm/test/CodeGen/AArch64/misched-detail-resource-booking-01.mir
M llvm/test/CodeGen/AArch64/misched-detail-resource-booking-02.mir
M llvm/test/CodeGen/AArch64/misched-sort-resource-in-trace.mir
A llvm/test/CodeGen/AArch64/ptrauth-sign-personality.ll
M llvm/test/CodeGen/AArch64/reduce-and.ll
M llvm/test/CodeGen/AArch64/reduce-or.ll
M llvm/test/CodeGen/AArch64/scmp.ll
M llvm/test/CodeGen/AArch64/selectopt-cast.ll
A llvm/test/CodeGen/AArch64/sme2-intrinsics-fp8-fdot.ll
M llvm/test/CodeGen/AArch64/sme2-intrinsics-int-dots.ll
M llvm/test/CodeGen/AArch64/sme2-intrinsics-vdot.ll
M llvm/test/CodeGen/AArch64/stack-tagging-ex-2.ll
A llvm/test/CodeGen/AArch64/sve-load-store-strict-align.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-cvt-fp-int-fp.ll
A llvm/test/CodeGen/AArch64/sve-unaligned-load-store-strict-align.ll
M llvm/test/CodeGen/AArch64/ucmp.ll
M llvm/test/CodeGen/AArch64/vecreduce-and-legalization.ll
M llvm/test/CodeGen/AArch64/vecreduce-bool.ll
M llvm/test/CodeGen/AArch64/vecreduce-umax-legalization.ll
M llvm/test/CodeGen/AArch64/vector-extract-last-active.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-and.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-merge-values.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-or.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-phi.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-shuffle-vector.s16.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-xor.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-zext.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/mmra.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/saddsat.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/ssubsat.ll
M llvm/test/CodeGen/AMDGPU/addrspacecast-constantexpr.ll
M llvm/test/CodeGen/AMDGPU/alloc-all-regs-reserved-in-class.mir
M llvm/test/CodeGen/AMDGPU/amdgpu-attributor-no-agpr.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-idiv.ll
A llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-image-function-signatures.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-ldexp.ll
M llvm/test/CodeGen/AMDGPU/amdgpu.private-memory.ll
M llvm/test/CodeGen/AMDGPU/annotate-existing-abi-attributes.ll
M llvm/test/CodeGen/AMDGPU/annotate-kernel-features-hsa-call.ll
M llvm/test/CodeGen/AMDGPU/annotate-kernel-features-hsa.ll
M llvm/test/CodeGen/AMDGPU/attr-amdgpu-max-num-workgroups-propagate.ll
M llvm/test/CodeGen/AMDGPU/attributor-flatscratchinit.ll
M llvm/test/CodeGen/AMDGPU/attributor-loop-issue-58639.ll
M llvm/test/CodeGen/AMDGPU/av-spill-expansion-with-machine-cp.mir
M llvm/test/CodeGen/AMDGPU/bf16-conversions.ll
M llvm/test/CodeGen/AMDGPU/bitreverse-inline-immediates.ll
M llvm/test/CodeGen/AMDGPU/bypass-div.ll
M llvm/test/CodeGen/AMDGPU/direct-indirect-call.ll
M llvm/test/CodeGen/AMDGPU/div_i128.ll
M llvm/test/CodeGen/AMDGPU/duplicate-attribute-indirect.ll
M llvm/test/CodeGen/AMDGPU/gfx12_scalar_subword_loads.ll
M llvm/test/CodeGen/AMDGPU/hazards-gfx950.mir
M llvm/test/CodeGen/AMDGPU/illegal-eviction-assert.mir
M llvm/test/CodeGen/AMDGPU/implicitarg-offset-attributes.ll
M llvm/test/CodeGen/AMDGPU/indirect-call-set-from-other-function.ll
M llvm/test/CodeGen/AMDGPU/inline-attr.ll
M llvm/test/CodeGen/AMDGPU/invalid-inline-asm-constraint-crash.ll
M llvm/test/CodeGen/AMDGPU/issue48473.mir
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.bitop3.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.read.tr.gfx950.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.gfx950.bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.gfx950.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.prng.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.atomic.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.atomic.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.buffer.prefetch.data.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.prefetch.data.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.smfmac.gfx950.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.atomic.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.atomic.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.update.dpp.gfx90a.ll
M llvm/test/CodeGen/AMDGPU/llvm.set.rounding.ll
M llvm/test/CodeGen/AMDGPU/load-store-opt-addc0.mir
M llvm/test/CodeGen/AMDGPU/mai-hazards-mfma-scale.gfx950.mir
M llvm/test/CodeGen/AMDGPU/mmra.ll
M llvm/test/CodeGen/AMDGPU/propagate-flat-work-group-size.ll
M llvm/test/CodeGen/AMDGPU/propagate-waves-per-eu.ll
A llvm/test/CodeGen/AMDGPU/ran-out-of-registers-error-all-regs-reserved.ll
A llvm/test/CodeGen/AMDGPU/ran-out-of-registers-errors.ll
M llvm/test/CodeGen/AMDGPU/recursive_global_initializer.ll
M llvm/test/CodeGen/AMDGPU/regalloc-illegal-eviction-assert.ll
M llvm/test/CodeGen/AMDGPU/remaining-virtual-register-operands.ll
M llvm/test/CodeGen/AMDGPU/remove-no-kernel-id-attribute.ll
M llvm/test/CodeGen/AMDGPU/simple-indirect-call-2.ll
M llvm/test/CodeGen/AMDGPU/simple-indirect-call.ll
M llvm/test/CodeGen/AMDGPU/simplify-libcalls.ll
M llvm/test/CodeGen/AMDGPU/udiv64.ll
M llvm/test/CodeGen/AMDGPU/uniform-work-group-attribute-missing.ll
M llvm/test/CodeGen/AMDGPU/uniform-work-group-multistep.ll
M llvm/test/CodeGen/AMDGPU/uniform-work-group-nested-function-calls.ll
M llvm/test/CodeGen/AMDGPU/uniform-work-group-prevent-attribute-propagation.ll
M llvm/test/CodeGen/AMDGPU/uniform-work-group-propagate-attribute.ll
M llvm/test/CodeGen/AMDGPU/uniform-work-group-recursion-test.ll
M llvm/test/CodeGen/AMDGPU/uniform-work-group-test.ll
M llvm/test/CodeGen/AMDGPU/urem64.ll
M llvm/test/CodeGen/AMDGPU/v_swap_b16.ll
M llvm/test/CodeGen/ARC/addrmode.ll
M llvm/test/CodeGen/ARC/alu.ll
M llvm/test/CodeGen/ARC/brcc.ll
M llvm/test/CodeGen/ARC/call.ll
M llvm/test/CodeGen/ARC/intrinsics.ll
M llvm/test/CodeGen/ARC/ldst.ll
A llvm/test/CodeGen/ARM/dagcombine-ld-op-st.ll
M llvm/test/CodeGen/ARM/single-issue-r52.mir
M llvm/test/CodeGen/AVR/PR31344.ll
M llvm/test/CodeGen/AVR/PR31345.ll
M llvm/test/CodeGen/AVR/PR37143.ll
M llvm/test/CodeGen/AVR/add.ll
M llvm/test/CodeGen/AVR/alloca.ll
M llvm/test/CodeGen/AVR/and.ll
M llvm/test/CodeGen/AVR/atomics/fence.ll
M llvm/test/CodeGen/AVR/atomics/load-store-16-unexpected-register-bug.ll
M llvm/test/CodeGen/AVR/atomics/load16.ll
M llvm/test/CodeGen/AVR/atomics/load32.ll
M llvm/test/CodeGen/AVR/atomics/load64.ll
M llvm/test/CodeGen/AVR/atomics/load8.ll
M llvm/test/CodeGen/AVR/atomics/store.ll
M llvm/test/CodeGen/AVR/atomics/store16.ll
M llvm/test/CodeGen/AVR/atomics/swap.ll
M llvm/test/CodeGen/AVR/avr-rust-issue-123.ll
M llvm/test/CodeGen/AVR/block-address-is-in-progmem-space.ll
M llvm/test/CodeGen/AVR/branch-relaxation-long.ll
M llvm/test/CodeGen/AVR/branch-relaxation.ll
M llvm/test/CodeGen/AVR/brind.ll
M llvm/test/CodeGen/AVR/calling-conv/c/call.ll
M llvm/test/CodeGen/AVR/calling-conv/c/call_aggr.ll
M llvm/test/CodeGen/AVR/calling-conv/c/return.ll
M llvm/test/CodeGen/AVR/calling-conv/c/return_aggr.ll
M llvm/test/CodeGen/AVR/clear-bss.ll
M llvm/test/CodeGen/AVR/cmp.ll
M llvm/test/CodeGen/AVR/copy-data-to-ram.ll
M llvm/test/CodeGen/AVR/ctlz.ll
M llvm/test/CodeGen/AVR/ctpop.ll
M llvm/test/CodeGen/AVR/cttz.ll
M llvm/test/CodeGen/AVR/directmem.ll
M llvm/test/CodeGen/AVR/div.ll
M llvm/test/CodeGen/AVR/dynalloca.ll
M llvm/test/CodeGen/AVR/eor.ll
M llvm/test/CodeGen/AVR/expand-integer-failure.ll
M llvm/test/CodeGen/AVR/features/avr25.ll
M llvm/test/CodeGen/AVR/features/xmega_io.ll
M llvm/test/CodeGen/AVR/frame.ll
M llvm/test/CodeGen/AVR/frmidx-iterator-bug.ll
M llvm/test/CodeGen/AVR/high-pressure-on-ptrregs.ll
M llvm/test/CodeGen/AVR/icall-func-pointer-correct-addr-space.ll
M llvm/test/CodeGen/AVR/impossible-reg-to-reg-copy.ll
M llvm/test/CodeGen/AVR/inline-asm/inline-asm.ll
M llvm/test/CodeGen/AVR/inline-asm/inline-asm2.ll
M llvm/test/CodeGen/AVR/integration/blink.ll
M llvm/test/CodeGen/AVR/interrupts.ll
M llvm/test/CodeGen/AVR/intrinsics/named-reg-alloc.ll
M llvm/test/CodeGen/AVR/intrinsics/named-reg-special.ll
M llvm/test/CodeGen/AVR/intrinsics/stacksave-restore.ll
M llvm/test/CodeGen/AVR/io.ll
M llvm/test/CodeGen/AVR/issue-cannot-select-bswap.ll
M llvm/test/CodeGen/AVR/issue-regalloc-stackframe-folding-earlyclobber.ll
M llvm/test/CodeGen/AVR/large-return-size.ll
M llvm/test/CodeGen/AVR/ldd-immediate-overflow.ll
M llvm/test/CodeGen/AVR/load.ll
M llvm/test/CodeGen/AVR/lower-formal-args-struct-return.ll
M llvm/test/CodeGen/AVR/lower-formal-arguments-assertion.ll
M llvm/test/CodeGen/AVR/no-clear-bss.ll
M llvm/test/CodeGen/AVR/no-copy-data.ll
M llvm/test/CodeGen/AVR/no-print-operand-twice.ll
M llvm/test/CodeGen/AVR/or.ll
M llvm/test/CodeGen/AVR/pre-schedule.ll
M llvm/test/CodeGen/AVR/progmem-extended.ll
M llvm/test/CodeGen/AVR/progmem.ll
M llvm/test/CodeGen/AVR/pseudo/LDDWRdYQ.mir
M llvm/test/CodeGen/AVR/rem.ll
M llvm/test/CodeGen/AVR/runtime-trig.ll
M llvm/test/CodeGen/AVR/rust-avr-bug-112.ll
M llvm/test/CodeGen/AVR/rust-avr-bug-37.ll
M llvm/test/CodeGen/AVR/rust-avr-bug-95.ll
M llvm/test/CodeGen/AVR/rust-avr-bug-99.ll
M llvm/test/CodeGen/AVR/rust-bug-98167.ll
M llvm/test/CodeGen/AVR/select-must-add-unconditional-jump.ll
M llvm/test/CodeGen/AVR/sext.ll
M llvm/test/CodeGen/AVR/shift.ll
M llvm/test/CodeGen/AVR/sign-extension.ll
M llvm/test/CodeGen/AVR/smul-with-overflow.ll
M llvm/test/CodeGen/AVR/software-mul.ll
M llvm/test/CodeGen/AVR/std-immediate-overflow.ll
M llvm/test/CodeGen/AVR/std-ldd-immediate-overflow.ll
M llvm/test/CodeGen/AVR/stdwstk.ll
M llvm/test/CodeGen/AVR/store-undef.ll
M llvm/test/CodeGen/AVR/store.ll
M llvm/test/CodeGen/AVR/sub.ll
M llvm/test/CodeGen/AVR/trunc.ll
M llvm/test/CodeGen/AVR/umul-with-overflow.ll
M llvm/test/CodeGen/AVR/umul.with.overflow.i16-bug.ll
M llvm/test/CodeGen/AVR/unaligned-atomic-ops.ll
M llvm/test/CodeGen/AVR/varargs.ll
M llvm/test/CodeGen/AVR/xor.ll
M llvm/test/CodeGen/AVR/zeroreg.ll
M llvm/test/CodeGen/AVR/zext.ll
M llvm/test/CodeGen/BPF/32-bit-subreg-alu.ll
M llvm/test/CodeGen/BPF/32-bit-subreg-cond-select.ll
M llvm/test/CodeGen/BPF/32-bit-subreg-load-store.ll
M llvm/test/CodeGen/BPF/32-bit-subreg-peephole-phi-1.ll
M llvm/test/CodeGen/BPF/32-bit-subreg-peephole-phi-2.ll
M llvm/test/CodeGen/BPF/32-bit-subreg-peephole-phi-3.ll
M llvm/test/CodeGen/BPF/32-bit-subreg-peephole.ll
M llvm/test/CodeGen/BPF/32-bit-subreg-zext.ll
M llvm/test/CodeGen/BPF/BTF/array-1d-char.ll
M llvm/test/CodeGen/BPF/BTF/array-1d-int.ll
M llvm/test/CodeGen/BPF/BTF/array-2d-int.ll
M llvm/test/CodeGen/BPF/BTF/array-size-0.ll
M llvm/test/CodeGen/BPF/BTF/array-typedef.ll
M llvm/test/CodeGen/BPF/BTF/atomics.ll
M llvm/test/CodeGen/BPF/BTF/char-no-debuginfo.ll
M llvm/test/CodeGen/BPF/BTF/char.ll
M llvm/test/CodeGen/BPF/BTF/double.ll
M llvm/test/CodeGen/BPF/BTF/empty-btf.ll
M llvm/test/CodeGen/BPF/BTF/enum-basic.ll
M llvm/test/CodeGen/BPF/BTF/extern-builtin.ll
M llvm/test/CodeGen/BPF/BTF/extern-func-arg.ll
M llvm/test/CodeGen/BPF/BTF/extern-func-ptr.ll
M llvm/test/CodeGen/BPF/BTF/extern-global-var.ll
M llvm/test/CodeGen/BPF/BTF/extern-var-func-weak-section.ll
M llvm/test/CodeGen/BPF/BTF/extern-var-func-weak.ll
M llvm/test/CodeGen/BPF/BTF/extern-var-func.ll
M llvm/test/CodeGen/BPF/BTF/extern-var-func2.ll
M llvm/test/CodeGen/BPF/BTF/extern-var-section.ll
M llvm/test/CodeGen/BPF/BTF/extern-var-struct-weak.ll
M llvm/test/CodeGen/BPF/BTF/extern-var-struct.ll
M llvm/test/CodeGen/BPF/BTF/extern-var-weak-section.ll
M llvm/test/CodeGen/BPF/BTF/filename.ll
M llvm/test/CodeGen/BPF/BTF/float.ll
M llvm/test/CodeGen/BPF/BTF/func-func-ptr.ll
M llvm/test/CodeGen/BPF/BTF/func-non-void.ll
M llvm/test/CodeGen/BPF/BTF/func-source.ll
M llvm/test/CodeGen/BPF/BTF/func-typedef.ll
M llvm/test/CodeGen/BPF/BTF/func-unused-arg.ll
M llvm/test/CodeGen/BPF/BTF/func-void.ll
M llvm/test/CodeGen/BPF/BTF/fwd-no-define.ll
M llvm/test/CodeGen/BPF/BTF/fwd-with-define.ll
M llvm/test/CodeGen/BPF/BTF/global-var-bss-and-data.ll
M llvm/test/CodeGen/BPF/BTF/global-var-inited.ll
M llvm/test/CodeGen/BPF/BTF/global-var-sec-readonly.ll
M llvm/test/CodeGen/BPF/BTF/global-var-sec.ll
M llvm/test/CodeGen/BPF/BTF/incomplete-debuginfo.ll
M llvm/test/CodeGen/BPF/BTF/int.ll
M llvm/test/CodeGen/BPF/BTF/local-var-readonly-1.ll
M llvm/test/CodeGen/BPF/BTF/local-var-readonly-2.ll
M llvm/test/CodeGen/BPF/BTF/local-var.ll
M llvm/test/CodeGen/BPF/BTF/longlong.ll
M llvm/test/CodeGen/BPF/BTF/map-def-2.ll
M llvm/test/CodeGen/BPF/BTF/map-def-3.ll
M llvm/test/CodeGen/BPF/BTF/map-def.ll
M llvm/test/CodeGen/BPF/BTF/pruning-const.ll
M llvm/test/CodeGen/BPF/BTF/pruning-dup-ptr-struct.ll
M llvm/test/CodeGen/BPF/BTF/pruning-multi-derived-type.ll
M llvm/test/CodeGen/BPF/BTF/pruning-typedef.ll
M llvm/test/CodeGen/BPF/BTF/ptr-const-void.ll
M llvm/test/CodeGen/BPF/BTF/ptr-func-1.ll
M llvm/test/CodeGen/BPF/BTF/ptr-func-2.ll
M llvm/test/CodeGen/BPF/BTF/ptr-func-3.ll
M llvm/test/CodeGen/BPF/BTF/ptr-int.ll
M llvm/test/CodeGen/BPF/BTF/ptr-prune-type.ll
M llvm/test/CodeGen/BPF/BTF/ptr-void.ll
M llvm/test/CodeGen/BPF/BTF/ptr-volatile-const-void.ll
M llvm/test/CodeGen/BPF/BTF/ptr-volatile-void.ll
M llvm/test/CodeGen/BPF/BTF/restrict-ptr.ll
M llvm/test/CodeGen/BPF/BTF/short.ll
M llvm/test/CodeGen/BPF/BTF/static-func.ll
M llvm/test/CodeGen/BPF/BTF/static-var-derived-type.ll
M llvm/test/CodeGen/BPF/BTF/static-var-inited-sec.ll
M llvm/test/CodeGen/BPF/BTF/static-var-inited.ll
M llvm/test/CodeGen/BPF/BTF/static-var-readonly-sec.ll
M llvm/test/CodeGen/BPF/BTF/static-var-readonly.ll
M llvm/test/CodeGen/BPF/BTF/static-var-sec.ll
M llvm/test/CodeGen/BPF/BTF/static-var-zerolen-array.ll
M llvm/test/CodeGen/BPF/BTF/static-var.ll
M llvm/test/CodeGen/BPF/BTF/struct-anon-2.ll
M llvm/test/CodeGen/BPF/BTF/struct-anon.ll
M llvm/test/CodeGen/BPF/BTF/struct-basic.ll
M llvm/test/CodeGen/BPF/BTF/struct-bitfield-typedef.ll
M llvm/test/CodeGen/BPF/BTF/struct-enum.ll
M llvm/test/CodeGen/BPF/BTF/tag-1.ll
M llvm/test/CodeGen/BPF/BTF/tag-2.ll
M llvm/test/CodeGen/BPF/BTF/tag-extern-func.ll
M llvm/test/CodeGen/BPF/BTF/tag-typedef.ll
M llvm/test/CodeGen/BPF/BTF/type-tag-fixup-fwd.ll
M llvm/test/CodeGen/BPF/BTF/type-tag-fixup-resolved.ll
M llvm/test/CodeGen/BPF/BTF/type-tag-var.ll
M llvm/test/CodeGen/BPF/BTF/uchar.ll
M llvm/test/CodeGen/BPF/BTF/uint.ll
M llvm/test/CodeGen/BPF/BTF/ulonglong.ll
M llvm/test/CodeGen/BPF/BTF/union-array-typedef.ll
M llvm/test/CodeGen/BPF/BTF/ushort.ll
M llvm/test/CodeGen/BPF/BTF/weak-global-2.ll
M llvm/test/CodeGen/BPF/BTF/weak-global-3.ll
M llvm/test/CodeGen/BPF/BTF/weak-global.ll
M llvm/test/CodeGen/BPF/CORE/field-reloc-st-imm.ll
M llvm/test/CodeGen/BPF/CORE/simplifypatable-nullptr.ll
M llvm/test/CodeGen/BPF/addr-space-cast.ll
M llvm/test/CodeGen/BPF/addr-space-globals.ll
M llvm/test/CodeGen/BPF/addr-space-globals2.ll
M llvm/test/CodeGen/BPF/alu8.ll
M llvm/test/CodeGen/BPF/atomics.ll
M llvm/test/CodeGen/BPF/atomics_2.ll
M llvm/test/CodeGen/BPF/atomics_mem_order_v1.ll
M llvm/test/CodeGen/BPF/atomics_mem_order_v3.ll
M llvm/test/CodeGen/BPF/atomics_sub64_relaxed_v1.ll
M llvm/test/CodeGen/BPF/basictest.ll
M llvm/test/CodeGen/BPF/bpf-fastcall-1.ll
M llvm/test/CodeGen/BPF/bpf-fastcall-2.ll
M llvm/test/CodeGen/BPF/bpf-fastcall-3.ll
M llvm/test/CodeGen/BPF/bpf-fastcall-4.ll
M llvm/test/CodeGen/BPF/bpf-fastcall-5.ll
M llvm/test/CodeGen/BPF/bpf-fastcall-regmask-1.ll
M llvm/test/CodeGen/BPF/bswap.ll
M llvm/test/CodeGen/BPF/byval.ll
M llvm/test/CodeGen/BPF/callx.ll
M llvm/test/CodeGen/BPF/cc_args.ll
M llvm/test/CodeGen/BPF/cc_args_be.ll
M llvm/test/CodeGen/BPF/cc_ret.ll
M llvm/test/CodeGen/BPF/cmp.ll
M llvm/test/CodeGen/BPF/cttz-ctlz.ll
M llvm/test/CodeGen/BPF/dwarfdump.ll
M llvm/test/CodeGen/BPF/ex1.ll
M llvm/test/CodeGen/BPF/fi_ri.ll
M llvm/test/CodeGen/BPF/gotol.ll
M llvm/test/CodeGen/BPF/i128.ll
M llvm/test/CodeGen/BPF/inline_asm.ll
M llvm/test/CodeGen/BPF/inlineasm-wreg.ll
M llvm/test/CodeGen/BPF/intrinsics.ll
M llvm/test/CodeGen/BPF/is_trunc_free.ll
M llvm/test/CodeGen/BPF/is_zext_free.ll
M llvm/test/CodeGen/BPF/ldsx.ll
M llvm/test/CodeGen/BPF/load.ll
M llvm/test/CodeGen/BPF/loops.ll
M llvm/test/CodeGen/BPF/many_args1.ll
M llvm/test/CodeGen/BPF/many_args2.ll
M llvm/test/CodeGen/BPF/mem_offset.ll
M llvm/test/CodeGen/BPF/mem_offset_be.ll
M llvm/test/CodeGen/BPF/memcmp.ll
M llvm/test/CodeGen/BPF/memcpy-expand-in-order.ll
M llvm/test/CodeGen/BPF/movsx.ll
M llvm/test/CodeGen/BPF/no-merge-attr.ll
M llvm/test/CodeGen/BPF/optnone-1.ll
M llvm/test/CodeGen/BPF/optnone-2.ll
M llvm/test/CodeGen/BPF/remove_truncate_1.ll
M llvm/test/CodeGen/BPF/remove_truncate_2.ll
M llvm/test/CodeGen/BPF/remove_truncate_3.ll
M llvm/test/CodeGen/BPF/remove_truncate_4.ll
M llvm/test/CodeGen/BPF/remove_truncate_5.ll
M llvm/test/CodeGen/BPF/remove_truncate_6.ll
M llvm/test/CodeGen/BPF/remove_truncate_7.ll
M llvm/test/CodeGen/BPF/remove_truncate_8.ll
M llvm/test/CodeGen/BPF/remove_truncate_9.ll
M llvm/test/CodeGen/BPF/rodata_1.ll
M llvm/test/CodeGen/BPF/rodata_2.ll
M llvm/test/CodeGen/BPF/rodata_3.ll
M llvm/test/CodeGen/BPF/rodata_4.ll
M llvm/test/CodeGen/BPF/rodata_5.ll
M llvm/test/CodeGen/BPF/rodata_6.ll
M llvm/test/CodeGen/BPF/rodata_7.ll
M llvm/test/CodeGen/BPF/sdiv_smod.ll
M llvm/test/CodeGen/BPF/sdiv_to_mul.ll
M llvm/test/CodeGen/BPF/select_ri.ll
M llvm/test/CodeGen/BPF/selectiondag-bug.ll
M llvm/test/CodeGen/BPF/setcc.ll
M llvm/test/CodeGen/BPF/shifts.ll
M llvm/test/CodeGen/BPF/sockex2.ll
M llvm/test/CodeGen/BPF/spill-alu32.ll
M llvm/test/CodeGen/BPF/store_imm.ll
M llvm/test/CodeGen/BPF/struct-arg.ll
M llvm/test/CodeGen/BPF/struct_ret1.ll
M llvm/test/CodeGen/BPF/struct_ret2.ll
M llvm/test/CodeGen/BPF/undef.ll
M llvm/test/CodeGen/BPF/vararg1.ll
M llvm/test/CodeGen/BPF/warn-call.ll
M llvm/test/CodeGen/BPF/warn-stack.ll
M llvm/test/CodeGen/BPF/xadd.ll
M llvm/test/CodeGen/BPF/xadd_legal.ll
M llvm/test/CodeGen/BPF/xaddd_v1.ll
M llvm/test/CodeGen/Hexagon/64bit_tstbit.ll
M llvm/test/CodeGen/Hexagon/Atomics.ll
M llvm/test/CodeGen/Hexagon/BranchPredict.ll
M llvm/test/CodeGen/Hexagon/Halide_vec_cast_trunc1.ll
M llvm/test/CodeGen/Hexagon/Halide_vec_cast_trunc2.ll
M llvm/test/CodeGen/Hexagon/M4_mpyri_addi_global.ll
M llvm/test/CodeGen/Hexagon/M4_mpyrr_addi_global.ll
M llvm/test/CodeGen/Hexagon/NVJumpCmp.ll
M llvm/test/CodeGen/Hexagon/P08214.ll
M llvm/test/CodeGen/Hexagon/PR33749.ll
M llvm/test/CodeGen/Hexagon/SUnit-boundary-prob.ll
M llvm/test/CodeGen/Hexagon/V60-VDblNew.ll
M llvm/test/CodeGen/Hexagon/abi-padding-2.ll
M llvm/test/CodeGen/Hexagon/abi-padding.ll
M llvm/test/CodeGen/Hexagon/abs.ll
M llvm/test/CodeGen/Hexagon/absaddr-store.ll
M llvm/test/CodeGen/Hexagon/absimm.ll
M llvm/test/CodeGen/Hexagon/add-use.ll
M llvm/test/CodeGen/Hexagon/add_int_double.ll
M llvm/test/CodeGen/Hexagon/add_mpi_RRR.ll
M llvm/test/CodeGen/Hexagon/addaddi.ll
M llvm/test/CodeGen/Hexagon/addasl-address.ll
M llvm/test/CodeGen/Hexagon/addh-sext-trunc.ll
M llvm/test/CodeGen/Hexagon/addh-shifted.ll
M llvm/test/CodeGen/Hexagon/addh.ll
M llvm/test/CodeGen/Hexagon/addr-calc-opt.ll
M llvm/test/CodeGen/Hexagon/addr-mode-opt.ll
M llvm/test/CodeGen/Hexagon/addrmode-align.ll
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M llvm/test/CodeGen/Hexagon/addrmode-immop.mir
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M llvm/test/CodeGen/Hexagon/addrmode-keepdeadphis.ll
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M llvm/test/CodeGen/Hexagon/addrmode-opt-assert.mir
M llvm/test/CodeGen/Hexagon/addrmode-rr-to-io.mir
M llvm/test/CodeGen/Hexagon/addsubcarry.ll
M llvm/test/CodeGen/Hexagon/adjust-latency-stackST.ll
M llvm/test/CodeGen/Hexagon/aggr-antidep-tied.ll
M llvm/test/CodeGen/Hexagon/aggr-copy-order.ll
M llvm/test/CodeGen/Hexagon/aggr-licm.ll
M llvm/test/CodeGen/Hexagon/aggressive_licm.ll
M llvm/test/CodeGen/Hexagon/align_Os.ll
M llvm/test/CodeGen/Hexagon/align_test.ll
M llvm/test/CodeGen/Hexagon/alu64.ll
M llvm/test/CodeGen/Hexagon/always-ext.ll
M llvm/test/CodeGen/Hexagon/anti-dep-partial.mir
M llvm/test/CodeGen/Hexagon/args.ll
M llvm/test/CodeGen/Hexagon/ashift-left-right.ll
M llvm/test/CodeGen/Hexagon/asr-rnd.ll
M llvm/test/CodeGen/Hexagon/asr-rnd64.ll
M llvm/test/CodeGen/Hexagon/assert-postinc-ptr-not-value.ll
M llvm/test/CodeGen/Hexagon/atomic-opaque-basic.ll
M llvm/test/CodeGen/Hexagon/atomic-rmw-add.ll
M llvm/test/CodeGen/Hexagon/atomicrmw-cond-sub-clamp.ll
M llvm/test/CodeGen/Hexagon/atomicrmw-uinc-udec-wrap.ll
M llvm/test/CodeGen/Hexagon/autohvx/abs.ll
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M llvm/test/CodeGen/Hexagon/autohvx/arith.ll
M llvm/test/CodeGen/Hexagon/autohvx/bitcount-128b.ll
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M llvm/test/CodeGen/Hexagon/autohvx/bitwise-pred-128b.ll
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M llvm/test/CodeGen/Hexagon/autohvx/bswap.ll
M llvm/test/CodeGen/Hexagon/autohvx/build-vector-float-type.ll
M llvm/test/CodeGen/Hexagon/autohvx/build-vector-i32-128b.ll
M llvm/test/CodeGen/Hexagon/autohvx/build-vector-i32-64b.ll
M llvm/test/CodeGen/Hexagon/autohvx/build-vector-i32-type.ll
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M llvm/test/CodeGen/Hexagon/autohvx/concat-vectors-128b.ll
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M llvm/test/CodeGen/Hexagon/autohvx/contract-128b.ll
M llvm/test/CodeGen/Hexagon/autohvx/contract-64b.ll
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M llvm/test/CodeGen/Hexagon/autohvx/conv-fp-int-ieee.ll
M llvm/test/CodeGen/Hexagon/autohvx/ctpop-split.ll
M llvm/test/CodeGen/Hexagon/autohvx/deal-128b.ll
M llvm/test/CodeGen/Hexagon/autohvx/deal-64b.ll
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M llvm/test/CodeGen/Hexagon/autohvx/delta-64b.ll
M llvm/test/CodeGen/Hexagon/autohvx/delta2-64b.ll
M llvm/test/CodeGen/Hexagon/autohvx/extract-element.ll
M llvm/test/CodeGen/Hexagon/autohvx/float-cost.ll
M llvm/test/CodeGen/Hexagon/autohvx/fp-to-int.ll
M llvm/test/CodeGen/Hexagon/autohvx/funnel-128b.ll
M llvm/test/CodeGen/Hexagon/autohvx/hfinsert.ll
M llvm/test/CodeGen/Hexagon/autohvx/hvx-idiom-empty-results.ll
M llvm/test/CodeGen/Hexagon/autohvx/int-to-fp.ll
M llvm/test/CodeGen/Hexagon/autohvx/interleave.ll
M llvm/test/CodeGen/Hexagon/autohvx/isel-anyext-inreg.ll
M llvm/test/CodeGen/Hexagon/autohvx/isel-anyext-pair.ll
M llvm/test/CodeGen/Hexagon/autohvx/isel-bitcast-vsplat.ll
M llvm/test/CodeGen/Hexagon/autohvx/isel-bitcast-vsplat2.ll
M llvm/test/CodeGen/Hexagon/autohvx/isel-bool-vector.ll
M llvm/test/CodeGen/Hexagon/autohvx/isel-build-undef.ll
M llvm/test/CodeGen/Hexagon/autohvx/isel-build-vector.ll
M llvm/test/CodeGen/Hexagon/autohvx/isel-concat-multiple.ll
M llvm/test/CodeGen/Hexagon/autohvx/isel-concat-vectors-bool.ll
M llvm/test/CodeGen/Hexagon/autohvx/isel-concat-vectors.ll
M llvm/test/CodeGen/Hexagon/autohvx/isel-const-splat-bitcast.ll
M llvm/test/CodeGen/Hexagon/autohvx/isel-const-splat-imm.ll
M llvm/test/CodeGen/Hexagon/autohvx/isel-const-splat.ll
M llvm/test/CodeGen/Hexagon/autohvx/isel-const-vector.ll
M llvm/test/CodeGen/Hexagon/autohvx/isel-expand-unaligned-loads-noindexed.ll
M llvm/test/CodeGen/Hexagon/autohvx/isel-expand-unaligned-loads.ll
M llvm/test/CodeGen/Hexagon/autohvx/isel-extractelt-illegal-type.ll
M llvm/test/CodeGen/Hexagon/autohvx/isel-hvx-concat-truncate.ll
M llvm/test/CodeGen/Hexagon/autohvx/isel-hvx-pred-bitcast.ll
M llvm/test/CodeGen/Hexagon/autohvx/isel-insert-subvector-v4i8.ll
M llvm/test/CodeGen/Hexagon/autohvx/isel-intrinsics.ll
M llvm/test/CodeGen/Hexagon/autohvx/isel-mstore-fp16.ll
M llvm/test/CodeGen/Hexagon/autohvx/isel-q-legalization-loop.ll
M llvm/test/CodeGen/Hexagon/autohvx/isel-q2v-pair.ll
M llvm/test/CodeGen/Hexagon/autohvx/isel-qfalse.ll
M llvm/test/CodeGen/Hexagon/autohvx/isel-select-const.ll
M llvm/test/CodeGen/Hexagon/autohvx/isel-select-q.ll
M llvm/test/CodeGen/Hexagon/autohvx/isel-setcc-pair-fp.ll
M llvm/test/CodeGen/Hexagon/autohvx/isel-setcc-pair.ll
M llvm/test/CodeGen/Hexagon/autohvx/isel-setcc-v256i1.ll
M llvm/test/CodeGen/Hexagon/autohvx/isel-sext-inreg.ll
M llvm/test/CodeGen/Hexagon/autohvx/isel-shift-byte.ll
M llvm/test/CodeGen/Hexagon/autohvx/isel-shuff-single.ll
M llvm/test/CodeGen/Hexagon/autohvx/isel-shuffle-gather.ll
M llvm/test/CodeGen/Hexagon/autohvx/isel-shuffle-isdisel.ll
M llvm/test/CodeGen/Hexagon/autohvx/isel-shuffle-no-perfect-completion.ll
M llvm/test/CodeGen/Hexagon/autohvx/isel-shuffle-pack.ll
M llvm/test/CodeGen/Hexagon/autohvx/isel-split-masked.ll
M llvm/test/CodeGen/Hexagon/autohvx/isel-store-bitcast-v128i1.ll
M llvm/test/CodeGen/Hexagon/autohvx/isel-truncate-legal.ll
M llvm/test/CodeGen/Hexagon/autohvx/isel-truncate.ll
M llvm/test/CodeGen/Hexagon/autohvx/isel-undef-not-zero.ll
M llvm/test/CodeGen/Hexagon/autohvx/isel-vec-ext.ll
M llvm/test/CodeGen/Hexagon/autohvx/isel-vpackew.ll
M llvm/test/CodeGen/Hexagon/autohvx/isel-vsplat-pair.ll
M llvm/test/CodeGen/Hexagon/autohvx/isel-widen-memop.ll
M llvm/test/CodeGen/Hexagon/autohvx/isel-widen-store.ll
M llvm/test/CodeGen/Hexagon/autohvx/isel-widen-truncate-illegal-elem.ll
M llvm/test/CodeGen/Hexagon/autohvx/isel-widen-truncate-op.ll
M llvm/test/CodeGen/Hexagon/autohvx/isel-widen-truncate-pair.ll
M llvm/test/CodeGen/Hexagon/autohvx/isel-widen-truncate.ll
M llvm/test/CodeGen/Hexagon/autohvx/logical-128b.ll
M llvm/test/CodeGen/Hexagon/autohvx/logical-64b.ll
M llvm/test/CodeGen/Hexagon/autohvx/lower-insert-elt.ll
M llvm/test/CodeGen/Hexagon/autohvx/masked-vmem-basic.ll
M llvm/test/CodeGen/Hexagon/autohvx/maximize-bandwidth.ll
M llvm/test/CodeGen/Hexagon/autohvx/minmax-128b.ll
M llvm/test/CodeGen/Hexagon/autohvx/minmax-64b.ll
M llvm/test/CodeGen/Hexagon/autohvx/minmax-float.ll
M llvm/test/CodeGen/Hexagon/autohvx/mulh.ll
M llvm/test/CodeGen/Hexagon/autohvx/non-simple-hvx-type.ll
M llvm/test/CodeGen/Hexagon/autohvx/perfect-single.ll
M llvm/test/CodeGen/Hexagon/autohvx/pred-vmem-128b.ll
M llvm/test/CodeGen/Hexagon/autohvx/pred-vmem-64b.ll
M llvm/test/CodeGen/Hexagon/autohvx/qmul-add-over-32-bit.ll
M llvm/test/CodeGen/Hexagon/autohvx/qmul-chop.ll
M llvm/test/CodeGen/Hexagon/autohvx/qmul.ll
M llvm/test/CodeGen/Hexagon/autohvx/reg-sequence.ll
M llvm/test/CodeGen/Hexagon/autohvx/shift-128b.ll
M llvm/test/CodeGen/Hexagon/autohvx/shift-64b.ll
M llvm/test/CodeGen/Hexagon/autohvx/shuff-128b.ll
M llvm/test/CodeGen/Hexagon/autohvx/shuff-64b.ll
M llvm/test/CodeGen/Hexagon/autohvx/shuff-combos-128b.ll
M llvm/test/CodeGen/Hexagon/autohvx/shuff-combos-64b.ll
M llvm/test/CodeGen/Hexagon/autohvx/shuff-perfect-inverted-pair.ll
M llvm/test/CodeGen/Hexagon/autohvx/shuff-single.ll
M llvm/test/CodeGen/Hexagon/autohvx/shuffle-expanding-128b.ll
M llvm/test/CodeGen/Hexagon/autohvx/shuffle-expanding-64b.ll
M llvm/test/CodeGen/Hexagon/autohvx/shuffle-half-128b.ll
M llvm/test/CodeGen/Hexagon/autohvx/shuffle-half-64b.ll
M llvm/test/CodeGen/Hexagon/autohvx/splat.ll
M llvm/test/CodeGen/Hexagon/autohvx/vdd0.ll
M llvm/test/CodeGen/Hexagon/autohvx/vector-align-addr.ll
M llvm/test/CodeGen/Hexagon/autohvx/vector-align-bad-move.ll
M llvm/test/CodeGen/Hexagon/autohvx/vector-align-bad-move3.ll
M llvm/test/CodeGen/Hexagon/autohvx/vector-align-base-type-mismatch.ll
M llvm/test/CodeGen/Hexagon/autohvx/vector-align-basic.ll
M llvm/test/CodeGen/Hexagon/autohvx/vector-align-interleaved.ll
M llvm/test/CodeGen/Hexagon/autohvx/vector-align-only-phi-use.ll
M llvm/test/CodeGen/Hexagon/autohvx/vector-align-order.ll
M llvm/test/CodeGen/Hexagon/autohvx/vector-align-rescale-nonint.ll
M llvm/test/CodeGen/Hexagon/autohvx/vector-align-scalar-mask.ll
M llvm/test/CodeGen/Hexagon/autohvx/vector-align-store-mask.ll
M llvm/test/CodeGen/Hexagon/autohvx/vector-align-store.ll
M llvm/test/CodeGen/Hexagon/autohvx/vector-align-terminator.ll
M llvm/test/CodeGen/Hexagon/autohvx/vector-align-use-in-different-block.ll
M llvm/test/CodeGen/Hexagon/autohvx/vector-compare-128b.ll
M llvm/test/CodeGen/Hexagon/autohvx/vector-compare-64b.ll
M llvm/test/CodeGen/Hexagon/autohvx/vector-compare-float.ll
M llvm/test/CodeGen/Hexagon/autohvx/vector-load-store-basic.ll
M llvm/test/CodeGen/Hexagon/autohvx/vector-predicate-typecast.ll
M llvm/test/CodeGen/Hexagon/autohvx/vext-128b.ll
M llvm/test/CodeGen/Hexagon/autohvx/vext-64b.ll
M llvm/test/CodeGen/Hexagon/autohvx/vmpy-parts.ll
M llvm/test/CodeGen/Hexagon/autohvx/vmux-order.ll
M llvm/test/CodeGen/Hexagon/autohvx/widen-ext.ll
M llvm/test/CodeGen/Hexagon/autohvx/widen-setcc.ll
M llvm/test/CodeGen/Hexagon/autohvx/widen-trunc.ll
M llvm/test/CodeGen/Hexagon/avoid-predspill-calleesaved.ll
M llvm/test/CodeGen/Hexagon/avoid-predspill.ll
M llvm/test/CodeGen/Hexagon/avoidVectorLowering.ll
M llvm/test/CodeGen/Hexagon/bank-conflict-load.mir
M llvm/test/CodeGen/Hexagon/bank-conflict.mir
M llvm/test/CodeGen/Hexagon/barrier-flag.ll
M llvm/test/CodeGen/Hexagon/base-offset-addr.ll
M llvm/test/CodeGen/Hexagon/base-offset-post.ll
M llvm/test/CodeGen/Hexagon/base-offset-stv4.ll
M llvm/test/CodeGen/Hexagon/bit-addr-align.mir
M llvm/test/CodeGen/Hexagon/bit-bitsplit-at.ll
M llvm/test/CodeGen/Hexagon/bit-bitsplit-regclass.ll
M llvm/test/CodeGen/Hexagon/bit-bitsplit-src.ll
M llvm/test/CodeGen/Hexagon/bit-bitsplit.ll
M llvm/test/CodeGen/Hexagon/bit-cmp0.mir
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M llvm/test/CodeGen/Hexagon/bit-ext-sat.ll
M llvm/test/CodeGen/Hexagon/bit-extract-off.ll
M llvm/test/CodeGen/Hexagon/bit-extract.ll
M llvm/test/CodeGen/Hexagon/bit-extractu-half.ll
M llvm/test/CodeGen/Hexagon/bit-gen-rseq.ll
M llvm/test/CodeGen/Hexagon/bit-has.ll
M llvm/test/CodeGen/Hexagon/bit-loop-rc-mismatch.ll
M llvm/test/CodeGen/Hexagon/bit-loop.ll
M llvm/test/CodeGen/Hexagon/bit-phi.ll
M llvm/test/CodeGen/Hexagon/bit-rie.ll
M llvm/test/CodeGen/Hexagon/bit-skip-byval.ll
M llvm/test/CodeGen/Hexagon/bit-store-upper-sub-hi.mir
M llvm/test/CodeGen/Hexagon/bit-validate-reg.ll
M llvm/test/CodeGen/Hexagon/bit-visit-flowq.ll
M llvm/test/CodeGen/Hexagon/bitcast-i128-to-v128i1.ll
M llvm/test/CodeGen/Hexagon/bitconvert-vector.ll
M llvm/test/CodeGen/Hexagon/bitmanip.ll
M llvm/test/CodeGen/Hexagon/bkfir.ll
M llvm/test/CodeGen/Hexagon/block-addr.ll
M llvm/test/CodeGen/Hexagon/block-address.ll
M llvm/test/CodeGen/Hexagon/block-ranges-nodef.ll
M llvm/test/CodeGen/Hexagon/blockaddr-fpic.ll
M llvm/test/CodeGen/Hexagon/branch-folder-hoist-kills.mir
M llvm/test/CodeGen/Hexagon/branch-non-mbb.ll
M llvm/test/CodeGen/Hexagon/branchfolder-insert-impdef.mir
M llvm/test/CodeGen/Hexagon/branchfolder-keep-impdef.ll
M llvm/test/CodeGen/Hexagon/brcond-setne.ll
M llvm/test/CodeGen/Hexagon/brev_ld.ll
M llvm/test/CodeGen/Hexagon/brev_st.ll
M llvm/test/CodeGen/Hexagon/bss-local.ll
M llvm/test/CodeGen/Hexagon/bug-aa4463-ifconv-vecpred.ll
M llvm/test/CodeGen/Hexagon/bug-allocframe-size.ll
M llvm/test/CodeGen/Hexagon/bug-hcp-tied-kill.ll
M llvm/test/CodeGen/Hexagon/bug14859-iv-cleanup-lpad.ll
M llvm/test/CodeGen/Hexagon/bug14859-split-const-block-addr.ll
M llvm/test/CodeGen/Hexagon/bug15515-shuffle.ll
M llvm/test/CodeGen/Hexagon/bug17276.ll
M llvm/test/CodeGen/Hexagon/bug17386.ll
M llvm/test/CodeGen/Hexagon/bug18008.ll
M llvm/test/CodeGen/Hexagon/bug18491-optsize.ll
M llvm/test/CodeGen/Hexagon/bug19076.ll
M llvm/test/CodeGen/Hexagon/bug19119.ll
M llvm/test/CodeGen/Hexagon/bug19254-ifconv-vec.ll
M llvm/test/CodeGen/Hexagon/bug27085.ll
M llvm/test/CodeGen/Hexagon/bug31839.ll
M llvm/test/CodeGen/Hexagon/bug6757-endloop.ll
M llvm/test/CodeGen/Hexagon/bug9049.ll
M llvm/test/CodeGen/Hexagon/bug9963.ll
M llvm/test/CodeGen/Hexagon/bugAsmHWloop.ll
M llvm/test/CodeGen/Hexagon/build-vector-shuffle.ll
M llvm/test/CodeGen/Hexagon/build-vector-v4i8-zext.ll
M llvm/test/CodeGen/Hexagon/builtin-expect.ll
M llvm/test/CodeGen/Hexagon/builtin-prefetch-offset.ll
M llvm/test/CodeGen/Hexagon/builtin-prefetch.ll
M llvm/test/CodeGen/Hexagon/call-long1.ll
M llvm/test/CodeGen/Hexagon/call-ret-i1.ll
M llvm/test/CodeGen/Hexagon/call-v4.ll
M llvm/test/CodeGen/Hexagon/callR_noreturn.ll
M llvm/test/CodeGen/Hexagon/calling-conv-2.ll
M llvm/test/CodeGen/Hexagon/calling-conv.ll
M llvm/test/CodeGen/Hexagon/callr-dep-edge.ll
M llvm/test/CodeGen/Hexagon/cext-check.ll
M llvm/test/CodeGen/Hexagon/cext-ice.ll
M llvm/test/CodeGen/Hexagon/cext-opt-basic.mir
M llvm/test/CodeGen/Hexagon/cext-opt-block-addr.mir
M llvm/test/CodeGen/Hexagon/cext-opt-negative-fi.mir
M llvm/test/CodeGen/Hexagon/cext-opt-numops.mir
M llvm/test/CodeGen/Hexagon/cext-opt-range-assert.mir
M llvm/test/CodeGen/Hexagon/cext-opt-range-offset.mir
M llvm/test/CodeGen/Hexagon/cext-opt-shifted-range.mir
M llvm/test/CodeGen/Hexagon/cext-opt-stack-no-rr.mir
M llvm/test/CodeGen/Hexagon/cext-unnamed-global.mir
M llvm/test/CodeGen/Hexagon/cext-valid-packet1.ll
M llvm/test/CodeGen/Hexagon/cext-valid-packet2.ll
M llvm/test/CodeGen/Hexagon/cext.ll
M llvm/test/CodeGen/Hexagon/cexti16.ll
M llvm/test/CodeGen/Hexagon/cfgopt-fall-through.ll
M llvm/test/CodeGen/Hexagon/cfi-late-and-regpressure-init.ll
M llvm/test/CodeGen/Hexagon/cfi-late.ll
M llvm/test/CodeGen/Hexagon/cfi-offset.ll
M llvm/test/CodeGen/Hexagon/cfi_offset.ll
M llvm/test/CodeGen/Hexagon/cfi_offset2.ll
M llvm/test/CodeGen/Hexagon/check-dot-new.ll
M llvm/test/CodeGen/Hexagon/check-subregister-for-latency.ll
M llvm/test/CodeGen/Hexagon/checktabs.ll
M llvm/test/CodeGen/Hexagon/circ-load-isel.ll
M llvm/test/CodeGen/Hexagon/circ_ld.ll
M llvm/test/CodeGen/Hexagon/circ_ldd_bug.ll
M llvm/test/CodeGen/Hexagon/circ_ldw.ll
M llvm/test/CodeGen/Hexagon/circ_new.ll
M llvm/test/CodeGen/Hexagon/circ_pcr_assert.ll
M llvm/test/CodeGen/Hexagon/circ_st.ll
M llvm/test/CodeGen/Hexagon/clr_set_toggle.ll
M llvm/test/CodeGen/Hexagon/cmp-extend.ll
M llvm/test/CodeGen/Hexagon/cmp-promote.ll
M llvm/test/CodeGen/Hexagon/cmp-to-genreg.ll
M llvm/test/CodeGen/Hexagon/cmp-to-predreg.ll
M llvm/test/CodeGen/Hexagon/cmp_pred.ll
M llvm/test/CodeGen/Hexagon/cmp_pred2.ll
M llvm/test/CodeGen/Hexagon/cmp_pred_reg.ll
M llvm/test/CodeGen/Hexagon/cmpb-dec-imm.ll
M llvm/test/CodeGen/Hexagon/cmpb-eq.ll
M llvm/test/CodeGen/Hexagon/cmpb_gtu.ll
M llvm/test/CodeGen/Hexagon/cmpb_pred.ll
M llvm/test/CodeGen/Hexagon/cmpbeq.ll
M llvm/test/CodeGen/Hexagon/cmph-gtu.ll
M llvm/test/CodeGen/Hexagon/cmpy-round.ll
M llvm/test/CodeGen/Hexagon/coalesce_tfri.ll
M llvm/test/CodeGen/Hexagon/coalescing-hvx-across-calls.ll
M llvm/test/CodeGen/Hexagon/combine-imm-ext.ll
M llvm/test/CodeGen/Hexagon/combine-imm-ext2.ll
M llvm/test/CodeGen/Hexagon/combine.ll
M llvm/test/CodeGen/Hexagon/combine_ir.ll
M llvm/test/CodeGen/Hexagon/combine_lh.ll
M llvm/test/CodeGen/Hexagon/combiner-lts.ll
M llvm/test/CodeGen/Hexagon/common-gep-basic.ll
M llvm/test/CodeGen/Hexagon/common-gep-icm.ll
M llvm/test/CodeGen/Hexagon/common-gep-inbounds.ll
M llvm/test/CodeGen/Hexagon/common-global-addr.ll
M llvm/test/CodeGen/Hexagon/concat-vectors-legalize.ll
M llvm/test/CodeGen/Hexagon/const-combine.ll
M llvm/test/CodeGen/Hexagon/const-pool-tf.ll
M llvm/test/CodeGen/Hexagon/constant_compound.ll
M llvm/test/CodeGen/Hexagon/constext-call.ll
M llvm/test/CodeGen/Hexagon/constext-immstore.ll
M llvm/test/CodeGen/Hexagon/constext-replace.ll
M llvm/test/CodeGen/Hexagon/constp-andir-global.mir
M llvm/test/CodeGen/Hexagon/constp-clb.ll
M llvm/test/CodeGen/Hexagon/constp-combine-neg.ll
M llvm/test/CodeGen/Hexagon/constp-ctb.ll
M llvm/test/CodeGen/Hexagon/constp-extract.ll
M llvm/test/CodeGen/Hexagon/constp-rewrite-branches.ll
M llvm/test/CodeGen/Hexagon/constp-rseq.ll
M llvm/test/CodeGen/Hexagon/constp-vsplat.ll
M llvm/test/CodeGen/Hexagon/convert_const_i1_to_i8.ll
M llvm/test/CodeGen/Hexagon/convertdptoint.ll
M llvm/test/CodeGen/Hexagon/convertdptoll.ll
M llvm/test/CodeGen/Hexagon/convertsptoint.ll
M llvm/test/CodeGen/Hexagon/convertsptoll.ll
M llvm/test/CodeGen/Hexagon/copy-to-combine-const64.mir
M llvm/test/CodeGen/Hexagon/copy-to-combine-dbg.ll
M llvm/test/CodeGen/Hexagon/count_0s.ll
M llvm/test/CodeGen/Hexagon/countbits-basic.ll
M llvm/test/CodeGen/Hexagon/csr-func-usedef.ll
M llvm/test/CodeGen/Hexagon/csr_stub_calls_dwarf_frame_info.ll
M llvm/test/CodeGen/Hexagon/ctor.ll
M llvm/test/CodeGen/Hexagon/dadd.ll
M llvm/test/CodeGen/Hexagon/dag-combine-select-or0.ll
M llvm/test/CodeGen/Hexagon/dag-indexed.ll
M llvm/test/CodeGen/Hexagon/dccleana.ll
M llvm/test/CodeGen/Hexagon/dead-store-stack.ll
M llvm/test/CodeGen/Hexagon/dealloc-store.ll
M llvm/test/CodeGen/Hexagon/dealloc_return.ll
M llvm/test/CodeGen/Hexagon/debug-line_table_start.ll
M llvm/test/CodeGen/Hexagon/debug-prologue-loc.ll
M llvm/test/CodeGen/Hexagon/debug-prologue.ll
M llvm/test/CodeGen/Hexagon/def-undef-deps.ll
M llvm/test/CodeGen/Hexagon/default-align.ll
M llvm/test/CodeGen/Hexagon/deflate.ll
M llvm/test/CodeGen/Hexagon/df-min-max.ll
M llvm/test/CodeGen/Hexagon/dfp.ll
M llvm/test/CodeGen/Hexagon/dhry.ll
M llvm/test/CodeGen/Hexagon/dhry_proc8.ll
M llvm/test/CodeGen/Hexagon/dhry_stall.ll
M llvm/test/CodeGen/Hexagon/disable-const64.ll
M llvm/test/CodeGen/Hexagon/dmul.ll
M llvm/test/CodeGen/Hexagon/dont_rotate_pregs_at_O2.ll
M llvm/test/CodeGen/Hexagon/double.ll
M llvm/test/CodeGen/Hexagon/dsub.ll
M llvm/test/CodeGen/Hexagon/duplex-addi-global-imm.mir
M llvm/test/CodeGen/Hexagon/dwarf-discriminator.ll
M llvm/test/CodeGen/Hexagon/early-if-conv-lifetime.mir
M llvm/test/CodeGen/Hexagon/early-if-conversion-bug1.ll
M llvm/test/CodeGen/Hexagon/early-if-debug.mir
M llvm/test/CodeGen/Hexagon/early-if-low8.mir
M llvm/test/CodeGen/Hexagon/early-if-merge-loop.ll
M llvm/test/CodeGen/Hexagon/early-if-phi-i1.ll
M llvm/test/CodeGen/Hexagon/early-if-predicator.mir
M llvm/test/CodeGen/Hexagon/early-if-spare.ll
M llvm/test/CodeGen/Hexagon/early-if-vecpi.ll
M llvm/test/CodeGen/Hexagon/early-if-vecpred.ll
M llvm/test/CodeGen/Hexagon/early-if.ll
M llvm/test/CodeGen/Hexagon/eh_return-r30.ll
M llvm/test/CodeGen/Hexagon/eh_return.ll
M llvm/test/CodeGen/Hexagon/eh_save_restore.ll
M llvm/test/CodeGen/Hexagon/ehabi.ll
M llvm/test/CodeGen/Hexagon/eliminate-pred-spill.ll
M llvm/test/CodeGen/Hexagon/entryBB-isLoopHdr.ll
M llvm/test/CodeGen/Hexagon/expand-condsets-basic.ll
M llvm/test/CodeGen/Hexagon/expand-condsets-copy-lis.ll
M llvm/test/CodeGen/Hexagon/expand-condsets-dead-bad.ll
M llvm/test/CodeGen/Hexagon/expand-condsets-dead-pred.ll
M llvm/test/CodeGen/Hexagon/expand-condsets-dead.ll
M llvm/test/CodeGen/Hexagon/expand-condsets-def-undef.mir
M llvm/test/CodeGen/Hexagon/expand-condsets-extend.ll
M llvm/test/CodeGen/Hexagon/expand-condsets-imm.mir
M llvm/test/CodeGen/Hexagon/expand-condsets-impuse.mir
M llvm/test/CodeGen/Hexagon/expand-condsets-impuse2.mir
M llvm/test/CodeGen/Hexagon/expand-condsets-phys-reg.mir
M llvm/test/CodeGen/Hexagon/expand-condsets-pred-undef.ll
M llvm/test/CodeGen/Hexagon/expand-condsets-pred-undef2.ll
M llvm/test/CodeGen/Hexagon/expand-condsets-rm-reg.mir
M llvm/test/CodeGen/Hexagon/expand-condsets-rm-segment.ll
M llvm/test/CodeGen/Hexagon/expand-condsets-same-inputs.mir
M llvm/test/CodeGen/Hexagon/expand-condsets-undef2.ll
M llvm/test/CodeGen/Hexagon/expand-condsets-undefvni.ll
M llvm/test/CodeGen/Hexagon/expand-condsets.ll
M llvm/test/CodeGen/Hexagon/expand-copyw-undef.mir
M llvm/test/CodeGen/Hexagon/expand-vselect-kill.mir
M llvm/test/CodeGen/Hexagon/expand-vstorerw-undef.ll
M llvm/test/CodeGen/Hexagon/expand-vstorerw-undef2.ll
M llvm/test/CodeGen/Hexagon/expand-wselect.mir
M llvm/test/CodeGen/Hexagon/extload-combine.ll
M llvm/test/CodeGen/Hexagon/extract-basic.ll
M llvm/test/CodeGen/Hexagon/extract_0bits.ll
M llvm/test/CodeGen/Hexagon/extractu_0bits.ll
M llvm/test/CodeGen/Hexagon/fadd.ll
M llvm/test/CodeGen/Hexagon/fcmp.ll
M llvm/test/CodeGen/Hexagon/feature-compound.ll
M llvm/test/CodeGen/Hexagon/feature-memops.ll
M llvm/test/CodeGen/Hexagon/find-loop-instr.ll
M llvm/test/CodeGen/Hexagon/find-loop.ll
M llvm/test/CodeGen/Hexagon/fixed-spill-mutable.ll
M llvm/test/CodeGen/Hexagon/float-amode.ll
M llvm/test/CodeGen/Hexagon/float-bitcast.ll
M llvm/test/CodeGen/Hexagon/float-const64-G0.ll
M llvm/test/CodeGen/Hexagon/float-gen-cmpop.ll
M llvm/test/CodeGen/Hexagon/float.ll
M llvm/test/CodeGen/Hexagon/floatconvert-ieee-rnd-near.ll
M llvm/test/CodeGen/Hexagon/fltnvjump.ll
M llvm/test/CodeGen/Hexagon/fmadd.ll
M llvm/test/CodeGen/Hexagon/fminmax.ll
M llvm/test/CodeGen/Hexagon/fmul-v67.ll
M llvm/test/CodeGen/Hexagon/fmul.ll
M llvm/test/CodeGen/Hexagon/formal-args-i1.ll
M llvm/test/CodeGen/Hexagon/fp16.ll
M llvm/test/CodeGen/Hexagon/fp_latency.ll
M llvm/test/CodeGen/Hexagon/fpelim-basic.ll
M llvm/test/CodeGen/Hexagon/frame-offset-overflow.ll
M llvm/test/CodeGen/Hexagon/fsel.ll
M llvm/test/CodeGen/Hexagon/fsub.ll
M llvm/test/CodeGen/Hexagon/funnel-shift.ll
M llvm/test/CodeGen/Hexagon/fusedandshift.ll
M llvm/test/CodeGen/Hexagon/generate-const-buildvector32.ll
M llvm/test/CodeGen/Hexagon/getBlockAddress.ll
M llvm/test/CodeGen/Hexagon/glob-align-volatile.ll
M llvm/test/CodeGen/Hexagon/global-const-gep.ll
M llvm/test/CodeGen/Hexagon/global-ctor-pcrel.ll
M llvm/test/CodeGen/Hexagon/global64bitbug.ll
M llvm/test/CodeGen/Hexagon/gp-plus-offset-load.ll
M llvm/test/CodeGen/Hexagon/gp-plus-offset-store.ll
M llvm/test/CodeGen/Hexagon/gp-rel.ll
M llvm/test/CodeGen/Hexagon/hasfp-crash1.ll
M llvm/test/CodeGen/Hexagon/hasfp-crash2.ll
M llvm/test/CodeGen/Hexagon/hello-world-v55.ll
M llvm/test/CodeGen/Hexagon/hello-world-v60.ll
M llvm/test/CodeGen/Hexagon/hexagon-cond-jumpr31.ll
M llvm/test/CodeGen/Hexagon/hexagon-copy-hoisting.mir
M llvm/test/CodeGen/Hexagon/hexagon-tfr-add.ll
M llvm/test/CodeGen/Hexagon/hexagon-verify-implicit-use.ll
M llvm/test/CodeGen/Hexagon/hexagon_cfi_offset.ll
M llvm/test/CodeGen/Hexagon/hidden-relocation.ll
M llvm/test/CodeGen/Hexagon/honor-optsize.ll
M llvm/test/CodeGen/Hexagon/hrc-stack-coloring.ll
M llvm/test/CodeGen/Hexagon/hvx-bitcast-v64i1.ll
M llvm/test/CodeGen/Hexagon/hvx-byte-store-double.ll
M llvm/test/CodeGen/Hexagon/hvx-byte-store.ll
M llvm/test/CodeGen/Hexagon/hvx-concat-lower.ll
M llvm/test/CodeGen/Hexagon/hvx-dbl-dual-output.ll
M llvm/test/CodeGen/Hexagon/hvx-double-vzero.ll
M llvm/test/CodeGen/Hexagon/hvx-dual-output.ll
M llvm/test/CodeGen/Hexagon/hvx-isel-vselect-v256i16.ll
M llvm/test/CodeGen/Hexagon/hvx-nontemporal.ll
M llvm/test/CodeGen/Hexagon/hvx-reuse-fi-base.ll
M llvm/test/CodeGen/Hexagon/hvx-vzero.ll
M llvm/test/CodeGen/Hexagon/hwloop-cleanup.ll
M llvm/test/CodeGen/Hexagon/hwloop-const.ll
M llvm/test/CodeGen/Hexagon/hwloop-crit-edge.ll
M llvm/test/CodeGen/Hexagon/hwloop-dbg-register.mir
M llvm/test/CodeGen/Hexagon/hwloop-dbg.ll
M llvm/test/CodeGen/Hexagon/hwloop-ice.ll
M llvm/test/CodeGen/Hexagon/hwloop-le.ll
M llvm/test/CodeGen/Hexagon/hwloop-long.ll
M llvm/test/CodeGen/Hexagon/hwloop-loop1.ll
M llvm/test/CodeGen/Hexagon/hwloop-lt.ll
M llvm/test/CodeGen/Hexagon/hwloop-lt1.ll
M llvm/test/CodeGen/Hexagon/hwloop-missed.ll
M llvm/test/CodeGen/Hexagon/hwloop-ne.ll
M llvm/test/CodeGen/Hexagon/hwloop-noreturn-call.ll
M llvm/test/CodeGen/Hexagon/hwloop-ph-deadcode.ll
M llvm/test/CodeGen/Hexagon/hwloop-phi-subreg.ll
M llvm/test/CodeGen/Hexagon/hwloop-pos-ivbump1.ll
M llvm/test/CodeGen/Hexagon/hwloop-preh.ll
M llvm/test/CodeGen/Hexagon/hwloop-preheader.ll
M llvm/test/CodeGen/Hexagon/hwloop-range.ll
M llvm/test/CodeGen/Hexagon/hwloop-recursion.ll
M llvm/test/CodeGen/Hexagon/hwloop-redef-imm.mir
M llvm/test/CodeGen/Hexagon/hwloop-subreg.ll
M llvm/test/CodeGen/Hexagon/hwloop-swap.ll
M llvm/test/CodeGen/Hexagon/hwloop-with-return-call.ll
M llvm/test/CodeGen/Hexagon/hwloop-wrap.ll
M llvm/test/CodeGen/Hexagon/hwloop-wrap2.ll
M llvm/test/CodeGen/Hexagon/hwloop1.ll
M llvm/test/CodeGen/Hexagon/hwloop2.ll
M llvm/test/CodeGen/Hexagon/hwloop3.ll
M llvm/test/CodeGen/Hexagon/hwloop4.ll
M llvm/test/CodeGen/Hexagon/hwloop5.ll
M llvm/test/CodeGen/Hexagon/hx_V6_lo_hi.ll
M llvm/test/CodeGen/Hexagon/i128-bitop.ll
M llvm/test/CodeGen/Hexagon/i16_VarArg.ll
M llvm/test/CodeGen/Hexagon/i1_VarArg.ll
M llvm/test/CodeGen/Hexagon/i8_VarArg.ll
M llvm/test/CodeGen/Hexagon/idxload-with-zero-offset.ll
M llvm/test/CodeGen/Hexagon/ifcvt-common-kill.mir
M llvm/test/CodeGen/Hexagon/ifcvt-diamond-bad.ll
M llvm/test/CodeGen/Hexagon/ifcvt-diamond-bug-2016-08-26.ll
M llvm/test/CodeGen/Hexagon/ifcvt-diamond-ret.mir
M llvm/test/CodeGen/Hexagon/ifcvt-edge-weight.ll
M llvm/test/CodeGen/Hexagon/ifcvt-impuse-livein.mir
M llvm/test/CodeGen/Hexagon/ifcvt-live-subreg.mir
M llvm/test/CodeGen/Hexagon/ifcvt-simple-bprob.ll
M llvm/test/CodeGen/Hexagon/ignore-terminal-mbb.ll
M llvm/test/CodeGen/Hexagon/imm-range-check.ll
M llvm/test/CodeGen/Hexagon/indirect-br.ll
M llvm/test/CodeGen/Hexagon/initial-exec.ll
M llvm/test/CodeGen/Hexagon/inline-asm-a.ll
M llvm/test/CodeGen/Hexagon/inline-asm-bad-constraint.ll
M llvm/test/CodeGen/Hexagon/inline-asm-clobber-lr.ll
M llvm/test/CodeGen/Hexagon/inline-asm-error.ll
M llvm/test/CodeGen/Hexagon/inline-asm-hexagon.ll
M llvm/test/CodeGen/Hexagon/inline-asm-i1.ll
M llvm/test/CodeGen/Hexagon/inline-asm-qv.ll
M llvm/test/CodeGen/Hexagon/inline-asm-vecpred128.ll
M llvm/test/CodeGen/Hexagon/inline-division-space.ll
M llvm/test/CodeGen/Hexagon/inline-division.ll
M llvm/test/CodeGen/Hexagon/insert-basic.ll
M llvm/test/CodeGen/Hexagon/insert.ll
M llvm/test/CodeGen/Hexagon/insert4.ll
M llvm/test/CodeGen/Hexagon/instrprof-custom.ll
M llvm/test/CodeGen/Hexagon/intrinsics-v60-alu.ll
M llvm/test/CodeGen/Hexagon/intrinsics-v60-misc.ll
M llvm/test/CodeGen/Hexagon/intrinsics-v60-permute.ll
M llvm/test/CodeGen/Hexagon/intrinsics-v60-shift.ll
M llvm/test/CodeGen/Hexagon/intrinsics-v60-vcmp.ll
M llvm/test/CodeGen/Hexagon/intrinsics-v60-vmpy-acc-128B.ll
M llvm/test/CodeGen/Hexagon/intrinsics-v60-vmpy-acc.ll
M llvm/test/CodeGen/Hexagon/intrinsics-v60-vmpy.ll
M llvm/test/CodeGen/Hexagon/intrinsics-v66.ll
M llvm/test/CodeGen/Hexagon/intrinsics-v67.ll
M llvm/test/CodeGen/Hexagon/intrinsics/alu32_alu.ll
M llvm/test/CodeGen/Hexagon/intrinsics/alu32_perm.ll
M llvm/test/CodeGen/Hexagon/intrinsics/atomic_load.ll
M llvm/test/CodeGen/Hexagon/intrinsics/atomic_store.ll
M llvm/test/CodeGen/Hexagon/intrinsics/atomicrmw_addsub_native.ll
M llvm/test/CodeGen/Hexagon/intrinsics/atomicrmw_bitwise_native.ll
M llvm/test/CodeGen/Hexagon/intrinsics/atomicrmw_nand.ll
M llvm/test/CodeGen/Hexagon/intrinsics/byte-store-double.ll
M llvm/test/CodeGen/Hexagon/intrinsics/byte-store.ll
M llvm/test/CodeGen/Hexagon/intrinsics/cr.ll
M llvm/test/CodeGen/Hexagon/intrinsics/fence.ll
M llvm/test/CodeGen/Hexagon/intrinsics/llsc_bundling.ll
M llvm/test/CodeGen/Hexagon/intrinsics/system_user.ll
M llvm/test/CodeGen/Hexagon/intrinsics/v65-gather-double.ll
M llvm/test/CodeGen/Hexagon/intrinsics/v65-gather.ll
M llvm/test/CodeGen/Hexagon/intrinsics/v65-scatter-double.ll
M llvm/test/CodeGen/Hexagon/intrinsics/v65-scatter-gather.ll
M llvm/test/CodeGen/Hexagon/intrinsics/v65-scatter.ll
M llvm/test/CodeGen/Hexagon/intrinsics/v65.ll
M llvm/test/CodeGen/Hexagon/intrinsics/xtype_alu.ll
M llvm/test/CodeGen/Hexagon/intrinsics/xtype_bit.ll
M llvm/test/CodeGen/Hexagon/intrinsics/xtype_complex.ll
M llvm/test/CodeGen/Hexagon/intrinsics/xtype_fp.ll
M llvm/test/CodeGen/Hexagon/intrinsics/xtype_mpy.ll
M llvm/test/CodeGen/Hexagon/intrinsics/xtype_perm.ll
M llvm/test/CodeGen/Hexagon/intrinsics/xtype_pred.ll
M llvm/test/CodeGen/Hexagon/intrinsics/xtype_shift.ll
M llvm/test/CodeGen/Hexagon/invalid-dotnew-attempt.mir
M llvm/test/CodeGen/Hexagon/invalid-memrefs.ll
M llvm/test/CodeGen/Hexagon/is-legal-void.ll
M llvm/test/CodeGen/Hexagon/isel-bitcast-v1i8-i8.ll
M llvm/test/CodeGen/Hexagon/isel-bitcast-v8i1-i8.ll
M llvm/test/CodeGen/Hexagon/isel-bitcast-v8i8-v4i16.ll
M llvm/test/CodeGen/Hexagon/isel-buildvector-v2f16.ll
M llvm/test/CodeGen/Hexagon/isel-combine-half.ll
M llvm/test/CodeGen/Hexagon/isel-dcfetch-intrin-map.ll
M llvm/test/CodeGen/Hexagon/isel-exti1.ll
M llvm/test/CodeGen/Hexagon/isel-extload-i1.ll
M llvm/test/CodeGen/Hexagon/isel-extract-pred.ll
M llvm/test/CodeGen/Hexagon/isel-global-offset-alignment.ll
M llvm/test/CodeGen/Hexagon/isel-hvx-pred-bitcast-order.ll
M llvm/test/CodeGen/Hexagon/isel-i1arg-crash.ll
M llvm/test/CodeGen/Hexagon/isel-insert-pred.ll
M llvm/test/CodeGen/Hexagon/isel-memory-vNi1.ll
M llvm/test/CodeGen/Hexagon/isel-minmax-v64bit.ll
M llvm/test/CodeGen/Hexagon/isel-op-zext-i1.ll
M llvm/test/CodeGen/Hexagon/isel-prefer.ll
M llvm/test/CodeGen/Hexagon/isel-select-v4i8.ll
M llvm/test/CodeGen/Hexagon/isel-setcc-i1.ll
M llvm/test/CodeGen/Hexagon/isel-setcc-legalize-loop.ll
M llvm/test/CodeGen/Hexagon/isel-simplify-crash.ll
M llvm/test/CodeGen/Hexagon/isel-splat-vector-crash.ll
M llvm/test/CodeGen/Hexagon/isel-splat-vector-dag-crash.ll
M llvm/test/CodeGen/Hexagon/isel-splat-vector-neg-i8.ll
M llvm/test/CodeGen/Hexagon/isel-store-rr-i1.ll
M llvm/test/CodeGen/Hexagon/isel-uaddo-1-i64.ll
M llvm/test/CodeGen/Hexagon/isel-uaddo-1.ll
M llvm/test/CodeGen/Hexagon/isel-v3i16.ll
M llvm/test/CodeGen/Hexagon/isel-vacopy.ll
M llvm/test/CodeGen/Hexagon/isel-vlsr-v2i16.ll
M llvm/test/CodeGen/Hexagon/isel-vselect-v4i8.ll
M llvm/test/CodeGen/Hexagon/isel-zext-vNi1.ll
M llvm/test/CodeGen/Hexagon/isel/cmp-i1.ll
M llvm/test/CodeGen/Hexagon/isel/cmp-v2i1.ll
M llvm/test/CodeGen/Hexagon/isel/cmp-v4i1.ll
M llvm/test/CodeGen/Hexagon/isel/cmp-v8i1.ll
M llvm/test/CodeGen/Hexagon/isel/extload-i1.ll
M llvm/test/CodeGen/Hexagon/isel/logical.ll
M llvm/test/CodeGen/Hexagon/isel/mulh-scalar.ll
M llvm/test/CodeGen/Hexagon/isel/select-i1.ll
M llvm/test/CodeGen/Hexagon/isel/select-vec.ll
M llvm/test/CodeGen/Hexagon/isel/trunc-vNi1.ll
M llvm/test/CodeGen/Hexagon/jump-prob.ll
M llvm/test/CodeGen/Hexagon/jump-table-g0.ll
M llvm/test/CodeGen/Hexagon/jump-table-isel.ll
M llvm/test/CodeGen/Hexagon/large-number-of-preds.ll
M llvm/test/CodeGen/Hexagon/late-pred.ll
M llvm/test/CodeGen/Hexagon/late_instr.ll
M llvm/test/CodeGen/Hexagon/lcomm.ll
M llvm/test/CodeGen/Hexagon/ldst_vector_offset.ll
M llvm/test/CodeGen/Hexagon/livephysregs-add-pristines.mir
M llvm/test/CodeGen/Hexagon/livephysregs-lane-masks.mir
M llvm/test/CodeGen/Hexagon/livephysregs-lane-masks2.mir
M llvm/test/CodeGen/Hexagon/livephysregs-regmask-clobber.mir
M llvm/test/CodeGen/Hexagon/load-abs.ll
M llvm/test/CodeGen/Hexagon/load-const-extend-opt.ll
M llvm/test/CodeGen/Hexagon/load-widen.ll
M llvm/test/CodeGen/Hexagon/loadi1-G0.ll
M llvm/test/CodeGen/Hexagon/loadi1-v4-G0.ll
M llvm/test/CodeGen/Hexagon/loadi1-v4.ll
M llvm/test/CodeGen/Hexagon/loadi1.ll
M llvm/test/CodeGen/Hexagon/local-exec.ll
M llvm/test/CodeGen/Hexagon/loop-balign.ll
M llvm/test/CodeGen/Hexagon/loop-idiom/pmpy-infinite-loop.ll
M llvm/test/CodeGen/Hexagon/loop-idiom/pmpy-long-loop.ll
M llvm/test/CodeGen/Hexagon/loop-idiom/pmpy-mod.ll
M llvm/test/CodeGen/Hexagon/loop-idiom/pmpy-shiftconv-fail.ll
M llvm/test/CodeGen/Hexagon/loop-prefetch.ll
M llvm/test/CodeGen/Hexagon/loop-rotate-bug.ll
M llvm/test/CodeGen/Hexagon/loop-rotate-liveins.ll
M llvm/test/CodeGen/Hexagon/loop_align_count.ll
M llvm/test/CodeGen/Hexagon/loop_align_count.mir
M llvm/test/CodeGen/Hexagon/loop_correctness.ll
M llvm/test/CodeGen/Hexagon/lower-extract-subvector.ll
M llvm/test/CodeGen/Hexagon/lower-i1.ll
M llvm/test/CodeGen/Hexagon/lsr-post-inc-cross-use-offsets.ll
M llvm/test/CodeGen/Hexagon/lsr-postinc-nested-loop.ll
M llvm/test/CodeGen/Hexagon/machine-cp-clobbers.mir
M llvm/test/CodeGen/Hexagon/machine-sink-float-usr.mir
M llvm/test/CodeGen/Hexagon/machine-sink.ll
M llvm/test/CodeGen/Hexagon/macint.ll
M llvm/test/CodeGen/Hexagon/maddsubu.ll
M llvm/test/CodeGen/Hexagon/mapped_intrinsics.ll
M llvm/test/CodeGen/Hexagon/mask-instr.ll
M llvm/test/CodeGen/Hexagon/maxd.ll
M llvm/test/CodeGen/Hexagon/maxh.ll
M llvm/test/CodeGen/Hexagon/maxud.ll
M llvm/test/CodeGen/Hexagon/maxuw.ll
M llvm/test/CodeGen/Hexagon/maxw.ll
M llvm/test/CodeGen/Hexagon/mem-load-circ.ll
M llvm/test/CodeGen/Hexagon/mem-ops-sub.ll
M llvm/test/CodeGen/Hexagon/mem-ops-sub_01.ll
M llvm/test/CodeGen/Hexagon/mem-ops-sub_i16.ll
M llvm/test/CodeGen/Hexagon/mem-ops-sub_i16_01.ll
M llvm/test/CodeGen/Hexagon/memcmp.ll
M llvm/test/CodeGen/Hexagon/memcpy-likely-aligned.ll
M llvm/test/CodeGen/Hexagon/memcpy-memmove-inline.ll
M llvm/test/CodeGen/Hexagon/memop-bit18.ll
M llvm/test/CodeGen/Hexagon/memops-stack.ll
M llvm/test/CodeGen/Hexagon/memops.ll
M llvm/test/CodeGen/Hexagon/memops1.ll
M llvm/test/CodeGen/Hexagon/memops2.ll
M llvm/test/CodeGen/Hexagon/memops3.ll
M llvm/test/CodeGen/Hexagon/memops_global.ll
M llvm/test/CodeGen/Hexagon/memset-inline.ll
M llvm/test/CodeGen/Hexagon/mind.ll
M llvm/test/CodeGen/Hexagon/minu-zext-16.ll
M llvm/test/CodeGen/Hexagon/minu-zext-8.ll
M llvm/test/CodeGen/Hexagon/minud.ll
M llvm/test/CodeGen/Hexagon/minuw.ll
M llvm/test/CodeGen/Hexagon/minw.ll
M llvm/test/CodeGen/Hexagon/mipi-double-small.ll
M llvm/test/CodeGen/Hexagon/misaligned-access.ll
M llvm/test/CodeGen/Hexagon/misaligned-const-load.ll
M llvm/test/CodeGen/Hexagon/misaligned-const-store.ll
M llvm/test/CodeGen/Hexagon/misaligned_double_vector_store_not_fast.ll
M llvm/test/CodeGen/Hexagon/misched-top-rptracker-sync.ll
M llvm/test/CodeGen/Hexagon/mnaci_v66.ll
M llvm/test/CodeGen/Hexagon/mpy.ll
M llvm/test/CodeGen/Hexagon/mpysin-imm.ll
M llvm/test/CodeGen/Hexagon/mul64-sext.ll
M llvm/test/CodeGen/Hexagon/mul64.ll
M llvm/test/CodeGen/Hexagon/mulh.ll
M llvm/test/CodeGen/Hexagon/mulhs.ll
M llvm/test/CodeGen/Hexagon/multi-cycle.ll
M llvm/test/CodeGen/Hexagon/mux-kill1.mir
M llvm/test/CodeGen/Hexagon/mux-kill2.mir
M llvm/test/CodeGen/Hexagon/mux-kill3.mir
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M llvm/test/CodeGen/Hexagon/muxii-bug.ll
M llvm/test/CodeGen/Hexagon/muxii-crash.ll
M llvm/test/CodeGen/Hexagon/namedreg.ll
M llvm/test/CodeGen/Hexagon/nbench1.ll
M llvm/test/CodeGen/Hexagon/neg.ll
M llvm/test/CodeGen/Hexagon/newify-crash.ll
M llvm/test/CodeGen/Hexagon/newvalueSameReg.ll
M llvm/test/CodeGen/Hexagon/newvaluejump-c4.mir
M llvm/test/CodeGen/Hexagon/newvaluejump-float.mir
M llvm/test/CodeGen/Hexagon/newvaluejump-kill.ll
M llvm/test/CodeGen/Hexagon/newvaluejump-kill2.mir
M llvm/test/CodeGen/Hexagon/newvaluejump-postinc.ll
M llvm/test/CodeGen/Hexagon/newvaluejump-solo.mir
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M llvm/test/CodeGen/Hexagon/v6-inlasm3.ll
M llvm/test/CodeGen/Hexagon/v6-inlasm4.ll
M llvm/test/CodeGen/Hexagon/v6-shuffl.ll
M llvm/test/CodeGen/Hexagon/v6-spill1.ll
M llvm/test/CodeGen/Hexagon/v6-unaligned-spill.ll
M llvm/test/CodeGen/Hexagon/v6-vecpred-copy.ll
M llvm/test/CodeGen/Hexagon/v60-align.ll
M llvm/test/CodeGen/Hexagon/v60-cur.ll
M llvm/test/CodeGen/Hexagon/v60-haar-postinc.ll
M llvm/test/CodeGen/Hexagon/v60-halide-vcombinei8.ll
M llvm/test/CodeGen/Hexagon/v60-vec-128b-1.ll
M llvm/test/CodeGen/Hexagon/v60-vecpred-spill.ll
M llvm/test/CodeGen/Hexagon/v60-vsel1.ll
M llvm/test/CodeGen/Hexagon/v60-vsel2.ll
M llvm/test/CodeGen/Hexagon/v60Intrins.ll
M llvm/test/CodeGen/Hexagon/v60Vasr.ll
M llvm/test/CodeGen/Hexagon/v60_Q6_P_rol_PI.ll
M llvm/test/CodeGen/Hexagon/v60_sort16.ll
M llvm/test/CodeGen/Hexagon/v60rol-instrs.ll
M llvm/test/CodeGen/Hexagon/v60small.ll
M llvm/test/CodeGen/Hexagon/v62-CJAllSlots.ll
M llvm/test/CodeGen/Hexagon/v62-inlasm4.ll
M llvm/test/CodeGen/Hexagon/v6vassignp.ll
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M llvm/test/CodeGen/Hexagon/v6vec-vmemu2.ll
M llvm/test/CodeGen/Hexagon/v6vec-vprint.ll
M llvm/test/CodeGen/Hexagon/v6vec-vshuff.ll
M llvm/test/CodeGen/Hexagon/v6vec_inc1.ll
M llvm/test/CodeGen/Hexagon/v6vec_zero.ll
M llvm/test/CodeGen/Hexagon/v6vect-dbl-fail1.ll
M llvm/test/CodeGen/Hexagon/v6vect-dbl-spill.ll
M llvm/test/CodeGen/Hexagon/v6vect-dbl.ll
M llvm/test/CodeGen/Hexagon/v6vect-dh1.ll
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M llvm/test/CodeGen/Hexagon/v6vect-spill-kill.ll
M llvm/test/CodeGen/Hexagon/v6vect-vmem1.ll
M llvm/test/CodeGen/Hexagon/v6vect-vsplat.ll
M llvm/test/CodeGen/Hexagon/vacopy.ll
M llvm/test/CodeGen/Hexagon/vadd1.ll
M llvm/test/CodeGen/Hexagon/vaddh.ll
M llvm/test/CodeGen/Hexagon/validate-offset.ll
M llvm/test/CodeGen/Hexagon/vararg-deallocate-sp.ll
M llvm/test/CodeGen/Hexagon/vararg-formal.ll
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M llvm/test/CodeGen/Hexagon/vararg_double_onstack.ll
M llvm/test/CodeGen/Hexagon/vararg_named.ll
M llvm/test/CodeGen/Hexagon/varargs-memv.ll
M llvm/test/CodeGen/Hexagon/vassign-to-combine.ll
M llvm/test/CodeGen/Hexagon/vcombine128_to_req_seq.ll
M llvm/test/CodeGen/Hexagon/vcombine_subreg.ll
M llvm/test/CodeGen/Hexagon/vcombine_to_req_seq.ll
M llvm/test/CodeGen/Hexagon/vcombine_zero_diff_ptrs.ll
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M llvm/test/CodeGen/Hexagon/vec-vararg-align.ll
M llvm/test/CodeGen/Hexagon/vecPred2Vec.ll
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M llvm/test/CodeGen/Hexagon/vect-dbl-post-inc.ll
M llvm/test/CodeGen/Hexagon/vect-downscale.ll
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M llvm/test/CodeGen/Hexagon/vect/setcc-not.ll
M llvm/test/CodeGen/Hexagon/vect/setcc-v2i32.ll
M llvm/test/CodeGen/Hexagon/vect/setcc-v32.ll
M llvm/test/CodeGen/Hexagon/vect/shuff-32.ll
M llvm/test/CodeGen/Hexagon/vect/shuff-64.ll
M llvm/test/CodeGen/Hexagon/vect/vect-anyextend.ll
M llvm/test/CodeGen/Hexagon/vect/vect-apint-truncate.ll
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M llvm/test/CodeGen/Hexagon/vect/vect-bitcast-1.ll
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M llvm/test/CodeGen/Hexagon/vect/vect-bool-basic-compile.ll
M llvm/test/CodeGen/Hexagon/vect/vect-bool-isel-crash.ll
M llvm/test/CodeGen/Hexagon/vect/vect-cst-v4i32.ll
M llvm/test/CodeGen/Hexagon/vect/vect-cst-v4i8.ll
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M llvm/test/CodeGen/Hexagon/vect/vect-extract-i1-debug.ll
M llvm/test/CodeGen/Hexagon/vect/vect-extract-i1.ll
M llvm/test/CodeGen/Hexagon/vect/vect-extract.ll
M llvm/test/CodeGen/Hexagon/vect/vect-fma.ll
M llvm/test/CodeGen/Hexagon/vect/vect-illegal-type.ll
M llvm/test/CodeGen/Hexagon/vect/vect-infloop.ll
M llvm/test/CodeGen/Hexagon/vect/vect-insert-extract-elt.ll
M llvm/test/CodeGen/Hexagon/vect/vect-load-1.ll
M llvm/test/CodeGen/Hexagon/vect/vect-load-v4i16.ll
M llvm/test/CodeGen/Hexagon/vect/vect-load.ll
M llvm/test/CodeGen/Hexagon/vect/vect-mul-v2i16.ll
M llvm/test/CodeGen/Hexagon/vect/vect-mul-v2i32.ll
M llvm/test/CodeGen/Hexagon/vect/vect-mul-v4i16.ll
M llvm/test/CodeGen/Hexagon/vect/vect-mul-v4i8.ll
M llvm/test/CodeGen/Hexagon/vect/vect-mul-v8i8.ll
M llvm/test/CodeGen/Hexagon/vect/vect-no-tfrs-1.ll
M llvm/test/CodeGen/Hexagon/vect/vect-no-tfrs.ll
M llvm/test/CodeGen/Hexagon/vect/vect-shift-imm.ll
M llvm/test/CodeGen/Hexagon/vect/vect-shifts.ll
M llvm/test/CodeGen/Hexagon/vect/vect-shuffle.ll
M llvm/test/CodeGen/Hexagon/vect/vect-splat.ll
M llvm/test/CodeGen/Hexagon/vect/vect-store-v2i16.ll
M llvm/test/CodeGen/Hexagon/vect/vect-truncate.ll
M llvm/test/CodeGen/Hexagon/vect/vect-v4i16.ll
M llvm/test/CodeGen/Hexagon/vect/vect-vaddb-1.ll
M llvm/test/CodeGen/Hexagon/vect/vect-vaddb.ll
M llvm/test/CodeGen/Hexagon/vect/vect-vaddh-1.ll
M llvm/test/CodeGen/Hexagon/vect/vect-vaddh.ll
M llvm/test/CodeGen/Hexagon/vect/vect-vaddw.ll
M llvm/test/CodeGen/Hexagon/vect/vect-vaslw.ll
M llvm/test/CodeGen/Hexagon/vect/vect-vshifts.ll
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M llvm/test/CodeGen/Hexagon/vect/vect-vsubw.ll
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M llvm/test/CodeGen/Hexagon/vect/zext-v4i1.ll
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M llvm/test/CodeGen/Hexagon/verify-sink-code.ll
M llvm/test/CodeGen/Hexagon/verify-undef.ll
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M llvm/test/CodeGen/Hexagon/vgather-packetize.mir
M llvm/test/CodeGen/Hexagon/vload-postinc-sel.ll
M llvm/test/CodeGen/Hexagon/vmemu-128.ll
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M llvm/test/CodeGen/Hexagon/vselect-pseudo.ll
M llvm/test/CodeGen/Hexagon/vsplat-ext.ll
M llvm/test/CodeGen/Hexagon/vsplat-isel.ll
M llvm/test/CodeGen/Hexagon/wcsrtomb.ll
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M llvm/test/CodeGen/MIR/X86/cfi-def-cfa-offset.mir
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M llvm/test/CodeGen/MIR/X86/def-register-already-tied-error.mir
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M llvm/test/CodeGen/MIR/X86/expected-metadata-node-in-stack-object.mir
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M llvm/test/CodeGen/MIR/X86/expected-named-register-in-functions-livein.mir
M llvm/test/CodeGen/MIR/X86/expected-named-register-livein.mir
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M llvm/test/CodeGen/MIR/X86/frame-info-save-restore-points.mir
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M llvm/test/CodeGen/MIR/X86/function-liveins.mir
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M llvm/test/CodeGen/MIR/X86/instr-cfi-type.mir
M llvm/test/CodeGen/MIR/X86/instr-heap-alloc-operands.mir
M llvm/test/CodeGen/MIR/X86/instr-pcsections.mir
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M llvm/test/CodeGen/MIR/X86/invalid-constant-pool-item.mir
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M llvm/test/CodeGen/MIR/X86/machine-basic-block-operands.mir
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M llvm/test/CodeGen/MIR/X86/machine-verifier-address.mir
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M llvm/test/CodeGen/MIR/X86/named-registers.mir
M llvm/test/CodeGen/MIR/X86/newline-handling.mir
M llvm/test/CodeGen/MIR/X86/null-register-operands.mir
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M llvm/test/CodeGen/MIR/X86/register-operand-class-invalid0.mir
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M llvm/test/CodeGen/MIR/X86/register-operands-target-flag-error.mir
M llvm/test/CodeGen/MIR/X86/renamable-register-flag.mir
M llvm/test/CodeGen/MIR/X86/simple-register-allocation-hints.mir
M llvm/test/CodeGen/MIR/X86/spill-slot-fixed-stack-object-aliased.mir
M llvm/test/CodeGen/MIR/X86/spill-slot-fixed-stack-object-immutable.mir
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M llvm/test/CodeGen/MIR/X86/standalone-register-error.mir
M llvm/test/CodeGen/MIR/X86/subreg-on-physreg.mir
M llvm/test/CodeGen/MIR/X86/subregister-index-operands.mir
M llvm/test/CodeGen/MIR/X86/subregister-operands.mir
M llvm/test/CodeGen/MIR/X86/successor-basic-blocks-weights.mir
M llvm/test/CodeGen/MIR/X86/successor-basic-blocks.mir
M llvm/test/CodeGen/MIR/X86/tied-def-operand-invalid.mir
M llvm/test/CodeGen/MIR/X86/tied-physical-regs-match.mir
M llvm/test/CodeGen/MIR/X86/undef-register-flag.mir
M llvm/test/CodeGen/MIR/X86/undefined-fixed-stack-object.mir
M llvm/test/CodeGen/MIR/X86/undefined-global-value.mir
M llvm/test/CodeGen/MIR/X86/undefined-ir-block-in-blockaddress.mir
M llvm/test/CodeGen/MIR/X86/undefined-ir-block-slot-in-blockaddress.mir
M llvm/test/CodeGen/MIR/X86/undefined-jump-table-id.mir
M llvm/test/CodeGen/MIR/X86/undefined-named-global-value.mir
M llvm/test/CodeGen/MIR/X86/undefined-register-class.mir
M llvm/test/CodeGen/MIR/X86/undefined-stack-object.mir
M llvm/test/CodeGen/MIR/X86/undefined-value-in-memory-operand.mir
M llvm/test/CodeGen/MIR/X86/undefined-virtual-register.mir
M llvm/test/CodeGen/MIR/X86/unexpected-type-phys.mir
M llvm/test/CodeGen/MIR/X86/unknown-instruction.mir
M llvm/test/CodeGen/MIR/X86/unknown-machine-basic-block.mir
M llvm/test/CodeGen/MIR/X86/unknown-metadata-keyword.mir
M llvm/test/CodeGen/MIR/X86/unknown-metadata-node.mir
M llvm/test/CodeGen/MIR/X86/unknown-named-machine-basic-block.mir
M llvm/test/CodeGen/MIR/X86/unknown-register.mir
M llvm/test/CodeGen/MIR/X86/unknown-subregister-index-op.mir
M llvm/test/CodeGen/MIR/X86/unknown-subregister-index.mir
M llvm/test/CodeGen/MIR/X86/unrecognized-character.mir
M llvm/test/CodeGen/MIR/X86/variable-sized-stack-object-size-error.mir
M llvm/test/CodeGen/MIR/X86/variable-sized-stack-objects.mir
M llvm/test/CodeGen/MIR/X86/virtual-register-redefinition-error.mir
M llvm/test/CodeGen/MIR/X86/virtual-registers.mir
M llvm/test/CodeGen/MSP430/2009-05-17-Rot.ll
M llvm/test/CodeGen/MSP430/2009-05-17-Shift.ll
M llvm/test/CodeGen/MSP430/2009-05-19-DoubleSplit.ll
M llvm/test/CodeGen/MSP430/2009-10-10-OrImpDef.ll
M llvm/test/CodeGen/MSP430/2009-11-20-NewNode.ll
M llvm/test/CodeGen/MSP430/AddrMode-bis-rx.ll
M llvm/test/CodeGen/MSP430/AddrMode-bis-xr.ll
M llvm/test/CodeGen/MSP430/AddrMode-mov-rx.ll
M llvm/test/CodeGen/MSP430/AddrMode-mov-xr.ll
M llvm/test/CodeGen/MSP430/BranchSelector.ll
M llvm/test/CodeGen/MSP430/DbgValueOtherTargets.test
M llvm/test/CodeGen/MSP430/Inst16mi.ll
M llvm/test/CodeGen/MSP430/Inst16mm.ll
M llvm/test/CodeGen/MSP430/Inst16mr.ll
M llvm/test/CodeGen/MSP430/Inst16ri.ll
M llvm/test/CodeGen/MSP430/Inst16rm.ll
M llvm/test/CodeGen/MSP430/Inst16rr.ll
M llvm/test/CodeGen/MSP430/Inst8mi.ll
M llvm/test/CodeGen/MSP430/Inst8mm.ll
M llvm/test/CodeGen/MSP430/Inst8mr.ll
M llvm/test/CodeGen/MSP430/Inst8ri.ll
M llvm/test/CodeGen/MSP430/Inst8rm.ll
M llvm/test/CodeGen/MSP430/Inst8rr.ll
M llvm/test/CodeGen/MSP430/InstII.ll
M llvm/test/CodeGen/MSP430/bit.ll
M llvm/test/CodeGen/MSP430/flt_rounds.ll
M llvm/test/CodeGen/MSP430/indirectbr.ll
M llvm/test/CodeGen/MSP430/indirectbr2.ll
M llvm/test/CodeGen/MSP430/mult-alt-generic-msp430.ll
M llvm/test/CodeGen/MSP430/select-use-sr.ll
M llvm/test/CodeGen/MSP430/setcc.ll
M llvm/test/CodeGen/MSP430/spill-to-stack.ll
M llvm/test/CodeGen/MSP430/stacksave_restore.ll
M llvm/test/CodeGen/MSP430/umulo-16.ll
M llvm/test/CodeGen/Mips/2008-07-16-SignExtInReg.ll
M llvm/test/CodeGen/Mips/GlobalISel/legalizer/icmp.mir
M llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/icmp.ll
M llvm/test/CodeGen/Mips/beqzc.ll
M llvm/test/CodeGen/Mips/beqzc1.ll
M llvm/test/CodeGen/Mips/blockaddr.ll
M llvm/test/CodeGen/Mips/brsize3.ll
M llvm/test/CodeGen/Mips/brsize3a.ll
M llvm/test/CodeGen/Mips/ci2.ll
M llvm/test/CodeGen/Mips/const1.ll
M llvm/test/CodeGen/Mips/const4a.ll
M llvm/test/CodeGen/Mips/const6.ll
M llvm/test/CodeGen/Mips/const6a.ll
M llvm/test/CodeGen/Mips/ctlz.ll
M llvm/test/CodeGen/Mips/f16abs.ll
M llvm/test/CodeGen/Mips/fixdfsf.ll
M llvm/test/CodeGen/Mips/fp16instrinsmc.ll
M llvm/test/CodeGen/Mips/fp16mix.ll
M llvm/test/CodeGen/Mips/fpnotneeded.ll
M llvm/test/CodeGen/Mips/funnel-shift-rot.ll
M llvm/test/CodeGen/Mips/funnel-shift.ll
M llvm/test/CodeGen/Mips/helloworld.ll
M llvm/test/CodeGen/Mips/hf16call32.ll
M llvm/test/CodeGen/Mips/hf16call32_body.ll
M llvm/test/CodeGen/Mips/hf1_body.ll
M llvm/test/CodeGen/Mips/hfptrcall.ll
M llvm/test/CodeGen/Mips/i32k.ll
M llvm/test/CodeGen/Mips/l3mc.ll
M llvm/test/CodeGen/Mips/lcb2.ll
M llvm/test/CodeGen/Mips/lcb3c.ll
M llvm/test/CodeGen/Mips/lcb4a.ll
M llvm/test/CodeGen/Mips/lcb5.ll
M llvm/test/CodeGen/Mips/mbrsize4a.ll
M llvm/test/CodeGen/Mips/mips16-hf-attr-2.ll
M llvm/test/CodeGen/Mips/mips16-hf-attr.ll
M llvm/test/CodeGen/Mips/mips16_fpret.ll
M llvm/test/CodeGen/Mips/nomips16.ll
M llvm/test/CodeGen/Mips/powif64_16.ll
M llvm/test/CodeGen/Mips/rotate.ll
M llvm/test/CodeGen/Mips/s2rem.ll
M llvm/test/CodeGen/Mips/sel1c.ll
M llvm/test/CodeGen/Mips/sel2c.ll
M llvm/test/CodeGen/Mips/simplebr.ll
M llvm/test/CodeGen/Mips/small-section-reserve-gp.ll
M llvm/test/CodeGen/Mips/sr1.ll
M llvm/test/CodeGen/Mips/tail16.ll
M llvm/test/CodeGen/Mips/trap1.ll
M llvm/test/CodeGen/NVPTX/APIntLoadStore.ll
M llvm/test/CodeGen/NVPTX/APIntParam.ll
M llvm/test/CodeGen/NVPTX/APIntSextParam.ll
M llvm/test/CodeGen/NVPTX/APIntZextParam.ll
M llvm/test/CodeGen/NVPTX/access-non-generic.ll
M llvm/test/CodeGen/NVPTX/activemask.ll
M llvm/test/CodeGen/NVPTX/add-sub-128bit.ll
M llvm/test/CodeGen/NVPTX/addr-mode.ll
M llvm/test/CodeGen/NVPTX/addrspacecast-gvar.ll
M llvm/test/CodeGen/NVPTX/addrspacecast.ll
M llvm/test/CodeGen/NVPTX/aggr-param.ll
M llvm/test/CodeGen/NVPTX/aggregate-return.ll
M llvm/test/CodeGen/NVPTX/alias-errors.ll
M llvm/test/CodeGen/NVPTX/alias.ll
M llvm/test/CodeGen/NVPTX/annotations.ll
M llvm/test/CodeGen/NVPTX/anonymous-fn-param.ll
M llvm/test/CodeGen/NVPTX/arg-lowering.ll
M llvm/test/CodeGen/NVPTX/arithmetic-fp-sm20.ll
M llvm/test/CodeGen/NVPTX/arithmetic-int.ll
M llvm/test/CodeGen/NVPTX/async-copy.ll
M llvm/test/CodeGen/NVPTX/atomicrmw-expand.ll
M llvm/test/CodeGen/NVPTX/atomics-sm60.ll
M llvm/test/CodeGen/NVPTX/atomics-sm70.ll
M llvm/test/CodeGen/NVPTX/atomics-sm90.ll
M llvm/test/CodeGen/NVPTX/atomics-with-scope.ll
M llvm/test/CodeGen/NVPTX/atomics.ll
Log Message:
-----------
Merge branch 'main' into users/fmayer/spr/apply-alignment-size-in-linker-rather-than-ir
Compare: https://github.com/llvm/llvm-project/compare/1bf6c19b8140...360f0a6a89ea
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