[all-commits] [llvm/llvm-project] 3b17d0: [AArch64][SVE] Don't require 16-byte aligned SVE l...

[Benjamin Maxwell via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 3b17d041dd775e033cca499f2a25548c8c22bb86
      https://github.com/llvm/llvm-project/commit/3b17d041dd775e033cca499f2a25548c8c22bb86
  Author: Benjamin Maxwell <benjamin.maxwell at arm.com>
  Date:   2024-12-16 (Mon, 16 Dec 2024)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
    A llvm/test/CodeGen/AArch64/sve-load-store-strict-align.ll
    A llvm/test/CodeGen/AArch64/sve-unaligned-load-store-strict-align.ll

  Log Message:
  -----------
  [AArch64][SVE] Don't require 16-byte aligned SVE loads/stores with +strict-align (#119732)

Instead, allow any alignment >= the element size (in bytes). This is all
that is needed for (predicated) vector loads even if unaligned accesses
are disabled.

See:
https://developer.arm.com/documentation/ddi0602/2024-09/Shared-Pseudocode/aarch64-functions-memory?lang=en#impl-aarch64.Mem.read.3

Specifically:
```
// Check alignment on size of element accessed, not overall access size.
constant integer alignment = if accdesc.ispair then size DIV 2 else size;
```

The `size` passed to `Mem` by SVE load/store instructions is the element
size.



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