[all-commits] [llvm/llvm-project] 474639: [VPlan] Omit zero add in VPWidenIntOrFpInductionRe...

[Luke Lau via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 4746395bd75bc234dfd026bad672613b99e87e7a
      https://github.com/llvm/llvm-project/commit/4746395bd75bc234dfd026bad672613b99e87e7a
  Author: Luke Lau <luke at igalia.com>
  Date:   2024-12-16 (Mon, 16 Dec 2024)

  Changed paths:
    M llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
    M llvm/test/Transforms/LoopVectorize/AArch64/clamped-trip-count.ll
    M llvm/test/Transforms/LoopVectorize/AArch64/divs-with-scalable-vfs.ll
    M llvm/test/Transforms/LoopVectorize/AArch64/outer_loop_prefer_scalable.ll
    M llvm/test/Transforms/LoopVectorize/AArch64/scalable-avoid-scalarization.ll
    M llvm/test/Transforms/LoopVectorize/AArch64/sve-inductions-unusual-types.ll
    M llvm/test/Transforms/LoopVectorize/AArch64/sve-tail-folding.ll
    M llvm/test/Transforms/LoopVectorize/RISCV/blocks-with-dead-instructions.ll
    M llvm/test/Transforms/LoopVectorize/RISCV/dead-ops-cost.ll
    M llvm/test/Transforms/LoopVectorize/RISCV/induction-costs.ll
    M llvm/test/Transforms/LoopVectorize/RISCV/mask-index-type.ll
    M llvm/test/Transforms/LoopVectorize/RISCV/masked_gather_scatter.ll
    M llvm/test/Transforms/LoopVectorize/RISCV/pr87378-vpinstruction-or-drop-poison-generating-flags.ll
    M llvm/test/Transforms/LoopVectorize/RISCV/strided-accesses.ll
    M llvm/test/Transforms/LoopVectorize/RISCV/uniform-load-store.ll
    M llvm/test/Transforms/LoopVectorize/RISCV/vectorize-force-tail-with-evl-cond-reduction.ll
    M llvm/test/Transforms/LoopVectorize/RISCV/vectorize-force-tail-with-evl-interleave.ll
    M llvm/test/Transforms/LoopVectorize/outer_loop_scalable.ll

  Log Message:
  -----------
  [VPlan] Omit zero add in VPWidenIntOrFpInductionRecipe (#119668)

I'm not sure if getStepVector was used for other things in the past
where StartIdx was non-zero, but nowadays VPWidenIntOrFpInductionRecipe
is the only user of it, and just passes zero to it. I presume
InstCombine was already catching this so hopefully removing this won't
affect codegen.



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