[all-commits] [llvm/llvm-project] 40a4cb: [MIR, test] Change llc -march=x86-64 to -mtriple=x8...

Sun Dec 15 11:23:32 PST 2024

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 40a4cbb0f200e5e0bafbd58d55c2da6daab9515d
      https://github.com/llvm/llvm-project/commit/40a4cbb0f200e5e0bafbd58d55c2da6daab9515d
  Author: Fangrui Song <i at maskray.me>
  Date:   2024-12-15 (Sun, 15 Dec 2024)

  Changed paths:
    M llvm/test/CodeGen/MIR/X86/basic-block-liveins.mir
    M llvm/test/CodeGen/MIR/X86/basic-block-not-at-start-of-line-error.mir
    M llvm/test/CodeGen/MIR/X86/block-address-operands.mir
    M llvm/test/CodeGen/MIR/X86/callee-saved-info.mir
    M llvm/test/CodeGen/MIR/X86/cfi-def-cfa-offset.mir
    M llvm/test/CodeGen/MIR/X86/cfi-def-cfa-register.mir
    M llvm/test/CodeGen/MIR/X86/cfi-offset.mir
    M llvm/test/CodeGen/MIR/X86/constant-pool-item-redefinition-error.mir
    M llvm/test/CodeGen/MIR/X86/constant-pool.mir
    M llvm/test/CodeGen/MIR/X86/constant-value-error.mir
    M llvm/test/CodeGen/MIR/X86/copyIRflags.mir
    M llvm/test/CodeGen/MIR/X86/dead-register-flag.mir
    M llvm/test/CodeGen/MIR/X86/def-register-already-tied-error.mir
    M llvm/test/CodeGen/MIR/X86/duplicate-memory-operand-flag.mir
    M llvm/test/CodeGen/MIR/X86/duplicate-register-flag-error.mir
    M llvm/test/CodeGen/MIR/X86/early-clobber-register-flag.mir
    M llvm/test/CodeGen/MIR/X86/exception-function-state.mir
    M llvm/test/CodeGen/MIR/X86/expected-align-in-memory-operand.mir
    M llvm/test/CodeGen/MIR/X86/expected-alignment-after-align-in-memory-operand.mir
    M llvm/test/CodeGen/MIR/X86/expected-basic-block-at-start-of-body.mir
    M llvm/test/CodeGen/MIR/X86/expected-block-reference-in-blockaddress.mir
    M llvm/test/CodeGen/MIR/X86/expected-comma-after-cfi-register.mir
    M llvm/test/CodeGen/MIR/X86/expected-comma-after-memory-operand.mir
    M llvm/test/CodeGen/MIR/X86/expected-different-implicit-operand.mir
    M llvm/test/CodeGen/MIR/X86/expected-different-implicit-register-flag.mir
    M llvm/test/CodeGen/MIR/X86/expected-function-reference-after-blockaddress.mir
    M llvm/test/CodeGen/MIR/X86/expected-global-value-after-blockaddress.mir
    M llvm/test/CodeGen/MIR/X86/expected-integer-after-offset-sign.mir
    M llvm/test/CodeGen/MIR/X86/expected-integer-after-tied-def.mir
    M llvm/test/CodeGen/MIR/X86/expected-integer-in-successor-weight.mir
    M llvm/test/CodeGen/MIR/X86/expected-load-or-store-in-memory-operand.mir
    M llvm/test/CodeGen/MIR/X86/expected-machine-operand.mir
    M llvm/test/CodeGen/MIR/X86/expected-metadata-node-after-debug-location.mir
    M llvm/test/CodeGen/MIR/X86/expected-metadata-node-after-exclaim.mir
    M llvm/test/CodeGen/MIR/X86/expected-metadata-node-in-stack-object.mir
    M llvm/test/CodeGen/MIR/X86/expected-named-register-in-allocation-hint.mir
    M llvm/test/CodeGen/MIR/X86/expected-named-register-in-callee-saved-register.mir
    M llvm/test/CodeGen/MIR/X86/expected-named-register-in-functions-livein.mir
    M llvm/test/CodeGen/MIR/X86/expected-named-register-livein.mir
    M llvm/test/CodeGen/MIR/X86/expected-newline-at-end-of-list.mir
    M llvm/test/CodeGen/MIR/X86/expected-number-after-bb.mir
    M llvm/test/CodeGen/MIR/X86/expected-offset-after-cfi-operand.mir
    M llvm/test/CodeGen/MIR/X86/expected-pointer-value-in-memory-operand.mir
    M llvm/test/CodeGen/MIR/X86/expected-positive-alignment-after-align.mir
    M llvm/test/CodeGen/MIR/X86/expected-power-of-2-after-align.mir
    M llvm/test/CodeGen/MIR/X86/expected-register-after-cfi-operand.mir
    M llvm/test/CodeGen/MIR/X86/expected-register-after-flags.mir
    M llvm/test/CodeGen/MIR/X86/expected-size-integer-after-memory-operation.mir
    M llvm/test/CodeGen/MIR/X86/expected-size-integer-after-memory-operation2.mir
    M llvm/test/CodeGen/MIR/X86/expected-stack-object-function-context.mir
    M llvm/test/CodeGen/MIR/X86/expected-stack-object.mir
    M llvm/test/CodeGen/MIR/X86/expected-subregister-after-colon.mir
    M llvm/test/CodeGen/MIR/X86/expected-target-flag-name.mir
    M llvm/test/CodeGen/MIR/X86/expected-tied-def-after-lparen.mir
    M llvm/test/CodeGen/MIR/X86/expected-value-in-memory-operand.mir
    M llvm/test/CodeGen/MIR/X86/expected-virtual-register-in-functions-livein.mir
    M llvm/test/CodeGen/MIR/X86/external-symbol-operands.mir
    M llvm/test/CodeGen/MIR/X86/fastmath.mir
    M llvm/test/CodeGen/MIR/X86/frame-info-save-restore-points.mir
    M llvm/test/CodeGen/MIR/X86/frame-info-stack-references.mir
    M llvm/test/CodeGen/MIR/X86/frame-setup-instruction-flag.mir
    M llvm/test/CodeGen/MIR/X86/function-liveins.mir
    M llvm/test/CodeGen/MIR/X86/generic-instr-type.mir
    M llvm/test/CodeGen/MIR/X86/global-value-operands.mir
    M llvm/test/CodeGen/MIR/X86/immediate-operands.mir
    M llvm/test/CodeGen/MIR/X86/implicit-register-flag.mir
    M llvm/test/CodeGen/MIR/X86/inline-asm-registers.mir
    M llvm/test/CodeGen/MIR/X86/instr-cfi-type.mir
    M llvm/test/CodeGen/MIR/X86/instr-heap-alloc-operands.mir
    M llvm/test/CodeGen/MIR/X86/instr-pcsections.mir
    M llvm/test/CodeGen/MIR/X86/instr-symbols-and-mcsymbol-operands.mir
    M llvm/test/CodeGen/MIR/X86/instructions-debug-location.mir
    M llvm/test/CodeGen/MIR/X86/invalid-constant-pool-item.mir
    M llvm/test/CodeGen/MIR/X86/invalid-metadata-node-type.mir
    M llvm/test/CodeGen/MIR/X86/invalid-target-flag-name.mir
    M llvm/test/CodeGen/MIR/X86/invalid-tied-def-index-error.mir
    M llvm/test/CodeGen/MIR/X86/jump-table-info.mir
    M llvm/test/CodeGen/MIR/X86/jump-table-redefinition-error.mir
    M llvm/test/CodeGen/MIR/X86/killed-register-flag.mir
    M llvm/test/CodeGen/MIR/X86/large-cfi-offset-number-error.mir
    M llvm/test/CodeGen/MIR/X86/large-immediate-operand-error.mir
    M llvm/test/CodeGen/MIR/X86/large-index-number-error.mir
    M llvm/test/CodeGen/MIR/X86/large-offset-number-error.mir
    M llvm/test/CodeGen/MIR/X86/large-size-in-memory-operand-error.mir
    M llvm/test/CodeGen/MIR/X86/liveout-register-mask.mir
    M llvm/test/CodeGen/MIR/X86/load-with-max-alignment.mir
    M llvm/test/CodeGen/MIR/X86/machine-basic-block-operands.mir
    M llvm/test/CodeGen/MIR/X86/machine-instructions.mir
    M llvm/test/CodeGen/MIR/X86/machine-verifier-address.mir
    M llvm/test/CodeGen/MIR/X86/machine-verifier.mir
    M llvm/test/CodeGen/MIR/X86/memory-operands.mir
    M llvm/test/CodeGen/MIR/X86/metadata-operands.mir
    M llvm/test/CodeGen/MIR/X86/mircanon-flags.mir
    M llvm/test/CodeGen/MIR/X86/missing-closing-quote.mir
    M llvm/test/CodeGen/MIR/X86/missing-comma.mir
    M llvm/test/CodeGen/MIR/X86/missing-implicit-operand.mir
    M llvm/test/CodeGen/MIR/X86/named-registers.mir
    M llvm/test/CodeGen/MIR/X86/newline-handling.mir
    M llvm/test/CodeGen/MIR/X86/null-register-operands.mir
    M llvm/test/CodeGen/MIR/X86/register-mask-operands.mir
    M llvm/test/CodeGen/MIR/X86/register-operand-class-invalid0.mir
    M llvm/test/CodeGen/MIR/X86/register-operand-class-invalid1.mir
    M llvm/test/CodeGen/MIR/X86/register-operand-class.mir
    M llvm/test/CodeGen/MIR/X86/register-operands-target-flag-error.mir
    M llvm/test/CodeGen/MIR/X86/renamable-register-flag.mir
    M llvm/test/CodeGen/MIR/X86/simple-register-allocation-hints.mir
    M llvm/test/CodeGen/MIR/X86/spill-slot-fixed-stack-object-aliased.mir
    M llvm/test/CodeGen/MIR/X86/spill-slot-fixed-stack-object-immutable.mir
    M llvm/test/CodeGen/MIR/X86/spill-slot-fixed-stack-objects.mir
    M llvm/test/CodeGen/MIR/X86/stack-object-debug-info.mir
    M llvm/test/CodeGen/MIR/X86/stack-object-invalid-name.mir
    M llvm/test/CodeGen/MIR/X86/stack-object-operand-name-mismatch-error.mir
    M llvm/test/CodeGen/MIR/X86/stack-object-redefinition-error.mir
    M llvm/test/CodeGen/MIR/X86/stack-objects.mir
    M llvm/test/CodeGen/MIR/X86/standalone-register-error.mir
    M llvm/test/CodeGen/MIR/X86/subreg-on-physreg.mir
    M llvm/test/CodeGen/MIR/X86/subregister-index-operands.mir
    M llvm/test/CodeGen/MIR/X86/subregister-operands.mir
    M llvm/test/CodeGen/MIR/X86/successor-basic-blocks-weights.mir
    M llvm/test/CodeGen/MIR/X86/successor-basic-blocks.mir
    M llvm/test/CodeGen/MIR/X86/tied-def-operand-invalid.mir
    M llvm/test/CodeGen/MIR/X86/tied-physical-regs-match.mir
    M llvm/test/CodeGen/MIR/X86/undef-register-flag.mir
    M llvm/test/CodeGen/MIR/X86/undefined-fixed-stack-object.mir
    M llvm/test/CodeGen/MIR/X86/undefined-global-value.mir
    M llvm/test/CodeGen/MIR/X86/undefined-ir-block-in-blockaddress.mir
    M llvm/test/CodeGen/MIR/X86/undefined-ir-block-slot-in-blockaddress.mir
    M llvm/test/CodeGen/MIR/X86/undefined-jump-table-id.mir
    M llvm/test/CodeGen/MIR/X86/undefined-named-global-value.mir
    M llvm/test/CodeGen/MIR/X86/undefined-register-class.mir
    M llvm/test/CodeGen/MIR/X86/undefined-stack-object.mir
    M llvm/test/CodeGen/MIR/X86/undefined-value-in-memory-operand.mir
    M llvm/test/CodeGen/MIR/X86/undefined-virtual-register.mir
    M llvm/test/CodeGen/MIR/X86/unexpected-type-phys.mir
    M llvm/test/CodeGen/MIR/X86/unknown-instruction.mir
    M llvm/test/CodeGen/MIR/X86/unknown-machine-basic-block.mir
    M llvm/test/CodeGen/MIR/X86/unknown-metadata-keyword.mir
    M llvm/test/CodeGen/MIR/X86/unknown-metadata-node.mir
    M llvm/test/CodeGen/MIR/X86/unknown-named-machine-basic-block.mir
    M llvm/test/CodeGen/MIR/X86/unknown-register.mir
    M llvm/test/CodeGen/MIR/X86/unknown-subregister-index-op.mir
    M llvm/test/CodeGen/MIR/X86/unknown-subregister-index.mir
    M llvm/test/CodeGen/MIR/X86/unrecognized-character.mir
    M llvm/test/CodeGen/MIR/X86/variable-sized-stack-object-size-error.mir
    M llvm/test/CodeGen/MIR/X86/variable-sized-stack-objects.mir
    M llvm/test/CodeGen/MIR/X86/virtual-register-redefinition-error.mir
    M llvm/test/CodeGen/MIR/X86/virtual-registers.mir
    M llvm/test/DebugInfo/MIR/InstrRef/instr-ref-roundtrip.mir
    M llvm/test/DebugInfo/MIR/InstrRef/livedebugvalues_illegal_locs.mir
    M llvm/test/DebugInfo/MIR/InstrRef/livedebugvalues_instrref_tolocs.mir
    M llvm/test/DebugInfo/MIR/InstrRef/livedebugvalues_recover_clobbers.mir
    M llvm/test/DebugInfo/MIR/InstrRef/livedebugvalues_stackslot_subregs.mir
    M llvm/test/DebugInfo/MIR/InstrRef/livedebugvalues_subreg_substitutions.mir
    M llvm/test/DebugInfo/MIR/InstrRef/memory-operand-tracking.mir
    M llvm/test/DebugInfo/MIR/InstrRef/no-duplicates.mir
    M llvm/test/DebugInfo/MIR/InstrRef/no-metainstrs.mir
    M llvm/test/DebugInfo/MIR/InstrRef/out-of-scope-blocks.mir
    M llvm/test/DebugInfo/MIR/InstrRef/pretty-print.mir
    M llvm/test/DebugInfo/MIR/InstrRef/single-assign-propagation.mir
    M llvm/test/DebugInfo/MIR/InstrRef/substitusions-roundtrip.mir
    M llvm/test/DebugInfo/MIR/X86/dbginfo-entryvals.mir
    M llvm/test/DebugInfo/MIR/X86/live-debug-values-restore.mir
    M llvm/test/DebugInfo/MIR/X86/livedebugvalues-ignores-metaInstructions.mir
    M llvm/test/DebugInfo/MIR/X86/livedebugvalues_basic_diamond.mir
    M llvm/test/DebugInfo/MIR/X86/livedebugvalues_basic_diamond_match_clobber.mir
    M llvm/test/DebugInfo/MIR/X86/livedebugvalues_basic_diamond_match_move.mir
    M llvm/test/DebugInfo/MIR/X86/livedebugvalues_basic_diamond_one_clobber.mir
    M llvm/test/DebugInfo/MIR/X86/livedebugvalues_basic_diamond_one_move.mir
    M llvm/test/DebugInfo/MIR/X86/livedebugvalues_basic_loop.mir
    M llvm/test/DebugInfo/MIR/X86/livedebugvalues_bb_to_bb.mir
    M llvm/test/DebugInfo/MIR/X86/livedebugvalues_bb_to_bb_clobbered.mir
    M llvm/test/DebugInfo/MIR/X86/livedebugvalues_bb_to_bb_move_to_clobber.mir
    M llvm/test/DebugInfo/MIR/X86/livedebugvalues_load_in_loop.mir
    M llvm/test/DebugInfo/MIR/X86/livedebugvalues_loop_break.mir
    M llvm/test/DebugInfo/MIR/X86/livedebugvalues_loop_break_clobbered.mir
    M llvm/test/DebugInfo/MIR/X86/livedebugvalues_loop_clobbered.mir
    M llvm/test/DebugInfo/MIR/X86/livedebugvalues_loop_diamond.mir
    M llvm/test/DebugInfo/MIR/X86/livedebugvalues_loop_diamond_clobber.mir
    M llvm/test/DebugInfo/MIR/X86/livedebugvalues_loop_diamond_move.mir
    M llvm/test/DebugInfo/MIR/X86/livedebugvalues_loop_early_clobber.mir
    M llvm/test/DebugInfo/MIR/X86/livedebugvalues_loop_terminated.mir
    M llvm/test/DebugInfo/MIR/X86/livedebugvalues_loop_two_backedge.mir
    M llvm/test/DebugInfo/MIR/X86/livedebugvalues_loop_two_backedge_clobbered.mir
    M llvm/test/DebugInfo/MIR/X86/livedebugvalues_loop_within_loop.mir
    M llvm/test/DebugInfo/MIR/X86/livedebugvalues_loop_within_loop_clobbered.mir
    M llvm/test/DebugInfo/MIR/X86/livedebugvalues_loop_within_loop_moved.mir
    M llvm/test/DebugInfo/MIR/X86/livedebugvalues_loop_within_loop_outer_moved.mir
    M llvm/test/DebugInfo/MIR/X86/livedebugvalues_many_loop_heads.mir
    M llvm/test/DebugInfo/MIR/X86/multiple-param-dbg-value-entry.mir
    M llvm/test/DebugInfo/MIR/X86/no-cfi-loc.mir

  Log Message:
  -----------
  [MIR,test] Change llc -march=x86-64 to -mtriple=x86_64

Similar to 806761a7629df268c8aed49657aeccffa6bca449

-mtriple= specifies the full target triple while -march= merely sets the
architecture part of the default target triple (e.g. Windows, macOS).

Therefore, -march= is error-prone and not recommended for tests without
a target triple. The issue has been benign as these MIR tests do not
utilize object file format specific detail, but it's good to change
these tests to neighbor files that use -mtriple=x86_64

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