[all-commits] [llvm/llvm-project] 82459e: [RISCV] Split OPERAND_SEW operand type for mask on...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 82459ecf3ebbc697bdde265320d126773111ae0f
      https://github.com/llvm/llvm-project/commit/82459ecf3ebbc697bdde265320d126773111ae0f
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2024-12-13 (Fri, 13 Dec 2024)

  Changed paths:
    M llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
    M llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
    M llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
    M llvm/test/CodeGen/RISCV/rvv/rvv-peephole-vmerge-to-vmv.mir

  Log Message:
  -----------
  [RISCV] Split OPERAND_SEW operand type for mask only instructions. (#119776)

Mask only instructions like vmand and vmsbf should always have 0 for
their Log2SEW operand.  Non-mask instructions should only have
3, 4, 5, or 6 for their Log2SEW operand.

Split the operand type so we can verify these cases separately.

I had to fix the SEW for whole register move to vmv.v.v copy
optimization and update an mir test. The vmv.v.v change isn't
functional since we have already done vsetvli insertion before and
nothing else uses the field after copy expansion. I can split these
changes off if desired.



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