[all-commits] [llvm/llvm-project] 3b3394: [RISCV] Use Log2SEW=0 for VMNAND/VMSET created for...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 3b3394baec18d77e8d5b984882c82f7b3a59f981
      https://github.com/llvm/llvm-project/commit/3b3394baec18d77e8d5b984882c82f7b3a59f981
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2024-12-13 (Fri, 13 Dec 2024)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
    M llvm/test/CodeGen/RISCV/rvv/vmsgeu.ll

  Log Message:
  -----------
  [RISCV] Use Log2SEW=0 for VMNAND/VMSET created for riscv_vmsge(u) intrinsics. (#119767)

These instructions should always be created with Log2SEW=0 and an LMUL
based on SEW=8. This is used by the vsetvli pass to know these
instructions only care about the ratio and not the specific value.

Looks like I fixed riscv_vmsge(u)_mask intrinsics years ago, but forgot
the unmasked intrinsics.

I'm working on an enhancement to our MachineVerifier checks that will
require VMNAND and VMSET to have Log2SEW=0.



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