[all-commits] [llvm/llvm-project] 668d96: [RISCV] Add Qualcomm uC Xqcilsm (Load Store Multip...

Sudharsan Veeravalli via All-commits all-commits at lists.llvm.org
Fri Dec 13 10:37:19 PST 2024


  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 668d9688ac8aa97d9156cecabd25bf2a8e82bc9d
      https://github.com/llvm/llvm-project/commit/668d9688ac8aa97d9156cecabd25bf2a8e82bc9d
  Author: Sudharsan Veeravalli <quic_svs at quicinc.com>
  Date:   2024-12-14 (Sat, 14 Dec 2024)

  Changed paths:
    M clang/test/Driver/print-supported-extensions-riscv.c
    M llvm/docs/RISCVUsage.rst
    M llvm/docs/ReleaseNotes.md
    M llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
    M llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
    M llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
    M llvm/lib/Target/RISCV/RISCVFeatures.td
    M llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
    M llvm/lib/TargetParser/RISCVISAInfo.cpp
    M llvm/test/CodeGen/RISCV/attributes.ll
    A llvm/test/MC/RISCV/xqcilsm-aliases-valid.s
    A llvm/test/MC/RISCV/xqcilsm-invalid.s
    A llvm/test/MC/RISCV/xqcilsm-valid.s
    M llvm/unittests/TargetParser/RISCVISAInfoTest.cpp

  Log Message:
  -----------
  [RISCV] Add Qualcomm uC Xqcilsm (Load Store Multiple) extension (#119823)

This extension adds 6 instructions that can do multi-word load/store.

The current spec can be found at:
https://github.com/quic/riscv-unified-db/releases/latest

This patch adds assembler only support.



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