[all-commits] [llvm/llvm-project] 4ef1f6: RegAlloc: Fix verifier error after failed allocation

[Matt Arsenault via All-commits]

  Branch: refs/heads/users/arsenm/regalloc-fix-verifier-error-after-fail
  Home:   https://github.com/llvm/llvm-project
  Commit: 4ef1f6eb46bc892a01e91dae9b6effd94827a32b
      https://github.com/llvm/llvm-project/commit/4ef1f6eb46bc892a01e91dae9b6effd94827a32b
  Author: Matt Arsenault <Matthew.Arsenault at amd.com>
  Date:   2024-12-13 (Fri, 13 Dec 2024)

  Changed paths:
    M llvm/lib/CodeGen/RegAllocBase.cpp
    M llvm/lib/CodeGen/RegAllocBase.h
    M llvm/lib/CodeGen/RegAllocBasic.cpp
    M llvm/lib/CodeGen/RegAllocGreedy.cpp
    M llvm/test/CodeGen/AMDGPU/illegal-eviction-assert.mir
    M llvm/test/CodeGen/AMDGPU/issue48473.mir
    M llvm/test/CodeGen/AMDGPU/ran-out-of-registers-error-all-regs-reserved.ll
    M llvm/test/CodeGen/AMDGPU/regalloc-failure-overlapping-insert-assert.mir
    A llvm/test/CodeGen/AMDGPU/register-killed-error-after-alloc-failure0.mir
    A llvm/test/CodeGen/AMDGPU/register-killed-error-after-alloc-failure1.ll
    M llvm/test/CodeGen/AMDGPU/remaining-virtual-register-operands.ll

  Log Message:
  -----------
  RegAlloc: Fix verifier error after failed allocation

In some cases after reporting an allocation failure, this would fail
the verifier. It picks the first allocatable register and assigns it,
but didn't update the liveness appropriately. When VirtRegRewriter
relied on the liveness to set kill flags, it would incorrectly add
kill flags if there was another overlapping kill of the virtual
register.

We can't properly assign the register to an overlapping range, so
break the liveness of the failing register (and any other interfering
registers) instead. Give the virtual register dummy liveness by
effectively deleting all the uses by setting them to undef.

The edge case not tested here which I'm worried about is if the read
of the register is a def of a subregister. I've been unable to come up
with a test where this occurs.

https://reviews.llvm.org/D122616



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