[all-commits] [llvm/llvm-project] a67bd9: [ValueTracking] Add missing operand checks in `com...
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Thu Dec 12 16:53:05 PST 2024
Branch: refs/heads/users/pcc/spr/targetparser-aarch64-add-part-numbers-for-apple-cpus
Home: https://github.com/llvm/llvm-project
Commit: a67bd94fdafce716b42e0cb5409ee451b20f1749
https://github.com/llvm/llvm-project/commit/a67bd94fdafce716b42e0cb5409ee451b20f1749
Author: Yingwei Zheng <dtcxzyw2333 at gmail.com>
Date: 2024-12-12 (Thu, 12 Dec 2024)
Changed paths:
M llvm/lib/Analysis/ValueTracking.cpp
M llvm/test/Transforms/InstCombine/fpclass-from-dom-cond.ll
Log Message:
-----------
[ValueTracking] Add missing operand checks in `computeKnownFPClassFromCond` (#119579)
After https://github.com/llvm/llvm-project/pull/118257, we may call
`computeKnownFPClassFromCond` with unrelated conditions. Then
miscompilations may occur due to a lack of operand checks.
This bug was introduced by
https://github.com/llvm/llvm-project/commit/d2404ea6ced5fce9442260bde08a02d607fdd50d
and https://github.com/llvm/llvm-project/pull/80740. However, the
miscompilation couldn't have happened before
https://github.com/llvm/llvm-project/pull/118257, because we only added
related conditions to `DomConditionCache/AssumptionCache`.
Fix the miscompilation reported in
https://github.com/llvm/llvm-project/pull/118257#issuecomment-2536182166.
Commit: 22f0ebb19cd216a1748263c4dbabcd832206f3ea
https://github.com/llvm/llvm-project/commit/22f0ebb19cd216a1748263c4dbabcd832206f3ea
Author: Owen Anderson <resistor at mac.com>
Date: 2024-12-12 (Thu, 12 Dec 2024)
Changed paths:
M llvm/include/llvm/Analysis/TargetLibraryInfo.h
M llvm/lib/Analysis/TargetLibraryInfo.cpp
M llvm/lib/Transforms/Utils/SimplifyLibCalls.cpp
M llvm/test/Transforms/InstCombine/stdio-custom-dl.ll
M llvm/test/Transforms/InstCombine/strcpy-nonzero-as.ll
M llvm/test/Transforms/MergeICmps/X86/distinct-index-width-crash.ll
Log Message:
-----------
TargetLibraryInfo: Use pointer index size to determine getSizeTSize(). (#118747)
When using non-integral pointer types, such as on CHERI targets, size_t
is equivalent
to the index size, which is allowed to be smaller than the size of the
pointer.
Commit: fd2f8d485df7742320317b14d49b9d808f70625c
https://github.com/llvm/llvm-project/commit/fd2f8d485df7742320317b14d49b9d808f70625c
Author: Vyacheslav Klochkov <vyacheslav.n.klochkov at intel.com>
Date: 2024-12-11 (Wed, 11 Dec 2024)
Changed paths:
M llvm/lib/Transforms/Vectorize/LoadStoreVectorizer.cpp
A llvm/test/Transforms/LoadStoreVectorizer/X86/massive_indirection.ll
Log Message:
-----------
[LoadStoreVectorizer] Postprocess and merge equivalence classes (#114501)
This patch introduces a new method:
void Vectorizer::mergeEquivalenceClasses(EquivalenceClassMap &EQClasses)
const
The method is called at the end of
Vectorizer::collectEquivalenceClasses() and is needed to merge
equivalence classes that differ only by their underlying objects (UO1
and UO2), where UO1 is 1-level-indirection underlying base for UO2. This
situation arises due to the limited lookup depth used during the search
of underlying bases with llvm::getUnderlyingObject(ptr).
Using any fixed lookup depth can result into creation of multiple
equivalence classes that only differ by 1-level indirection bases.
The new approach merges equivalence classes if they have adjacent bases
(1-level indirection). If a series of equivalence classes form ladder
formed of 1-step/level indirections, they are all merged into a single
equivalence class. This provides more opportunities for the load-store
vectorizer to generate better vectors.
---------
Signed-off-by: Klochkov, Vyacheslav N <vyacheslav.n.klochkov at intel.com>
Commit: da71203e6fc6b8e08c9979204506d385e9cb07b8
https://github.com/llvm/llvm-project/commit/da71203e6fc6b8e08c9979204506d385e9cb07b8
Author: Pengcheng Wang <wangpengcheng.pp at bytedance.com>
Date: 2024-12-12 (Thu, 12 Dec 2024)
Changed paths:
M llvm/include/llvm/CodeGen/MachineScheduler.h
M llvm/lib/CodeGen/MachineScheduler.cpp
M llvm/lib/CodeGen/VLIWMachineScheduler.cpp
M llvm/test/CodeGen/AArch64/dump-schedule-trace.mir
M llvm/test/CodeGen/AArch64/force-enable-intervals.mir
M llvm/test/CodeGen/AArch64/misched-detail-resource-booking-01.mir
M llvm/test/CodeGen/AArch64/misched-detail-resource-booking-02.mir
M llvm/test/CodeGen/AArch64/misched-sort-resource-in-trace.mir
M llvm/test/CodeGen/ARM/single-issue-r52.mir
M llvm/test/CodeGen/RISCV/sifive7-enable-intervals.mir
M llvm/test/CodeGen/X86/handle-move.ll
M llvm/test/CodeGen/X86/misched-aa-colored.ll
M llvm/test/CodeGen/X86/misched-matrix.ll
M llvm/test/CodeGen/X86/misched-new.ll
Log Message:
-----------
[MISched] Unify the way to specify scheduling direction (#119518)
For pre-ra scheduling, we use two options `-misched-topdown` and
`-misched-bottomup` to force the direction.
While for post-ra scheduling, we use `-misched-postra-direction`
with enumerated values (`topdown`, `bottomup` and `bidirectional`).
This is not unified and adds some mental burdens. Here we replace
these two options `-misched-topdown` and `-misched-bottomup` with
`-misched-prera-direction` with the same enumerated values.
To avoid the condition of `getNumOccurrences() > 0`, we add a new
enum value `Unspecified` and make it the default initial value.
These options are hidden, so we needn't keep the compatibility.
Commit: 0e80f9a1b51e0e068adeae1278d59cd7baacd5d8
https://github.com/llvm/llvm-project/commit/0e80f9a1b51e0e068adeae1278d59cd7baacd5d8
Author: Shubham Sandeep Rastogi <srastogi22 at apple.com>
Date: 2024-12-11 (Wed, 11 Dec 2024)
Changed paths:
A llvm/include/llvm/CodeGen/DroppedVariableStats.h
M llvm/include/llvm/Passes/StandardInstrumentations.h
M llvm/lib/CodeGen/CMakeLists.txt
A llvm/lib/CodeGen/DroppedVariableStats.cpp
M llvm/lib/Passes/StandardInstrumentations.cpp
M llvm/unittests/IR/CMakeLists.txt
A llvm/unittests/IR/DroppedVariableStatsIRTest.cpp
R llvm/unittests/IR/DroppedVariableStatsTest.cpp
Log Message:
-----------
Reland 2de78815604e9027efd93cac27c517bf732587d2 (#119650)
[NFC] Move DroppedVariableStats to its own file and redesign it to be
extensible. (#115563)
Move DroppedVariableStats code to its own file and change the class to
have an extensible design so that we can use it to add dropped
statistics to MIR passes and the instruction selector.
Removed the default virtual destructor from the base class and added an
empty one instead.
Commit: 990b6f08ad8089790dec52c6a9f8eec164d7caca
https://github.com/llvm/llvm-project/commit/990b6f08ad8089790dec52c6a9f8eec164d7caca
Author: LLVM GN Syncbot <llvmgnsyncbot at gmail.com>
Date: 2024-12-12 (Thu, 12 Dec 2024)
Changed paths:
M llvm/utils/gn/secondary/llvm/lib/CodeGen/BUILD.gn
M llvm/utils/gn/secondary/llvm/unittests/IR/BUILD.gn
Log Message:
-----------
[gn build] Port 0e80f9a1b51e
Commit: 10ed7d94b52c21317a1e02ef1e2c3ff2b2d08301
https://github.com/llvm/llvm-project/commit/10ed7d94b52c21317a1e02ef1e2c3ff2b2d08301
Author: Shubham Sandeep Rastogi <srastogi22 at apple.com>
Date: 2024-12-11 (Wed, 11 Dec 2024)
Changed paths:
M llvm/unittests/CodeGen/CMakeLists.txt
A llvm/unittests/CodeGen/DroppedVariableStatsIRTest.cpp
M llvm/unittests/IR/CMakeLists.txt
R llvm/unittests/IR/DroppedVariableStatsIRTest.cpp
Log Message:
-----------
Move DroppedVariableStatsIRTest.cpp to CodeGen folder
Commit: ed5d897938d4344304a37a7d634b9cc4ed174e8b
https://github.com/llvm/llvm-project/commit/ed5d897938d4344304a37a7d634b9cc4ed174e8b
Author: LLVM GN Syncbot <llvmgnsyncbot at gmail.com>
Date: 2024-12-12 (Thu, 12 Dec 2024)
Changed paths:
M llvm/utils/gn/secondary/llvm/unittests/CodeGen/BUILD.gn
M llvm/utils/gn/secondary/llvm/unittests/IR/BUILD.gn
Log Message:
-----------
[gn build] Port 10ed7d94b52c
Commit: 04313b86a52541b2a618d14f7fa1f23ea7adfa47
https://github.com/llvm/llvm-project/commit/04313b86a52541b2a618d14f7fa1f23ea7adfa47
Author: Michal Paszkowski <michal at paszkowski.org>
Date: 2024-12-11 (Wed, 11 Dec 2024)
Changed paths:
M llvm/lib/Transforms/Vectorize/LoadStoreVectorizer.cpp
R llvm/test/Transforms/LoadStoreVectorizer/X86/massive_indirection.ll
Log Message:
-----------
Revert "[LoadStoreVectorizer] Postprocess and merge equivalence classes" (#119657)
Reverts llvm/llvm-project#114501, due to the following failure:
https://lab.llvm.org/buildbot/#/builders/55/builds/4171
Commit: 64fadf17cf9a2ad26b16a778fc4e2141ae6a8d64
https://github.com/llvm/llvm-project/commit/64fadf17cf9a2ad26b16a778fc4e2141ae6a8d64
Author: Kazu Hirata <kazu at google.com>
Date: 2024-12-11 (Wed, 11 Dec 2024)
Changed paths:
M llvm/unittests/ProfileData/MemProfTest.cpp
Log Message:
-----------
[memprof] Use IndexedMemProfData in unit tests (NFC) (#119648)
This patch uses IndexedMemProfData in unit tests even when we only
need CallStacks. This way, we get to use addCallStack. Also, the
look is more consistent with other unit tests, where we typically do:
IndexMemProfData MemProfData;
MemProfData.addFrame(...);
MemProfData.addCallStack(...);
// Run some tests
Commit: 48ed91871dccf12dbe27e96b457ccee373c68a1e
https://github.com/llvm/llvm-project/commit/48ed91871dccf12dbe27e96b457ccee373c68a1e
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-12-11 (Wed, 11 Dec 2024)
Changed paths:
M llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
Log Message:
-----------
[RISCV] Use OperandType from MCInstrDesc in RISCVInstrInfo::createMIROperandComment. NFCI (#119637)
We can use the OperandType to directly get the type of operand. This
avoids the need to hardcode specific opcodes or match the operand index
against sew operand number or policy operand number.
Commit: 02dd73a5d585af9a950baa38855305fdb17c76af
https://github.com/llvm/llvm-project/commit/02dd73a5d585af9a950baa38855305fdb17c76af
Author: Kazu Hirata <kazu at google.com>
Date: 2024-12-11 (Wed, 11 Dec 2024)
Changed paths:
M clang/include/clang/Lex/PreprocessingRecord.h
M clang/include/clang/Lex/Preprocessor.h
M clang/lib/Analysis/PathDiagnostic.cpp
M clang/lib/Basic/FileManager.cpp
M clang/lib/Index/FileIndexRecord.cpp
M clang/lib/Index/IndexDecl.cpp
M clang/tools/libclang/CIndex.cpp
M clang/tools/libclang/CIndexCXX.cpp
M clang/utils/TableGen/ClangDiagnosticsEmitter.cpp
Log Message:
-----------
[clang] Migrate away from PointerUnion::{is,get} (NFC) (#119654)
Note that PointerUnion::{is,get} have been soft deprecated in
PointerUnion.h:
// FIXME: Replace the uses of is(), get() and dyn_cast() with
// isa<T>, cast<T> and the llvm::dyn_cast<T>
I'm not touching PointerUnion::dyn_cast for now because it's a bit
complicated; we could blindly migrate it to dyn_cast_if_present, but
we should probably use dyn_cast when the operand is known to be
non-null.
Commit: 2698fc699bfd6d62c5f9c2febfdbd2f3505bfdaf
https://github.com/llvm/llvm-project/commit/2698fc699bfd6d62c5f9c2febfdbd2f3505bfdaf
Author: Luke Lau <luke at igalia.com>
Date: 2024-12-12 (Thu, 12 Dec 2024)
Changed paths:
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
Log Message:
-----------
[RISCV] Refactor helper in isDesirableToCommuteWithShift. NFC (#119526)
Instead of duplicating the loop twice, add arguments to the lambda.
I plan on reusing this in #119527
Commit: b26fe5b7e9833b7813459c6a0dc4577b350754f1
https://github.com/llvm/llvm-project/commit/b26fe5b7e9833b7813459c6a0dc4577b350754f1
Author: Luke Lau <luke at igalia.com>
Date: 2024-12-12 (Thu, 12 Dec 2024)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlan.cpp
M llvm/lib/Transforms/Vectorize/VPlanAnalysis.cpp
M llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
Log Message:
-----------
[VPlan] Use variadic isa<> in a few more places. NFC (#119538)
Commit: 088db868f3370ffe01c9750f75732679efecd1fe
https://github.com/llvm/llvm-project/commit/088db868f3370ffe01c9750f75732679efecd1fe
Author: Luke Lau <luke at igalia.com>
Date: 2024-12-12 (Thu, 12 Dec 2024)
Changed paths:
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-shuffles.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-shuffles.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-interleaved-access.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-deinterleave.ll
Log Message:
-----------
[RISCV] Merge shuffle sources if lanes are disjoint (#119401)
In x264, there's a few kernels with shuffles like this:
%41 = add nsw <16 x i32> %39, %40
%42 = sub nsw <16 x i32> %39, %40
%43 = shufflevector <16 x i32> %41, <16 x i32> %42, <16 x i32> <i32 11,
i32 15, i32 7, i32 3, i32 26, i32 30, i32 22, i32 18, i32 9, i32 13, i32
5, i32 1, i32 24, i32 28, i32 20, i32 16>
Because this is a complex two-source shuffle, this will get lowered as
two vrgather.vvs that are blended together.
vadd.vv v20, v16, v12
vsub.vv v12, v16, v12
vrgatherei16.vv v24, v20, v10
vrgatherei16.vv v24, v12, v16, v0.t
However the indices coming from each source are disjoint, so we can
blend the two together and perform a single source shuffle instead:
%41 = add nsw <16 x i32> %39, %40
%42 = sub nsw <16 x i32> %39, %40
%43 = select <0,0,0,0,1,1,1,1,0,0,0,0,1,1,1,1> %41, %42
%44 = shufflevector <16 x i32> %43, <16 x i32> poison, <16 x i32> <i32
11, i32 15, i32 7, i32 3, i32 10, i32 14, i32 6, i32 2, i32 9, i32 13,
i32 5, i32 1, i32 8, i32 12, i32 4, i32 0>
The select will likely get merged into the preceding instruction, and
then we only have to do one vrgather.vv:
vadd.vv v20, v16, v12
vsub.vv v20, v16, v12, v0.t
vrgatherei16.vv v24, v20, v10
This patch bails if either of the sources are a broadcast/splat/identity
shuffle, since that will usually already have some sort of cheaper
lowering.
This improves performance on 525.x264_r by 4.12% with -O3 -flto
-march=rva22u64_v on the spacemit-x60.
Commit: 0614c601b44ca2f214a9868a8b672ea695d5d56a
https://github.com/llvm/llvm-project/commit/0614c601b44ca2f214a9868a8b672ea695d5d56a
Author: quic_hchandel <165007698+hchandel at users.noreply.github.com>
Date: 2024-12-12 (Thu, 12 Dec 2024)
Changed paths:
M clang/test/Driver/print-supported-extensions-riscv.c
M llvm/docs/RISCVUsage.rst
M llvm/docs/ReleaseNotes.md
M llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
M llvm/lib/Target/RISCV/RISCVFeatures.td
M llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
M llvm/lib/TargetParser/RISCVISAInfo.cpp
M llvm/test/CodeGen/RISCV/attributes.ll
A llvm/test/MC/RISCV/xqcics-invalid.s
A llvm/test/MC/RISCV/xqcics-valid.s
M llvm/unittests/TargetParser/RISCVISAInfoTest.cpp
Log Message:
-----------
[RISCV] Add Qualcomm uC Xqcics(Conditional Select) extension (#119504)
The Qualcomm uC Xqcics extension adds 8 conditional select instructions.
The current spec can be found at:
https://github.com/quic/riscv-unified-db/releases/latest
This patch adds assembler only support.
---------
Co-authored-by: Harsh Chandel <hchandel at qti.qualcomm.com>
Commit: 22d26ae3040095c7bfe4e2f1678b9738bf81fd4a
https://github.com/llvm/llvm-project/commit/22d26ae3040095c7bfe4e2f1678b9738bf81fd4a
Author: Piotr Fusik <p.fusik at samsung.com>
Date: 2024-12-12 (Thu, 12 Dec 2024)
Changed paths:
M llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
A llvm/test/CodeGen/RISCV/and-shl.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp2i.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-buildvec.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-gather.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-scatter.ll
Log Message:
-----------
[RISCV] Optimize (slli (srli (slli X, C1), C1), C2) -> (srli (slli X, C1), C1-C2) (#119567)
Masking out most significant bits can be done with shl followed by srl
with same shift amount. If this is followed by a shl, we could instead
srl by a smaller amount of bits.
This transform is already implemented in tablegen for masking out
32 most significant bits.
Emits better code for e.g.
float *index(float *p, int i)
{
return p + (i & (1 << 30) - 1);
}
Commit: 077cc3deeebedbd088c6183a191b4dd67861b350
https://github.com/llvm/llvm-project/commit/077cc3deeebedbd088c6183a191b4dd67861b350
Author: Shubham Sandeep Rastogi <srastogi22 at apple.com>
Date: 2024-12-11 (Wed, 11 Dec 2024)
Changed paths:
R llvm/include/llvm/CodeGen/DroppedVariableStats.h
M llvm/include/llvm/Passes/StandardInstrumentations.h
M llvm/lib/CodeGen/CMakeLists.txt
R llvm/lib/CodeGen/DroppedVariableStats.cpp
M llvm/lib/Passes/StandardInstrumentations.cpp
M llvm/unittests/CodeGen/CMakeLists.txt
R llvm/unittests/CodeGen/DroppedVariableStatsIRTest.cpp
M llvm/unittests/IR/CMakeLists.txt
A llvm/unittests/IR/DroppedVariableStatsTest.cpp
Log Message:
-----------
Revert "Move DroppedVariableStatsIRTest.cpp to CodeGen folder"
This reverts commit 10ed7d94b52c21317a1e02ef1e2c3ff2b2d08301.
Revert "Reland 2de78815604e9027efd93cac27c517bf732587d2 (#119650)"
This reverts commit 0e80f9a1b51e0e068adeae1278d59cd7baacd5d8.
This is because the clang-ppc64le-linux-multistage bot breaks with error
undefined reference to `vtable for llvm::DroppedVariableStatsIR'
Commit: 925471ed903dad871042d7ed0bab89ab6566a564
https://github.com/llvm/llvm-project/commit/925471ed903dad871042d7ed0bab89ab6566a564
Author: Dmitry Vasilyev <dvassiliev at accesssoftek.com>
Date: 2024-12-12 (Thu, 12 Dec 2024)
Changed paths:
M llvm/lib/Support/Windows/Path.inc
Log Message:
-----------
[llvm][Support][Windows] Avoid crash calling remove_directories() (#118677)
We faced an unexpected crash in SHELL32_CallFileCopyHooks() on the buildbot
[lldb-remote-linux-win](https://lab.llvm.org/staging/#/builders/197/builds/1066).
The host is Windows Server 2022 w/o any 3rd party shell extensions. See #118032 for more details.
Based on [this article](https://devblogs.microsoft.com/oldnewthing/20120330-00/?p=7963).
Commit: bff6fee6303909651cd3018b6403f9a709421fa6
https://github.com/llvm/llvm-project/commit/bff6fee6303909651cd3018b6403f9a709421fa6
Author: LLVM GN Syncbot <llvmgnsyncbot at gmail.com>
Date: 2024-12-12 (Thu, 12 Dec 2024)
Changed paths:
M llvm/utils/gn/secondary/llvm/lib/CodeGen/BUILD.gn
M llvm/utils/gn/secondary/llvm/unittests/CodeGen/BUILD.gn
M llvm/utils/gn/secondary/llvm/unittests/IR/BUILD.gn
Log Message:
-----------
[gn build] Port 077cc3deeebe
Commit: ef28e963e3cf5bca8cb37b053f5840f8541987b3
https://github.com/llvm/llvm-project/commit/ef28e963e3cf5bca8cb37b053f5840f8541987b3
Author: Chandler Carruth <chandlerc at gmail.com>
Date: 2024-12-11 (Wed, 11 Dec 2024)
Changed paths:
A llvm/include/llvm/ADT/StringTable.h
M llvm/unittests/ADT/CMakeLists.txt
A llvm/unittests/ADT/StringTableTest.cpp
Log Message:
-----------
Add a super simple wrapper for a merged string table. (#119488)
Suggestions welcome on what to better name this -- `StringTable` as I
currently have it seems too general, but wasn't sure what other name
would be better.
It currently has a *very* minimal API. I'm happy to expand it if folks
have ideas for what API would be useful, but this actually seemed like
it might be all we really need.
Commit: 9992b1624303262407ff82413563f39ba40544a0
https://github.com/llvm/llvm-project/commit/9992b1624303262407ff82413563f39ba40544a0
Author: LLVM GN Syncbot <llvmgnsyncbot at gmail.com>
Date: 2024-12-12 (Thu, 12 Dec 2024)
Changed paths:
M llvm/utils/gn/secondary/llvm/unittests/ADT/BUILD.gn
Log Message:
-----------
[gn build] Port ef28e963e3cf
Commit: 9c50182bf4942f88cc9876eb29e70802448cddc8
https://github.com/llvm/llvm-project/commit/9c50182bf4942f88cc9876eb29e70802448cddc8
Author: Malavika Samak <malavika.samak at gmail.com>
Date: 2024-12-12 (Thu, 12 Dec 2024)
Changed paths:
M clang/lib/Analysis/UnsafeBufferUsage.cpp
M clang/test/SemaCXX/warn-unsafe-buffer-usage-array.cpp
M clang/test/SemaCXX/warn-unsafe-buffer-usage-field-attr.cpp
M clang/test/SemaCXX/warn-unsafe-buffer-usage-fixits-parm-unsupported.cpp
M clang/test/SemaCXX/warn-unsafe-buffer-usage.cpp
Log Message:
-----------
[-Wunsafe-buffer-usage] Suppress warning for multi-dimensional constant arrays (#118249)
Do not warn about unsafe buffer access, when multi-dimensional constant
arrays are accessed and their indices are within the bounds of the
buffer. Warning in such cases would be a false positive. Such a
suppression already exists for 1-d
arrays and it is now extended to multi-dimensional arrays.
(rdar://137926311)
(rdar://140320139)
Co-authored-by: MalavikaSamak <malavika2 at apple.com>
Commit: 8713914d76cb9d6b54278dd75fecb68bb93f6ea5
https://github.com/llvm/llvm-project/commit/8713914d76cb9d6b54278dd75fecb68bb93f6ea5
Author: Timm Baeder <tbaeder at redhat.com>
Date: 2024-12-12 (Thu, 12 Dec 2024)
Changed paths:
M clang/lib/AST/ByteCode/BitcastBuffer.h
M clang/lib/AST/ByteCode/InterpBuiltin.cpp
M clang/lib/AST/ByteCode/InterpBuiltinBitCast.cpp
M clang/lib/AST/ByteCode/InterpBuiltinBitCast.h
M clang/test/AST/ByteCode/builtin-functions.cpp
Log Message:
-----------
[clang][bytecode] Handle __builtin_memcmp (#119544)
Commit: cfad8f14f846860b5c2e413c41c9b2b56466662e
https://github.com/llvm/llvm-project/commit/cfad8f14f846860b5c2e413c41c9b2b56466662e
Author: Timm Bäder <tbaeder at redhat.com>
Date: 2024-12-12 (Thu, 12 Dec 2024)
Changed paths:
M clang/lib/AST/ByteCode/InterpBuiltin.cpp
Log Message:
-----------
[clang][bytecode] Fix a build failure on aarch64
This broke e.g.
https://lab.llvm.org/buildbot/#/builders/190/builds/11216
Commit: 737d78a9785ea3e928de2b36a4e3e7decd8c9491
https://github.com/llvm/llvm-project/commit/737d78a9785ea3e928de2b36a4e3e7decd8c9491
Author: Carlo Cabrera <github at carlo.cab>
Date: 2024-12-12 (Thu, 12 Dec 2024)
Changed paths:
M clang/lib/Driver/ToolChains/Darwin.cpp
M clang/test/Driver/sysroot.c
Log Message:
-----------
[Darwin][Driver][clang] Prioritise command line args over `DEFAULT_SYSROOT` (#115993)
If a toolchain is configured with `DEFAULT_SYSROOT`, then this could
result in an unintended value for `-syslibroot` being passed to the
linker if the user manually sets `-isysroot` or `SDKROOT`.
Let's fix this by prioritising command line flags when determining
`-syslibroot` before checking `getSysRoot`.
Downstream bug report:
https://github.com/Homebrew/homebrew-core/issues/197277
Co-authored-by: Bo Anderson <mail at boanderson.me>
Co-authored-by: Bo Anderson <mail at boanderson.me>
Commit: 0876c11ceeb093904decc4d89bef213d483a5656
https://github.com/llvm/llvm-project/commit/0876c11ceeb093904decc4d89bef213d483a5656
Author: Akshat Oke <Akshat.Oke at amd.com>
Date: 2024-12-12 (Thu, 12 Dec 2024)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
M llvm/test/tools/llc/new-pm/regalloc-amdgpu.mir
Log Message:
-----------
[AMDGPU] Parse wwm filter flag for regalloc fast (#119347)
Commit: b3cba9be41bfa89bc0ec212706c6028a901e127a
https://github.com/llvm/llvm-project/commit/b3cba9be41bfa89bc0ec212706c6028a901e127a
Author: Mel Chen <mel.chen at sifive.com>
Date: 2024-12-12 (Thu, 12 Dec 2024)
Changed paths:
M llvm/include/llvm/Analysis/IVDescriptors.h
M llvm/include/llvm/Transforms/Utils/LoopUtils.h
M llvm/lib/Analysis/IVDescriptors.cpp
M llvm/lib/Transforms/Utils/LoopUtils.cpp
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
M llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
A llvm/test/Transforms/LoopVectorize/iv-select-cmp-blend.ll
M llvm/test/Transforms/LoopVectorize/iv-select-cmp-no-wrap.ll
M llvm/test/Transforms/LoopVectorize/iv-select-cmp-trunc.ll
M llvm/test/Transforms/LoopVectorize/iv-select-cmp.ll
M llvm/test/Transforms/LoopVectorize/select-min-index.ll
Log Message:
-----------
[LoopVectorize] Vectorize select-cmp reduction pattern for increasing integer induction variable (#67812)
Consider the following loop:
```
int rdx = init;
for (int i = 0; i < n; ++i)
rdx = (a[i] > b[i]) ? i : rdx;
```
We can vectorize this loop if `i` is an increasing induction variable.
The final reduced value will be the maximum of `i` that the condition
`a[i] > b[i]` is satisfied, or the start value `init`.
This patch added new RecurKind enums - IFindLastIV and FFindLastIV.
---------
Co-authored-by: Alexey Bataev <5361294+alexey-bataev at users.noreply.github.com>
Commit: 2a825cd2f93b5f83029c36d6c8229f65b6ef2ec7
https://github.com/llvm/llvm-project/commit/2a825cd2f93b5f83029c36d6c8229f65b6ef2ec7
Author: Kazu Hirata <kazu at google.com>
Date: 2024-12-12 (Thu, 12 Dec 2024)
Changed paths:
M clang/include/clang/AST/APValue.h
M clang/include/clang/AST/Decl.h
M clang/include/clang/AST/DeclContextInternals.h
M clang/include/clang/AST/DeclTemplate.h
M clang/include/clang/AST/ExprConcepts.h
M clang/include/clang/AST/ExternalASTSource.h
M clang/include/clang/AST/Redeclarable.h
M clang/include/clang/AST/Type.h
Log Message:
-----------
[AST] Migrate away from PointerUnion::{is,get} (NFC) (#119673)
Note that PointerUnion::{is,get} have been soft deprecated in
PointerUnion.h:
// FIXME: Replace the uses of is(), get() and dyn_cast() with
// isa<T>, cast<T> and the llvm::dyn_cast<T>
I'm not touching PointerUnion::dyn_cast for now because it's a bit
complicated; we could blindly migrate it to dyn_cast_if_present, but
we should probably use dyn_cast when the operand is known to be
non-null.
Commit: e84566ff2b8e9bb67ccc6764d7003871535e550e
https://github.com/llvm/llvm-project/commit/e84566ff2b8e9bb67ccc6764d7003871535e550e
Author: Carlo Cabrera <github at carlo.cab>
Date: 2024-12-12 (Thu, 12 Dec 2024)
Changed paths:
M libc/CMakeLists.txt
Log Message:
-----------
[libc] Fail fast when building standalone (#119426)
Building with the source directory rooted in the libc subdirectory isn't
tested in CI and can lead to subtle build problems (cf. #118871).
Let's fail fast with a helpful error message instead to help users
configure libc correctly.
Co-authored-by: Nick Desaulniers <nickdesaulniers at users.noreply.github.com>
Commit: 08c9bb21482db443a8d5f84e9821abfbce4e9452
https://github.com/llvm/llvm-project/commit/08c9bb21482db443a8d5f84e9821abfbce4e9452
Author: Sudharsan Veeravalli <quic_svs at quicinc.com>
Date: 2024-12-12 (Thu, 12 Dec 2024)
Changed paths:
M llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
Log Message:
-----------
[RISCV] Change func to funct in RISCVInstrInfoXqci.td. NFC (#119669)
Commit: 32403f79f4fcdb74b1576eed19cde7b104191808
https://github.com/llvm/llvm-project/commit/32403f79f4fcdb74b1576eed19cde7b104191808
Author: Tom Eccles <tom.eccles at arm.com>
Date: 2024-12-12 (Thu, 12 Dec 2024)
Changed paths:
M flang/unittests/Runtime/AccessTest.cpp
Log Message:
-----------
[flang][unittests] fix test broken when run as root (#119604)
It is convenient to run tests as root inside of a docker container.
The test (and the library function it is testing) are already
unsupported on Windows so it is safe to use UNIX-isms here.
Commit: ff13f61ec9bc8ae170ef8ab4eb66b00408f302f6
https://github.com/llvm/llvm-project/commit/ff13f61ec9bc8ae170ef8ab4eb66b00408f302f6
Author: Nikita Popov <npopov at redhat.com>
Date: 2024-12-12 (Thu, 12 Dec 2024)
Changed paths:
M llvm/Maintainers.md
Log Message:
-----------
[LLVM] Update TableGen maintainer (#119569)
Update the maintainer for TableGen to jurahul, who has been driving
most of the recent development in this area.
Commit: e3352904309a539eddcf3ddd9fb11ca2aef29d65
https://github.com/llvm/llvm-project/commit/e3352904309a539eddcf3ddd9fb11ca2aef29d65
Author: Nikita Popov <npopov at redhat.com>
Date: 2024-12-12 (Thu, 12 Dec 2024)
Changed paths:
M llvm/Maintainers.md
Log Message:
-----------
[LLVM] Update MC maintainer (#119571)
We currently list Jim Grosbach as the maintainer for the MC layer --
however, he hasn't been involved in LLVM for about ten years.
I'd like to propose MaskRay as the replacement. I think he has done
most of the substantial MC work in recent times.
Commit: 5013c81b781eb95af8e429956d63c8f9c16a4647
https://github.com/llvm/llvm-project/commit/5013c81b781eb95af8e429956d63c8f9c16a4647
Author: Nikita Popov <npopov at redhat.com>
Date: 2024-12-12 (Thu, 12 Dec 2024)
Changed paths:
M llvm/include/llvm/Transforms/Utils/Evaluator.h
M llvm/lib/Transforms/Utils/Evaluator.cpp
M llvm/test/Transforms/GlobalOpt/evaluate-call-errors.ll
M llvm/test/Transforms/GlobalOpt/evaluate-constfold-call.ll
A llvm/test/Transforms/GlobalOpt/evaluate-ret-void-mismatch.ll
Log Message:
-----------
[GlobalOpt][Evaluator] Don't evaluate calls with signature mismatch (#119548)
The global ctor evaluator tries to evalute function calls where the call
function type and function type do not match, by performing bitcasts.
This currently causes a crash when calling a void function with non-void
return type.
I've opted to remove this functionality entirely rather than fixing this
specific case. With opaque pointers, there shouldn't be a legitimate use
case for this anymore, as we don't need to look through pointer type
casts. Doing other bitcasts is very iffy because it ignores ABI
considerations. We should at least leave adjusting the signatures to
make them line up to InstCombine (which also does some iffy things, but
is at least somewhat more constrained).
Fixes https://github.com/llvm/llvm-project/issues/118725.
Commit: 98470c0b2e0eef52e6900bf2d524a390edac9d58
https://github.com/llvm/llvm-project/commit/98470c0b2e0eef52e6900bf2d524a390edac9d58
Author: Timm Baeder <tbaeder at redhat.com>
Date: 2024-12-12 (Thu, 12 Dec 2024)
Changed paths:
M clang/lib/AST/ByteCode/InterpBuiltin.cpp
M clang/test/AST/ByteCode/builtin-functions.cpp
Log Message:
-----------
[clang][bytecode] Handle __builtin_bcmp (#119678)
... the same as `__builtin_memcmp`. Also fix a bug we still had when we
couldn't find a difference in the two inputs after `Size` bytes.
Commit: 5ca26d769deedc931ce19b4a68a68c799f8d7564
https://github.com/llvm/llvm-project/commit/5ca26d769deedc931ce19b4a68a68c799f8d7564
Author: Kerry McLaughlin <kerry.mclaughlin at arm.com>
Date: 2024-12-12 (Thu, 12 Dec 2024)
Changed paths:
M llvm/lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
M llvm/lib/Target/AArch64/AArch64RegisterInfo.cpp
M llvm/lib/Target/AArch64/AArch64RegisterInfo.h
M llvm/lib/Target/AArch64/SMEInstrFormats.td
M llvm/test/CodeGen/AArch64/sme2-intrinsics-int-dots.ll
M llvm/test/CodeGen/AArch64/sme2-intrinsics-vdot.ll
Log Message:
-----------
[AArch64][SME2] Improve register allocation of multi-vector SME intrinsics (#116399)
The FORM_TRANSPOSED_REG_TUPLE pseudos have been created to
improve register allocation for intrinsics which use strided and
contiguous multi-vector registers, avoiding unnecessary copies.
If the operands of the pseudo are copies where the source register is in
the StridedOrContiguous class, the pseudo is used by
getRegAllocationHints
to suggest a contigious multi-vector register which matches the
subregister
sequence used by the operands.
If the operands do not match this pattern, the pseudos are expanded
to a REG_SEQUENCE.
Patch contains changes by Matthew Devereau.
Commit: ceb7214be0287f536b292a41f8a7dc2e1467d72d
https://github.com/llvm/llvm-project/commit/ceb7214be0287f536b292a41f8a7dc2e1467d72d
Author: Kristof Beyls <kristof.beyls at arm.com>
Date: 2024-12-12 (Thu, 12 Dec 2024)
Changed paths:
A bolt/docs/BinaryAnalysis.md
M bolt/include/bolt/Rewrite/RewriteInstance.h
M bolt/include/bolt/Utils/CommandLineOpts.h
M bolt/lib/Rewrite/RewriteInstance.cpp
M bolt/lib/Utils/CommandLineOpts.cpp
M bolt/test/CMakeLists.txt
A bolt/test/binary-analysis/AArch64/Inputs/dummy.txt
A bolt/test/binary-analysis/AArch64/cmdline-args.test
A bolt/test/binary-analysis/AArch64/lit.local.cfg
M bolt/test/lit.cfg.py
M bolt/tools/CMakeLists.txt
A bolt/tools/binary-analysis/CMakeLists.txt
A bolt/tools/binary-analysis/binary-analysis.cpp
Log Message:
-----------
[BOLT] Introduce binary analysis tool based on BOLT (#115330)
This initial commit does not add any specific binary analyses yet, it
merely contains the boilerplate to introduce a new BOLT-based tool.
This basically combines the 4 first patches from the prototype pac-ret
and stack-clash binary analyzer discussed in RFC
https://discourse.llvm.org/t/rfc-bolt-based-binary-analysis-tool-to-verify-correctness-of-security-hardening/78148
and published at
https://github.com/llvm/llvm-project/compare/main...kbeyls:llvm-project:bolt-gadget-scanner-prototype
The introduction of such a BOLT-based binary analysis tool was proposed
and discussed in at least the following places:
- The RFC pointed to above
- EuroLLVM 2024 round table
https://discourse.llvm.org/t/summary-of-bolt-as-a-binary-analysis-tool-round-table-at-eurollvm/78441
The round table showed quite a few people interested in being able to
build a custom binary analysis quickly with a tool like this.
- Also at the US LLVM dev meeting a few weeks ago, I heard interest from
a few people, asking when the tool would be available upstream.
- The presentation "Adding Pointer Authentication ABI support for your
ELF platform"
(https://llvm.swoogo.com/2024devmtg/session/2512720/adding-pointer-authentication-abi-support-for-your-elf-platform)
explicitly mentioned interest to extend the prototype tool to verify
correct implementation of pauthabi.
Commit: 2fae58e9c7becc376454005da69acb3fa993350e
https://github.com/llvm/llvm-project/commit/2fae58e9c7becc376454005da69acb3fa993350e
Author: David Spickett <david.spickett at linaro.org>
Date: 2024-12-12 (Thu, 12 Dec 2024)
Changed paths:
M lldb/unittests/Host/PipeTest.cpp
Log Message:
-----------
[lldb][test] Disable WriteWithTimeout test on Windows
This is still flaky on our Windows on Arm bot:
******************** TEST 'lldb-unit :: Host/./HostTests.exe/8/10' FAILED ********************
Script(shard):
--
GTEST_OUTPUT=json:C:\Users\tcwg\llvm-worker\lldb-aarch64-windows\build\tools\lldb\unittests\Host\.\HostTests.exe-lldb-unit-3616-8-10.json GTEST_SHUFFLE=0 GTEST_TOTAL_SHARDS=10 GTEST_SHARD_INDEX=8 C:\Users\tcwg\llvm-worker\lldb-aarch64-windows\build\tools\lldb\unittests\Host\.\HostTests.exe
--
Script:
--
C:\Users\tcwg\llvm-worker\lldb-aarch64-windows\build\tools\lldb\unittests\Host\.\HostTests.exe --gtest_filter=PipeTest.WriteWithTimeout
--
C:\Users\tcwg\llvm-worker\lldb-aarch64-windows\llvm-project\lldb\unittests\Host\PipeTest.cpp(110): error: Expected: (dur) >= (std::chrono::seconds(2)), actual: 8-byte object <1C-A6 34-77 00-00 00-00> vs 8-byte object <02-00 00-00 00-00 00-00>
C:\Users\tcwg\llvm-worker\lldb-aarch64-windows\llvm-project\lldb\unittests\Host\PipeTest.cpp:110
Expected: (dur) >= (std::chrono::seconds(2)), actual: 8-byte object <1C-A6 34-77 00-00 00-00> vs 8-byte object <02-00 00-00 00-00 00-00>
Commit: 7f4312015291a32d811a0f37e24b4d9736c524f7
https://github.com/llvm/llvm-project/commit/7f4312015291a32d811a0f37e24b4d9736c524f7
Author: Ilya Biryukov <ibiryukov at google.com>
Date: 2024-12-12 (Thu, 12 Dec 2024)
Changed paths:
M clang/unittests/Serialization/LoadSpecLazilyTest.cpp
Log Message:
-----------
[Serialization] Free memory in LoadSpecLazilyTest
Default Clang invocations set DisableFree = true, which causes ASAN to
complain. Override it in tests that are not supposed to leak.
Commit: 5e247d726d7a54cf0acc997bc17b50e7494e6fa3
https://github.com/llvm/llvm-project/commit/5e247d726d7a54cf0acc997bc17b50e7494e6fa3
Author: David Green <david.green at arm.com>
Date: 2024-12-12 (Thu, 12 Dec 2024)
Changed paths:
M llvm/include/llvm/Analysis/PtrUseVisitor.h
M llvm/include/llvm/Transforms/Utils/SSAUpdater.h
M llvm/lib/Transforms/Scalar/SROA.cpp
M llvm/lib/Transforms/Utils/SSAUpdater.cpp
M llvm/test/Transforms/SROA/non-capturing-call-readonly.ll
M llvm/test/Transforms/SROA/readonlynocapture.ll
Log Message:
-----------
[SROA] Optimize reloaded values in allocas that escape into readonly nocapture calls. (#116645)
Given an alloca that potentially has many uses in big complex code and
escapes into a call that is readonly+nocapture, we cannot easily split
up the alloca. There are several optimizations that will attempt to take
a value that is stored and a reload, and replace the load with the
original stored value. Instcombine has some simple heuristics, GVN can
sometimes do it, as can CSE in limited situations. They all suffer from
the same issue with complex code - they start from a load/store and need
to prove no-alias for all code between, which in complex cases might be
a lot to look through. Especially if the ptr is an alloca with many uses
that is over the normal escape capture limits.
The pass that does do well with allocas is SROA, as it has a complete
view of all of the uses. This patch adds a case to SROA where it can
detect allocas that are passed into calls that are no-capture readonly.
It can then optimize the reloaded values inside the alloca slice with
the stored value knowing that it is valid no matter the location of the
loads/stores from the no-escaping nature of the alloca.
Commit: a611d67601528cb18ae26794a1482cff59ca5254
https://github.com/llvm/llvm-project/commit/a611d67601528cb18ae26794a1482cff59ca5254
Author: LiqinWeng <liqin.weng at spacemit.com>
Date: 2024-12-12 (Thu, 12 Dec 2024)
Changed paths:
M llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
M llvm/test/CodeGen/RISCV/rvv/sink-splat-operands.ll
Log Message:
-----------
[RISCV][TTI] Add llvm.fmuladd and llvm.vp.fmuladd into canSplatOperand (#119508)
The first or second operand of fmuladd is a splat operand , it can help
fmuladd fold vv instructions to vf instructions.
Commit: 5b077506de26b1dfce1926895548b86f2106bed9
https://github.com/llvm/llvm-project/commit/5b077506de26b1dfce1926895548b86f2106bed9
Author: Jie Fu <jiefu at tencent.com>
Date: 2024-12-12 (Thu, 12 Dec 2024)
Changed paths:
M llvm/lib/Transforms/Scalar/SROA.cpp
Log Message:
-----------
[Transforms] Silence a warning in SROA.cpp (NFC)
/llvm-project/llvm/lib/Transforms/Scalar/SROA.cpp:5526:48:
error: '&&' within '||' [-Werror,-Wlogical-op-parentheses]
if (!SI->isSimple() || PartitionType && UserTy != PartitionType)
~~ ~~~~~~~~~~~~~~^~~~~~~~~~~~~~~~~~~~~~~~~~
/llvm-project/llvm/lib/Transforms/Scalar/SROA.cpp:5526:48:
note: place parentheses around the '&&' expression to silence this warning
if (!SI->isSimple() || PartitionType && UserTy != PartitionType)
^
( )
1 error generated.
Commit: b604d23febe9ac25d274fd933044aa7846d4397e
https://github.com/llvm/llvm-project/commit/b604d23febe9ac25d274fd933044aa7846d4397e
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-12-12 (Thu, 12 Dec 2024)
Changed paths:
M llvm/lib/Transforms/Vectorize/VectorCombine.cpp
Log Message:
-----------
[VectorCombine] Pull out isa<VectorType> check.
Noticed while investigating a crash in #119559 - we don't account for I being replaced and its Type being reallocated. So hoist the checks to the start of the loop.
Commit: 625ec7ec8983e040c440928bc1b35143a6362eab
https://github.com/llvm/llvm-project/commit/625ec7ec8983e040c440928bc1b35143a6362eab
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-12-12 (Thu, 12 Dec 2024)
Changed paths:
R llvm/test/Transforms/PhaseOrdering/X86/concat-boolmasks.ll
A llvm/test/Transforms/VectorCombine/X86/concat-boolmasks.ll
Log Message:
-----------
[VectorCombine] Move concat-boolmasks.ll tests to be VectorCombine only
Suggested on #119559
Commit: a480d5172215ce8e49b492e5c0295de1f397954d
https://github.com/llvm/llvm-project/commit/a480d5172215ce8e49b492e5c0295de1f397954d
Author: Florian Hahn <flo at fhahn.com>
Date: 2024-12-12 (Thu, 12 Dec 2024)
Changed paths:
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
Log Message:
-----------
[VPlan] Use existing vector trip count VPValue for resume phi (NFC)
Instead of going through getOrAddLiveIn to get a VPValue for the vector
trip count retrieve it directly from VPlan via getVectorTripCount.
Small simplification following 0e70289f373.
Commit: 1d65c35ce16f1bc340649ac8319b34c833e23a1f
https://github.com/llvm/llvm-project/commit/1d65c35ce16f1bc340649ac8319b34c833e23a1f
Author: Mariya Podchishchaeva <mariya.podchishchaeva at intel.com>
Date: 2024-12-12 (Thu, 12 Dec 2024)
Changed paths:
M clang/docs/ReleaseNotes.rst
M clang/lib/Sema/DeclSpec.cpp
M clang/test/AST/ByteCode/complex.cpp
M clang/test/CodeGenCXX/ext-int.cpp
M clang/test/SemaCXX/ext-int.cpp
Log Message:
-----------
[clang] Reject `_Complex _BitInt` (#119402)
The C standard doesn't require support for these types and Codegen for
these types is incorrect ATM.
See https://github.com/llvm/llvm-project/issues/119352
Commit: 9472c5fcc78a1f7ff48d797f91b55246f7c80b1a
https://github.com/llvm/llvm-project/commit/9472c5fcc78a1f7ff48d797f91b55246f7c80b1a
Author: Luke Hutton <luke.hutton at arm.com>
Date: 2024-12-12 (Thu, 12 Dec 2024)
Changed paths:
M mlir/lib/Dialect/Tosa/Transforms/TosaValidation.cpp
M mlir/test/Dialect/Tosa/level_check.mlir
Log Message:
-----------
[TOSA] Make validation pass isValidElementType check more strict (#119671)
The validation pass is used to check alignment of the IR against the
TOSA specification. This commit updates the `isValidElement` check to
more strictly align with the specifications supported element types.
Signed-off-by: Luke Hutton <luke.hutton at arm.com>
Commit: 2be41e7aee1c72177019a219ccd8e0cfccdbb52b
https://github.com/llvm/llvm-project/commit/2be41e7aee1c72177019a219ccd8e0cfccdbb52b
Author: Nikita Popov <npopov at redhat.com>
Date: 2024-12-12 (Thu, 12 Dec 2024)
Changed paths:
M llvm/lib/Transforms/IPO/AlwaysInliner.cpp
A llvm/test/Transforms/Inline/always-inline-bfi.ll
Log Message:
-----------
[AlwaysInline] Fix analysis invalidation (#119566)
This is a followup to #117750. Currently, AlwaysInline only invalidates
analyses at the end, by returning that no analyses are preserved.
However, this means that analyses fetched during inlining may be
outdated. The aforementioned PR exposed this issue.
Instead, bring the logic closer to what the normal inliner does, by
directly invalidating the caller in FAM. This should make sure that we
don't receive any outdated analyses even if they are fetched during
inlining.
Also drop the BFI updating entirely -- there's no point in doing it if
we're going to invalidate everything anyway.
Commit: 0cbdad4bd2396b740742d9ae94cba7d7b8a32cb5
https://github.com/llvm/llvm-project/commit/0cbdad4bd2396b740742d9ae94cba7d7b8a32cb5
Author: Bo Anderson <mail at boanderson.me>
Date: 2024-12-12 (Thu, 12 Dec 2024)
Changed paths:
M clang/lib/Driver/Driver.cpp
M clang/test/Driver/config-file3.c
Log Message:
-----------
[clang][Driver] Support simplified triple versions for config files (#111387)
Currently, the config file system loads the full target triple, e.g.
`arm64-apple-darwin23.6.0.cfg`.
This is however not very useful as this is a moving target. In the case
of macOS, that target moves every ~2 months.
We can improve this by adding fallbacks that simplify the version
component of the triple. This pull request adds support for loading
`arm64-apple-darwin23.cfg` and `arm64-apple-darwin.cfg`. See the
included test for a demonstration on how it works.
Commit: 81825687b4b45e0a6839fd05cad7bedf18205315
https://github.com/llvm/llvm-project/commit/81825687b4b45e0a6839fd05cad7bedf18205315
Author: Jefferson Le Quellec <jefferson.lequellec at codeplay.com>
Date: 2024-12-12 (Thu, 12 Dec 2024)
Changed paths:
M mlir/include/mlir/Conversion/Passes.td
M mlir/lib/Conversion/GPUToLLVMSPV/GPUToLLVMSPV.cpp
M mlir/test/Conversion/GPUToLLVMSPV/gpu-to-llvm-spv.mlir
Log Message:
-----------
[MLIR][GPUToLLVMSPV] Update ConvertGpuOpsToLLVMSPVOps's option (#118818)
## Description
This PR updates the `ConvertGpuOpsToLLVMSPVOps`'s option by replacing
the `index-bitwidth` with a boolean option `use-64bit-index` (similar to
the `ConvertGPUToSPIRV` option).
The reason for this modification is because the
`ConvertGpuOpsToLLVMSPVOps`:
> Generate LLVM operations to be ingested by a SPIR-V backend for gpu
operations
In the context of SPIR-V specifications only two physical addressing
models are allowed: `Physical32` and `Physical64`.
This change guarantees output sanity by preventing invalid or
unsupported index bitwidths from being specified.
Commit: f85579fb510faa0a57500b8fd3642f0269c4a4a1
https://github.com/llvm/llvm-project/commit/f85579fb510faa0a57500b8fd3642f0269c4a4a1
Author: bernhardu <bernhardu at mailbox.org>
Date: 2024-12-12 (Thu, 12 Dec 2024)
Changed paths:
M compiler-rt/lib/interception/interception_win.cpp
M compiler-rt/lib/interception/tests/interception_win_test.cpp
Log Message:
-----------
[win/asan] GetInstructionSize: Fix `83 E4 XX` to return 3. (#119644)
This consolidates the two different lines for x86 and x86_64 into a
single line for both architectures.
And adds a test line.
CC: @zmodem
Commit: 6a9279ca407132eec848eb5c55c2222ce605df81
https://github.com/llvm/llvm-project/commit/6a9279ca407132eec848eb5c55c2222ce605df81
Author: Louis Dionne <ldionne.2 at gmail.com>
Date: 2024-12-12 (Thu, 12 Dec 2024)
Changed paths:
R libcxx/test/benchmarks/ContainerBenchmarks.h
R libcxx/test/benchmarks/algorithms.partition_point.bench.cpp
A libcxx/test/benchmarks/algorithms/algorithms.partition_point.bench.cpp
A libcxx/test/benchmarks/algorithms/lexicographical_compare_three_way.bench.cpp
A libcxx/test/benchmarks/containers/ContainerBenchmarks.h
A libcxx/test/benchmarks/containers/deque.bench.cpp
A libcxx/test/benchmarks/containers/deque_iterator.bench.cpp
A libcxx/test/benchmarks/containers/map.bench.cpp
A libcxx/test/benchmarks/containers/ordered_set.bench.cpp
A libcxx/test/benchmarks/containers/string.bench.cpp
A libcxx/test/benchmarks/containers/unordered_set_operations.bench.cpp
A libcxx/test/benchmarks/containers/vector_operations.bench.cpp
R libcxx/test/benchmarks/deque.bench.cpp
R libcxx/test/benchmarks/deque_iterator.bench.cpp
R libcxx/test/benchmarks/format.bench.cpp
A libcxx/test/benchmarks/format/format.bench.cpp
A libcxx/test/benchmarks/format/format_to.bench.cpp
A libcxx/test/benchmarks/format/format_to_n.bench.cpp
A libcxx/test/benchmarks/format/formatted_size.bench.cpp
A libcxx/test/benchmarks/format/formatter_float.bench.cpp
A libcxx/test/benchmarks/format/formatter_int.bench.cpp
A libcxx/test/benchmarks/format/std_format_spec_string_unicode.bench.cpp
A libcxx/test/benchmarks/format/std_format_spec_string_unicode_escape.bench.cpp
R libcxx/test/benchmarks/format_to.bench.cpp
R libcxx/test/benchmarks/format_to_n.bench.cpp
R libcxx/test/benchmarks/formatted_size.bench.cpp
R libcxx/test/benchmarks/formatter_float.bench.cpp
R libcxx/test/benchmarks/formatter_int.bench.cpp
R libcxx/test/benchmarks/lexicographical_compare_three_way.bench.cpp
R libcxx/test/benchmarks/map.bench.cpp
R libcxx/test/benchmarks/ordered_set.bench.cpp
R libcxx/test/benchmarks/std_format_spec_string_unicode.bench.cpp
R libcxx/test/benchmarks/std_format_spec_string_unicode_escape.bench.cpp
R libcxx/test/benchmarks/string.bench.cpp
R libcxx/test/benchmarks/unordered_set_operations.bench.cpp
R libcxx/test/benchmarks/vector_operations.bench.cpp
Log Message:
-----------
[libc++] Slight reorganization of the benchmarks (#119625)
Move various container benchmarks to the same subdirectory, and regroup
some format-related benchmarks.
Commit: f9734b9df15bc1eea84ef00973c2e5560e70c27d
https://github.com/llvm/llvm-project/commit/f9734b9df15bc1eea84ef00973c2e5560e70c27d
Author: Kareem Ergawy <kareem.ergawy at amd.com>
Date: 2024-12-12 (Thu, 12 Dec 2024)
Changed paths:
M flang/lib/Optimizer/OpenMP/MapsForPrivatizedSymbols.cpp
M llvm/lib/Frontend/OpenMP/OMPIRBuilder.cpp
M llvm/unittests/Frontend/OpenMPIRBuilderTest.cpp
M mlir/include/mlir/Dialect/OpenMP/OpenMPOps.td
M mlir/lib/Target/LLVMIR/Dialect/OpenMP/OpenMPToLLVMIRTranslation.cpp
M mlir/test/Target/LLVMIR/omptarget-byref-bycopy-generation-device.mlir
M mlir/test/Target/LLVMIR/omptarget-declare-target-llvm-device.mlir
A mlir/test/Target/LLVMIR/openmp-target-multiple-private.mlir
A mlir/test/Target/LLVMIR/openmp-target-private-allocatable.mlir
M mlir/test/Target/LLVMIR/openmp-target-private.mlir
M mlir/test/Target/LLVMIR/openmp-target-use-device-nested.mlir
M mlir/test/Target/LLVMIR/openmp-todo.mlir
Log Message:
-----------
[mlir][OpenMP] - MLIR to LLVMIR translation support for delayed privatization of allocatables in `omp.target` ops (#116576)
This PR adds support to translate the `private` clause from MLIR to
LLVMIR when used on allocatables in the context of an `omp.target` op.
This replaces https://github.com/llvm/llvm-project/pull/113208.
Parent PR: https://github.com/llvm/llvm-project/pull/116770. Only the
latest commit is relevant to the PR.
Commit: 86779da52be6c6900a57fbba243f6894b19bb9b1
https://github.com/llvm/llvm-project/commit/86779da52be6c6900a57fbba243f6894b19bb9b1
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-12-12 (Thu, 12 Dec 2024)
Changed paths:
M llvm/lib/Transforms/Vectorize/VectorCombine.cpp
M llvm/test/Transforms/VectorCombine/X86/concat-boolmasks.ll
Log Message:
-----------
[VectorCombine] Fold "(or (zext (bitcast X)), (shl (zext (bitcast Y)), C))" -> "(bitcast (concat X, Y))" MOVMSK bool mask style patterns (#119695)
Mask/Bool vectors are often bitcast to/from scalar integers, in particular when concatenating mask results, often this is due to the difficulties of working with vector of bools on C/C++. On x86 this typically involves the MOVMSK/KMOV instructions.
To concatenate bool masks, these are typically cast to scalars, which are then zero-extended, shifted and OR'd together.
This patch attempts to match these scalar concatenation patterns and convert them to vector shuffles instead. This in turn often assists with further vector combines, depending on the cost model.
Reapplied patch from #119559 - fixed use after free issue.
Fixes #111431
Commit: f4ee5a673f6e593e85306cdf65493b53e62f936e
https://github.com/llvm/llvm-project/commit/f4ee5a673f6e593e85306cdf65493b53e62f936e
Author: Joseph Huber <huberjn at outlook.com>
Date: 2024-12-12 (Thu, 12 Dec 2024)
Changed paths:
M offload/DeviceRTL/include/Synchronization.h
M offload/DeviceRTL/src/Synchronization.cpp
Log Message:
-----------
[OpenMP] Replace AMDGPU fences with generic scoped fences (#119619)
Summary:
This is simpler and more common. I would've replaced the CUDA uses and
made this the same but currently it doesn't codegen these fences fully
and just emits a full system wide barrier as a fallback.
Commit: 34d244a94195dbeb626573c9b2e388dc574f9300
https://github.com/llvm/llvm-project/commit/34d244a94195dbeb626573c9b2e388dc574f9300
Author: Yi Kong <yikong at google.com>
Date: 2024-12-12 (Thu, 12 Dec 2024)
Changed paths:
M compiler-rt/lib/rtsan/rtsan_interceptors_posix.cpp
Log Message:
-----------
Fix rtsan build with musl (#119674)
fd_set is defined by `sys/select.h`. On musl, this header is not
transitively included by the other headers.
Failure message:
```
compiler-rt/lib/rtsan/rtsan_interceptors_posix.cpp:761:37: error: unknown type name 'fd_set'; did you mean 'fd_t'?
761 | INTERCEPTOR(int, pselect, int nfds, fd_set *readfds, fd_set *writefds,
| ^~~~~~
| fd_t
```
Commit: 10ef20f6a629797d81252de143117e2a0bc6556d
https://github.com/llvm/llvm-project/commit/10ef20f6a629797d81252de143117e2a0bc6556d
Author: Nikita Popov <npopov at redhat.com>
Date: 2024-12-12 (Thu, 12 Dec 2024)
Changed paths:
M mlir/CMakeLists.txt
M mlir/cmake/modules/AddMLIR.cmake
M mlir/tools/mlir-cpu-runner/CMakeLists.txt
M mlir/tools/mlir-lsp-server/CMakeLists.txt
M mlir/tools/mlir-opt/CMakeLists.txt
M mlir/tools/mlir-parser-fuzzer/bytecode/CMakeLists.txt
M mlir/tools/mlir-parser-fuzzer/text/CMakeLists.txt
M mlir/tools/mlir-query/CMakeLists.txt
M mlir/tools/mlir-reduce/CMakeLists.txt
M mlir/tools/mlir-rewrite/CMakeLists.txt
M mlir/tools/mlir-translate/CMakeLists.txt
Log Message:
-----------
[mlir] Add support for MLIR_LINK_MLIR_DYLIB (#119408)
While MLIR currently supports building a libMLIR.so, it does not support
actually linking against it for its own tools. When building with LTO,
this means we have to relink the world for every tool, and the resulting
binaries are large.
This adds basic support for MLIR_LINK_MLIR_DYLIB, modelled after how
CLANG_LINK_CLANG_DYLIB is implemented: Libraries that are part of
libMLIR.so should be added via mlir_target_link_libraries instead of
target_link_libraries. This will replace them with libMLIR.so if
MLIR_LINK_MLIR_DYLIB is enabled.
This adds basic support, I think there are two more things that can be
done here:
* C API unit tests should link against libMLIR-C.so. Currently these
still link statically.
* Linking the test libs (not part of libMLIR.so) still pulls in
dependencies statically that should come from libMLIR.so.
Commit: e909c0ccd40e6d6aa2d10e0b60e8b992f3cde35b
https://github.com/llvm/llvm-project/commit/e909c0ccd40e6d6aa2d10e0b60e8b992f3cde35b
Author: Igor Kirillov <igor.kirillov at arm.com>
Date: 2024-12-12 (Thu, 12 Dec 2024)
Changed paths:
M llvm/lib/CodeGen/SelectOptimize.cpp
M llvm/test/CodeGen/AArch64/selectopt-cast.ll
Log Message:
-----------
[SelectOpt] Add support for AShr/LShr operands (#118495)
For conditional increments with sign check conditions like X < 0 or X >= 0,
the compiler may generate code like this:
%cmp = icmp sgt i64 %1, -1
%shift = ashr i64 %1, 63
%j.next = add nsw i64 %j, %shift
%sel = select i1 %cmp ...
, where %cmp is not in computation but in some other implicit or regular
expressions. This patch allows SelectOptimize pass to recognise these
cases.
Commit: 46ec271e039dfea0b8bb543290d27ca18b2e807b
https://github.com/llvm/llvm-project/commit/46ec271e039dfea0b8bb543290d27ca18b2e807b
Author: Jie Fu <jiefu at tencent.com>
Date: 2024-12-12 (Thu, 12 Dec 2024)
Changed paths:
M mlir/lib/Target/LLVMIR/Dialect/OpenMP/OpenMPToLLVMIRTranslation.cpp
Log Message:
-----------
[mlir] Fix -Wunused-variable in OpenMPToLLVMIRTranslation.cpp (NFC)
/llvm-project/mlir/lib/Target/LLVMIR/Dialect/OpenMP/OpenMPToLLVMIRTranslation.cpp:3921:12:
error: unused variable 'varType' [-Werror,-Wunused-variable]
Type varType = mapInfoOp.getVarType();
^
1 error generated.
Commit: e582865aa46b6b46d8c7e8a9244443247f5f173b
https://github.com/llvm/llvm-project/commit/e582865aa46b6b46d8c7e8a9244443247f5f173b
Author: Nikita Popov <npopov at redhat.com>
Date: 2024-12-12 (Thu, 12 Dec 2024)
Changed paths:
M mlir/tools/mlir-opt/CMakeLists.txt
Log Message:
-----------
[mlir] Link MLIRMlirOptMain against test_libs
In 10ef20f6a629797d81252de143117e2a0bc6556d I dropped $test_libs
from $LIBS to handle them separately for the mlir-opt tool.
However, they should still include them in LINK_LIBS for the
MLIRMlirOptMain library.
Commit: bdaa82a7bb14b1016dbee554ef919323a197754d
https://github.com/llvm/llvm-project/commit/bdaa82a7bb14b1016dbee554ef919323a197754d
Author: Pravin Jagtap <Pravin.Jagtap at amd.com>
Date: 2024-12-12 (Thu, 12 Dec 2024)
Changed paths:
M llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
M llvm/test/CodeGen/AMDGPU/av-spill-expansion-with-machine-cp.mir
Log Message:
-----------
[AMDGPU] Mark AGPR tuple implicit in the first instr of AGPR spills. (#115285)
When AGPRs are spilled to stack through VGPRs, the pei only marks the
AGPR tuple as implicit-def. To preserve the liveness, it should also
mark the tuple implicit.
Fixes: SWDEV-462189
Commit: bae383ba6b53b0d8257c83f99ceecdd751d0a378
https://github.com/llvm/llvm-project/commit/bae383ba6b53b0d8257c83f99ceecdd751d0a378
Author: Aaron Puchert <aaron.puchert at sap.com>
Date: 2024-12-12 (Thu, 12 Dec 2024)
Changed paths:
M clang/lib/Driver/ToolChains/CommonArgs.cpp
M clang/lib/Driver/ToolChains/CommonArgs.h
M clang/lib/Driver/ToolChains/FreeBSD.cpp
M clang/lib/Driver/ToolChains/Fuchsia.cpp
M clang/lib/Driver/ToolChains/Gnu.cpp
M clang/lib/Driver/ToolChains/Hexagon.cpp
M clang/lib/Driver/ToolChains/NetBSD.cpp
M clang/lib/Driver/ToolChains/OpenBSD.cpp
M clang/lib/Driver/ToolChains/Solaris.cpp
Log Message:
-----------
[Driver] Cache SanitizerArgs (NFC) (#119442)
The name getSanitizerArgs seems to mislead callers that this is a cheap
function, but it extracts the SanitizerArgs each time it is called.
So we try to reuse it a bit more.
Commit: bb1961ed7779e782f4c28ee38854decf6f53c82f
https://github.com/llvm/llvm-project/commit/bb1961ed7779e782f4c28ee38854decf6f53c82f
Author: Pravin Jagtap <Pravin.Jagtap at amd.com>
Date: 2024-12-12 (Thu, 12 Dec 2024)
Changed paths:
M llvm/lib/Target/AMDGPU/VOP3Instructions.td
Log Message:
-----------
[AMDGPU] Stop using True16 profile for v_bitop3_b16 of gfx950. (#119706)
Commit: 67eb05b2928ea707761bb040e6eb824f4ca9ef3a
https://github.com/llvm/llvm-project/commit/67eb05b2928ea707761bb040e6eb824f4ca9ef3a
Author: Stefan Pintilie <stefanp at ca.ibm.com>
Date: 2024-12-12 (Thu, 12 Dec 2024)
Changed paths:
M llvm/lib/Target/PowerPC/PPCISelLowering.cpp
M llvm/test/CodeGen/PowerPC/aix-cc-abi-mir.ll
M llvm/test/CodeGen/PowerPC/aix-cc-abi.ll
Log Message:
-----------
[PowerPC] Add special handling for arguments that are smaller than pointer size. (#119003)
When arguments are passed in memory instead of registers we currently
load the entire pointer size even though the argument may be smaller.
For exmaple if the pointer size if i32 then we use a load word even if
the argument is only an i8. This patch zeros / extends the bits that are
not required to ensure that we are getting the correct value even if the
load is larger.
Commit: bc28be0a428020ea803c94adb4df48ee4972e9f1
https://github.com/llvm/llvm-project/commit/bc28be0a428020ea803c94adb4df48ee4972e9f1
Author: Peng Huang <shawn.p.huang at gmail.com>
Date: 2024-12-12 (Thu, 12 Dec 2024)
Changed paths:
M clang/lib/Driver/ToolChains/OHOS.cpp
Log Message:
-----------
[Driver][OHOS] Fix lld link issue for OHOS (#118192)
For ohos targets, libclang_rt.builtins.a, clang_rt.crtbegin.o and
clang_rt.crtend.o are installed in
clang/20/lib/${arch}-unknown-linux-ohos. However OHOS toolchain search
them in clang/20/lib/${arch}-linux-ohos folder. It causes link error.
Fix the problem by seaching both folders.
Commit: 6f8a363a483489687597e29b8bda0975e821f188
https://github.com/llvm/llvm-project/commit/6f8a363a483489687597e29b8bda0975e821f188
Author: AidinT <at.aidin at gmail.com>
Date: 2024-12-12 (Thu, 12 Dec 2024)
Changed paths:
M llvm/docs/tutorial/MyFirstLanguageFrontend/LangImpl07.rst
M llvm/examples/Kaleidoscope/Chapter7/toy.cpp
Log Message:
-----------
[Kaleidoscope] Add mem2reg pass to function pass manager (#119707)
Kaleidoscope has switched to new pass manager before (#72324), but both
code and tutorial document have some missing parts.
This pull request fixes the following problems:
1. Adds `PromotePass` to the function pass manager. This pass was
removed during the switch from legacy pass manager to the new pass
manager.
2. Syncs the tutorial with the code.
Commit: 010d0115fc8e3834fc6f747f0841f3b1e467c4da
https://github.com/llvm/llvm-project/commit/010d0115fc8e3834fc6f747f0841f3b1e467c4da
Author: erichkeane <ekeane at nvidia.com>
Date: 2024-12-12 (Thu, 12 Dec 2024)
Changed paths:
M clang/include/clang-c/Index.h
M clang/include/clang/AST/RecursiveASTVisitor.h
M clang/include/clang/AST/StmtOpenACC.h
M clang/include/clang/AST/TextNodeDumper.h
M clang/include/clang/Basic/StmtNodes.td
M clang/include/clang/Serialization/ASTBitCodes.h
M clang/lib/AST/StmtOpenACC.cpp
M clang/lib/AST/StmtPrinter.cpp
M clang/lib/AST/StmtProfile.cpp
M clang/lib/AST/TextNodeDumper.cpp
M clang/lib/CodeGen/CGStmt.cpp
M clang/lib/CodeGen/CodeGenFunction.h
M clang/lib/Parse/ParseOpenACC.cpp
M clang/lib/Sema/SemaExceptionSpec.cpp
M clang/lib/Sema/SemaOpenACC.cpp
M clang/lib/Sema/TreeTransform.h
M clang/lib/Serialization/ASTReaderStmt.cpp
M clang/lib/Serialization/ASTWriterStmt.cpp
M clang/lib/StaticAnalyzer/Core/ExprEngine.cpp
A clang/test/AST/ast-print-openacc-data-construct.cpp
M clang/test/ParserOpenACC/parse-clauses.c
M clang/test/ParserOpenACC/parse-clauses.cpp
M clang/test/ParserOpenACC/parse-constructs.c
M clang/test/SemaOpenACC/combined-construct-collapse-clause.cpp
M clang/test/SemaOpenACC/combined-construct-default-clause.c
M clang/test/SemaOpenACC/combined-construct-if-clause.c
M clang/test/SemaOpenACC/compute-construct-default-clause.c
M clang/test/SemaOpenACC/compute-construct-device_type-clause.c
M clang/test/SemaOpenACC/compute-construct-if-clause.c
A clang/test/SemaOpenACC/data-construct-ast.cpp
A clang/test/SemaOpenACC/data-construct.cpp
M clang/test/SemaOpenACC/loop-construct-collapse-clause.cpp
M clang/tools/libclang/CIndex.cpp
M clang/tools/libclang/CXCursor.cpp
Log Message:
-----------
[OpenACC] Create AST nodes for 'data' constructs
These constructs are all very similar and closely related, so this patch
creates the AST nodes for them, serialization, printing/etc.
Additionally the restrictions are all added as tests/todos in the tests,
as those will have to be implemented once we get those clauses implemented.
Commit: f229ea2ffe9bb8380a4285bd379736aaadaf55ac
https://github.com/llvm/llvm-project/commit/f229ea2ffe9bb8380a4285bd379736aaadaf55ac
Author: Haojian Wu <hokein.wu at gmail.com>
Date: 2024-12-12 (Thu, 12 Dec 2024)
Changed paths:
M clang/docs/ReleaseNotes.rst
M clang/include/clang/Basic/DiagnosticSemaKinds.td
Log Message:
-----------
[clang] Enable the -Wdangling-capture diagnostic by default. (#119685)
We have tested this diagnostics internally, and we don't find see any
issues.
Commit: a8e66d7f17bc648865cebf6b1e58c7a9071c6a84
https://github.com/llvm/llvm-project/commit/a8e66d7f17bc648865cebf6b1e58c7a9071c6a84
Author: iseki <admin at iseki.space>
Date: 2024-12-12 (Thu, 12 Dec 2024)
Changed paths:
M clang/include/clang-c/CXString.h
Log Message:
-----------
[docs] Add a more detailed description in CXString.h. (#119090)
Emmm... Maybe I'm splitting hairs. But I really think the paragraph
should be more detailed. The orginal document makes me confused. Do I
take the ownership of the string data?
Here I don't refer the `clang_disposeString` function, because here's a
`clang_disposeStringSet`.
Co-authored-by: Saleem Abdulrasool <compnerd at compnerd.org>
Commit: 2f8238f849c4836b333082f387d91408234ea73b
https://github.com/llvm/llvm-project/commit/2f8238f849c4836b333082f387d91408234ea73b
Author: Kazu Hirata <kazu at google.com>
Date: 2024-12-12 (Thu, 12 Dec 2024)
Changed paths:
M llvm/lib/DWARFLinker/Parallel/DWARFLinkerCompileUnit.cpp
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
M llvm/unittests/IR/IRBuilderTest.cpp
Log Message:
-----------
[llvm] Migrate away from PointerUnion::{is,get} (NFC) (#119679)
Note that PointerUnion::{is,get} have been soft deprecated in
PointerUnion.h:
// FIXME: Replace the uses of is(), get() and dyn_cast() with
// isa<T>, cast<T> and the llvm::dyn_cast<T>
I'm not touching PointerUnion::dyn_cast for now because it's a bit
complicated; we could blindly migrate it to dyn_cast_if_present, but
we should probably use dyn_cast when the operand is known to be
non-null.
Commit: fda80a4fcad8bab67fc1f522d68012e572866066
https://github.com/llvm/llvm-project/commit/fda80a4fcad8bab67fc1f522d68012e572866066
Author: Kazu Hirata <kazu at google.com>
Date: 2024-12-12 (Thu, 12 Dec 2024)
Changed paths:
M llvm/unittests/ProfileData/MemProfTest.cpp
Log Message:
-----------
[memprof] Use addCallStack in a unit test (NFC) (#119651)
Here IndexedMemProfRecord just needs to reference a CallStackID, so we
can use addCallStack for a real hash-based CallStackId instead of a
fake value like 0x222.
Commit: 6c8f41d3367476d35ac730abf9f980291737193b
https://github.com/llvm/llvm-project/commit/6c8f41d3367476d35ac730abf9f980291737193b
Author: Florian Hahn <flo at fhahn.com>
Date: 2024-12-12 (Thu, 12 Dec 2024)
Changed paths:
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
M llvm/lib/Transforms/Vectorize/VPlan.cpp
M llvm/lib/Transforms/Vectorize/VPlan.h
M llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
M llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
M llvm/lib/Transforms/Vectorize/VPlanUnroll.cpp
M llvm/lib/Transforms/Vectorize/VPlanUtils.cpp
M llvm/lib/Transforms/Vectorize/VPlanVerifier.cpp
M llvm/test/Transforms/LoopVectorize/AArch64/sve-tail-folding-forced.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve-widen-gep.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve2-histcnt-vplan.ll
M llvm/test/Transforms/LoopVectorize/AArch64/synthesize-mask-for-call.ll
M llvm/test/Transforms/LoopVectorize/AArch64/widen-call-with-intrinsic-or-libfunc.ll
M llvm/test/Transforms/LoopVectorize/PowerPC/vplan-force-tail-with-evl.ll
M llvm/test/Transforms/LoopVectorize/RISCV/riscv-vector-reverse.ll
M llvm/test/Transforms/LoopVectorize/RISCV/vplan-vp-intrinsics-reduction.ll
M llvm/test/Transforms/LoopVectorize/RISCV/vplan-vp-select-intrinsics.ll
M llvm/test/Transforms/LoopVectorize/first-order-recurrence-chains-vplan.ll
M llvm/test/Transforms/LoopVectorize/first-order-recurrence-sink-replicate-region.ll
M llvm/test/Transforms/LoopVectorize/icmp-uniforms.ll
M llvm/test/Transforms/LoopVectorize/interleave-and-scalarize-only.ll
M llvm/test/Transforms/LoopVectorize/uncountable-early-exit-vplan.ll
M llvm/test/Transforms/LoopVectorize/vplan-dot-printing.ll
M llvm/test/Transforms/LoopVectorize/vplan-iv-transforms.ll
M llvm/test/Transforms/LoopVectorize/vplan-predicate-switch.ll
M llvm/test/Transforms/LoopVectorize/vplan-printing-before-execute.ll
M llvm/test/Transforms/LoopVectorize/vplan-printing-outer-loop.ll
M llvm/test/Transforms/LoopVectorize/vplan-printing.ll
M llvm/test/Transforms/LoopVectorize/vplan-sink-scalars-and-merge-vf1.ll
M llvm/test/Transforms/LoopVectorize/vplan-sink-scalars-and-merge.ll
M llvm/test/Transforms/LoopVectorize/vplan-unused-interleave-group.ll
M llvm/test/Transforms/PhaseOrdering/AArch64/hoist-runtime-checks.ll
M llvm/test/Transforms/PhaseOrdering/X86/hoist-load-of-baseptr.ll
M llvm/test/Transforms/PhaseOrdering/X86/preserve-access-group.ll
M llvm/unittests/Transforms/Vectorize/VPlanHCFGTest.cpp
M llvm/unittests/Transforms/Vectorize/VPlanTest.cpp
M llvm/unittests/Transforms/Vectorize/VPlanVerifierTest.cpp
Log Message:
-----------
[VPlan] Hook IR blocks into VPlan during skeleton creation (NFC) (#114292)
As a first step to move towards modeling the full skeleton in VPlan,
start by wrapping IR blocks created during legacy skeleton creation in
VPIRBasicBlocks and hook them into the VPlan. This means the skeleton
CFG is represented in VPlan, just before execute. This allows moving
parts of skeleton creation into recipes in the VPBBs gradually.
Note that this allows retiring some manual DT updates, as this will be
handled automatically during VPlan execution.
PR: https://github.com/llvm/llvm-project/pull/114292
Commit: e5371eded9c22ec4854634c9c58df793562f782d
https://github.com/llvm/llvm-project/commit/e5371eded9c22ec4854634c9c58df793562f782d
Author: Sander de Smalen <sander.desmalen at arm.com>
Date: 2024-12-12 (Thu, 12 Dec 2024)
Changed paths:
M compiler-rt/lib/builtins/CMakeLists.txt
Log Message:
-----------
[compiler-rt] Don't build SME routines if __arm_cpu_features is not initialised. (#119703)
According to the conversation
[here](https://github.com/llvm/llvm-project/pull/119414#issuecomment-2536495859),
some platforms don't enable `__arm_cpu_features` with a global
constructor, but rather do so lazily when called from the FMV resolver.
PR #119414 removed the CMake guard to check to see if the targetted
platform is baremetal or supports sys/auxv. Without this check, the
routines rely on `__arm_cpu_features` being initialised when they may
not be, depending on the platform.
This PR simply avoids building the SME routines for those platforms for
now.
Commit: 4aacafd49b74dc168e0d99018b4c8289ce9c923e
https://github.com/llvm/llvm-project/commit/4aacafd49b74dc168e0d99018b4c8289ce9c923e
Author: Clement Courbet <courbet at google.com>
Date: 2024-12-12 (Thu, 12 Dec 2024)
Changed paths:
M clang/include/clang/AST/RecursiveASTVisitor.h
M clang/unittests/AST/ASTContextParentMapTest.cpp
M clang/unittests/Analysis/FlowSensitive/TransferTest.cpp
Log Message:
-----------
[clang][ASTVisitor] Visit `HoldingVar` from `BindingDecl`. (#117858)
Tuple-like types introduce `VarDecl`s in the AST for their "holding
vars", but AST visitors do not visit those. As a result the `VarDecl`
for the holding var is orphaned when trying to retreive its parents.
Fix a `FlowSensitive` test that assumes that only a `BindingDecl` is
introduced with the given name (the matcher now can also reach the
`VarDecl` for the holding var).
Commit: 9c319d5bb40785c969d2af76535ca62448dfafa7
https://github.com/llvm/llvm-project/commit/9c319d5bb40785c969d2af76535ca62448dfafa7
Author: Sander de Smalen <sander.desmalen at arm.com>
Date: 2024-12-12 (Thu, 12 Dec 2024)
Changed paths:
M llvm/lib/Target/AArch64/AArch64Subtarget.cpp
M llvm/test/CodeGen/AArch64/Atomics/aarch64-atomicrmw-lse2_lse128.ll
M llvm/test/CodeGen/AArch64/Atomics/aarch64-atomicrmw-v8_1a.ll
M llvm/test/CodeGen/AArch64/Atomics/aarch64_be-atomicrmw-lse2_lse128.ll
M llvm/test/CodeGen/AArch64/Atomics/aarch64_be-atomicrmw-v8_1a.ll
M llvm/test/CodeGen/AArch64/GlobalISel/arm64-atomic-128.ll
M llvm/test/CodeGen/AArch64/GlobalISel/arm64-atomic.ll
M llvm/test/CodeGen/AArch64/GlobalISel/arm64-pcsections.ll
M llvm/test/CodeGen/AArch64/GlobalISel/combine-udiv.ll
M llvm/test/CodeGen/AArch64/GlobalISel/insert-vector-elt-pr63826.ll
M llvm/test/CodeGen/AArch64/aarch64-addv.ll
M llvm/test/CodeGen/AArch64/aarch64-be-bv.ll
M llvm/test/CodeGen/AArch64/aarch64-bf16-dotprod-intrinsics.ll
M llvm/test/CodeGen/AArch64/aarch64-bif-gen.ll
M llvm/test/CodeGen/AArch64/aarch64-bit-gen.ll
M llvm/test/CodeGen/AArch64/aarch64-combine-add-sub-mul.ll
M llvm/test/CodeGen/AArch64/aarch64-combine-add-zext.ll
M llvm/test/CodeGen/AArch64/aarch64-dup-ext-scalable.ll
M llvm/test/CodeGen/AArch64/aarch64-dup-ext.ll
M llvm/test/CodeGen/AArch64/aarch64-dup-extract-scalable.ll
M llvm/test/CodeGen/AArch64/aarch64-fold-lslfast.ll
M llvm/test/CodeGen/AArch64/aarch64-interleaved-access-w-undef.ll
M llvm/test/CodeGen/AArch64/aarch64-load-ext.ll
M llvm/test/CodeGen/AArch64/aarch64-matrix-umull-smull.ll
M llvm/test/CodeGen/AArch64/aarch64-minmaxv.ll
M llvm/test/CodeGen/AArch64/aarch64-mops-mte.ll
M llvm/test/CodeGen/AArch64/aarch64-mops.ll
M llvm/test/CodeGen/AArch64/aarch64-mull-masks.ll
M llvm/test/CodeGen/AArch64/aarch64-mulv.ll
M llvm/test/CodeGen/AArch64/aarch64-neon-vector-insert-uaddlv.ll
M llvm/test/CodeGen/AArch64/aarch64-scalarize-vec-load-ext.ll
M llvm/test/CodeGen/AArch64/aarch64-sysreg128.ll
M llvm/test/CodeGen/AArch64/aarch64-wide-shuffle.ll
M llvm/test/CodeGen/AArch64/abs.ll
M llvm/test/CodeGen/AArch64/active_lane_mask.ll
M llvm/test/CodeGen/AArch64/adc.ll
M llvm/test/CodeGen/AArch64/add-extract.ll
M llvm/test/CodeGen/AArch64/add.ll
M llvm/test/CodeGen/AArch64/addimm-mulimm.ll
M llvm/test/CodeGen/AArch64/addp-shuffle.ll
M llvm/test/CodeGen/AArch64/addsub_ext.ll
M llvm/test/CodeGen/AArch64/and-mask-removal.ll
M llvm/test/CodeGen/AArch64/andorxor.ll
M llvm/test/CodeGen/AArch64/arm64-abi-varargs.ll
M llvm/test/CodeGen/AArch64/arm64-addp.ll
M llvm/test/CodeGen/AArch64/arm64-addr-type-promotion.ll
M llvm/test/CodeGen/AArch64/arm64-atomic-128.ll
M llvm/test/CodeGen/AArch64/arm64-bitfield-extract.ll
M llvm/test/CodeGen/AArch64/arm64-build-vector.ll
M llvm/test/CodeGen/AArch64/arm64-collect-loh.ll
M llvm/test/CodeGen/AArch64/arm64-dup.ll
M llvm/test/CodeGen/AArch64/arm64-ext.ll
M llvm/test/CodeGen/AArch64/arm64-extract-insert-varidx.ll
M llvm/test/CodeGen/AArch64/arm64-extract_subvector.ll
M llvm/test/CodeGen/AArch64/arm64-fcopysign.ll
M llvm/test/CodeGen/AArch64/arm64-fixed-point-scalar-cvt-dagcombine.ll
M llvm/test/CodeGen/AArch64/arm64-fmax.ll
M llvm/test/CodeGen/AArch64/arm64-fp128.ll
M llvm/test/CodeGen/AArch64/arm64-indexed-vector-ldst.ll
M llvm/test/CodeGen/AArch64/arm64-instruction-mix-remarks.ll
M llvm/test/CodeGen/AArch64/arm64-ld1.ll
M llvm/test/CodeGen/AArch64/arm64-ldxr-stxr.ll
M llvm/test/CodeGen/AArch64/arm64-mul.ll
M llvm/test/CodeGen/AArch64/arm64-neon-2velem-high.ll
M llvm/test/CodeGen/AArch64/arm64-neon-2velem.ll
M llvm/test/CodeGen/AArch64/arm64-neon-3vdiff.ll
M llvm/test/CodeGen/AArch64/arm64-neon-add-pairwise.ll
M llvm/test/CodeGen/AArch64/arm64-neon-copy.ll
M llvm/test/CodeGen/AArch64/arm64-neon-copyPhysReg-tuple.ll
M llvm/test/CodeGen/AArch64/arm64-neon-mul-div.ll
M llvm/test/CodeGen/AArch64/arm64-neon-scalar-by-elem-mul.ll
M llvm/test/CodeGen/AArch64/arm64-neon-select_cc.ll
M llvm/test/CodeGen/AArch64/arm64-neon-simd-ldst-one.ll
M llvm/test/CodeGen/AArch64/arm64-neon-simd-shift.ll
M llvm/test/CodeGen/AArch64/arm64-neon-simd-vget.ll
M llvm/test/CodeGen/AArch64/arm64-neon-v1i1-setcc.ll
M llvm/test/CodeGen/AArch64/arm64-neon-v8.1a.ll
M llvm/test/CodeGen/AArch64/arm64-nvcast.ll
M llvm/test/CodeGen/AArch64/arm64-popcnt.ll
M llvm/test/CodeGen/AArch64/arm64-rev.ll
M llvm/test/CodeGen/AArch64/arm64-shifted-sext.ll
M llvm/test/CodeGen/AArch64/arm64-shrink-wrapping.ll
M llvm/test/CodeGen/AArch64/arm64-stp.ll
M llvm/test/CodeGen/AArch64/arm64-subvector-extend.ll
M llvm/test/CodeGen/AArch64/arm64-tbl.ll
M llvm/test/CodeGen/AArch64/arm64-vadd.ll
M llvm/test/CodeGen/AArch64/arm64-vaddv.ll
M llvm/test/CodeGen/AArch64/arm64-vcvt_f.ll
M llvm/test/CodeGen/AArch64/arm64-vector-insertion.ll
M llvm/test/CodeGen/AArch64/arm64-vmul.ll
M llvm/test/CodeGen/AArch64/arm64-zip.ll
M llvm/test/CodeGen/AArch64/arm64_32-addrs.ll
M llvm/test/CodeGen/AArch64/arm64ec-entry-thunks.ll
M llvm/test/CodeGen/AArch64/arm64ec-exit-thunks.ll
M llvm/test/CodeGen/AArch64/atomic-ops-lse.ll
M llvm/test/CodeGen/AArch64/atomic-ops-msvc.ll
M llvm/test/CodeGen/AArch64/atomic-ops.ll
M llvm/test/CodeGen/AArch64/atomicrmw-fadd.ll
M llvm/test/CodeGen/AArch64/atomicrmw-fmax.ll
M llvm/test/CodeGen/AArch64/atomicrmw-fmin.ll
M llvm/test/CodeGen/AArch64/atomicrmw-fsub.ll
M llvm/test/CodeGen/AArch64/atomicrmw-xchg-fp.ll
M llvm/test/CodeGen/AArch64/bf16-instructions.ll
M llvm/test/CodeGen/AArch64/bf16-select.ll
M llvm/test/CodeGen/AArch64/bf16-shuffle.ll
M llvm/test/CodeGen/AArch64/bf16-v4-instructions.ll
M llvm/test/CodeGen/AArch64/bf16-v8-instructions.ll
M llvm/test/CodeGen/AArch64/bf16-vector-shuffle.ll
M llvm/test/CodeGen/AArch64/bitcast-promote-widen.ll
M llvm/test/CodeGen/AArch64/bitcast.ll
M llvm/test/CodeGen/AArch64/bitfield-insert.ll
M llvm/test/CodeGen/AArch64/bswap.ll
M llvm/test/CodeGen/AArch64/build-one-lane.ll
M llvm/test/CodeGen/AArch64/build-vector-extract.ll
M llvm/test/CodeGen/AArch64/build-vector-two-dup.ll
M llvm/test/CodeGen/AArch64/check-sign-bit-before-extension.ll
M llvm/test/CodeGen/AArch64/cmp-to-cmn.ll
M llvm/test/CodeGen/AArch64/cmpxchg-idioms.ll
M llvm/test/CodeGen/AArch64/combine-andintoload.ll
M llvm/test/CodeGen/AArch64/complex-deinterleaving-f16-add.ll
M llvm/test/CodeGen/AArch64/complex-deinterleaving-f16-mul.ll
M llvm/test/CodeGen/AArch64/complex-deinterleaving-multiuses.ll
M llvm/test/CodeGen/AArch64/complex-deinterleaving-reductions-predicated-scalable.ll
M llvm/test/CodeGen/AArch64/complex-deinterleaving-reductions-scalable.ll
M llvm/test/CodeGen/AArch64/complex-deinterleaving-splat-scalable.ll
M llvm/test/CodeGen/AArch64/complex-deinterleaving-splat.ll
M llvm/test/CodeGen/AArch64/complex-deinterleaving-uniform-cases.ll
M llvm/test/CodeGen/AArch64/concat-vector.ll
M llvm/test/CodeGen/AArch64/concatbinop.ll
M llvm/test/CodeGen/AArch64/cvt-fp-int-fp.ll
M llvm/test/CodeGen/AArch64/dag-numsignbits.ll
M llvm/test/CodeGen/AArch64/dup.ll
M llvm/test/CodeGen/AArch64/duplane-index-patfrags.ll
M llvm/test/CodeGen/AArch64/ext-narrow-index.ll
M llvm/test/CodeGen/AArch64/extbinopload.ll
M llvm/test/CodeGen/AArch64/extract-bits.ll
M llvm/test/CodeGen/AArch64/extract-insert.ll
M llvm/test/CodeGen/AArch64/extract-lowbits.ll
M llvm/test/CodeGen/AArch64/extract-sext-zext.ll
M llvm/test/CodeGen/AArch64/extract-subvec-combine.ll
M llvm/test/CodeGen/AArch64/extract-vector-cmp.ll
M llvm/test/CodeGen/AArch64/extract-vector-elt.ll
M llvm/test/CodeGen/AArch64/f16-instructions.ll
M llvm/test/CodeGen/AArch64/fabs-fp128.ll
M llvm/test/CodeGen/AArch64/fabs.ll
M llvm/test/CodeGen/AArch64/faddp-half.ll
M llvm/test/CodeGen/AArch64/faddp.ll
M llvm/test/CodeGen/AArch64/faddsub.ll
M llvm/test/CodeGen/AArch64/fast-isel-addressing-modes.ll
M llvm/test/CodeGen/AArch64/fast-isel-gep.ll
M llvm/test/CodeGen/AArch64/fast-isel-shift.ll
M llvm/test/CodeGen/AArch64/fcmp.ll
M llvm/test/CodeGen/AArch64/fcopysign-noneon.ll
M llvm/test/CodeGen/AArch64/fcopysign.ll
M llvm/test/CodeGen/AArch64/fcvt.ll
M llvm/test/CodeGen/AArch64/fcvt_combine.ll
M llvm/test/CodeGen/AArch64/fdiv-combine.ll
M llvm/test/CodeGen/AArch64/fdiv.ll
M llvm/test/CodeGen/AArch64/fexplog.ll
M llvm/test/CodeGen/AArch64/fixed-point-conv-vec-pat.ll
M llvm/test/CodeGen/AArch64/fixed-vector-deinterleave.ll
M llvm/test/CodeGen/AArch64/fixed-vector-interleave.ll
M llvm/test/CodeGen/AArch64/fmaximum-legalization.ll
M llvm/test/CodeGen/AArch64/fminimummaximum.ll
M llvm/test/CodeGen/AArch64/fminmax.ll
M llvm/test/CodeGen/AArch64/fmla.ll
M llvm/test/CodeGen/AArch64/fmul.ll
M llvm/test/CodeGen/AArch64/fneg.ll
M llvm/test/CodeGen/AArch64/fold-int-pow2-with-fmul-or-fdiv.ll
M llvm/test/CodeGen/AArch64/fp-conversion-to-tbl.ll
M llvm/test/CodeGen/AArch64/fp-intrinsics-vector.ll
M llvm/test/CodeGen/AArch64/fp-maximumnum-minimumnum.ll
M llvm/test/CodeGen/AArch64/fp16-v8-instructions.ll
M llvm/test/CodeGen/AArch64/fp16-vector-shuffle.ll
M llvm/test/CodeGen/AArch64/fp16_intrinsic_lane.ll
M llvm/test/CodeGen/AArch64/fp8-sve-cvtn.ll
M llvm/test/CodeGen/AArch64/fpclamptosat_vec.ll
M llvm/test/CodeGen/AArch64/fpext.ll
M llvm/test/CodeGen/AArch64/fpmode.ll
M llvm/test/CodeGen/AArch64/fpow.ll
M llvm/test/CodeGen/AArch64/fpowi.ll
M llvm/test/CodeGen/AArch64/fptoi.ll
M llvm/test/CodeGen/AArch64/fptosi-sat-vector.ll
M llvm/test/CodeGen/AArch64/fptoui-sat-vector.ll
M llvm/test/CodeGen/AArch64/fptrunc.ll
M llvm/test/CodeGen/AArch64/freeze.ll
M llvm/test/CodeGen/AArch64/frem-power2.ll
M llvm/test/CodeGen/AArch64/frem.ll
M llvm/test/CodeGen/AArch64/fsincos.ll
M llvm/test/CodeGen/AArch64/fsqrt.ll
M llvm/test/CodeGen/AArch64/funnel-shift.ll
M llvm/test/CodeGen/AArch64/get-active-lane-mask-extract.ll
M llvm/test/CodeGen/AArch64/get_vector_length.ll
M llvm/test/CodeGen/AArch64/half.ll
M llvm/test/CodeGen/AArch64/hoist-and-by-const-from-lshr-in-eqcmp-zero.ll
M llvm/test/CodeGen/AArch64/hoist-and-by-const-from-shl-in-eqcmp-zero.ll
M llvm/test/CodeGen/AArch64/icmp.ll
M llvm/test/CodeGen/AArch64/implicit-def-remat-requires-impdef-check.mir
M llvm/test/CodeGen/AArch64/implicit-def-subreg-to-reg-regression.ll
M llvm/test/CodeGen/AArch64/implicit-def-with-impdef-greedy-assert.mir
M llvm/test/CodeGen/AArch64/insert-extend.ll
M llvm/test/CodeGen/AArch64/insert-subvector.ll
M llvm/test/CodeGen/AArch64/insertextract.ll
M llvm/test/CodeGen/AArch64/insertshuffleload.ll
M llvm/test/CodeGen/AArch64/intrinsic-cttz-elts-sve.ll
M llvm/test/CodeGen/AArch64/intrinsic-vector-match-sve2.ll
M llvm/test/CodeGen/AArch64/itofp-bf16.ll
M llvm/test/CodeGen/AArch64/itofp.ll
M llvm/test/CodeGen/AArch64/ldexp.ll
M llvm/test/CodeGen/AArch64/llrint-conv-fp16.ll
M llvm/test/CodeGen/AArch64/llrint-conv.ll
M llvm/test/CodeGen/AArch64/llround-conv-fp16.ll
M llvm/test/CodeGen/AArch64/llvm.exp10.ll
M llvm/test/CodeGen/AArch64/llvm.frexp.ll
M llvm/test/CodeGen/AArch64/llvm.sincos.ll
M llvm/test/CodeGen/AArch64/load.ll
M llvm/test/CodeGen/AArch64/logic-shift.ll
M llvm/test/CodeGen/AArch64/lrint-conv-fp16.ll
M llvm/test/CodeGen/AArch64/lrint-conv.ll
M llvm/test/CodeGen/AArch64/lround-conv-fp16.ll
M llvm/test/CodeGen/AArch64/lslfast.ll
M llvm/test/CodeGen/AArch64/machine-combiner-copy.ll
M llvm/test/CodeGen/AArch64/machine-licm-sub-loop.ll
M llvm/test/CodeGen/AArch64/memset-inline.ll
M llvm/test/CodeGen/AArch64/memset-vs-memset-inline.ll
M llvm/test/CodeGen/AArch64/misched-detail-resource-booking-01.mir
M llvm/test/CodeGen/AArch64/mla_mls_merge.ll
M llvm/test/CodeGen/AArch64/mul.ll
M llvm/test/CodeGen/AArch64/neon-bitcast.ll
M llvm/test/CodeGen/AArch64/neon-bitwise-instructions.ll
M llvm/test/CodeGen/AArch64/neon-dot-product.ll
M llvm/test/CodeGen/AArch64/neon-extadd-extract.ll
M llvm/test/CodeGen/AArch64/neon-extract.ll
M llvm/test/CodeGen/AArch64/neon-extracttruncate.ll
M llvm/test/CodeGen/AArch64/neon-insert-sve-elt.ll
M llvm/test/CodeGen/AArch64/neon-insextbitcast.ll
M llvm/test/CodeGen/AArch64/neon-luti.ll
M llvm/test/CodeGen/AArch64/neon-partial-reduce-dot-product.ll
M llvm/test/CodeGen/AArch64/neon-perm.ll
M llvm/test/CodeGen/AArch64/neon-reverseshuffle.ll
M llvm/test/CodeGen/AArch64/neon-rshrn.ll
M llvm/test/CodeGen/AArch64/neon-scalar-by-elem-fma.ll
M llvm/test/CodeGen/AArch64/neon-scalarize-histogram.ll
M llvm/test/CodeGen/AArch64/neon-shuffle-vector-tbl.ll
M llvm/test/CodeGen/AArch64/neon-truncstore.ll
M llvm/test/CodeGen/AArch64/neon-vcmla.ll
M llvm/test/CodeGen/AArch64/neon-wide-splat.ll
M llvm/test/CodeGen/AArch64/neon-widen-shuffle.ll
M llvm/test/CodeGen/AArch64/nontemporal-load.ll
M llvm/test/CodeGen/AArch64/nontemporal.ll
M llvm/test/CodeGen/AArch64/phi.ll
M llvm/test/CodeGen/AArch64/popcount.ll
M llvm/test/CodeGen/AArch64/pow.ll
M llvm/test/CodeGen/AArch64/pr-cf624b2.ll
M llvm/test/CodeGen/AArch64/pr58350.ll
M llvm/test/CodeGen/AArch64/pr58431.ll
M llvm/test/CodeGen/AArch64/pr61111.ll
M llvm/test/CodeGen/AArch64/preserve_nonecc_varargs_win64.ll
M llvm/test/CodeGen/AArch64/ptradd.ll
M llvm/test/CodeGen/AArch64/qmovn.ll
M llvm/test/CodeGen/AArch64/rcpc3.ll
M llvm/test/CodeGen/AArch64/reduce-and.ll
M llvm/test/CodeGen/AArch64/reduce-or.ll
M llvm/test/CodeGen/AArch64/reduce-shuffle.ll
M llvm/test/CodeGen/AArch64/reduce-xor.ll
M llvm/test/CodeGen/AArch64/regalloc-last-chance-recolor-with-split.mir
M llvm/test/CodeGen/AArch64/rem.ll
M llvm/test/CodeGen/AArch64/round-fptosi-sat-scalar.ll
M llvm/test/CodeGen/AArch64/select-constant-xor.ll
M llvm/test/CodeGen/AArch64/seqpairspill.mir
M llvm/test/CodeGen/AArch64/setcc_knownbits.ll
M llvm/test/CodeGen/AArch64/sext.ll
M llvm/test/CodeGen/AArch64/shift-amount-mod.ll
M llvm/test/CodeGen/AArch64/shift-by-signext.ll
M llvm/test/CodeGen/AArch64/shift-mod.ll
M llvm/test/CodeGen/AArch64/shift.ll
M llvm/test/CodeGen/AArch64/shift_minsize.ll
M llvm/test/CodeGen/AArch64/shuffle-tbl34.ll
M llvm/test/CodeGen/AArch64/shuffles.ll
M llvm/test/CodeGen/AArch64/shufflevector.ll
M llvm/test/CodeGen/AArch64/sink-and-fold.ll
M llvm/test/CodeGen/AArch64/sme-aarch64-svcount.ll
M llvm/test/CodeGen/AArch64/sme-avoid-coalescing-locally-streaming.ll
M llvm/test/CodeGen/AArch64/sme-intrinsics-loads.ll
M llvm/test/CodeGen/AArch64/sme-intrinsics-stores.ll
M llvm/test/CodeGen/AArch64/sme-pstate-sm-changing-call-disable-coalescing.ll
M llvm/test/CodeGen/AArch64/sme-streaming-body.ll
M llvm/test/CodeGen/AArch64/sme-streaming-compatible-interface.ll
M llvm/test/CodeGen/AArch64/sme2-fp8-intrinsics-cvt.ll
M llvm/test/CodeGen/AArch64/sme2-intrinsics-add-sub-za16.ll
M llvm/test/CodeGen/AArch64/sme2-intrinsics-add.ll
M llvm/test/CodeGen/AArch64/sme2-intrinsics-cvtn.ll
M llvm/test/CodeGen/AArch64/sme2-intrinsics-faminmax.ll
M llvm/test/CodeGen/AArch64/sme2-intrinsics-fmlas.ll
M llvm/test/CodeGen/AArch64/sme2-intrinsics-fp-dots.ll
M llvm/test/CodeGen/AArch64/sme2-intrinsics-fscale.ll
M llvm/test/CodeGen/AArch64/sme2-intrinsics-insert-mova.ll
M llvm/test/CodeGen/AArch64/sme2-intrinsics-luti4.ll
M llvm/test/CodeGen/AArch64/sme2-intrinsics-max.ll
M llvm/test/CodeGen/AArch64/sme2-intrinsics-min.ll
M llvm/test/CodeGen/AArch64/sme2-intrinsics-mlall.ll
M llvm/test/CodeGen/AArch64/sme2-intrinsics-mlals.ll
M llvm/test/CodeGen/AArch64/sme2-intrinsics-rshl.ll
M llvm/test/CodeGen/AArch64/sme2-intrinsics-select-sme-tileslice.ll
M llvm/test/CodeGen/AArch64/sme2-intrinsics-sqdmulh.ll
M llvm/test/CodeGen/AArch64/sme2-intrinsics-sub.ll
M llvm/test/CodeGen/AArch64/sme2-intrinsics-vdot.ll
M llvm/test/CodeGen/AArch64/smul_fix_sat.ll
M llvm/test/CodeGen/AArch64/spill-fold.mir
M llvm/test/CodeGen/AArch64/split-vector-insert.ll
M llvm/test/CodeGen/AArch64/srem-vector-lkk.ll
M llvm/test/CodeGen/AArch64/store.ll
M llvm/test/CodeGen/AArch64/sub.ll
M llvm/test/CodeGen/AArch64/sve-cntp-combine-i32.ll
M llvm/test/CodeGen/AArch64/sve-doublereduct.ll
M llvm/test/CodeGen/AArch64/sve-extract-element.ll
M llvm/test/CodeGen/AArch64/sve-extract-fixed-from-scalable-vector.ll
M llvm/test/CodeGen/AArch64/sve-extract-fixed-vector.ll
M llvm/test/CodeGen/AArch64/sve-extract-scalable-vector.ll
M llvm/test/CodeGen/AArch64/sve-fadda-select.ll
M llvm/test/CodeGen/AArch64/sve-fixed-length-bit-counting.ll
M llvm/test/CodeGen/AArch64/sve-fixed-length-concat.ll
M llvm/test/CodeGen/AArch64/sve-fixed-length-extract-subvector.ll
M llvm/test/CodeGen/AArch64/sve-fixed-length-extract-vector-elt.ll
M llvm/test/CodeGen/AArch64/sve-fixed-length-fp-extend-trunc.ll
M llvm/test/CodeGen/AArch64/sve-fixed-length-fp-reduce.ll
M llvm/test/CodeGen/AArch64/sve-fixed-length-fp-select.ll
M llvm/test/CodeGen/AArch64/sve-fixed-length-fp-to-int.ll
M llvm/test/CodeGen/AArch64/sve-fixed-length-fp128.ll
M llvm/test/CodeGen/AArch64/sve-fixed-length-insert-vector-elt.ll
M llvm/test/CodeGen/AArch64/sve-fixed-length-int-arith.ll
M llvm/test/CodeGen/AArch64/sve-fixed-length-int-div.ll
M llvm/test/CodeGen/AArch64/sve-fixed-length-int-extends.ll
M llvm/test/CodeGen/AArch64/sve-fixed-length-int-minmax.ll
M llvm/test/CodeGen/AArch64/sve-fixed-length-int-mulh.ll
M llvm/test/CodeGen/AArch64/sve-fixed-length-int-reduce.ll
M llvm/test/CodeGen/AArch64/sve-fixed-length-int-rem.ll
M llvm/test/CodeGen/AArch64/sve-fixed-length-int-select.ll
M llvm/test/CodeGen/AArch64/sve-fixed-length-int-to-fp.ll
M llvm/test/CodeGen/AArch64/sve-fixed-length-log-reduce.ll
M llvm/test/CodeGen/AArch64/sve-fixed-length-masked-128bit-loads.ll
M llvm/test/CodeGen/AArch64/sve-fixed-length-masked-loads.ll
M llvm/test/CodeGen/AArch64/sve-fixed-length-no-vscale-range.ll
M llvm/test/CodeGen/AArch64/sve-fixed-length-reshuffle.ll
M llvm/test/CodeGen/AArch64/sve-fixed-length-rev.ll
M llvm/test/CodeGen/AArch64/sve-fixed-length-sdiv-pow2.ll
M llvm/test/CodeGen/AArch64/sve-fixed-length-shuffles.ll
M llvm/test/CodeGen/AArch64/sve-fixed-length-splat-vector.ll
M llvm/test/CodeGen/AArch64/sve-fixed-length-subvector.ll
M llvm/test/CodeGen/AArch64/sve-fixed-length-trunc.ll
M llvm/test/CodeGen/AArch64/sve-fixed-length-vector-shuffle-tbl.ll
M llvm/test/CodeGen/AArch64/sve-fixed-vector-llrint.ll
M llvm/test/CodeGen/AArch64/sve-fixed-vector-lrint.ll
M llvm/test/CodeGen/AArch64/sve-fp-reduce-fadda.ll
M llvm/test/CodeGen/AArch64/sve-fp-reduce.ll
M llvm/test/CodeGen/AArch64/sve-i1-add-reduce.ll
M llvm/test/CodeGen/AArch64/sve-implicit-zero-filling.ll
M llvm/test/CodeGen/AArch64/sve-index-const-step-vector.ll
M llvm/test/CodeGen/AArch64/sve-insert-element.ll
M llvm/test/CodeGen/AArch64/sve-insert-vector.ll
M llvm/test/CodeGen/AArch64/sve-int-reduce.ll
M llvm/test/CodeGen/AArch64/sve-intrinsics-counting-elems-i32.ll
M llvm/test/CodeGen/AArch64/sve-intrinsics-dup-x.ll
M llvm/test/CodeGen/AArch64/sve-intrinsics-fp-reduce.ll
M llvm/test/CodeGen/AArch64/sve-intrinsics-perm-select.ll
M llvm/test/CodeGen/AArch64/sve-intrinsics-reinterpret.ll
M llvm/test/CodeGen/AArch64/sve-intrinsics-shifts.ll
M llvm/test/CodeGen/AArch64/sve-intrinsics-sqdec.ll
M llvm/test/CodeGen/AArch64/sve-intrinsics-sqinc.ll
M llvm/test/CodeGen/AArch64/sve-intrinsics-stN-reg-imm-addr-mode.ll
M llvm/test/CodeGen/AArch64/sve-intrinsics-stN-reg-reg-addr-mode.ll
M llvm/test/CodeGen/AArch64/sve-intrinsics-stores.ll
M llvm/test/CodeGen/AArch64/sve-merging-stores.ll
M llvm/test/CodeGen/AArch64/sve-nontemporal-masked-ldst.ll
M llvm/test/CodeGen/AArch64/sve-pr62151.ll
M llvm/test/CodeGen/AArch64/sve-pred-selectop.ll
M llvm/test/CodeGen/AArch64/sve-select.ll
M llvm/test/CodeGen/AArch64/sve-split-extract-elt.ll
M llvm/test/CodeGen/AArch64/sve-split-fp-reduce.ll
M llvm/test/CodeGen/AArch64/sve-split-int-reduce.ll
M llvm/test/CodeGen/AArch64/sve-stack-frame-layout.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-and-combine.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-bit-counting.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-bitselect.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-build-vector.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-concat.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-ext-loads.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-extract-subvector.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-extract-vector-elt.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fcopysign.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-arith.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-compares.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-extend-trunc.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-fma.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-minmax.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-reduce-fa64.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-reduce.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-rounding.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-select.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-to-int.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-vselect.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-insert-vector-elt.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-arith.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-compares.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-div.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-extends.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-log.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-minmax.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-mla-neon-fa64.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-mul.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-mulh.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-reduce.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-rem.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-select.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-shifts.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-to-fp.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-vselect.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-ld2-alloca.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-limit-duplane.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-loads.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-log-reduce.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-masked-gather-scatter.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-masked-load.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-masked-store.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-permute-rev.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-ptest.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-reductions.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-reshuffle.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-rev.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-sdiv-pow2.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-shuffle.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-splat-vector.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-trunc-stores.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-trunc.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-vector-shuffle.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-test-register-mov.ll
M llvm/test/CodeGen/AArch64/sve-vecreduce-dot.ll
M llvm/test/CodeGen/AArch64/sve-vector-compress.ll
M llvm/test/CodeGen/AArch64/sve-vector-splat.ll
M llvm/test/CodeGen/AArch64/sve-vl-arith.ll
M llvm/test/CodeGen/AArch64/sve2-histcnt.ll
M llvm/test/CodeGen/AArch64/sve2-intrinsics-luti.ll
M llvm/test/CodeGen/AArch64/sve2-intrinsics-perm-tb.ll
M llvm/test/CodeGen/AArch64/sve2p1-intrinsics-bfclamp.ll
M llvm/test/CodeGen/AArch64/sve2p1-intrinsics-fclamp.ll
M llvm/test/CodeGen/AArch64/sve2p1-intrinsics-multivec-stores.ll
M llvm/test/CodeGen/AArch64/sve2p1-intrinsics-sclamp.ll
M llvm/test/CodeGen/AArch64/sve2p1-intrinsics-selx4.ll
M llvm/test/CodeGen/AArch64/sve2p1-intrinsics-stores.ll
M llvm/test/CodeGen/AArch64/sve2p1-intrinsics-uclamp.ll
M llvm/test/CodeGen/AArch64/sve2p1-intrinsics-uzpx4.ll
M llvm/test/CodeGen/AArch64/sve2p1-intrinsics-while-pp.ll
M llvm/test/CodeGen/AArch64/swift-error-unreachable-use.ll
M llvm/test/CodeGen/AArch64/tbl-loops.ll
M llvm/test/CodeGen/AArch64/trunc-to-tbl.ll
M llvm/test/CodeGen/AArch64/uaddlv-vaddlp-combine.ll
M llvm/test/CodeGen/AArch64/umul_fix_sat.ll
M llvm/test/CodeGen/AArch64/urem-vector-lkk.ll
M llvm/test/CodeGen/AArch64/vec-combine-compare-to-bitmask.ll
M llvm/test/CodeGen/AArch64/vec-libcalls.ll
M llvm/test/CodeGen/AArch64/vecreduce-add-legalization.ll
M llvm/test/CodeGen/AArch64/vecreduce-add.ll
M llvm/test/CodeGen/AArch64/vecreduce-and-legalization.ll
M llvm/test/CodeGen/AArch64/vecreduce-bool.ll
M llvm/test/CodeGen/AArch64/vecreduce-fadd-legalization-strict.ll
M llvm/test/CodeGen/AArch64/vecreduce-fadd-legalization.ll
M llvm/test/CodeGen/AArch64/vecreduce-fadd-strict.ll
M llvm/test/CodeGen/AArch64/vecreduce-fadd.ll
M llvm/test/CodeGen/AArch64/vecreduce-fmax-legalization-nan.ll
M llvm/test/CodeGen/AArch64/vecreduce-fmax-legalization.ll
M llvm/test/CodeGen/AArch64/vecreduce-fmaximum.ll
M llvm/test/CodeGen/AArch64/vecreduce-fmin-legalization.ll
M llvm/test/CodeGen/AArch64/vecreduce-fminimum.ll
M llvm/test/CodeGen/AArch64/vecreduce-fmul-legalization-strict.ll
M llvm/test/CodeGen/AArch64/vecreduce-fmul-strict.ll
M llvm/test/CodeGen/AArch64/vecreduce-fmul.ll
M llvm/test/CodeGen/AArch64/vecreduce-umax-legalization.ll
M llvm/test/CodeGen/AArch64/vector-compress.ll
M llvm/test/CodeGen/AArch64/vector-fcopysign.ll
M llvm/test/CodeGen/AArch64/vector-fcvt.ll
M llvm/test/CodeGen/AArch64/vector-llrint.ll
M llvm/test/CodeGen/AArch64/vector-lrint.ll
M llvm/test/CodeGen/AArch64/vldn_shuffle.ll
M llvm/test/CodeGen/AArch64/win64-fpowi.ll
M llvm/test/CodeGen/AArch64/win64_vararg.ll
M llvm/test/CodeGen/AArch64/xtn.ll
M llvm/test/CodeGen/AArch64/zext.ll
Log Message:
-----------
[AArch64] Enable subreg liveness tracking by default.
Internal testing didn't flag up any functional- or performance regressions.
Commit: 60d9e6fba884048e1047a208b61f0dfd8baabaaa
https://github.com/llvm/llvm-project/commit/60d9e6fba884048e1047a208b61f0dfd8baabaaa
Author: Jan Ječmen <JanJecmen at users.noreply.github.com>
Date: 2024-12-12 (Thu, 12 Dec 2024)
Changed paths:
M llvm/lib/Transforms/Scalar/InductiveRangeCheckElimination.cpp
M llvm/test/Transforms/IRCE/low-iterations.ll
A llvm/test/Transforms/IRCE/profitability.ll
Log Message:
-----------
[IRCE] Relax profitability check (#104659)
IRCE currently has two profitability checks:
1. min number of iterations (10 by default)
2. branch is highly biased (> 15/16)
However, it may still be profitable to eliminate range checks even if
the branch isn't as biased. Consider, for example, a loop with 100
iterations, where IRCE currently eliminates all 100 range checks. The
same range checks performed over a loop with 200 iterations aren't
eliminated because the branch is 50-50.
This patch proposes to relax the profitability checks of IRCE. Namely,
instead of the two checks currenly in place, consider IRCE profitable if
the branch probability scaled by the expected number of iterations
(i.e., the estimated number of eliminated checks) is over a threshold.
This covers the minimum number of iterations check (there are at least
as many iterations as eliminated range checks), and changes the bias
check from a percent of iterations to at least a constant threshold of
eliminated checks.
If the number of iterations can't be estimated, the check falls back to
the current 15/16 likelihood check.
Commit: bdd365825d0766b6991c8f5443f8a9f76e75011a
https://github.com/llvm/llvm-project/commit/bdd365825d0766b6991c8f5443f8a9f76e75011a
Author: Benoit Jacob <jacob.benoit.1 at gmail.com>
Date: 2024-12-12 (Thu, 12 Dec 2024)
Changed paths:
M mlir/lib/Conversion/ComplexToStandard/ComplexToStandard.cpp
M mlir/test/Conversion/ComplexToStandard/convert-to-standard.mlir
Log Message:
-----------
[MLIR] Fix `ComplexToStandard` lowering of `complex::MulOp` (#119591)
A complex multiplication should lower simply to the familiar 4 real
multiplications, 1 real addition, 1 real subtraction. No special-casing
of infinite or NaN values should be made, instead the complex numbers
should be thought as just vectors of two reals, naturally bottoming out
on the reals' semantics, IEEE754 or otherwise. That is what nearly
everybody else is doing ("nearly" because at the end of this PR
description we pinpoint the actual source of this in C99 `_Complex`),
and this pattern, by trying to do something different, was generating
much larger code, which was much slower and a departure from the
naturally expected floating-point behavior.
This code had originally been introduced in
https://reviews.llvm.org/D105270, which stated this rationale:
> The lowering handles special cases with NaN or infinity like C++.
I don't think that the C++ standard is a particularly important thing to
follow in this instance. What matters more is what people actually do in
practice with complex numbers, which rarely involves the C++
`std::complex` library type.
But out of curiosity, I checked, and the above statement seems
incorrect. The [current C++
standard](https://www.open-std.org/jtc1/sc22/wg21/docs/papers/2023/n4928.pdf)
library specification for `std::complex` does not say anything about the
implementation of complex multiplication: paragraph `[complex.ops]`
falls back on `[complex.member.ops]` which says:
> Effects: Multiplies the complex value rhs by the complex value *this
and stores the product in *this.
I also checked cppreference which often has useful information in case
something changed in a c++ language revision, but likewise, nothing at
all there:
https://en.cppreference.com/w/cpp/numeric/complex/operator_arith3
Finally, I checked in Compiler Explorer what Clang 19 currently
generates:
https://godbolt.org/z/oY7Ks4j95
That is just the familiar 4 multiplications.... and then there is some
weird check (`fcmp`) and conditionally a call to an external `__mulsc3`.
Googled that, found this StackOverflow answer:
https://stackoverflow.com/a/49438578
Summary: this is not about C++ (this post confirms my reading of the C++
standard not mandating anything about this). This is about C, and it
just happens that this C++ standard library implementation bottoms out
on code shared with the C `_Complex` implementation.
Another nuance missing in that SO answer: this is actually
[implementation-defined
behavior](https://en.cppreference.com/w/c/preprocessor/impl). There are
two modes, controlled by
```c
#pragma STDC CX_LIMITED_RANGE {ON,OFF,DEFAULT}
```
It is implementation-defined which is the default. Clang defaults to
OFF, but that's just Clang. In that mode, the check is required:
https://en.cppreference.com/w/c/language/arithmetic_types#Complex_floating_types
And the specific point in the [C99
standard](https://www.open-std.org/jtc1/sc22/wg14/www/docs/n1256.pdf)
is: `G.5.1 Multiplicative operators`.
But set it to ON and the check is gone:
https://godbolt.org/z/aG8fnbYoP
Summary: the argument has moved from C++ to C --- and even there, to
implementation-defined behavior with a standard opt-out mechanism.
Like with C++, I maintain that the C standard is not a particularly
meaningful thing for MLIR to follow here, because people doing business
with complex numbers tend to lower them to real numbers themselves, or
have their own specialized complex types, either way not relying on
C99's `_Complex` type --- and the very poor performance of the
`CX_LIMITED_RANGE OFF` behavior (default in Clang) is certainly a key
reason why people who care prefer to stay away from `_Complex` and
`std::complex`.
A good example that's relevant to MLIR's space is CUDA's `cuComplex`
type (used in the cuBLAS CGEMM interface). Here is its multiplication
function. The comment about competitiveness is interesting: it's not a
quirk of this particular function, it's the spirit underpinning
numerical code that matters.
https://github.com/tpn/cuda-samples/blob/1bf5cd15c51ce80fc9b387c0ff89a9f535b42bf5/v8.0/include/cuComplex.h#L106-L120
```c
/* This implementation could suffer from intermediate overflow even though
* the final result would be in range. However, various implementations do
* not guard against this (presumably to avoid losing performance), so we
* don't do it either to stay competitive.
*/
__host__ __device__ static __inline__ cuFloatComplex cuCmulf (cuFloatComplex x,
cuFloatComplex y)
{
cuFloatComplex prod;
prod = make_cuFloatComplex ((cuCrealf(x) * cuCrealf(y)) -
(cuCimagf(x) * cuCimagf(y)),
(cuCrealf(x) * cuCimagf(y)) +
(cuCimagf(x) * cuCrealf(y)));
return prod;
}
```
Another instance in CUTLASS:
https://github.com/NVIDIA/cutlass/blob/main/include/cutlass/complex.h#L231-L236
Signed-off-by: Benoit Jacob <jacob.benoit.1 at gmail.com>
Commit: c95af0844d64f15b99fab37c25efb01a8d783847
https://github.com/llvm/llvm-project/commit/c95af0844d64f15b99fab37c25efb01a8d783847
Author: Florian Hahn <flo at fhahn.com>
Date: 2024-12-12 (Thu, 12 Dec 2024)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlan.cpp
Log Message:
-----------
[VPlan] Move ::getVectorLoopRegion out of ifdef (NFC).
Fixes a build failure with assertions disabled after
6c8f41d336747.
Commit: 8eec301fe3ac5fdcb4de4757806661b99c9e6580
https://github.com/llvm/llvm-project/commit/8eec301fe3ac5fdcb4de4757806661b99c9e6580
Author: erichkeane <ekeane at nvidia.com>
Date: 2024-12-12 (Thu, 12 Dec 2024)
Changed paths:
M clang/lib/Sema/SemaOpenACC.cpp
M clang/test/AST/ast-print-openacc-data-construct.cpp
A clang/test/SemaOpenACC/data-construct-device_type-ast.cpp
A clang/test/SemaOpenACC/data-construct-device_type-clause.c
M clang/test/SemaOpenACC/data-construct.cpp
Log Message:
-----------
[OpenACC] Implement 'device_type' for 'data' construct
Semantically this is identical to all other constructs with this tag,
except in this case the 'wait' and 'async' are the only ones allowed
after it. This patch implements that rule using the existing
infrastructure.
Commit: 4a5f82b43be7328d7b7b4cd9912487fd3f284b49
https://github.com/llvm/llvm-project/commit/4a5f82b43be7328d7b7b4cd9912487fd3f284b49
Author: Aleksei Vetrov <vetaleha at gmail.com>
Date: 2024-12-12 (Thu, 12 Dec 2024)
Changed paths:
M llvm/lib/MC/MCParser/AsmParser.cpp
A llvm/test/MC/ELF/debug-hash-file-empty-dwarf.s
M llvm/test/MC/ELF/debug-hash-file.s
Log Message:
-----------
[MC] Fix DWARF file table for files with empty DWARF (#119572)
Update root file in DWARF file/line table as soon as we see the first
"#line" directive.
This was moved from "enabledGenDwarfForAssembly", which is called right
before we emit DWARF information. But if the file is empty or contains
expressions that doesn't need DWARF, it is never called, leaving an
original root file and not the file in the "#line" directive.
Add a test checking for this case.
This is reapply of #119229 with the following fix:
"MCContext::setMCLineTableRootFile" has the effect of adding
".debug_line" section to the output, even if DWARF generation is
disabled. Add a check and a test for this case.
Fixes: #119020
Fixes: #119229
Commit: 6edd867e43cb5eb3bb84561c0490e5ebb9d06d90
https://github.com/llvm/llvm-project/commit/6edd867e43cb5eb3bb84561c0490e5ebb9d06d90
Author: Abhina Sreeskantharajan <Abhina.Sreeskantharajan at ibm.com>
Date: 2024-12-12 (Thu, 12 Dec 2024)
Changed paths:
M clang/lib/Basic/SourceManager.cpp
Log Message:
-----------
[SystemZ][z/OS] Replace assert with updated return statement to check if a file size will grow due to conversion
Commit: 4cce10743d2275710d3d2e0de8013386a9799092
https://github.com/llvm/llvm-project/commit/4cce10743d2275710d3d2e0de8013386a9799092
Author: knickish <knickish at gmail.com>
Date: 2024-12-12 (Thu, 12 Dec 2024)
Changed paths:
M llvm/lib/Target/M68k/Disassembler/M68kDisassembler.cpp
M llvm/lib/Target/M68k/M68kISelDAGToDAG.cpp
M llvm/lib/Target/M68k/M68kInstrAtomics.td
M llvm/test/CodeGen/M68k/Atomics/load-store.ll
M llvm/test/CodeGen/M68k/Atomics/rmw.ll
A llvm/test/CodeGen/M68k/CodeModel/Large/Atomics/cmpxchg.ll
A llvm/test/CodeGen/M68k/CodeModel/Large/Atomics/fence.ll
A llvm/test/CodeGen/M68k/CodeModel/Large/Atomics/load-store.ll
A llvm/test/CodeGen/M68k/CodeModel/Large/Atomics/rmw.ll
A llvm/test/CodeGen/M68k/CodeModel/Large/large-pic.ll
A llvm/test/CodeGen/M68k/CodeModel/Large/large-pie-global-access.ll
A llvm/test/CodeGen/M68k/CodeModel/Large/large-pie.ll
A llvm/test/CodeGen/M68k/CodeModel/Large/large-static.ll
A llvm/test/CodeGen/M68k/CodeModel/Medium/medium-pic.ll
A llvm/test/CodeGen/M68k/CodeModel/Medium/medium-pie-global-access.ll
A llvm/test/CodeGen/M68k/CodeModel/Medium/medium-pie.ll
A llvm/test/CodeGen/M68k/CodeModel/Medium/medium-static.ll
A llvm/test/CodeGen/M68k/CodeModel/Small/small-pic.ll
A llvm/test/CodeGen/M68k/CodeModel/Small/small-pie-global-access.ll
A llvm/test/CodeGen/M68k/CodeModel/Small/small-pie.ll
A llvm/test/CodeGen/M68k/CodeModel/Small/small-static.ll
R llvm/test/CodeGen/M68k/CodeModel/large-pic.ll
R llvm/test/CodeGen/M68k/CodeModel/large-pie-global-access.ll
R llvm/test/CodeGen/M68k/CodeModel/large-pie.ll
R llvm/test/CodeGen/M68k/CodeModel/large-static.ll
R llvm/test/CodeGen/M68k/CodeModel/medium-pic.ll
R llvm/test/CodeGen/M68k/CodeModel/medium-pie-global-access.ll
R llvm/test/CodeGen/M68k/CodeModel/medium-pie.ll
R llvm/test/CodeGen/M68k/CodeModel/medium-static.ll
R llvm/test/CodeGen/M68k/CodeModel/small-pic.ll
R llvm/test/CodeGen/M68k/CodeModel/small-pie-global-access.ll
R llvm/test/CodeGen/M68k/CodeModel/small-pie.ll
R llvm/test/CodeGen/M68k/CodeModel/small-static.ll
A llvm/test/CodeGen/M68k/TLS/tls-arid.ll
M llvm/test/MC/M68k/Atomics/cas.s
Log Message:
-----------
[M68k] Add remaining addressing modes for Atomic operations (#115523)
Had been doing this piece by piece, but makes more sense to do it in a
single PR. Adds support for `ARID`, `PCI`, `PCD`, `AL`, and `ARD`
addressing modes for atomic operations, along with a variety of tests.
The `CodeModel` tests have been rearranged, as some of the new
addressing modes are only exercised under some combinations of
`CodeModel` and relocation mode
Commit: e17d2b585b4d35b9cab0673cf77a35fa933dd030
https://github.com/llvm/llvm-project/commit/e17d2b585b4d35b9cab0673cf77a35fa933dd030
Author: Nick Desaulniers <nickdesaulniers at users.noreply.github.com>
Date: 2024-12-12 (Thu, 12 Dec 2024)
Changed paths:
A libc/docs/headers/arpa/inet.rst
M libc/docs/headers/index.rst
A libc/docs/headers/sys/mman.rst
A libc/utils/docgen/arpa/inet.json
M libc/utils/docgen/docgen.py
M libc/utils/docgen/header.py
A libc/utils/docgen/sys/mman.json
Log Message:
-----------
[libc][docgen] support non-top-level headers (#119621)
such as arpa/inet, sys/*
Commit: 61510b51c33464a6bc15e4cf5b1ee07e2e0ec1c9
https://github.com/llvm/llvm-project/commit/61510b51c33464a6bc15e4cf5b1ee07e2e0ec1c9
Author: Sander de Smalen <sander.desmalen at arm.com>
Date: 2024-12-12 (Thu, 12 Dec 2024)
Changed paths:
M llvm/lib/Target/AArch64/AArch64Subtarget.cpp
M llvm/test/CodeGen/AArch64/Atomics/aarch64-atomicrmw-lse2_lse128.ll
M llvm/test/CodeGen/AArch64/Atomics/aarch64-atomicrmw-v8_1a.ll
M llvm/test/CodeGen/AArch64/Atomics/aarch64_be-atomicrmw-lse2_lse128.ll
M llvm/test/CodeGen/AArch64/Atomics/aarch64_be-atomicrmw-v8_1a.ll
M llvm/test/CodeGen/AArch64/GlobalISel/arm64-atomic-128.ll
M llvm/test/CodeGen/AArch64/GlobalISel/arm64-atomic.ll
M llvm/test/CodeGen/AArch64/GlobalISel/arm64-pcsections.ll
M llvm/test/CodeGen/AArch64/GlobalISel/combine-udiv.ll
M llvm/test/CodeGen/AArch64/GlobalISel/insert-vector-elt-pr63826.ll
M llvm/test/CodeGen/AArch64/aarch64-addv.ll
M llvm/test/CodeGen/AArch64/aarch64-be-bv.ll
M llvm/test/CodeGen/AArch64/aarch64-bf16-dotprod-intrinsics.ll
M llvm/test/CodeGen/AArch64/aarch64-bif-gen.ll
M llvm/test/CodeGen/AArch64/aarch64-bit-gen.ll
M llvm/test/CodeGen/AArch64/aarch64-combine-add-sub-mul.ll
M llvm/test/CodeGen/AArch64/aarch64-combine-add-zext.ll
M llvm/test/CodeGen/AArch64/aarch64-dup-ext-scalable.ll
M llvm/test/CodeGen/AArch64/aarch64-dup-ext.ll
M llvm/test/CodeGen/AArch64/aarch64-dup-extract-scalable.ll
M llvm/test/CodeGen/AArch64/aarch64-fold-lslfast.ll
M llvm/test/CodeGen/AArch64/aarch64-interleaved-access-w-undef.ll
M llvm/test/CodeGen/AArch64/aarch64-load-ext.ll
M llvm/test/CodeGen/AArch64/aarch64-matrix-umull-smull.ll
M llvm/test/CodeGen/AArch64/aarch64-minmaxv.ll
M llvm/test/CodeGen/AArch64/aarch64-mops-mte.ll
M llvm/test/CodeGen/AArch64/aarch64-mops.ll
M llvm/test/CodeGen/AArch64/aarch64-mull-masks.ll
M llvm/test/CodeGen/AArch64/aarch64-mulv.ll
M llvm/test/CodeGen/AArch64/aarch64-neon-vector-insert-uaddlv.ll
M llvm/test/CodeGen/AArch64/aarch64-scalarize-vec-load-ext.ll
M llvm/test/CodeGen/AArch64/aarch64-sysreg128.ll
M llvm/test/CodeGen/AArch64/aarch64-wide-shuffle.ll
M llvm/test/CodeGen/AArch64/abs.ll
M llvm/test/CodeGen/AArch64/active_lane_mask.ll
M llvm/test/CodeGen/AArch64/adc.ll
M llvm/test/CodeGen/AArch64/add-extract.ll
M llvm/test/CodeGen/AArch64/add.ll
M llvm/test/CodeGen/AArch64/addimm-mulimm.ll
M llvm/test/CodeGen/AArch64/addp-shuffle.ll
M llvm/test/CodeGen/AArch64/addsub_ext.ll
M llvm/test/CodeGen/AArch64/and-mask-removal.ll
M llvm/test/CodeGen/AArch64/andorxor.ll
M llvm/test/CodeGen/AArch64/arm64-abi-varargs.ll
M llvm/test/CodeGen/AArch64/arm64-addp.ll
M llvm/test/CodeGen/AArch64/arm64-addr-type-promotion.ll
M llvm/test/CodeGen/AArch64/arm64-atomic-128.ll
M llvm/test/CodeGen/AArch64/arm64-bitfield-extract.ll
M llvm/test/CodeGen/AArch64/arm64-build-vector.ll
M llvm/test/CodeGen/AArch64/arm64-collect-loh.ll
M llvm/test/CodeGen/AArch64/arm64-dup.ll
M llvm/test/CodeGen/AArch64/arm64-ext.ll
M llvm/test/CodeGen/AArch64/arm64-extract-insert-varidx.ll
M llvm/test/CodeGen/AArch64/arm64-extract_subvector.ll
M llvm/test/CodeGen/AArch64/arm64-fcopysign.ll
M llvm/test/CodeGen/AArch64/arm64-fixed-point-scalar-cvt-dagcombine.ll
M llvm/test/CodeGen/AArch64/arm64-fmax.ll
M llvm/test/CodeGen/AArch64/arm64-fp128.ll
M llvm/test/CodeGen/AArch64/arm64-indexed-vector-ldst.ll
M llvm/test/CodeGen/AArch64/arm64-instruction-mix-remarks.ll
M llvm/test/CodeGen/AArch64/arm64-ld1.ll
M llvm/test/CodeGen/AArch64/arm64-ldxr-stxr.ll
M llvm/test/CodeGen/AArch64/arm64-mul.ll
M llvm/test/CodeGen/AArch64/arm64-neon-2velem-high.ll
M llvm/test/CodeGen/AArch64/arm64-neon-2velem.ll
M llvm/test/CodeGen/AArch64/arm64-neon-3vdiff.ll
M llvm/test/CodeGen/AArch64/arm64-neon-add-pairwise.ll
M llvm/test/CodeGen/AArch64/arm64-neon-copy.ll
M llvm/test/CodeGen/AArch64/arm64-neon-copyPhysReg-tuple.ll
M llvm/test/CodeGen/AArch64/arm64-neon-mul-div.ll
M llvm/test/CodeGen/AArch64/arm64-neon-scalar-by-elem-mul.ll
M llvm/test/CodeGen/AArch64/arm64-neon-select_cc.ll
M llvm/test/CodeGen/AArch64/arm64-neon-simd-ldst-one.ll
M llvm/test/CodeGen/AArch64/arm64-neon-simd-shift.ll
M llvm/test/CodeGen/AArch64/arm64-neon-simd-vget.ll
M llvm/test/CodeGen/AArch64/arm64-neon-v1i1-setcc.ll
M llvm/test/CodeGen/AArch64/arm64-neon-v8.1a.ll
M llvm/test/CodeGen/AArch64/arm64-nvcast.ll
M llvm/test/CodeGen/AArch64/arm64-popcnt.ll
M llvm/test/CodeGen/AArch64/arm64-rev.ll
M llvm/test/CodeGen/AArch64/arm64-shifted-sext.ll
M llvm/test/CodeGen/AArch64/arm64-shrink-wrapping.ll
M llvm/test/CodeGen/AArch64/arm64-stp.ll
M llvm/test/CodeGen/AArch64/arm64-subvector-extend.ll
M llvm/test/CodeGen/AArch64/arm64-tbl.ll
M llvm/test/CodeGen/AArch64/arm64-vadd.ll
M llvm/test/CodeGen/AArch64/arm64-vaddv.ll
M llvm/test/CodeGen/AArch64/arm64-vcvt_f.ll
M llvm/test/CodeGen/AArch64/arm64-vector-insertion.ll
M llvm/test/CodeGen/AArch64/arm64-vmul.ll
M llvm/test/CodeGen/AArch64/arm64-zip.ll
M llvm/test/CodeGen/AArch64/arm64_32-addrs.ll
M llvm/test/CodeGen/AArch64/arm64ec-entry-thunks.ll
M llvm/test/CodeGen/AArch64/arm64ec-exit-thunks.ll
M llvm/test/CodeGen/AArch64/atomic-ops-lse.ll
M llvm/test/CodeGen/AArch64/atomic-ops-msvc.ll
M llvm/test/CodeGen/AArch64/atomic-ops.ll
M llvm/test/CodeGen/AArch64/atomicrmw-fadd.ll
M llvm/test/CodeGen/AArch64/atomicrmw-fmax.ll
M llvm/test/CodeGen/AArch64/atomicrmw-fmin.ll
M llvm/test/CodeGen/AArch64/atomicrmw-fsub.ll
M llvm/test/CodeGen/AArch64/atomicrmw-xchg-fp.ll
M llvm/test/CodeGen/AArch64/bf16-instructions.ll
M llvm/test/CodeGen/AArch64/bf16-select.ll
M llvm/test/CodeGen/AArch64/bf16-shuffle.ll
M llvm/test/CodeGen/AArch64/bf16-v4-instructions.ll
M llvm/test/CodeGen/AArch64/bf16-v8-instructions.ll
M llvm/test/CodeGen/AArch64/bf16-vector-shuffle.ll
M llvm/test/CodeGen/AArch64/bitcast-promote-widen.ll
M llvm/test/CodeGen/AArch64/bitcast.ll
M llvm/test/CodeGen/AArch64/bitfield-insert.ll
M llvm/test/CodeGen/AArch64/bswap.ll
M llvm/test/CodeGen/AArch64/build-one-lane.ll
M llvm/test/CodeGen/AArch64/build-vector-extract.ll
M llvm/test/CodeGen/AArch64/build-vector-two-dup.ll
M llvm/test/CodeGen/AArch64/check-sign-bit-before-extension.ll
M llvm/test/CodeGen/AArch64/cmp-to-cmn.ll
M llvm/test/CodeGen/AArch64/cmpxchg-idioms.ll
M llvm/test/CodeGen/AArch64/combine-andintoload.ll
M llvm/test/CodeGen/AArch64/complex-deinterleaving-f16-add.ll
M llvm/test/CodeGen/AArch64/complex-deinterleaving-f16-mul.ll
M llvm/test/CodeGen/AArch64/complex-deinterleaving-multiuses.ll
M llvm/test/CodeGen/AArch64/complex-deinterleaving-reductions-predicated-scalable.ll
M llvm/test/CodeGen/AArch64/complex-deinterleaving-reductions-scalable.ll
M llvm/test/CodeGen/AArch64/complex-deinterleaving-splat-scalable.ll
M llvm/test/CodeGen/AArch64/complex-deinterleaving-splat.ll
M llvm/test/CodeGen/AArch64/complex-deinterleaving-uniform-cases.ll
M llvm/test/CodeGen/AArch64/concat-vector.ll
M llvm/test/CodeGen/AArch64/concatbinop.ll
M llvm/test/CodeGen/AArch64/cvt-fp-int-fp.ll
M llvm/test/CodeGen/AArch64/dag-numsignbits.ll
M llvm/test/CodeGen/AArch64/dup.ll
M llvm/test/CodeGen/AArch64/duplane-index-patfrags.ll
M llvm/test/CodeGen/AArch64/ext-narrow-index.ll
M llvm/test/CodeGen/AArch64/extbinopload.ll
M llvm/test/CodeGen/AArch64/extract-bits.ll
M llvm/test/CodeGen/AArch64/extract-insert.ll
M llvm/test/CodeGen/AArch64/extract-lowbits.ll
M llvm/test/CodeGen/AArch64/extract-sext-zext.ll
M llvm/test/CodeGen/AArch64/extract-subvec-combine.ll
M llvm/test/CodeGen/AArch64/extract-vector-cmp.ll
M llvm/test/CodeGen/AArch64/extract-vector-elt.ll
M llvm/test/CodeGen/AArch64/f16-instructions.ll
M llvm/test/CodeGen/AArch64/fabs-fp128.ll
M llvm/test/CodeGen/AArch64/fabs.ll
M llvm/test/CodeGen/AArch64/faddp-half.ll
M llvm/test/CodeGen/AArch64/faddp.ll
M llvm/test/CodeGen/AArch64/faddsub.ll
M llvm/test/CodeGen/AArch64/fast-isel-addressing-modes.ll
M llvm/test/CodeGen/AArch64/fast-isel-gep.ll
M llvm/test/CodeGen/AArch64/fast-isel-shift.ll
M llvm/test/CodeGen/AArch64/fcmp.ll
M llvm/test/CodeGen/AArch64/fcopysign-noneon.ll
M llvm/test/CodeGen/AArch64/fcopysign.ll
M llvm/test/CodeGen/AArch64/fcvt.ll
M llvm/test/CodeGen/AArch64/fcvt_combine.ll
M llvm/test/CodeGen/AArch64/fdiv-combine.ll
M llvm/test/CodeGen/AArch64/fdiv.ll
M llvm/test/CodeGen/AArch64/fexplog.ll
M llvm/test/CodeGen/AArch64/fixed-point-conv-vec-pat.ll
M llvm/test/CodeGen/AArch64/fixed-vector-deinterleave.ll
M llvm/test/CodeGen/AArch64/fixed-vector-interleave.ll
M llvm/test/CodeGen/AArch64/fmaximum-legalization.ll
M llvm/test/CodeGen/AArch64/fminimummaximum.ll
M llvm/test/CodeGen/AArch64/fminmax.ll
M llvm/test/CodeGen/AArch64/fmla.ll
M llvm/test/CodeGen/AArch64/fmul.ll
M llvm/test/CodeGen/AArch64/fneg.ll
M llvm/test/CodeGen/AArch64/fold-int-pow2-with-fmul-or-fdiv.ll
M llvm/test/CodeGen/AArch64/fp-conversion-to-tbl.ll
M llvm/test/CodeGen/AArch64/fp-intrinsics-vector.ll
M llvm/test/CodeGen/AArch64/fp-maximumnum-minimumnum.ll
M llvm/test/CodeGen/AArch64/fp16-v8-instructions.ll
M llvm/test/CodeGen/AArch64/fp16-vector-shuffle.ll
M llvm/test/CodeGen/AArch64/fp16_intrinsic_lane.ll
M llvm/test/CodeGen/AArch64/fp8-sve-cvtn.ll
M llvm/test/CodeGen/AArch64/fpclamptosat_vec.ll
M llvm/test/CodeGen/AArch64/fpext.ll
M llvm/test/CodeGen/AArch64/fpmode.ll
M llvm/test/CodeGen/AArch64/fpow.ll
M llvm/test/CodeGen/AArch64/fpowi.ll
M llvm/test/CodeGen/AArch64/fptoi.ll
M llvm/test/CodeGen/AArch64/fptosi-sat-vector.ll
M llvm/test/CodeGen/AArch64/fptoui-sat-vector.ll
M llvm/test/CodeGen/AArch64/fptrunc.ll
M llvm/test/CodeGen/AArch64/freeze.ll
M llvm/test/CodeGen/AArch64/frem-power2.ll
M llvm/test/CodeGen/AArch64/frem.ll
M llvm/test/CodeGen/AArch64/fsincos.ll
M llvm/test/CodeGen/AArch64/fsqrt.ll
M llvm/test/CodeGen/AArch64/funnel-shift.ll
M llvm/test/CodeGen/AArch64/get-active-lane-mask-extract.ll
M llvm/test/CodeGen/AArch64/get_vector_length.ll
M llvm/test/CodeGen/AArch64/half.ll
M llvm/test/CodeGen/AArch64/hoist-and-by-const-from-lshr-in-eqcmp-zero.ll
M llvm/test/CodeGen/AArch64/hoist-and-by-const-from-shl-in-eqcmp-zero.ll
M llvm/test/CodeGen/AArch64/icmp.ll
M llvm/test/CodeGen/AArch64/implicit-def-remat-requires-impdef-check.mir
M llvm/test/CodeGen/AArch64/implicit-def-subreg-to-reg-regression.ll
M llvm/test/CodeGen/AArch64/implicit-def-with-impdef-greedy-assert.mir
M llvm/test/CodeGen/AArch64/insert-extend.ll
M llvm/test/CodeGen/AArch64/insert-subvector.ll
M llvm/test/CodeGen/AArch64/insertextract.ll
M llvm/test/CodeGen/AArch64/insertshuffleload.ll
M llvm/test/CodeGen/AArch64/intrinsic-cttz-elts-sve.ll
M llvm/test/CodeGen/AArch64/intrinsic-vector-match-sve2.ll
M llvm/test/CodeGen/AArch64/itofp-bf16.ll
M llvm/test/CodeGen/AArch64/itofp.ll
M llvm/test/CodeGen/AArch64/ldexp.ll
M llvm/test/CodeGen/AArch64/llrint-conv-fp16.ll
M llvm/test/CodeGen/AArch64/llrint-conv.ll
M llvm/test/CodeGen/AArch64/llround-conv-fp16.ll
M llvm/test/CodeGen/AArch64/llvm.exp10.ll
M llvm/test/CodeGen/AArch64/llvm.frexp.ll
M llvm/test/CodeGen/AArch64/llvm.sincos.ll
M llvm/test/CodeGen/AArch64/load.ll
M llvm/test/CodeGen/AArch64/logic-shift.ll
M llvm/test/CodeGen/AArch64/lrint-conv-fp16.ll
M llvm/test/CodeGen/AArch64/lrint-conv.ll
M llvm/test/CodeGen/AArch64/lround-conv-fp16.ll
M llvm/test/CodeGen/AArch64/lslfast.ll
M llvm/test/CodeGen/AArch64/machine-combiner-copy.ll
M llvm/test/CodeGen/AArch64/machine-licm-sub-loop.ll
M llvm/test/CodeGen/AArch64/memset-inline.ll
M llvm/test/CodeGen/AArch64/memset-vs-memset-inline.ll
M llvm/test/CodeGen/AArch64/misched-detail-resource-booking-01.mir
M llvm/test/CodeGen/AArch64/mla_mls_merge.ll
M llvm/test/CodeGen/AArch64/mul.ll
M llvm/test/CodeGen/AArch64/neon-bitcast.ll
M llvm/test/CodeGen/AArch64/neon-bitwise-instructions.ll
M llvm/test/CodeGen/AArch64/neon-dot-product.ll
M llvm/test/CodeGen/AArch64/neon-extadd-extract.ll
M llvm/test/CodeGen/AArch64/neon-extract.ll
M llvm/test/CodeGen/AArch64/neon-extracttruncate.ll
M llvm/test/CodeGen/AArch64/neon-insert-sve-elt.ll
M llvm/test/CodeGen/AArch64/neon-insextbitcast.ll
M llvm/test/CodeGen/AArch64/neon-luti.ll
M llvm/test/CodeGen/AArch64/neon-partial-reduce-dot-product.ll
M llvm/test/CodeGen/AArch64/neon-perm.ll
M llvm/test/CodeGen/AArch64/neon-reverseshuffle.ll
M llvm/test/CodeGen/AArch64/neon-rshrn.ll
M llvm/test/CodeGen/AArch64/neon-scalar-by-elem-fma.ll
M llvm/test/CodeGen/AArch64/neon-scalarize-histogram.ll
M llvm/test/CodeGen/AArch64/neon-shuffle-vector-tbl.ll
M llvm/test/CodeGen/AArch64/neon-truncstore.ll
M llvm/test/CodeGen/AArch64/neon-vcmla.ll
M llvm/test/CodeGen/AArch64/neon-wide-splat.ll
M llvm/test/CodeGen/AArch64/neon-widen-shuffle.ll
M llvm/test/CodeGen/AArch64/nontemporal-load.ll
M llvm/test/CodeGen/AArch64/nontemporal.ll
M llvm/test/CodeGen/AArch64/phi.ll
M llvm/test/CodeGen/AArch64/popcount.ll
M llvm/test/CodeGen/AArch64/pow.ll
M llvm/test/CodeGen/AArch64/pr-cf624b2.ll
M llvm/test/CodeGen/AArch64/pr58350.ll
M llvm/test/CodeGen/AArch64/pr58431.ll
M llvm/test/CodeGen/AArch64/pr61111.ll
M llvm/test/CodeGen/AArch64/preserve_nonecc_varargs_win64.ll
M llvm/test/CodeGen/AArch64/ptradd.ll
M llvm/test/CodeGen/AArch64/qmovn.ll
M llvm/test/CodeGen/AArch64/rcpc3.ll
M llvm/test/CodeGen/AArch64/reduce-and.ll
M llvm/test/CodeGen/AArch64/reduce-or.ll
M llvm/test/CodeGen/AArch64/reduce-shuffle.ll
M llvm/test/CodeGen/AArch64/reduce-xor.ll
M llvm/test/CodeGen/AArch64/regalloc-last-chance-recolor-with-split.mir
M llvm/test/CodeGen/AArch64/rem.ll
M llvm/test/CodeGen/AArch64/round-fptosi-sat-scalar.ll
M llvm/test/CodeGen/AArch64/select-constant-xor.ll
M llvm/test/CodeGen/AArch64/seqpairspill.mir
M llvm/test/CodeGen/AArch64/setcc_knownbits.ll
M llvm/test/CodeGen/AArch64/sext.ll
M llvm/test/CodeGen/AArch64/shift-amount-mod.ll
M llvm/test/CodeGen/AArch64/shift-by-signext.ll
M llvm/test/CodeGen/AArch64/shift-mod.ll
M llvm/test/CodeGen/AArch64/shift.ll
M llvm/test/CodeGen/AArch64/shift_minsize.ll
M llvm/test/CodeGen/AArch64/shuffle-tbl34.ll
M llvm/test/CodeGen/AArch64/shuffles.ll
M llvm/test/CodeGen/AArch64/shufflevector.ll
M llvm/test/CodeGen/AArch64/sink-and-fold.ll
M llvm/test/CodeGen/AArch64/sme-aarch64-svcount.ll
M llvm/test/CodeGen/AArch64/sme-avoid-coalescing-locally-streaming.ll
M llvm/test/CodeGen/AArch64/sme-intrinsics-loads.ll
M llvm/test/CodeGen/AArch64/sme-intrinsics-stores.ll
M llvm/test/CodeGen/AArch64/sme-pstate-sm-changing-call-disable-coalescing.ll
M llvm/test/CodeGen/AArch64/sme-streaming-body.ll
M llvm/test/CodeGen/AArch64/sme-streaming-compatible-interface.ll
M llvm/test/CodeGen/AArch64/sme2-fp8-intrinsics-cvt.ll
M llvm/test/CodeGen/AArch64/sme2-intrinsics-add-sub-za16.ll
M llvm/test/CodeGen/AArch64/sme2-intrinsics-add.ll
M llvm/test/CodeGen/AArch64/sme2-intrinsics-cvtn.ll
M llvm/test/CodeGen/AArch64/sme2-intrinsics-faminmax.ll
M llvm/test/CodeGen/AArch64/sme2-intrinsics-fmlas.ll
M llvm/test/CodeGen/AArch64/sme2-intrinsics-fp-dots.ll
M llvm/test/CodeGen/AArch64/sme2-intrinsics-fscale.ll
M llvm/test/CodeGen/AArch64/sme2-intrinsics-insert-mova.ll
M llvm/test/CodeGen/AArch64/sme2-intrinsics-luti4.ll
M llvm/test/CodeGen/AArch64/sme2-intrinsics-max.ll
M llvm/test/CodeGen/AArch64/sme2-intrinsics-min.ll
M llvm/test/CodeGen/AArch64/sme2-intrinsics-mlall.ll
M llvm/test/CodeGen/AArch64/sme2-intrinsics-mlals.ll
M llvm/test/CodeGen/AArch64/sme2-intrinsics-rshl.ll
M llvm/test/CodeGen/AArch64/sme2-intrinsics-select-sme-tileslice.ll
M llvm/test/CodeGen/AArch64/sme2-intrinsics-sqdmulh.ll
M llvm/test/CodeGen/AArch64/sme2-intrinsics-sub.ll
M llvm/test/CodeGen/AArch64/sme2-intrinsics-vdot.ll
M llvm/test/CodeGen/AArch64/smul_fix_sat.ll
M llvm/test/CodeGen/AArch64/spill-fold.mir
M llvm/test/CodeGen/AArch64/split-vector-insert.ll
M llvm/test/CodeGen/AArch64/srem-vector-lkk.ll
M llvm/test/CodeGen/AArch64/store.ll
M llvm/test/CodeGen/AArch64/sub.ll
M llvm/test/CodeGen/AArch64/sve-cntp-combine-i32.ll
M llvm/test/CodeGen/AArch64/sve-doublereduct.ll
M llvm/test/CodeGen/AArch64/sve-extract-element.ll
M llvm/test/CodeGen/AArch64/sve-extract-fixed-from-scalable-vector.ll
M llvm/test/CodeGen/AArch64/sve-extract-fixed-vector.ll
M llvm/test/CodeGen/AArch64/sve-extract-scalable-vector.ll
M llvm/test/CodeGen/AArch64/sve-fadda-select.ll
M llvm/test/CodeGen/AArch64/sve-fixed-length-bit-counting.ll
M llvm/test/CodeGen/AArch64/sve-fixed-length-concat.ll
M llvm/test/CodeGen/AArch64/sve-fixed-length-extract-subvector.ll
M llvm/test/CodeGen/AArch64/sve-fixed-length-extract-vector-elt.ll
M llvm/test/CodeGen/AArch64/sve-fixed-length-fp-extend-trunc.ll
M llvm/test/CodeGen/AArch64/sve-fixed-length-fp-reduce.ll
M llvm/test/CodeGen/AArch64/sve-fixed-length-fp-select.ll
M llvm/test/CodeGen/AArch64/sve-fixed-length-fp-to-int.ll
M llvm/test/CodeGen/AArch64/sve-fixed-length-fp128.ll
M llvm/test/CodeGen/AArch64/sve-fixed-length-insert-vector-elt.ll
M llvm/test/CodeGen/AArch64/sve-fixed-length-int-arith.ll
M llvm/test/CodeGen/AArch64/sve-fixed-length-int-div.ll
M llvm/test/CodeGen/AArch64/sve-fixed-length-int-extends.ll
M llvm/test/CodeGen/AArch64/sve-fixed-length-int-minmax.ll
M llvm/test/CodeGen/AArch64/sve-fixed-length-int-mulh.ll
M llvm/test/CodeGen/AArch64/sve-fixed-length-int-reduce.ll
M llvm/test/CodeGen/AArch64/sve-fixed-length-int-rem.ll
M llvm/test/CodeGen/AArch64/sve-fixed-length-int-select.ll
M llvm/test/CodeGen/AArch64/sve-fixed-length-int-to-fp.ll
M llvm/test/CodeGen/AArch64/sve-fixed-length-log-reduce.ll
M llvm/test/CodeGen/AArch64/sve-fixed-length-masked-128bit-loads.ll
M llvm/test/CodeGen/AArch64/sve-fixed-length-masked-loads.ll
M llvm/test/CodeGen/AArch64/sve-fixed-length-no-vscale-range.ll
M llvm/test/CodeGen/AArch64/sve-fixed-length-reshuffle.ll
M llvm/test/CodeGen/AArch64/sve-fixed-length-rev.ll
M llvm/test/CodeGen/AArch64/sve-fixed-length-sdiv-pow2.ll
M llvm/test/CodeGen/AArch64/sve-fixed-length-shuffles.ll
M llvm/test/CodeGen/AArch64/sve-fixed-length-splat-vector.ll
M llvm/test/CodeGen/AArch64/sve-fixed-length-subvector.ll
M llvm/test/CodeGen/AArch64/sve-fixed-length-trunc.ll
M llvm/test/CodeGen/AArch64/sve-fixed-length-vector-shuffle-tbl.ll
M llvm/test/CodeGen/AArch64/sve-fixed-vector-llrint.ll
M llvm/test/CodeGen/AArch64/sve-fixed-vector-lrint.ll
M llvm/test/CodeGen/AArch64/sve-fp-reduce-fadda.ll
M llvm/test/CodeGen/AArch64/sve-fp-reduce.ll
M llvm/test/CodeGen/AArch64/sve-i1-add-reduce.ll
M llvm/test/CodeGen/AArch64/sve-implicit-zero-filling.ll
M llvm/test/CodeGen/AArch64/sve-index-const-step-vector.ll
M llvm/test/CodeGen/AArch64/sve-insert-element.ll
M llvm/test/CodeGen/AArch64/sve-insert-vector.ll
M llvm/test/CodeGen/AArch64/sve-int-reduce.ll
M llvm/test/CodeGen/AArch64/sve-intrinsics-counting-elems-i32.ll
M llvm/test/CodeGen/AArch64/sve-intrinsics-dup-x.ll
M llvm/test/CodeGen/AArch64/sve-intrinsics-fp-reduce.ll
M llvm/test/CodeGen/AArch64/sve-intrinsics-perm-select.ll
M llvm/test/CodeGen/AArch64/sve-intrinsics-reinterpret.ll
M llvm/test/CodeGen/AArch64/sve-intrinsics-shifts.ll
M llvm/test/CodeGen/AArch64/sve-intrinsics-sqdec.ll
M llvm/test/CodeGen/AArch64/sve-intrinsics-sqinc.ll
M llvm/test/CodeGen/AArch64/sve-intrinsics-stN-reg-imm-addr-mode.ll
M llvm/test/CodeGen/AArch64/sve-intrinsics-stN-reg-reg-addr-mode.ll
M llvm/test/CodeGen/AArch64/sve-intrinsics-stores.ll
M llvm/test/CodeGen/AArch64/sve-merging-stores.ll
M llvm/test/CodeGen/AArch64/sve-nontemporal-masked-ldst.ll
M llvm/test/CodeGen/AArch64/sve-pr62151.ll
M llvm/test/CodeGen/AArch64/sve-pred-selectop.ll
M llvm/test/CodeGen/AArch64/sve-select.ll
M llvm/test/CodeGen/AArch64/sve-split-extract-elt.ll
M llvm/test/CodeGen/AArch64/sve-split-fp-reduce.ll
M llvm/test/CodeGen/AArch64/sve-split-int-reduce.ll
M llvm/test/CodeGen/AArch64/sve-stack-frame-layout.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-and-combine.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-bit-counting.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-bitselect.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-build-vector.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-concat.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-ext-loads.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-extract-subvector.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-extract-vector-elt.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fcopysign.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-arith.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-compares.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-extend-trunc.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-fma.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-minmax.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-reduce-fa64.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-reduce.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-rounding.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-select.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-to-int.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-vselect.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-insert-vector-elt.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-arith.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-compares.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-div.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-extends.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-log.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-minmax.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-mla-neon-fa64.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-mul.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-mulh.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-reduce.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-rem.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-select.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-shifts.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-to-fp.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-vselect.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-ld2-alloca.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-limit-duplane.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-loads.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-log-reduce.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-masked-gather-scatter.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-masked-load.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-masked-store.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-permute-rev.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-ptest.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-reductions.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-reshuffle.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-rev.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-sdiv-pow2.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-shuffle.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-splat-vector.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-trunc-stores.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-trunc.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-vector-shuffle.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-test-register-mov.ll
M llvm/test/CodeGen/AArch64/sve-vecreduce-dot.ll
M llvm/test/CodeGen/AArch64/sve-vector-compress.ll
M llvm/test/CodeGen/AArch64/sve-vector-splat.ll
M llvm/test/CodeGen/AArch64/sve-vl-arith.ll
M llvm/test/CodeGen/AArch64/sve2-histcnt.ll
M llvm/test/CodeGen/AArch64/sve2-intrinsics-luti.ll
M llvm/test/CodeGen/AArch64/sve2-intrinsics-perm-tb.ll
M llvm/test/CodeGen/AArch64/sve2p1-intrinsics-bfclamp.ll
M llvm/test/CodeGen/AArch64/sve2p1-intrinsics-fclamp.ll
M llvm/test/CodeGen/AArch64/sve2p1-intrinsics-multivec-stores.ll
M llvm/test/CodeGen/AArch64/sve2p1-intrinsics-sclamp.ll
M llvm/test/CodeGen/AArch64/sve2p1-intrinsics-selx4.ll
M llvm/test/CodeGen/AArch64/sve2p1-intrinsics-stores.ll
M llvm/test/CodeGen/AArch64/sve2p1-intrinsics-uclamp.ll
M llvm/test/CodeGen/AArch64/sve2p1-intrinsics-uzpx4.ll
M llvm/test/CodeGen/AArch64/sve2p1-intrinsics-while-pp.ll
M llvm/test/CodeGen/AArch64/swift-error-unreachable-use.ll
M llvm/test/CodeGen/AArch64/tbl-loops.ll
M llvm/test/CodeGen/AArch64/trunc-to-tbl.ll
M llvm/test/CodeGen/AArch64/uaddlv-vaddlp-combine.ll
M llvm/test/CodeGen/AArch64/umul_fix_sat.ll
M llvm/test/CodeGen/AArch64/urem-vector-lkk.ll
M llvm/test/CodeGen/AArch64/vec-combine-compare-to-bitmask.ll
M llvm/test/CodeGen/AArch64/vec-libcalls.ll
M llvm/test/CodeGen/AArch64/vecreduce-add-legalization.ll
M llvm/test/CodeGen/AArch64/vecreduce-add.ll
M llvm/test/CodeGen/AArch64/vecreduce-and-legalization.ll
M llvm/test/CodeGen/AArch64/vecreduce-bool.ll
M llvm/test/CodeGen/AArch64/vecreduce-fadd-legalization-strict.ll
M llvm/test/CodeGen/AArch64/vecreduce-fadd-legalization.ll
M llvm/test/CodeGen/AArch64/vecreduce-fadd-strict.ll
M llvm/test/CodeGen/AArch64/vecreduce-fadd.ll
M llvm/test/CodeGen/AArch64/vecreduce-fmax-legalization-nan.ll
M llvm/test/CodeGen/AArch64/vecreduce-fmax-legalization.ll
M llvm/test/CodeGen/AArch64/vecreduce-fmaximum.ll
M llvm/test/CodeGen/AArch64/vecreduce-fmin-legalization.ll
M llvm/test/CodeGen/AArch64/vecreduce-fminimum.ll
M llvm/test/CodeGen/AArch64/vecreduce-fmul-legalization-strict.ll
M llvm/test/CodeGen/AArch64/vecreduce-fmul-strict.ll
M llvm/test/CodeGen/AArch64/vecreduce-fmul.ll
M llvm/test/CodeGen/AArch64/vecreduce-umax-legalization.ll
M llvm/test/CodeGen/AArch64/vector-compress.ll
M llvm/test/CodeGen/AArch64/vector-fcopysign.ll
M llvm/test/CodeGen/AArch64/vector-fcvt.ll
M llvm/test/CodeGen/AArch64/vector-llrint.ll
M llvm/test/CodeGen/AArch64/vector-lrint.ll
M llvm/test/CodeGen/AArch64/vldn_shuffle.ll
M llvm/test/CodeGen/AArch64/win64-fpowi.ll
M llvm/test/CodeGen/AArch64/win64_vararg.ll
M llvm/test/CodeGen/AArch64/xtn.ll
M llvm/test/CodeGen/AArch64/zext.ll
Log Message:
-----------
Revert "[AArch64] Enable subreg liveness tracking by default."
This reverts commit 9c319d5bb40785c969d2af76535ca62448dfafa7.
Some issues were discovered with the bootstrap builds, which
seem like they were caused by this commit. I'm reverting to investigate.
Commit: 3f136f7dfb41542c76c1b352544009bffbc399d2
https://github.com/llvm/llvm-project/commit/3f136f7dfb41542c76c1b352544009bffbc399d2
Author: Nirvedh Meshram <96096277+nirvedhmeshram at users.noreply.github.com>
Date: 2024-12-12 (Thu, 12 Dec 2024)
Changed paths:
M mlir/lib/Dialect/Tensor/IR/TensorTilingInterfaceImpl.cpp
Log Message:
-----------
[Tensor] Simplify tenor.pad tiling length calculations. (#119039)
The current calculations calculate ending location of the new length and
then subtract the new offset from that location. It is possible to
directly calculate new length. Along with requiring less operations
(which can matter in dynamic case) this also has the advantage that the
values are upper bounded by length rather than source size which is more
friendly for range analysis. I believe the change is already being
tested by
`test/Dialect/Linalg/subtensor-of-padtensor.mlir` and
`test/Dialect/Linalg/tile-and-fuse-tensors.mlir`
---------
Signed-off-by: Nirvedh <nirvedh at gmail.com>
Commit: d99c9994db5e051dc4b71c7bce6e56f8c9c72c1a
https://github.com/llvm/llvm-project/commit/d99c9994db5e051dc4b71c7bce6e56f8c9c72c1a
Author: Michael Maitland <michaeltmaitland at gmail.com>
Date: 2024-12-12 (Thu, 12 Dec 2024)
Changed paths:
M llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp
M llvm/test/CodeGen/RISCV/rvv/vl-opt-instrs.ll
M llvm/test/CodeGen/RISCV/rvv/vl-opt-op-info.mir
Log Message:
-----------
[RISCV][VLOPT] Add support for mask-register logical instructions and set mask instructions (#112231)
We need to adjust getEMULEqualsEEWDivSEWTimesLMUL to account for the
fact that Log2EEW for mask instructions is 0 but their EMUL is
calculated using Log2EEW=3.
Commit: 2e9bfcadbc25e8056ea8f7011786a835c3307a1b
https://github.com/llvm/llvm-project/commit/2e9bfcadbc25e8056ea8f7011786a835c3307a1b
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-12-12 (Thu, 12 Dec 2024)
Changed paths:
M llvm/lib/Target/RISCV/RISCVGISel.td
Log Message:
-----------
[RISCV] Remove unused SDNodeXForm from RISCVGISel.td. NFC
Leftover from when we tried to make i32 legal.
Commit: 77400103da63118e433cbee1feb20146a9fb782c
https://github.com/llvm/llvm-project/commit/77400103da63118e433cbee1feb20146a9fb782c
Author: Nirvedh Meshram <96096277+nirvedhmeshram at users.noreply.github.com>
Date: 2024-12-12 (Thu, 12 Dec 2024)
Changed paths:
M mlir/lib/Dialect/Tensor/IR/TensorTilingInterfaceImpl.cpp
Log Message:
-----------
NfC fix comment in #119039 (#119727)
Missed commiting clang-fomrat in
[#19903](https://github.com/llvm/llvm-project/pull/119039)
Commit: f7e868fe432da733f30379c01076f5f4c9792501
https://github.com/llvm/llvm-project/commit/f7e868fe432da733f30379c01076f5f4c9792501
Author: Ryosuke Niwa <rniwa at webkit.org>
Date: 2024-12-12 (Thu, 12 Dec 2024)
Changed paths:
M clang/lib/StaticAnalyzer/Checkers/WebKit/ASTUtils.cpp
M clang/test/Analysis/Checkers/WebKit/call-args.cpp
Log Message:
-----------
Fix a bug that CXXConstructExpr wasn't recognized by tryToFindPtrOrigin (#119336)
Prior to this PR, only CXXTemporaryObjectExpr, not CXXConstructExpr was
recognized in tryToFindPtrOrigin.
Commit: 9b14ded131aaff617568f1344a7164ba5520d341
https://github.com/llvm/llvm-project/commit/9b14ded131aaff617568f1344a7164ba5520d341
Author: Kazu Hirata <kazu at google.com>
Date: 2024-12-12 (Thu, 12 Dec 2024)
Changed paths:
M llvm/unittests/ProfileData/MemProfTest.cpp
Log Message:
-----------
[memprof] Use return values from addFrame and addCallStack (NFC) (#119676)
Migrating away from Frame::hash and hashCallStack further encapsulates
how the IDs are calculated.
Note that unit tests are the only places where Frame::hash and
hashCallStack are used. The code proper (i.e. llvm/lib) uses
IndexedMemProfData::{addFrame,addCallStack}; they do not directly use
Frame::hash or hashCallStack.
Commit: 357d00d7c7c81768047e9e9668c6f507c6c24cb3
https://github.com/llvm/llvm-project/commit/357d00d7c7c81768047e9e9668c6f507c6c24cb3
Author: Paul Kirth <paulkirth at google.com>
Date: 2024-12-12 (Thu, 12 Dec 2024)
Changed paths:
M clang/lib/Driver/ToolChains/Clang.cpp
M clang/test/Driver/stack-clash-protection.c
Log Message:
-----------
[clang][Driver] Allow `-fstack-clash-protection` for Fuchsia targets (#119633)
Fuchsia uses guard pages for the stack, similar to Linux
and other targets, which are required for stack-clash-protection.
This patch adds Fuchsia to the list of allowed targets.
Commit: 2db2dc8ab917de54a085776b874e93f4fdfd2e8c
https://github.com/llvm/llvm-project/commit/2db2dc8ab917de54a085776b874e93f4fdfd2e8c
Author: Tim Gymnich <tim at gymni.ch>
Date: 2024-12-12 (Thu, 12 Dec 2024)
Changed paths:
M llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
M llvm/lib/CodeGen/GlobalISel/Utils.cpp
M llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
Log Message:
-----------
[GlobalISel][NFC] Fix LLT Propagation (#119587)
Retain LLT type information by creating new LLTs from the original LLT
instead of only using the original scalar size.
This PR prepares for the [LLT FPInfo
RFC](https://discourse.llvm.org/t/rfc-globalisel-adding-fp-type-information-to-llt/83349/24)
where LLTs will carry additional floating point type information in
addition to the scalar size.
Commit: 52db903888eace2e4053a751c8f058ac7c98b49d
https://github.com/llvm/llvm-project/commit/52db903888eace2e4053a751c8f058ac7c98b49d
Author: Nick Desaulniers <ndesaulniers at google.com>
Date: 2024-12-12 (Thu, 12 Dec 2024)
Changed paths:
M libc/utils/docgen/docgen.py
Log Message:
-----------
[libc][docs] fix typo
Fixes: #119621
Commit: 7ece560a50d09686bb384b309b8b05d8f63111e5
https://github.com/llvm/llvm-project/commit/7ece560a50d09686bb384b309b8b05d8f63111e5
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-12-12 (Thu, 12 Dec 2024)
Changed paths:
M llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
M llvm/test/CodeGen/AArch64/Atomics/aarch64-atomicrmw-lse2.ll
M llvm/test/CodeGen/AArch64/Atomics/aarch64-atomicrmw-lse2_lse128.ll
M llvm/test/CodeGen/AArch64/Atomics/aarch64-atomicrmw-outline_atomics.ll
M llvm/test/CodeGen/AArch64/Atomics/aarch64-atomicrmw-rcpc.ll
M llvm/test/CodeGen/AArch64/Atomics/aarch64-atomicrmw-rcpc3.ll
M llvm/test/CodeGen/AArch64/Atomics/aarch64-atomicrmw-v8_1a.ll
M llvm/test/CodeGen/AArch64/Atomics/aarch64-atomicrmw-v8a.ll
M llvm/test/CodeGen/AArch64/GlobalISel/legalize-cmp.mir
M llvm/test/CodeGen/AArch64/GlobalISel/legalize-threeway-cmp.mir
M llvm/test/CodeGen/AArch64/aarch64-minmaxv.ll
M llvm/test/CodeGen/AArch64/icmp.ll
M llvm/test/CodeGen/AArch64/scmp.ll
M llvm/test/CodeGen/AArch64/ucmp.ll
M llvm/test/CodeGen/AArch64/vecreduce-umax-legalization.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/saddsat.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/ssubsat.ll
M llvm/test/CodeGen/AMDGPU/div_i128.ll
M llvm/test/CodeGen/Mips/GlobalISel/legalizer/icmp.mir
M llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/icmp.ll
M llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-addo-subo-rv32.mir
M llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-icmp-rv32.mir
M llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-icmp-rv64.mir
M llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-sat-rv32.mir
M llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-smax-rv32.mir
M llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-smin-rv32.mir
M llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-umax-rv32.mir
M llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-umin-rv32.mir
M llvm/test/CodeGen/X86/isel-select-cmov.ll
Log Message:
-----------
[GISel] Support narrowing G_ICMP with more than 2 parts. (#119335)
This allows us to support i128 G_ICMP on RV32. I'm not sure how to test
the "left over" part of this as RISC-V always widens to a power of 2
before narrowing.
Commit: 85c91afb85be52399e0fc7f082dd1c99932dffaa
https://github.com/llvm/llvm-project/commit/85c91afb85be52399e0fc7f082dd1c99932dffaa
Author: Nirvedh <nirvedh at gmail.com>
Date: 2024-12-12 (Thu, 12 Dec 2024)
Changed paths:
M mlir/lib/Dialect/Tensor/IR/TensorTilingInterfaceImpl.cpp
Log Message:
-----------
[mlir][tensor] fix typo in pad tiling comment
Commit: 33927744db2a910fe1cdeecf9e074d488de2e787
https://github.com/llvm/llvm-project/commit/33927744db2a910fe1cdeecf9e074d488de2e787
Author: Nirvedh <nirvedh at gmail.com>
Date: 2024-12-12 (Thu, 12 Dec 2024)
Changed paths:
M mlir/lib/Dialect/Tensor/IR/TensorTilingInterfaceImpl.cpp
Log Message:
-----------
[mlir][tensor] fix typo in pad tiling comment
Commit: 6cfad635d5aaa01abb82edc386329d8ed25078e1
https://github.com/llvm/llvm-project/commit/6cfad635d5aaa01abb82edc386329d8ed25078e1
Author: erichkeane <ekeane at nvidia.com>
Date: 2024-12-12 (Thu, 12 Dec 2024)
Changed paths:
M clang/include/clang/Basic/OpenACCKinds.h
M clang/lib/Sema/SemaOpenACC.cpp
M clang/test/AST/ast-print-openacc-data-construct.cpp
M clang/test/SemaOpenACC/combined-construct-if-clause.c
M clang/test/SemaOpenACC/compute-construct-if-clause.c
A clang/test/SemaOpenACC/data-construct-if-ast.cpp
A clang/test/SemaOpenACC/data-construct-if-clause.c
M clang/test/SemaOpenACC/data-construct.cpp
Log Message:
-----------
[OpenACC] Implement 'if' clause sema for 'data' constructs
This is another one that has no additional sema work other than enabling
it, so this patch does just that.
Commit: 58f9c4fc0055821d88869aafd49e0424b1070a79
https://github.com/llvm/llvm-project/commit/58f9c4fc0055821d88869aafd49e0424b1070a79
Author: Krzysztof Parzyszek <Krzysztof.Parzyszek at amd.com>
Date: 2024-12-12 (Thu, 12 Dec 2024)
Changed paths:
M flang/include/flang/Parser/dump-parse-tree.h
M flang/include/flang/Parser/parse-tree.h
M flang/lib/Lower/OpenMP/Clauses.cpp
M flang/lib/Parser/openmp-parsers.cpp
M flang/lib/Parser/unparse.cpp
M flang/lib/Semantics/check-omp-structure.cpp
M flang/lib/Semantics/check-omp-structure.h
M flang/test/Parser/OpenMP/in-reduction-clause.f90
M flang/test/Parser/OpenMP/reduction-modifier.f90
A flang/test/Parser/OpenMP/task-reduction-clause.f90
M flang/test/Preprocessing/directive-contin-with-pp.F90
A flang/test/Semantics/OpenMP/in-reduction.f90
M flang/test/Semantics/OpenMP/symbol08.f90
A flang/test/Semantics/OpenMP/task-reduction.f90
M flang/test/Semantics/OpenMP/taskgroup01.f90
M llvm/include/llvm/Frontend/OpenMP/OMP.td
Log Message:
-----------
[flang][OpenMP] Semantic checks for IN_REDUCTION and TASK_REDUCTION (#118841)
Update parsing of these two clauses and add semantic checks for them.
Simplify some code in IsReductionAllowedForType and
CheckReductionOperator.
Commit: 03cbe42627c7a7940b47cc1a2cda0120bc9c6d5e
https://github.com/llvm/llvm-project/commit/03cbe42627c7a7940b47cc1a2cda0120bc9c6d5e
Author: Krzysztof Parzyszek <Krzysztof.Parzyszek at amd.com>
Date: 2024-12-12 (Thu, 12 Dec 2024)
Changed paths:
M flang/examples/FeatureList/FeatureList.cpp
M flang/include/flang/Parser/dump-parse-tree.h
M flang/include/flang/Parser/parse-tree-visitor.h
M flang/include/flang/Parser/parse-tree.h
M flang/include/flang/Semantics/openmp-modifiers.h
M flang/lib/Lower/OpenMP/Clauses.cpp
M flang/lib/Parser/openmp-parsers.cpp
M flang/lib/Parser/unparse.cpp
M flang/lib/Semantics/check-omp-structure.cpp
M flang/lib/Semantics/openmp-modifiers.cpp
M flang/lib/Semantics/resolve-directives.cpp
A flang/test/Parser/OpenMP/linear-clause.f90
M flang/test/Semantics/OpenMP/clause-validity01.f90
M flang/test/Semantics/OpenMP/linear-clause01.f90
A flang/test/Semantics/OpenMP/linear-clause02.f90
M flang/test/Semantics/OpenMP/linear-iter.f90
M llvm/include/llvm/Frontend/OpenMP/ClauseT.h
M llvm/unittests/Frontend/OpenMPDecompositionTest.cpp
Log Message:
-----------
[flang][OpenMP] Rework LINEAR clause (#119278)
The OmpLinearClause class was a variant of two classes, one for when the
linear modifier was present, and one for when it was absent. These two
classes did not follow the conventions for parse tree nodes, (i.e.
tuple/wrapper/union formats), which necessitated specialization of the
parse tree visitor.
The new form of OmpLinearClause is the standard tuple with a list of
modifiers and an object list. The specialization of parse tree visitor
for it has been removed.
Parsing and unparsing of the new form bears additional complexity due to
syntactical differences between OpenMP 5.2 and prior versions: in OpenMP
5.2 the argument list is post-modified, while in the prior versions, the
step modifier was a post-modifier while the linear modifier had an
unusual syntax of `modifier(list)`.
With this change the LINEAR clause is no different from any other
clauses in terms of its structure and use of modifiers. Modifier
validation and all other checks work the same as with other clauses.
Commit: 2546ae4ed09ff69274c184ae7e98f2aa72e7e7f7
https://github.com/llvm/llvm-project/commit/2546ae4ed09ff69274c184ae7e98f2aa72e7e7f7
Author: Han-Kuan Chen <hankuan.chen at sifive.com>
Date: 2024-12-13 (Fri, 13 Dec 2024)
Changed paths:
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
M llvm/test/Transforms/SLPVectorizer/RISCV/revec.ll
Log Message:
-----------
[SLP][REVEC] Fix the number of elements in the mask of a ShuffleVectorInst is not a power of 2. (#119689)
The following shufflevector should not be vectorized when
slp-vectorize-non-power-of-2 is enabled.
shufflevector <8 x float> %1, <8 x float> poison, <3 x i32> <i32 0, i32
1, i32 2>
shufflevector <8 x float> %1, <8 x float> poison, <3 x i32> <i32 4, i32
5, i32 6>
Commit: 139e69b7bcb05e6ff9db0f373d9180deb341a571
https://github.com/llvm/llvm-project/commit/139e69b7bcb05e6ff9db0f373d9180deb341a571
Author: Slava Zakharin <szakharin at nvidia.com>
Date: 2024-12-12 (Thu, 12 Dec 2024)
Changed paths:
M flang/include/flang/Optimizer/HLFIR/HLFIROps.td
M flang/lib/Optimizer/HLFIR/IR/HLFIROps.cpp
M flang/test/HLFIR/shapeof.fir
Log Message:
-----------
[flang] Simple folding for hlfir.shape_of. (#119649)
This folding makes sure there are no hlfir.shape_of users
of hlfir.elemental - this may enable more InlineElementals matches,
because it is looking for exactly two uses of an hlfir.elemental.
Commit: c047a5b3f6e2295dd74f1e8f17f1a023150b246c
https://github.com/llvm/llvm-project/commit/c047a5b3f6e2295dd74f1e8f17f1a023150b246c
Author: Nick Desaulniers <nickdesaulniers at users.noreply.github.com>
Date: 2024-12-12 (Thu, 12 Dec 2024)
Changed paths:
M libc/docs/headers/assert.rst
M libc/docs/headers/ctype.rst
M libc/docs/headers/errno.rst
M libc/docs/headers/fenv.rst
M libc/docs/headers/float.rst
M libc/docs/headers/inttypes.rst
M libc/docs/headers/locale.rst
M libc/docs/headers/signal.rst
M libc/docs/headers/stdlib.rst
M libc/docs/headers/string.rst
M libc/docs/headers/strings.rst
M libc/docs/headers/threads.rst
M libc/docs/headers/uchar.rst
M libc/docs/headers/wchar.rst
M libc/docs/headers/wctype.rst
M libc/utils/docgen/assert.json
M libc/utils/docgen/ctype.json
M libc/utils/docgen/docgen.py
M libc/utils/docgen/errno.json
M libc/utils/docgen/fenv.json
M libc/utils/docgen/float.json
M libc/utils/docgen/inttypes.json
M libc/utils/docgen/locale.json
M libc/utils/docgen/setjmp.json
M libc/utils/docgen/signal.json
M libc/utils/docgen/stdlib.json
M libc/utils/docgen/string.json
M libc/utils/docgen/strings.json
M libc/utils/docgen/threads.json
M libc/utils/docgen/uchar.json
Log Message:
-----------
[libc][docgen] simplify posix links (#119595)
Usually posix functions have individual doc pages, and each header has its own
list of required macro definitions. Use a simpler key of "in-latest-posix" to
signal that the URL convention can be followed.
Add support for a "removed-in-posix-2008" key which will link to the 2004 docs
for functions like bcmp, bcopy, bzero, index, and rindex from strings.h.
I don't want to add all of these links for pthreads.h, so automating this will
make documenting these go much faster.
Commit: f0f8434afac2d30ac143250377fb6433c68fc0a8
https://github.com/llvm/llvm-project/commit/f0f8434afac2d30ac143250377fb6433c68fc0a8
Author: erichkeane <ekeane at nvidia.com>
Date: 2024-12-12 (Thu, 12 Dec 2024)
Changed paths:
M clang/lib/Sema/SemaOpenACC.cpp
M clang/test/AST/ast-print-openacc-data-construct.cpp
M clang/test/ParserOpenACC/parse-clauses.c
A clang/test/SemaOpenACC/data-construct-async-ast.cpp
A clang/test/SemaOpenACC/data-construct-async-clause.c
M clang/test/SemaOpenACC/data-construct-device_type-clause.c
M clang/test/SemaOpenACC/data-construct.cpp
Log Message:
-----------
[OpenACC] Implement sema for 'async' on 'data' constructs
This also is a clause that doesn't have any special rules, so this patch
enables it and adds tests.
Commit: 4e2a9e50f6dd6760b12838517c7f85a0c9032921
https://github.com/llvm/llvm-project/commit/4e2a9e50f6dd6760b12838517c7f85a0c9032921
Author: Petr Hosek <phosek at google.com>
Date: 2024-12-12 (Thu, 12 Dec 2024)
Changed paths:
M libc/config/baremetal/aarch64/entrypoints.txt
M libc/config/baremetal/arm/entrypoints.txt
M libc/config/baremetal/riscv/entrypoints.txt
M libc/src/__support/CMakeLists.txt
A libc/src/__support/freelist_heap.cpp
M libc/src/stdlib/CMakeLists.txt
M libc/src/stdlib/baremetal/CMakeLists.txt
A libc/src/stdlib/baremetal/aligned_alloc.cpp
A libc/src/stdlib/baremetal/calloc.cpp
A libc/src/stdlib/baremetal/free.cpp
A libc/src/stdlib/baremetal/malloc.cpp
A libc/src/stdlib/baremetal/realloc.cpp
R libc/src/stdlib/freelist_malloc.cpp
M libc/test/src/__support/CMakeLists.txt
M libc/test/src/__support/freelist_heap_test.cpp
R libc/test/src/__support/freelist_malloc_test.cpp
Log Message:
-----------
[libc] Breakup freelist_malloc into separate files (#98784)
This better matches the structure we use for the rest of libc.
Commit: b03470b81485281d9f2bdce5e44cc2cac4220d97
https://github.com/llvm/llvm-project/commit/b03470b81485281d9f2bdce5e44cc2cac4220d97
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-12-12 (Thu, 12 Dec 2024)
Changed paths:
M llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
Log Message:
-----------
[RISCV] Use a switch instead of an if/else chain. NFC
Commit: 33b910cde3b305a49c98c6de88dbc22ced9dea61
https://github.com/llvm/llvm-project/commit/33b910cde3b305a49c98c6de88dbc22ced9dea61
Author: Haojian Wu <hokein.wu at gmail.com>
Date: 2024-12-12 (Thu, 12 Dec 2024)
Changed paths:
M clang/docs/ReleaseNotes.rst
M clang/lib/Sema/CheckExprLifetime.cpp
M clang/test/Sema/Inputs/lifetime-analysis.h
M clang/test/Sema/warn-lifetime-analysis-nocfg.cpp
Log Message:
-----------
[clang] Fix the post-filtering heuristic for GSLPointer. (#114044)
The lifetime analyzer processes GSL pointers:
- when encountering a constructor for a `gsl::pointer`, the analyzer
continues traversing the constructor argument, regardless of whether the
parameter has a `lifetimebound` annotation. This aims to catch cases
where a GSL pointer is constructed from a GSL owner, either directly
(e.g., `FooPointer(FooOwner)`) or through a chain of GSL pointers (e.g.,
`FooPointer(FooPointer(FooOwner))`);
- When a temporary object is reported in the callback, the analyzer has
heuristics to exclude non-owner types, aiming to avoid false positives
(like `FooPointer(FooPointer())`).
In the problematic case (discovered in
https://github.com/llvm/llvm-project/pull/112751#issuecomment-2441055471)
of `return foo.get();`:
- When the analyzer reports the local object `foo`, the `Path` is
`[GslPointerInit, Lifetimebound]`.
- The `Path` goes through
[`pathOnlyHandlesGslPointer`](https://github.com/llvm/llvm-project/blob/main/clang/lib/Sema/CheckExprLifetime.cpp#L1136)
and isn’t filtered out by the [[heuristics]](because `foo` is an owner
type), the analyzer treats it as the `FooPointer(FooOwner())` scenario,
thus triggering a diagnostic.
Filtering out base on the object 'foo' is wrong, because the GSLPointer
is constructed from the return result of the `foo.get()`. The patch
fixes this by teaching the heuristic to use the return result (only
`const GSLOwner&` is considered) of the lifetimebound annotated
function.
Commit: 4e828f8d741ff61317bb1e0b67f22e274632b07a
https://github.com/llvm/llvm-project/commit/4e828f8d741ff61317bb1e0b67f22e274632b07a
Author: Florian Hahn <flo at fhahn.com>
Date: 2024-12-12 (Thu, 12 Dec 2024)
Changed paths:
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
Log Message:
-----------
[VPlan] Perform DT expensive input DT verification earlier (NFC).
After 6c8f41d33674, DT adjustments for the skeleton are applied as VPBBs
are executed. Move input DT verification up before starting to execute
any VPBBs to avoid checking DT while the CFG and DT are in an incomplete
state.
This fixes a number of verification failures with expensive checks
enabled, including
https://lab.llvm.org/buildbot/#/builders/16/builds/10584
Commit: afcb7d4a2eab51977497e43ce6539d2b0ca01071
https://github.com/llvm/llvm-project/commit/afcb7d4a2eab51977497e43ce6539d2b0ca01071
Author: erichkeane <ekeane at nvidia.com>
Date: 2024-12-12 (Thu, 12 Dec 2024)
Changed paths:
M clang/lib/Sema/SemaOpenACC.cpp
M clang/test/AST/ast-print-openacc-data-construct.cpp
M clang/test/ParserOpenACC/parse-clauses.c
M clang/test/SemaOpenACC/data-construct-device_type-clause.c
A clang/test/SemaOpenACC/data-construct-wait-ast.cpp
A clang/test/SemaOpenACC/data-construct-wait-clause.c
M clang/test/SemaOpenACC/data-construct.cpp
Log Message:
-----------
[OpenACC] Implement 'wait' sema for data constructs
This is once again simply enabling this for 'data', 'enter data', and
'exit data' (and ensuring we error for 'host_data'). Implementation is
very simply to enable it rather than emit the not-implemented
diagnostic.
Commit: 463e93b95f0887145b51edb81b770eeb4463abc5
https://github.com/llvm/llvm-project/commit/463e93b95f0887145b51edb81b770eeb4463abc5
Author: choikwa <5455710+choikwa at users.noreply.github.com>
Date: 2024-12-12 (Thu, 12 Dec 2024)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPUCodeGenPrepare.cpp
M llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-idiv.ll
M llvm/test/CodeGen/AMDGPU/bypass-div.ll
M llvm/test/CodeGen/AMDGPU/udiv64.ll
M llvm/test/CodeGen/AMDGPU/urem64.ll
Log Message:
-----------
Reapply [AMDGPU] prevent shrinking udiv/urem if either operand exceeds signed max (#119325)
This reverts commit 254d206ee2a337cb38ba347c896f7c6a14c7f218.
+Added a fix in ExpandDivRem24 to disqualify if DivNumBits exceed 24.
Original commit & msg:
ce6e955ac374f2b86cbbb73b2f32174dffd85f25.
Handle signed and unsigned path differently in getDivNumBits. Using
computeKnownBits, this rejects shrinking unsigned div/rem if operands
exceed signed max since we know NumSignBits will be always 0.
Commit: 71418379574d2df5e435f67c4b8d7591bd2038e9
https://github.com/llvm/llvm-project/commit/71418379574d2df5e435f67c4b8d7591bd2038e9
Author: Valentin Clement (バレンタイン クレメン) <clementval at gmail.com>
Date: 2024-12-12 (Thu, 12 Dec 2024)
Changed paths:
M flang/lib/Semantics/resolve-names.cpp
M flang/test/Semantics/modfile55.cuf
Log Message:
-----------
[flang][cuda] Implicitly add DEVICE attribute in device/global functions (#119743)
Variables in global and device function/subroutine that have no CUDA
Fortran data attribute are implicitly DEVICE.
Commit: 186fac33d08b34be494caa58fe63972f69c6d6ab
https://github.com/llvm/llvm-project/commit/186fac33d08b34be494caa58fe63972f69c6d6ab
Author: jimingham <jingham at apple.com>
Date: 2024-12-12 (Thu, 12 Dec 2024)
Changed paths:
M lldb/include/lldb/Target/StackFrameList.h
M lldb/source/Target/StackFrameList.cpp
M lldb/source/Target/Thread.cpp
M lldb/test/API/api/multithreaded/TestMultithreaded.py
A lldb/test/API/api/multithreaded/deep_stack.cpp
A lldb/test/API/api/multithreaded/test_concurrent_unwind.cpp.template
Log Message:
-----------
Convert the StackFrameList mutex to a shared mutex. (#117252)
In fact, there's only one public API in StackFrameList that changes
the list explicitly. The rest only change the list if you happen to
ask for more frames than lldb has currently fetched and that
always adds frames "behind the user's back". So we were
much more prone to deadlocking than we needed to be.
This patch uses a shared_mutex instead, and when we have to add more
frames (in GetFramesUpTo) we switches to exclusive long enough to add
the frames, then goes back to shared.
Most of the work here was actually getting the stack frame list locking
to not
require a recursive mutex (shared mutexes aren't recursive).
I also added a test that has 5 threads progressively asking for more
frames simultaneously to make sure we get back valid frames and don't
deadlock.
Commit: 5048808859eece3aaa680aaecb4a89dfabe9627b
https://github.com/llvm/llvm-project/commit/5048808859eece3aaa680aaecb4a89dfabe9627b
Author: erichkeane <ekeane at nvidia.com>
Date: 2024-12-12 (Thu, 12 Dec 2024)
Changed paths:
M clang/lib/Sema/SemaOpenACC.cpp
M clang/test/AST/ast-print-openacc-data-construct.cpp
M clang/test/SemaOpenACC/combined-construct-default-ast.cpp
M clang/test/SemaOpenACC/combined-construct-default-clause.c
M clang/test/SemaOpenACC/compute-construct-default-clause.c
M clang/test/SemaOpenACC/data-construct-ast.cpp
A clang/test/SemaOpenACC/data-construct-default-ast.cpp
A clang/test/SemaOpenACC/data-construct-default-clause.c
M clang/test/SemaOpenACC/data-construct-if-ast.cpp
M clang/test/SemaOpenACC/data-construct-if-clause.c
M clang/test/SemaOpenACC/data-construct.cpp
Log Message:
-----------
[OpenACC] Implement 'default' Sema for 'data' clause
No additional rules here beyond enabling it, this patch just enables
'default' and adds tests.
Commit: 9b65b1ef25723fcbb61f1ca25a6abbe678bb1770
https://github.com/llvm/llvm-project/commit/9b65b1ef25723fcbb61f1ca25a6abbe678bb1770
Author: knickish <knickish at gmail.com>
Date: 2024-12-12 (Thu, 12 Dec 2024)
Changed paths:
M llvm/test/MC/Disassembler/M68k/control.txt
Log Message:
-----------
[M68k] update dissassmbly test to require atLeastM68020 for BSR32 (#119758)
Fixes test failure reported in #117371. `BSR32` was previously
(incorrectly) allowed for CPUs <M68020, this test was missed while
updating the rest to fit the new model
Commit: 88bcf7283b35b979ace0c6be32736b13f6b771ae
https://github.com/llvm/llvm-project/commit/88bcf7283b35b979ace0c6be32736b13f6b771ae
Author: Nick Desaulniers <nickdesaulniers at users.noreply.github.com>
Date: 2024-12-12 (Thu, 12 Dec 2024)
Changed paths:
R libc/utils/docgen/arpa/inet.json
A libc/utils/docgen/arpa/inet.yaml
R libc/utils/docgen/assert.json
A libc/utils/docgen/assert.yaml
R libc/utils/docgen/ctype.json
A libc/utils/docgen/ctype.yaml
M libc/utils/docgen/docgen.py
R libc/utils/docgen/errno.json
A libc/utils/docgen/errno.yaml
R libc/utils/docgen/fenv.json
A libc/utils/docgen/fenv.yaml
R libc/utils/docgen/float.json
A libc/utils/docgen/float.yaml
M libc/utils/docgen/header.py
R libc/utils/docgen/inttypes.json
A libc/utils/docgen/inttypes.yaml
R libc/utils/docgen/locale.json
A libc/utils/docgen/locale.yaml
R libc/utils/docgen/setjmp.json
A libc/utils/docgen/setjmp.yaml
R libc/utils/docgen/signal.json
A libc/utils/docgen/signal.yaml
R libc/utils/docgen/stdbit.json
A libc/utils/docgen/stdbit.yaml
R libc/utils/docgen/stdlib.json
A libc/utils/docgen/stdlib.yaml
R libc/utils/docgen/string.json
A libc/utils/docgen/string.yaml
R libc/utils/docgen/strings.json
R libc/utils/docgen/sys/mman.json
A libc/utils/docgen/sys/mman.yaml
R libc/utils/docgen/threads.json
A libc/utils/docgen/threads.yaml
R libc/utils/docgen/uchar.json
A libc/utils/docgen/uchar.yaml
R libc/utils/docgen/wchar.json
A libc/utils/docgen/wchar.yaml
R libc/utils/docgen/wctype.json
A libc/utils/docgen/wctype.yaml
Log Message:
-----------
[libc][docs] move docgen from json to yaml (#119744)
That way it can more easily be integrated into hdrgen.
Commit: 379cc44f56e6f220422ce85d2295833f849086e0
https://github.com/llvm/llvm-project/commit/379cc44f56e6f220422ce85d2295833f849086e0
Author: Petr Hosek <phosek at google.com>
Date: 2024-12-12 (Thu, 12 Dec 2024)
Changed paths:
M libc/config/baremetal/aarch64/entrypoints.txt
M libc/config/baremetal/arm/entrypoints.txt
M libc/config/baremetal/riscv/entrypoints.txt
M libc/src/__support/CMakeLists.txt
R libc/src/__support/freelist_heap.cpp
M libc/src/stdlib/CMakeLists.txt
M libc/src/stdlib/baremetal/CMakeLists.txt
R libc/src/stdlib/baremetal/aligned_alloc.cpp
R libc/src/stdlib/baremetal/calloc.cpp
R libc/src/stdlib/baremetal/free.cpp
R libc/src/stdlib/baremetal/malloc.cpp
R libc/src/stdlib/baremetal/realloc.cpp
A libc/src/stdlib/freelist_malloc.cpp
M libc/test/src/__support/CMakeLists.txt
M libc/test/src/__support/freelist_heap_test.cpp
A libc/test/src/__support/freelist_malloc_test.cpp
Log Message:
-----------
Revert "[libc] Breakup freelist_malloc into separate files" (#119749)
Reverts llvm/llvm-project#98784 which broke libc builders.
Commit: 23f53830e7c8b39e7d64f666d2f6d387e52cd905
https://github.com/llvm/llvm-project/commit/23f53830e7c8b39e7d64f666d2f6d387e52cd905
Author: Petr Hosek <phosek at google.com>
Date: 2024-12-12 (Thu, 12 Dec 2024)
Changed paths:
Log Message:
-----------
[𝘀𝗽𝗿] changes introduced through rebase
Created using spr 1.3.6-beta.1
[skip ci]
Commit: 3191293af041441e16efad12ce0bb257df41d276
https://github.com/llvm/llvm-project/commit/3191293af041441e16efad12ce0bb257df41d276
Author: Peter Collingbourne <pcc at google.com>
Date: 2024-12-12 (Thu, 12 Dec 2024)
Changed paths:
Log Message:
-----------
.
Created using spr 1.3.6-beta.1
Compare: https://github.com/llvm/llvm-project/compare/85d3d3e6fd0e...3191293af041
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