[all-commits] [llvm/llvm-project] d99c99: [RISCV][VLOPT] Add support for mask-register logic...
Michael Maitland via All-commits
all-commits at lists.llvm.org
Thu Dec 12 09:25:15 PST 2024
Branch: refs/heads/main
Home: https://github.com/llvm/llvm-project
Commit: d99c9994db5e051dc4b71c7bce6e56f8c9c72c1a
https://github.com/llvm/llvm-project/commit/d99c9994db5e051dc4b71c7bce6e56f8c9c72c1a
Author: Michael Maitland <michaeltmaitland at gmail.com>
Date: 2024-12-12 (Thu, 12 Dec 2024)
Changed paths:
M llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp
M llvm/test/CodeGen/RISCV/rvv/vl-opt-instrs.ll
M llvm/test/CodeGen/RISCV/rvv/vl-opt-op-info.mir
Log Message:
-----------
[RISCV][VLOPT] Add support for mask-register logical instructions and set mask instructions (#112231)
We need to adjust getEMULEqualsEEWDivSEWTimesLMUL to account for the
fact that Log2EEW for mask instructions is 0 but their EMUL is
calculated using Log2EEW=3.
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