[all-commits] [llvm/llvm-project] 61510b: Revert "[AArch64] Enable subreg liveness tracking ...

[Sander de Smalen via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 61510b51c33464a6bc15e4cf5b1ee07e2e0ec1c9
      https://github.com/llvm/llvm-project/commit/61510b51c33464a6bc15e4cf5b1ee07e2e0ec1c9
  Author: Sander de Smalen <sander.desmalen at arm.com>
  Date:   2024-12-12 (Thu, 12 Dec 2024)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64Subtarget.cpp
    M llvm/test/CodeGen/AArch64/Atomics/aarch64-atomicrmw-lse2_lse128.ll
    M llvm/test/CodeGen/AArch64/Atomics/aarch64-atomicrmw-v8_1a.ll
    M llvm/test/CodeGen/AArch64/Atomics/aarch64_be-atomicrmw-lse2_lse128.ll
    M llvm/test/CodeGen/AArch64/Atomics/aarch64_be-atomicrmw-v8_1a.ll
    M llvm/test/CodeGen/AArch64/GlobalISel/arm64-atomic-128.ll
    M llvm/test/CodeGen/AArch64/GlobalISel/arm64-atomic.ll
    M llvm/test/CodeGen/AArch64/GlobalISel/arm64-pcsections.ll
    M llvm/test/CodeGen/AArch64/GlobalISel/combine-udiv.ll
    M llvm/test/CodeGen/AArch64/GlobalISel/insert-vector-elt-pr63826.ll
    M llvm/test/CodeGen/AArch64/aarch64-addv.ll
    M llvm/test/CodeGen/AArch64/aarch64-be-bv.ll
    M llvm/test/CodeGen/AArch64/aarch64-bf16-dotprod-intrinsics.ll
    M llvm/test/CodeGen/AArch64/aarch64-bif-gen.ll
    M llvm/test/CodeGen/AArch64/aarch64-bit-gen.ll
    M llvm/test/CodeGen/AArch64/aarch64-combine-add-sub-mul.ll
    M llvm/test/CodeGen/AArch64/aarch64-combine-add-zext.ll
    M llvm/test/CodeGen/AArch64/aarch64-dup-ext-scalable.ll
    M llvm/test/CodeGen/AArch64/aarch64-dup-ext.ll
    M llvm/test/CodeGen/AArch64/aarch64-dup-extract-scalable.ll
    M llvm/test/CodeGen/AArch64/aarch64-fold-lslfast.ll
    M llvm/test/CodeGen/AArch64/aarch64-interleaved-access-w-undef.ll
    M llvm/test/CodeGen/AArch64/aarch64-load-ext.ll
    M llvm/test/CodeGen/AArch64/aarch64-matrix-umull-smull.ll
    M llvm/test/CodeGen/AArch64/aarch64-minmaxv.ll
    M llvm/test/CodeGen/AArch64/aarch64-mops-mte.ll
    M llvm/test/CodeGen/AArch64/aarch64-mops.ll
    M llvm/test/CodeGen/AArch64/aarch64-mull-masks.ll
    M llvm/test/CodeGen/AArch64/aarch64-mulv.ll
    M llvm/test/CodeGen/AArch64/aarch64-neon-vector-insert-uaddlv.ll
    M llvm/test/CodeGen/AArch64/aarch64-scalarize-vec-load-ext.ll
    M llvm/test/CodeGen/AArch64/aarch64-sysreg128.ll
    M llvm/test/CodeGen/AArch64/aarch64-wide-shuffle.ll
    M llvm/test/CodeGen/AArch64/abs.ll
    M llvm/test/CodeGen/AArch64/active_lane_mask.ll
    M llvm/test/CodeGen/AArch64/adc.ll
    M llvm/test/CodeGen/AArch64/add-extract.ll
    M llvm/test/CodeGen/AArch64/add.ll
    M llvm/test/CodeGen/AArch64/addimm-mulimm.ll
    M llvm/test/CodeGen/AArch64/addp-shuffle.ll
    M llvm/test/CodeGen/AArch64/addsub_ext.ll
    M llvm/test/CodeGen/AArch64/and-mask-removal.ll
    M llvm/test/CodeGen/AArch64/andorxor.ll
    M llvm/test/CodeGen/AArch64/arm64-abi-varargs.ll
    M llvm/test/CodeGen/AArch64/arm64-addp.ll
    M llvm/test/CodeGen/AArch64/arm64-addr-type-promotion.ll
    M llvm/test/CodeGen/AArch64/arm64-atomic-128.ll
    M llvm/test/CodeGen/AArch64/arm64-bitfield-extract.ll
    M llvm/test/CodeGen/AArch64/arm64-build-vector.ll
    M llvm/test/CodeGen/AArch64/arm64-collect-loh.ll
    M llvm/test/CodeGen/AArch64/arm64-dup.ll
    M llvm/test/CodeGen/AArch64/arm64-ext.ll
    M llvm/test/CodeGen/AArch64/arm64-extract-insert-varidx.ll
    M llvm/test/CodeGen/AArch64/arm64-extract_subvector.ll
    M llvm/test/CodeGen/AArch64/arm64-fcopysign.ll
    M llvm/test/CodeGen/AArch64/arm64-fixed-point-scalar-cvt-dagcombine.ll
    M llvm/test/CodeGen/AArch64/arm64-fmax.ll
    M llvm/test/CodeGen/AArch64/arm64-fp128.ll
    M llvm/test/CodeGen/AArch64/arm64-indexed-vector-ldst.ll
    M llvm/test/CodeGen/AArch64/arm64-instruction-mix-remarks.ll
    M llvm/test/CodeGen/AArch64/arm64-ld1.ll
    M llvm/test/CodeGen/AArch64/arm64-ldxr-stxr.ll
    M llvm/test/CodeGen/AArch64/arm64-mul.ll
    M llvm/test/CodeGen/AArch64/arm64-neon-2velem-high.ll
    M llvm/test/CodeGen/AArch64/arm64-neon-2velem.ll
    M llvm/test/CodeGen/AArch64/arm64-neon-3vdiff.ll
    M llvm/test/CodeGen/AArch64/arm64-neon-add-pairwise.ll
    M llvm/test/CodeGen/AArch64/arm64-neon-copy.ll
    M llvm/test/CodeGen/AArch64/arm64-neon-copyPhysReg-tuple.ll
    M llvm/test/CodeGen/AArch64/arm64-neon-mul-div.ll
    M llvm/test/CodeGen/AArch64/arm64-neon-scalar-by-elem-mul.ll
    M llvm/test/CodeGen/AArch64/arm64-neon-select_cc.ll
    M llvm/test/CodeGen/AArch64/arm64-neon-simd-ldst-one.ll
    M llvm/test/CodeGen/AArch64/arm64-neon-simd-shift.ll
    M llvm/test/CodeGen/AArch64/arm64-neon-simd-vget.ll
    M llvm/test/CodeGen/AArch64/arm64-neon-v1i1-setcc.ll
    M llvm/test/CodeGen/AArch64/arm64-neon-v8.1a.ll
    M llvm/test/CodeGen/AArch64/arm64-nvcast.ll
    M llvm/test/CodeGen/AArch64/arm64-popcnt.ll
    M llvm/test/CodeGen/AArch64/arm64-rev.ll
    M llvm/test/CodeGen/AArch64/arm64-shifted-sext.ll
    M llvm/test/CodeGen/AArch64/arm64-shrink-wrapping.ll
    M llvm/test/CodeGen/AArch64/arm64-stp.ll
    M llvm/test/CodeGen/AArch64/arm64-subvector-extend.ll
    M llvm/test/CodeGen/AArch64/arm64-tbl.ll
    M llvm/test/CodeGen/AArch64/arm64-vadd.ll
    M llvm/test/CodeGen/AArch64/arm64-vaddv.ll
    M llvm/test/CodeGen/AArch64/arm64-vcvt_f.ll
    M llvm/test/CodeGen/AArch64/arm64-vector-insertion.ll
    M llvm/test/CodeGen/AArch64/arm64-vmul.ll
    M llvm/test/CodeGen/AArch64/arm64-zip.ll
    M llvm/test/CodeGen/AArch64/arm64_32-addrs.ll
    M llvm/test/CodeGen/AArch64/arm64ec-entry-thunks.ll
    M llvm/test/CodeGen/AArch64/arm64ec-exit-thunks.ll
    M llvm/test/CodeGen/AArch64/atomic-ops-lse.ll
    M llvm/test/CodeGen/AArch64/atomic-ops-msvc.ll
    M llvm/test/CodeGen/AArch64/atomic-ops.ll
    M llvm/test/CodeGen/AArch64/atomicrmw-fadd.ll
    M llvm/test/CodeGen/AArch64/atomicrmw-fmax.ll
    M llvm/test/CodeGen/AArch64/atomicrmw-fmin.ll
    M llvm/test/CodeGen/AArch64/atomicrmw-fsub.ll
    M llvm/test/CodeGen/AArch64/atomicrmw-xchg-fp.ll
    M llvm/test/CodeGen/AArch64/bf16-instructions.ll
    M llvm/test/CodeGen/AArch64/bf16-select.ll
    M llvm/test/CodeGen/AArch64/bf16-shuffle.ll
    M llvm/test/CodeGen/AArch64/bf16-v4-instructions.ll
    M llvm/test/CodeGen/AArch64/bf16-v8-instructions.ll
    M llvm/test/CodeGen/AArch64/bf16-vector-shuffle.ll
    M llvm/test/CodeGen/AArch64/bitcast-promote-widen.ll
    M llvm/test/CodeGen/AArch64/bitcast.ll
    M llvm/test/CodeGen/AArch64/bitfield-insert.ll
    M llvm/test/CodeGen/AArch64/bswap.ll
    M llvm/test/CodeGen/AArch64/build-one-lane.ll
    M llvm/test/CodeGen/AArch64/build-vector-extract.ll
    M llvm/test/CodeGen/AArch64/build-vector-two-dup.ll
    M llvm/test/CodeGen/AArch64/check-sign-bit-before-extension.ll
    M llvm/test/CodeGen/AArch64/cmp-to-cmn.ll
    M llvm/test/CodeGen/AArch64/cmpxchg-idioms.ll
    M llvm/test/CodeGen/AArch64/combine-andintoload.ll
    M llvm/test/CodeGen/AArch64/complex-deinterleaving-f16-add.ll
    M llvm/test/CodeGen/AArch64/complex-deinterleaving-f16-mul.ll
    M llvm/test/CodeGen/AArch64/complex-deinterleaving-multiuses.ll
    M llvm/test/CodeGen/AArch64/complex-deinterleaving-reductions-predicated-scalable.ll
    M llvm/test/CodeGen/AArch64/complex-deinterleaving-reductions-scalable.ll
    M llvm/test/CodeGen/AArch64/complex-deinterleaving-splat-scalable.ll
    M llvm/test/CodeGen/AArch64/complex-deinterleaving-splat.ll
    M llvm/test/CodeGen/AArch64/complex-deinterleaving-uniform-cases.ll
    M llvm/test/CodeGen/AArch64/concat-vector.ll
    M llvm/test/CodeGen/AArch64/concatbinop.ll
    M llvm/test/CodeGen/AArch64/cvt-fp-int-fp.ll
    M llvm/test/CodeGen/AArch64/dag-numsignbits.ll
    M llvm/test/CodeGen/AArch64/dup.ll
    M llvm/test/CodeGen/AArch64/duplane-index-patfrags.ll
    M llvm/test/CodeGen/AArch64/ext-narrow-index.ll
    M llvm/test/CodeGen/AArch64/extbinopload.ll
    M llvm/test/CodeGen/AArch64/extract-bits.ll
    M llvm/test/CodeGen/AArch64/extract-insert.ll
    M llvm/test/CodeGen/AArch64/extract-lowbits.ll
    M llvm/test/CodeGen/AArch64/extract-sext-zext.ll
    M llvm/test/CodeGen/AArch64/extract-subvec-combine.ll
    M llvm/test/CodeGen/AArch64/extract-vector-cmp.ll
    M llvm/test/CodeGen/AArch64/extract-vector-elt.ll
    M llvm/test/CodeGen/AArch64/f16-instructions.ll
    M llvm/test/CodeGen/AArch64/fabs-fp128.ll
    M llvm/test/CodeGen/AArch64/fabs.ll
    M llvm/test/CodeGen/AArch64/faddp-half.ll
    M llvm/test/CodeGen/AArch64/faddp.ll
    M llvm/test/CodeGen/AArch64/faddsub.ll
    M llvm/test/CodeGen/AArch64/fast-isel-addressing-modes.ll
    M llvm/test/CodeGen/AArch64/fast-isel-gep.ll
    M llvm/test/CodeGen/AArch64/fast-isel-shift.ll
    M llvm/test/CodeGen/AArch64/fcmp.ll
    M llvm/test/CodeGen/AArch64/fcopysign-noneon.ll
    M llvm/test/CodeGen/AArch64/fcopysign.ll
    M llvm/test/CodeGen/AArch64/fcvt.ll
    M llvm/test/CodeGen/AArch64/fcvt_combine.ll
    M llvm/test/CodeGen/AArch64/fdiv-combine.ll
    M llvm/test/CodeGen/AArch64/fdiv.ll
    M llvm/test/CodeGen/AArch64/fexplog.ll
    M llvm/test/CodeGen/AArch64/fixed-point-conv-vec-pat.ll
    M llvm/test/CodeGen/AArch64/fixed-vector-deinterleave.ll
    M llvm/test/CodeGen/AArch64/fixed-vector-interleave.ll
    M llvm/test/CodeGen/AArch64/fmaximum-legalization.ll
    M llvm/test/CodeGen/AArch64/fminimummaximum.ll
    M llvm/test/CodeGen/AArch64/fminmax.ll
    M llvm/test/CodeGen/AArch64/fmla.ll
    M llvm/test/CodeGen/AArch64/fmul.ll
    M llvm/test/CodeGen/AArch64/fneg.ll
    M llvm/test/CodeGen/AArch64/fold-int-pow2-with-fmul-or-fdiv.ll
    M llvm/test/CodeGen/AArch64/fp-conversion-to-tbl.ll
    M llvm/test/CodeGen/AArch64/fp-intrinsics-vector.ll
    M llvm/test/CodeGen/AArch64/fp-maximumnum-minimumnum.ll
    M llvm/test/CodeGen/AArch64/fp16-v8-instructions.ll
    M llvm/test/CodeGen/AArch64/fp16-vector-shuffle.ll
    M llvm/test/CodeGen/AArch64/fp16_intrinsic_lane.ll
    M llvm/test/CodeGen/AArch64/fp8-sve-cvtn.ll
    M llvm/test/CodeGen/AArch64/fpclamptosat_vec.ll
    M llvm/test/CodeGen/AArch64/fpext.ll
    M llvm/test/CodeGen/AArch64/fpmode.ll
    M llvm/test/CodeGen/AArch64/fpow.ll
    M llvm/test/CodeGen/AArch64/fpowi.ll
    M llvm/test/CodeGen/AArch64/fptoi.ll
    M llvm/test/CodeGen/AArch64/fptosi-sat-vector.ll
    M llvm/test/CodeGen/AArch64/fptoui-sat-vector.ll
    M llvm/test/CodeGen/AArch64/fptrunc.ll
    M llvm/test/CodeGen/AArch64/freeze.ll
    M llvm/test/CodeGen/AArch64/frem-power2.ll
    M llvm/test/CodeGen/AArch64/frem.ll
    M llvm/test/CodeGen/AArch64/fsincos.ll
    M llvm/test/CodeGen/AArch64/fsqrt.ll
    M llvm/test/CodeGen/AArch64/funnel-shift.ll
    M llvm/test/CodeGen/AArch64/get-active-lane-mask-extract.ll
    M llvm/test/CodeGen/AArch64/get_vector_length.ll
    M llvm/test/CodeGen/AArch64/half.ll
    M llvm/test/CodeGen/AArch64/hoist-and-by-const-from-lshr-in-eqcmp-zero.ll
    M llvm/test/CodeGen/AArch64/hoist-and-by-const-from-shl-in-eqcmp-zero.ll
    M llvm/test/CodeGen/AArch64/icmp.ll
    M llvm/test/CodeGen/AArch64/implicit-def-remat-requires-impdef-check.mir
    M llvm/test/CodeGen/AArch64/implicit-def-subreg-to-reg-regression.ll
    M llvm/test/CodeGen/AArch64/implicit-def-with-impdef-greedy-assert.mir
    M llvm/test/CodeGen/AArch64/insert-extend.ll
    M llvm/test/CodeGen/AArch64/insert-subvector.ll
    M llvm/test/CodeGen/AArch64/insertextract.ll
    M llvm/test/CodeGen/AArch64/insertshuffleload.ll
    M llvm/test/CodeGen/AArch64/intrinsic-cttz-elts-sve.ll
    M llvm/test/CodeGen/AArch64/intrinsic-vector-match-sve2.ll
    M llvm/test/CodeGen/AArch64/itofp-bf16.ll
    M llvm/test/CodeGen/AArch64/itofp.ll
    M llvm/test/CodeGen/AArch64/ldexp.ll
    M llvm/test/CodeGen/AArch64/llrint-conv-fp16.ll
    M llvm/test/CodeGen/AArch64/llrint-conv.ll
    M llvm/test/CodeGen/AArch64/llround-conv-fp16.ll
    M llvm/test/CodeGen/AArch64/llvm.exp10.ll
    M llvm/test/CodeGen/AArch64/llvm.frexp.ll
    M llvm/test/CodeGen/AArch64/llvm.sincos.ll
    M llvm/test/CodeGen/AArch64/load.ll
    M llvm/test/CodeGen/AArch64/logic-shift.ll
    M llvm/test/CodeGen/AArch64/lrint-conv-fp16.ll
    M llvm/test/CodeGen/AArch64/lrint-conv.ll
    M llvm/test/CodeGen/AArch64/lround-conv-fp16.ll
    M llvm/test/CodeGen/AArch64/lslfast.ll
    M llvm/test/CodeGen/AArch64/machine-combiner-copy.ll
    M llvm/test/CodeGen/AArch64/machine-licm-sub-loop.ll
    M llvm/test/CodeGen/AArch64/memset-inline.ll
    M llvm/test/CodeGen/AArch64/memset-vs-memset-inline.ll
    M llvm/test/CodeGen/AArch64/misched-detail-resource-booking-01.mir
    M llvm/test/CodeGen/AArch64/mla_mls_merge.ll
    M llvm/test/CodeGen/AArch64/mul.ll
    M llvm/test/CodeGen/AArch64/neon-bitcast.ll
    M llvm/test/CodeGen/AArch64/neon-bitwise-instructions.ll
    M llvm/test/CodeGen/AArch64/neon-dot-product.ll
    M llvm/test/CodeGen/AArch64/neon-extadd-extract.ll
    M llvm/test/CodeGen/AArch64/neon-extract.ll
    M llvm/test/CodeGen/AArch64/neon-extracttruncate.ll
    M llvm/test/CodeGen/AArch64/neon-insert-sve-elt.ll
    M llvm/test/CodeGen/AArch64/neon-insextbitcast.ll
    M llvm/test/CodeGen/AArch64/neon-luti.ll
    M llvm/test/CodeGen/AArch64/neon-partial-reduce-dot-product.ll
    M llvm/test/CodeGen/AArch64/neon-perm.ll
    M llvm/test/CodeGen/AArch64/neon-reverseshuffle.ll
    M llvm/test/CodeGen/AArch64/neon-rshrn.ll
    M llvm/test/CodeGen/AArch64/neon-scalar-by-elem-fma.ll
    M llvm/test/CodeGen/AArch64/neon-scalarize-histogram.ll
    M llvm/test/CodeGen/AArch64/neon-shuffle-vector-tbl.ll
    M llvm/test/CodeGen/AArch64/neon-truncstore.ll
    M llvm/test/CodeGen/AArch64/neon-vcmla.ll
    M llvm/test/CodeGen/AArch64/neon-wide-splat.ll
    M llvm/test/CodeGen/AArch64/neon-widen-shuffle.ll
    M llvm/test/CodeGen/AArch64/nontemporal-load.ll
    M llvm/test/CodeGen/AArch64/nontemporal.ll
    M llvm/test/CodeGen/AArch64/phi.ll
    M llvm/test/CodeGen/AArch64/popcount.ll
    M llvm/test/CodeGen/AArch64/pow.ll
    M llvm/test/CodeGen/AArch64/pr-cf624b2.ll
    M llvm/test/CodeGen/AArch64/pr58350.ll
    M llvm/test/CodeGen/AArch64/pr58431.ll
    M llvm/test/CodeGen/AArch64/pr61111.ll
    M llvm/test/CodeGen/AArch64/preserve_nonecc_varargs_win64.ll
    M llvm/test/CodeGen/AArch64/ptradd.ll
    M llvm/test/CodeGen/AArch64/qmovn.ll
    M llvm/test/CodeGen/AArch64/rcpc3.ll
    M llvm/test/CodeGen/AArch64/reduce-and.ll
    M llvm/test/CodeGen/AArch64/reduce-or.ll
    M llvm/test/CodeGen/AArch64/reduce-shuffle.ll
    M llvm/test/CodeGen/AArch64/reduce-xor.ll
    M llvm/test/CodeGen/AArch64/regalloc-last-chance-recolor-with-split.mir
    M llvm/test/CodeGen/AArch64/rem.ll
    M llvm/test/CodeGen/AArch64/round-fptosi-sat-scalar.ll
    M llvm/test/CodeGen/AArch64/select-constant-xor.ll
    M llvm/test/CodeGen/AArch64/seqpairspill.mir
    M llvm/test/CodeGen/AArch64/setcc_knownbits.ll
    M llvm/test/CodeGen/AArch64/sext.ll
    M llvm/test/CodeGen/AArch64/shift-amount-mod.ll
    M llvm/test/CodeGen/AArch64/shift-by-signext.ll
    M llvm/test/CodeGen/AArch64/shift-mod.ll
    M llvm/test/CodeGen/AArch64/shift.ll
    M llvm/test/CodeGen/AArch64/shift_minsize.ll
    M llvm/test/CodeGen/AArch64/shuffle-tbl34.ll
    M llvm/test/CodeGen/AArch64/shuffles.ll
    M llvm/test/CodeGen/AArch64/shufflevector.ll
    M llvm/test/CodeGen/AArch64/sink-and-fold.ll
    M llvm/test/CodeGen/AArch64/sme-aarch64-svcount.ll
    M llvm/test/CodeGen/AArch64/sme-avoid-coalescing-locally-streaming.ll
    M llvm/test/CodeGen/AArch64/sme-intrinsics-loads.ll
    M llvm/test/CodeGen/AArch64/sme-intrinsics-stores.ll
    M llvm/test/CodeGen/AArch64/sme-pstate-sm-changing-call-disable-coalescing.ll
    M llvm/test/CodeGen/AArch64/sme-streaming-body.ll
    M llvm/test/CodeGen/AArch64/sme-streaming-compatible-interface.ll
    M llvm/test/CodeGen/AArch64/sme2-fp8-intrinsics-cvt.ll
    M llvm/test/CodeGen/AArch64/sme2-intrinsics-add-sub-za16.ll
    M llvm/test/CodeGen/AArch64/sme2-intrinsics-add.ll
    M llvm/test/CodeGen/AArch64/sme2-intrinsics-cvtn.ll
    M llvm/test/CodeGen/AArch64/sme2-intrinsics-faminmax.ll
    M llvm/test/CodeGen/AArch64/sme2-intrinsics-fmlas.ll
    M llvm/test/CodeGen/AArch64/sme2-intrinsics-fp-dots.ll
    M llvm/test/CodeGen/AArch64/sme2-intrinsics-fscale.ll
    M llvm/test/CodeGen/AArch64/sme2-intrinsics-insert-mova.ll
    M llvm/test/CodeGen/AArch64/sme2-intrinsics-luti4.ll
    M llvm/test/CodeGen/AArch64/sme2-intrinsics-max.ll
    M llvm/test/CodeGen/AArch64/sme2-intrinsics-min.ll
    M llvm/test/CodeGen/AArch64/sme2-intrinsics-mlall.ll
    M llvm/test/CodeGen/AArch64/sme2-intrinsics-mlals.ll
    M llvm/test/CodeGen/AArch64/sme2-intrinsics-rshl.ll
    M llvm/test/CodeGen/AArch64/sme2-intrinsics-select-sme-tileslice.ll
    M llvm/test/CodeGen/AArch64/sme2-intrinsics-sqdmulh.ll
    M llvm/test/CodeGen/AArch64/sme2-intrinsics-sub.ll
    M llvm/test/CodeGen/AArch64/sme2-intrinsics-vdot.ll
    M llvm/test/CodeGen/AArch64/smul_fix_sat.ll
    M llvm/test/CodeGen/AArch64/spill-fold.mir
    M llvm/test/CodeGen/AArch64/split-vector-insert.ll
    M llvm/test/CodeGen/AArch64/srem-vector-lkk.ll
    M llvm/test/CodeGen/AArch64/store.ll
    M llvm/test/CodeGen/AArch64/sub.ll
    M llvm/test/CodeGen/AArch64/sve-cntp-combine-i32.ll
    M llvm/test/CodeGen/AArch64/sve-doublereduct.ll
    M llvm/test/CodeGen/AArch64/sve-extract-element.ll
    M llvm/test/CodeGen/AArch64/sve-extract-fixed-from-scalable-vector.ll
    M llvm/test/CodeGen/AArch64/sve-extract-fixed-vector.ll
    M llvm/test/CodeGen/AArch64/sve-extract-scalable-vector.ll
    M llvm/test/CodeGen/AArch64/sve-fadda-select.ll
    M llvm/test/CodeGen/AArch64/sve-fixed-length-bit-counting.ll
    M llvm/test/CodeGen/AArch64/sve-fixed-length-concat.ll
    M llvm/test/CodeGen/AArch64/sve-fixed-length-extract-subvector.ll
    M llvm/test/CodeGen/AArch64/sve-fixed-length-extract-vector-elt.ll
    M llvm/test/CodeGen/AArch64/sve-fixed-length-fp-extend-trunc.ll
    M llvm/test/CodeGen/AArch64/sve-fixed-length-fp-reduce.ll
    M llvm/test/CodeGen/AArch64/sve-fixed-length-fp-select.ll
    M llvm/test/CodeGen/AArch64/sve-fixed-length-fp-to-int.ll
    M llvm/test/CodeGen/AArch64/sve-fixed-length-fp128.ll
    M llvm/test/CodeGen/AArch64/sve-fixed-length-insert-vector-elt.ll
    M llvm/test/CodeGen/AArch64/sve-fixed-length-int-arith.ll
    M llvm/test/CodeGen/AArch64/sve-fixed-length-int-div.ll
    M llvm/test/CodeGen/AArch64/sve-fixed-length-int-extends.ll
    M llvm/test/CodeGen/AArch64/sve-fixed-length-int-minmax.ll
    M llvm/test/CodeGen/AArch64/sve-fixed-length-int-mulh.ll
    M llvm/test/CodeGen/AArch64/sve-fixed-length-int-reduce.ll
    M llvm/test/CodeGen/AArch64/sve-fixed-length-int-rem.ll
    M llvm/test/CodeGen/AArch64/sve-fixed-length-int-select.ll
    M llvm/test/CodeGen/AArch64/sve-fixed-length-int-to-fp.ll
    M llvm/test/CodeGen/AArch64/sve-fixed-length-log-reduce.ll
    M llvm/test/CodeGen/AArch64/sve-fixed-length-masked-128bit-loads.ll
    M llvm/test/CodeGen/AArch64/sve-fixed-length-masked-loads.ll
    M llvm/test/CodeGen/AArch64/sve-fixed-length-no-vscale-range.ll
    M llvm/test/CodeGen/AArch64/sve-fixed-length-reshuffle.ll
    M llvm/test/CodeGen/AArch64/sve-fixed-length-rev.ll
    M llvm/test/CodeGen/AArch64/sve-fixed-length-sdiv-pow2.ll
    M llvm/test/CodeGen/AArch64/sve-fixed-length-shuffles.ll
    M llvm/test/CodeGen/AArch64/sve-fixed-length-splat-vector.ll
    M llvm/test/CodeGen/AArch64/sve-fixed-length-subvector.ll
    M llvm/test/CodeGen/AArch64/sve-fixed-length-trunc.ll
    M llvm/test/CodeGen/AArch64/sve-fixed-length-vector-shuffle-tbl.ll
    M llvm/test/CodeGen/AArch64/sve-fixed-vector-llrint.ll
    M llvm/test/CodeGen/AArch64/sve-fixed-vector-lrint.ll
    M llvm/test/CodeGen/AArch64/sve-fp-reduce-fadda.ll
    M llvm/test/CodeGen/AArch64/sve-fp-reduce.ll
    M llvm/test/CodeGen/AArch64/sve-i1-add-reduce.ll
    M llvm/test/CodeGen/AArch64/sve-implicit-zero-filling.ll
    M llvm/test/CodeGen/AArch64/sve-index-const-step-vector.ll
    M llvm/test/CodeGen/AArch64/sve-insert-element.ll
    M llvm/test/CodeGen/AArch64/sve-insert-vector.ll
    M llvm/test/CodeGen/AArch64/sve-int-reduce.ll
    M llvm/test/CodeGen/AArch64/sve-intrinsics-counting-elems-i32.ll
    M llvm/test/CodeGen/AArch64/sve-intrinsics-dup-x.ll
    M llvm/test/CodeGen/AArch64/sve-intrinsics-fp-reduce.ll
    M llvm/test/CodeGen/AArch64/sve-intrinsics-perm-select.ll
    M llvm/test/CodeGen/AArch64/sve-intrinsics-reinterpret.ll
    M llvm/test/CodeGen/AArch64/sve-intrinsics-shifts.ll
    M llvm/test/CodeGen/AArch64/sve-intrinsics-sqdec.ll
    M llvm/test/CodeGen/AArch64/sve-intrinsics-sqinc.ll
    M llvm/test/CodeGen/AArch64/sve-intrinsics-stN-reg-imm-addr-mode.ll
    M llvm/test/CodeGen/AArch64/sve-intrinsics-stN-reg-reg-addr-mode.ll
    M llvm/test/CodeGen/AArch64/sve-intrinsics-stores.ll
    M llvm/test/CodeGen/AArch64/sve-merging-stores.ll
    M llvm/test/CodeGen/AArch64/sve-nontemporal-masked-ldst.ll
    M llvm/test/CodeGen/AArch64/sve-pr62151.ll
    M llvm/test/CodeGen/AArch64/sve-pred-selectop.ll
    M llvm/test/CodeGen/AArch64/sve-select.ll
    M llvm/test/CodeGen/AArch64/sve-split-extract-elt.ll
    M llvm/test/CodeGen/AArch64/sve-split-fp-reduce.ll
    M llvm/test/CodeGen/AArch64/sve-split-int-reduce.ll
    M llvm/test/CodeGen/AArch64/sve-stack-frame-layout.ll
    M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-and-combine.ll
    M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-bit-counting.ll
    M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-bitselect.ll
    M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-build-vector.ll
    M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-concat.ll
    M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-ext-loads.ll
    M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-extract-subvector.ll
    M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-extract-vector-elt.ll
    M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fcopysign.ll
    M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-arith.ll
    M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-compares.ll
    M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-extend-trunc.ll
    M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-fma.ll
    M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-minmax.ll
    M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-reduce-fa64.ll
    M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-reduce.ll
    M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-rounding.ll
    M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-select.ll
    M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-to-int.ll
    M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-vselect.ll
    M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-insert-vector-elt.ll
    M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-arith.ll
    M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-compares.ll
    M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-div.ll
    M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-extends.ll
    M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-log.ll
    M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-minmax.ll
    M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-mla-neon-fa64.ll
    M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-mul.ll
    M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-mulh.ll
    M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-reduce.ll
    M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-rem.ll
    M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-select.ll
    M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-shifts.ll
    M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-to-fp.ll
    M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-vselect.ll
    M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-ld2-alloca.ll
    M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-limit-duplane.ll
    M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-loads.ll
    M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-log-reduce.ll
    M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-masked-gather-scatter.ll
    M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-masked-load.ll
    M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-masked-store.ll
    M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-permute-rev.ll
    M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-ptest.ll
    M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-reductions.ll
    M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-reshuffle.ll
    M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-rev.ll
    M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-sdiv-pow2.ll
    M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-shuffle.ll
    M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-splat-vector.ll
    M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-trunc-stores.ll
    M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-trunc.ll
    M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-vector-shuffle.ll
    M llvm/test/CodeGen/AArch64/sve-streaming-mode-test-register-mov.ll
    M llvm/test/CodeGen/AArch64/sve-vecreduce-dot.ll
    M llvm/test/CodeGen/AArch64/sve-vector-compress.ll
    M llvm/test/CodeGen/AArch64/sve-vector-splat.ll
    M llvm/test/CodeGen/AArch64/sve-vl-arith.ll
    M llvm/test/CodeGen/AArch64/sve2-histcnt.ll
    M llvm/test/CodeGen/AArch64/sve2-intrinsics-luti.ll
    M llvm/test/CodeGen/AArch64/sve2-intrinsics-perm-tb.ll
    M llvm/test/CodeGen/AArch64/sve2p1-intrinsics-bfclamp.ll
    M llvm/test/CodeGen/AArch64/sve2p1-intrinsics-fclamp.ll
    M llvm/test/CodeGen/AArch64/sve2p1-intrinsics-multivec-stores.ll
    M llvm/test/CodeGen/AArch64/sve2p1-intrinsics-sclamp.ll
    M llvm/test/CodeGen/AArch64/sve2p1-intrinsics-selx4.ll
    M llvm/test/CodeGen/AArch64/sve2p1-intrinsics-stores.ll
    M llvm/test/CodeGen/AArch64/sve2p1-intrinsics-uclamp.ll
    M llvm/test/CodeGen/AArch64/sve2p1-intrinsics-uzpx4.ll
    M llvm/test/CodeGen/AArch64/sve2p1-intrinsics-while-pp.ll
    M llvm/test/CodeGen/AArch64/swift-error-unreachable-use.ll
    M llvm/test/CodeGen/AArch64/tbl-loops.ll
    M llvm/test/CodeGen/AArch64/trunc-to-tbl.ll
    M llvm/test/CodeGen/AArch64/uaddlv-vaddlp-combine.ll
    M llvm/test/CodeGen/AArch64/umul_fix_sat.ll
    M llvm/test/CodeGen/AArch64/urem-vector-lkk.ll
    M llvm/test/CodeGen/AArch64/vec-combine-compare-to-bitmask.ll
    M llvm/test/CodeGen/AArch64/vec-libcalls.ll
    M llvm/test/CodeGen/AArch64/vecreduce-add-legalization.ll
    M llvm/test/CodeGen/AArch64/vecreduce-add.ll
    M llvm/test/CodeGen/AArch64/vecreduce-and-legalization.ll
    M llvm/test/CodeGen/AArch64/vecreduce-bool.ll
    M llvm/test/CodeGen/AArch64/vecreduce-fadd-legalization-strict.ll
    M llvm/test/CodeGen/AArch64/vecreduce-fadd-legalization.ll
    M llvm/test/CodeGen/AArch64/vecreduce-fadd-strict.ll
    M llvm/test/CodeGen/AArch64/vecreduce-fadd.ll
    M llvm/test/CodeGen/AArch64/vecreduce-fmax-legalization-nan.ll
    M llvm/test/CodeGen/AArch64/vecreduce-fmax-legalization.ll
    M llvm/test/CodeGen/AArch64/vecreduce-fmaximum.ll
    M llvm/test/CodeGen/AArch64/vecreduce-fmin-legalization.ll
    M llvm/test/CodeGen/AArch64/vecreduce-fminimum.ll
    M llvm/test/CodeGen/AArch64/vecreduce-fmul-legalization-strict.ll
    M llvm/test/CodeGen/AArch64/vecreduce-fmul-strict.ll
    M llvm/test/CodeGen/AArch64/vecreduce-fmul.ll
    M llvm/test/CodeGen/AArch64/vecreduce-umax-legalization.ll
    M llvm/test/CodeGen/AArch64/vector-compress.ll
    M llvm/test/CodeGen/AArch64/vector-fcopysign.ll
    M llvm/test/CodeGen/AArch64/vector-fcvt.ll
    M llvm/test/CodeGen/AArch64/vector-llrint.ll
    M llvm/test/CodeGen/AArch64/vector-lrint.ll
    M llvm/test/CodeGen/AArch64/vldn_shuffle.ll
    M llvm/test/CodeGen/AArch64/win64-fpowi.ll
    M llvm/test/CodeGen/AArch64/win64_vararg.ll
    M llvm/test/CodeGen/AArch64/xtn.ll
    M llvm/test/CodeGen/AArch64/zext.ll

  Log Message:
  -----------
  Revert "[AArch64] Enable subreg liveness tracking by default."

This reverts commit 9c319d5bb40785c969d2af76535ca62448dfafa7.

Some issues were discovered with the bootstrap builds, which
seem like they were caused by this commit. I'm reverting to investigate.



To unsubscribe from these emails, change your notification settings at https://github.com/llvm/llvm-project/settings/notifications