[all-commits] [llvm/llvm-project] 6c8f41: [VPlan] Hook IR blocks into VPlan during skeleton ...

[Florian Hahn via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 6c8f41d3367476d35ac730abf9f980291737193b
      https://github.com/llvm/llvm-project/commit/6c8f41d3367476d35ac730abf9f980291737193b
  Author: Florian Hahn <flo at fhahn.com>
  Date:   2024-12-12 (Thu, 12 Dec 2024)

  Changed paths:
    M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
    M llvm/lib/Transforms/Vectorize/VPlan.cpp
    M llvm/lib/Transforms/Vectorize/VPlan.h
    M llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
    M llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
    M llvm/lib/Transforms/Vectorize/VPlanUnroll.cpp
    M llvm/lib/Transforms/Vectorize/VPlanUtils.cpp
    M llvm/lib/Transforms/Vectorize/VPlanVerifier.cpp
    M llvm/test/Transforms/LoopVectorize/AArch64/sve-tail-folding-forced.ll
    M llvm/test/Transforms/LoopVectorize/AArch64/sve-widen-gep.ll
    M llvm/test/Transforms/LoopVectorize/AArch64/sve2-histcnt-vplan.ll
    M llvm/test/Transforms/LoopVectorize/AArch64/synthesize-mask-for-call.ll
    M llvm/test/Transforms/LoopVectorize/AArch64/widen-call-with-intrinsic-or-libfunc.ll
    M llvm/test/Transforms/LoopVectorize/PowerPC/vplan-force-tail-with-evl.ll
    M llvm/test/Transforms/LoopVectorize/RISCV/riscv-vector-reverse.ll
    M llvm/test/Transforms/LoopVectorize/RISCV/vplan-vp-intrinsics-reduction.ll
    M llvm/test/Transforms/LoopVectorize/RISCV/vplan-vp-select-intrinsics.ll
    M llvm/test/Transforms/LoopVectorize/first-order-recurrence-chains-vplan.ll
    M llvm/test/Transforms/LoopVectorize/first-order-recurrence-sink-replicate-region.ll
    M llvm/test/Transforms/LoopVectorize/icmp-uniforms.ll
    M llvm/test/Transforms/LoopVectorize/interleave-and-scalarize-only.ll
    M llvm/test/Transforms/LoopVectorize/uncountable-early-exit-vplan.ll
    M llvm/test/Transforms/LoopVectorize/vplan-dot-printing.ll
    M llvm/test/Transforms/LoopVectorize/vplan-iv-transforms.ll
    M llvm/test/Transforms/LoopVectorize/vplan-predicate-switch.ll
    M llvm/test/Transforms/LoopVectorize/vplan-printing-before-execute.ll
    M llvm/test/Transforms/LoopVectorize/vplan-printing-outer-loop.ll
    M llvm/test/Transforms/LoopVectorize/vplan-printing.ll
    M llvm/test/Transforms/LoopVectorize/vplan-sink-scalars-and-merge-vf1.ll
    M llvm/test/Transforms/LoopVectorize/vplan-sink-scalars-and-merge.ll
    M llvm/test/Transforms/LoopVectorize/vplan-unused-interleave-group.ll
    M llvm/test/Transforms/PhaseOrdering/AArch64/hoist-runtime-checks.ll
    M llvm/test/Transforms/PhaseOrdering/X86/hoist-load-of-baseptr.ll
    M llvm/test/Transforms/PhaseOrdering/X86/preserve-access-group.ll
    M llvm/unittests/Transforms/Vectorize/VPlanHCFGTest.cpp
    M llvm/unittests/Transforms/Vectorize/VPlanTest.cpp
    M llvm/unittests/Transforms/Vectorize/VPlanVerifierTest.cpp

  Log Message:
  -----------
  [VPlan] Hook IR blocks into VPlan during skeleton creation (NFC) (#114292)

As a first step to move towards modeling the full skeleton in VPlan,
start by wrapping IR blocks created during legacy skeleton creation in
VPIRBasicBlocks and hook them into the VPlan. This means the skeleton
CFG is represented in VPlan, just before execute. This allows moving
parts of skeleton creation into recipes in the VPBBs gradually.

Note that this allows retiring some manual DT updates, as this will be
handled automatically during VPlan execution.

PR: https://github.com/llvm/llvm-project/pull/114292



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