[all-commits] [llvm/llvm-project] 5ca26d: [AArch64][SME2] Improve register allocation of mul...

[Kerry McLaughlin via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 5ca26d769deedc931ce19b4a68a68c799f8d7564
      https://github.com/llvm/llvm-project/commit/5ca26d769deedc931ce19b4a68a68c799f8d7564
  Author: Kerry McLaughlin <kerry.mclaughlin at arm.com>
  Date:   2024-12-12 (Thu, 12 Dec 2024)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp
    M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
    M llvm/lib/Target/AArch64/AArch64RegisterInfo.cpp
    M llvm/lib/Target/AArch64/AArch64RegisterInfo.h
    M llvm/lib/Target/AArch64/SMEInstrFormats.td
    M llvm/test/CodeGen/AArch64/sme2-intrinsics-int-dots.ll
    M llvm/test/CodeGen/AArch64/sme2-intrinsics-vdot.ll

  Log Message:
  -----------
  [AArch64][SME2] Improve register allocation of multi-vector SME intrinsics (#116399)

The FORM_TRANSPOSED_REG_TUPLE pseudos have been created to
improve register allocation for intrinsics which use strided and
contiguous multi-vector registers, avoiding unnecessary copies.

If the operands of the pseudo are copies where the source register is in
the StridedOrContiguous class, the pseudo is used by
getRegAllocationHints
to suggest a contigious multi-vector register which matches the
subregister
sequence used by the operands.
If the operands do not match this pattern, the pseudos are expanded
to a REG_SEQUENCE.

Patch contains changes by Matthew Devereau.



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