[all-commits] [llvm/llvm-project] 22d26a: [RISCV] Optimize (slli (srli (slli X, C1), C1), C2...

[Piotr Fusik via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 22d26ae3040095c7bfe4e2f1678b9738bf81fd4a
      https://github.com/llvm/llvm-project/commit/22d26ae3040095c7bfe4e2f1678b9738bf81fd4a
  Author: Piotr Fusik <p.fusik at samsung.com>
  Date:   2024-12-12 (Thu, 12 Dec 2024)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
    A llvm/test/CodeGen/RISCV/and-shl.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp2i.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-buildvec.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-gather.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-scatter.ll

  Log Message:
  -----------
  [RISCV] Optimize (slli (srli (slli X, C1), C1), C2) -> (srli (slli X, C1), C1-C2) (#119567)

Masking out most significant bits can be done with shl followed by srl
with same shift amount. If this is followed by a shl, we could instead
srl by a smaller amount of bits.

This transform is already implemented in tablegen for masking out
32 most significant bits.

Emits better code for e.g.

    float *index(float *p, int i)
    {
        return p + (i & (1 << 30) - 1);
    }



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