[all-commits] [llvm/llvm-project] 2b5d43: [𝘀𝗽𝗿] changes introduced through rebase
Prabhuk via All-commits
all-commits at lists.llvm.org
Tue Dec 10 14:56:22 PST 2024
Branch: refs/heads/users/Prabhuk/sprclangcallgraphsection-add-type-id-metadata-to-indirect-call-and-targets-1
Home: https://github.com/llvm/llvm-project
Commit: 2b5d4304633caf8dcebce346184881089efbfad6
https://github.com/llvm/llvm-project/commit/2b5d4304633caf8dcebce346184881089efbfad6
Author: prabhukr <prabhukr at google.com>
Date: 2024-12-10 (Tue, 10 Dec 2024)
Changed paths:
M clang/include/clang/Basic/CodeGenOptions.def
M clang/include/clang/Driver/Options.td
M clang/lib/CodeGen/BackendUtil.cpp
M clang/lib/Driver/ToolChains/Clang.cpp
A clang/test/Driver/call-graph-section.c
M llvm/include/llvm/CodeGen/AsmPrinter.h
M llvm/include/llvm/CodeGen/CommandFlags.h
M llvm/include/llvm/CodeGen/MIRYamlMapping.h
M llvm/include/llvm/CodeGen/MachineFunction.h
M llvm/include/llvm/MC/MCObjectFileInfo.h
M llvm/include/llvm/Target/TargetOptions.h
M llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
M llvm/lib/CodeGen/CommandFlags.cpp
M llvm/lib/CodeGen/MIRParser/MIRParser.cpp
M llvm/lib/CodeGen/MIRPrinter.cpp
M llvm/lib/CodeGen/MachineFunction.cpp
M llvm/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp
M llvm/lib/IR/Verifier.cpp
M llvm/lib/MC/MCObjectFileInfo.cpp
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
M llvm/lib/Target/ARM/ARMISelLowering.cpp
M llvm/lib/Target/Mips/MipsISelLowering.cpp
M llvm/lib/Target/X86/X86FastISel.cpp
M llvm/lib/Target/X86/X86ISelLoweringCall.cpp
A llvm/test/CodeGen/AArch64/call-site-info-typeid.ll
A llvm/test/CodeGen/ARM/call-site-info-typeid.ll
A llvm/test/CodeGen/MIR/X86/call-site-info-typeid.ll
A llvm/test/CodeGen/MIR/X86/call-site-info-typeid.mir
A llvm/test/CodeGen/Mips/call-site-info-typeid.ll
A llvm/test/CodeGen/X86/call-site-info-typeid.ll
A llvm/test/CodeGen/call-graph-section.ll
M llvm/test/Verifier/operand-bundles.ll
Log Message:
-----------
[𝘀𝗽𝗿] changes introduced through rebase
Created using spr 1.3.6-beta.1
[skip ci]
Commit: feeeeffd924de1c19a800bb1548a786f28711fa6
https://github.com/llvm/llvm-project/commit/feeeeffd924de1c19a800bb1548a786f28711fa6
Author: prabhukr <prabhukr at google.com>
Date: 2024-12-10 (Tue, 10 Dec 2024)
Changed paths:
M clang/include/clang/Basic/CodeGenOptions.def
M clang/include/clang/Driver/Options.td
M clang/lib/CodeGen/BackendUtil.cpp
M clang/lib/CodeGen/CGCall.cpp
M clang/lib/CodeGen/CGExpr.cpp
M clang/lib/Driver/ToolChains/Clang.cpp
M clang/test/CodeGen/call-graph-section-1.cpp
M clang/test/CodeGen/call-graph-section-2.cpp
M clang/test/CodeGen/call-graph-section-3.cpp
M clang/test/CodeGen/call-graph-section.c
A clang/test/Driver/call-graph-section.c
M llvm/include/llvm/CodeGen/AsmPrinter.h
M llvm/include/llvm/CodeGen/CommandFlags.h
M llvm/include/llvm/CodeGen/MIRYamlMapping.h
M llvm/include/llvm/CodeGen/MachineFunction.h
M llvm/include/llvm/MC/MCObjectFileInfo.h
M llvm/include/llvm/Target/TargetOptions.h
M llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
M llvm/lib/CodeGen/CommandFlags.cpp
M llvm/lib/CodeGen/MIRParser/MIRParser.cpp
M llvm/lib/CodeGen/MIRPrinter.cpp
M llvm/lib/CodeGen/MachineFunction.cpp
M llvm/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp
M llvm/lib/IR/Verifier.cpp
M llvm/lib/MC/MCObjectFileInfo.cpp
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
M llvm/lib/Target/ARM/ARMISelLowering.cpp
M llvm/lib/Target/Mips/MipsISelLowering.cpp
M llvm/lib/Target/X86/X86FastISel.cpp
M llvm/lib/Target/X86/X86ISelLoweringCall.cpp
A llvm/test/CodeGen/AArch64/call-site-info-typeid.ll
A llvm/test/CodeGen/ARM/call-site-info-typeid.ll
A llvm/test/CodeGen/MIR/X86/call-site-info-typeid.ll
A llvm/test/CodeGen/MIR/X86/call-site-info-typeid.mir
A llvm/test/CodeGen/Mips/call-site-info-typeid.ll
A llvm/test/CodeGen/X86/call-site-info-typeid.ll
A llvm/test/CodeGen/call-graph-section.ll
M llvm/test/Verifier/operand-bundles.ll
Log Message:
-----------
Reorder commits. Fix clang codegen tests.
Created using spr 1.3.6-beta.1
Compare: https://github.com/llvm/llvm-project/compare/08d0dc10760d...feeeeffd924d
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