[all-commits] [llvm/llvm-project] 97ff96: [AArch64] Improve code generation of bool vector r...

[Csanád Hajdú via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 97ff96173abc0e914d5c8716ccc6356342aca043
      https://github.com/llvm/llvm-project/commit/97ff96173abc0e914d5c8716ccc6356342aca043
  Author: Csanád Hajdú <csanad.hajdu at arm.com>
  Date:   2024-12-10 (Tue, 10 Dec 2024)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
    M llvm/test/CodeGen/AArch64/dag-combine-setcc.ll
    M llvm/test/CodeGen/AArch64/illegal-floating-point-vector-compares.ll
    M llvm/test/CodeGen/AArch64/reduce-and.ll
    M llvm/test/CodeGen/AArch64/reduce-or.ll
    M llvm/test/CodeGen/AArch64/vecreduce-and-legalization.ll
    M llvm/test/CodeGen/AArch64/vecreduce-bool.ll
    M llvm/test/CodeGen/AArch64/vecreduce-umax-legalization.ll
    M llvm/test/CodeGen/AArch64/vector-extract-last-active.ll

  Log Message:
  -----------
  [AArch64] Improve code generation of bool vector reduce operations (#115713)

* Avoid unnecessary truncation of comparison results in vecreduce_xor
* Optimize generated code for vecreduce_and and vecreduce_or by
comparing against 0.0 to check if all/any of the values are set

Alive2 proof of vecreduce_and and vecreduce_or transformation:
https://alive2.llvm.org/ce/z/SRfPtw



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