[all-commits] [llvm/llvm-project] 3083ac: [DAGCombine] Remove oneuse restrictions for RISCV ...

[LiqinWeng via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 3083acc215e9d01c4c41064aa7dd75aeba975e29
      https://github.com/llvm/llvm-project/commit/3083acc215e9d01c4c41064aa7dd75aeba975e29
  Author: LiqinWeng <liqin.weng at spacemit.com>
  Date:   2024-12-10 (Tue, 10 Dec 2024)

  Changed paths:
    M llvm/include/llvm/CodeGen/TargetLowering.h
    M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
    M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
    M llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
    M llvm/lib/Target/ARM/ARMISelLowering.cpp
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    A llvm/test/CodeGen/RISCV/add_sext_shl_constant.ll
    A llvm/test/CodeGen/RISCV/add_shl_constant.ll
    R llvm/test/CodeGen/RISCV/riscv-shifted-extend.ll

  Log Message:
  -----------
  [DAGCombine] Remove oneuse restrictions for RISCV in folding (shl (add_nsw x, c1)), c2) and folding (shl(sext(add x, c1)), c2) in some scenarios (#101294)

This patch remove the restriction for folding (shl (add_nsw x, c1)), c2)
and folding (shl(sext(add x, c1)), c2), and test case from dhrystone ,
see this link:
riscv32: https://godbolt.org/z/o8GdMKrae
riscv64: https://godbolt.org/z/Yh5bPz56z



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