[all-commits] [llvm/llvm-project] 0b0d9a: [CodeGen] [AMDGPU] Attempt DAGCombine for fmul wit...

[Vikash Gupta via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 0b0d9a3bee47e9de05e869be306284fa66533f63
      https://github.com/llvm/llvm-project/commit/0b0d9a3bee47e9de05e869be306284fa66533f63
  Author: Vikash Gupta <Vikash.Gupta at amd.com>
  Date:   2024-12-09 (Mon, 09 Dec 2024)

  Changed paths:
    M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
    M llvm/lib/Target/AMDGPU/SIISelLowering.h
    M llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-pow-codegen.ll
    M llvm/test/CodeGen/AMDGPU/bf16.ll
    M llvm/test/CodeGen/AMDGPU/copysign-simplify-demanded-bits.ll
    M llvm/test/CodeGen/AMDGPU/dagcombine-fmul-sel.ll
    M llvm/test/CodeGen/AMDGPU/fdiv_flags.f32.ll
    M llvm/test/CodeGen/AMDGPU/fmul-to-ldexp.ll
    M llvm/test/CodeGen/AMDGPU/fsqrt.f32.ll
    M llvm/test/CodeGen/AMDGPU/llvm.exp2.ll
    M llvm/test/CodeGen/AMDGPU/llvm.log.ll
    M llvm/test/CodeGen/AMDGPU/llvm.log10.ll
    M llvm/test/CodeGen/AMDGPU/llvm.log2.ll
    M llvm/test/CodeGen/AMDGPU/pseudo-scalar-transcendental.ll
    M llvm/test/CodeGen/AMDGPU/rsq.f32.ll

  Log Message:
  -----------
  [CodeGen] [AMDGPU] Attempt DAGCombine for fmul with select to ldexp (#111109)

The materialization cost of 32-bit non-inline in case of fmul is quite
relatively more, rather than if possible to combine it into ldexp
instruction for specific scenarios (for datatypes like f64, f32 and f16)
as this is being handled here :

The dag combine for any pair of select values which are exact exponent
of 2.

```
fmul x, select(y, A, B)       -> ldexp (x, select i32 (y, a, b))
fmul x, select(y, -A, -B)    -> ldexp ((fneg x), select i32 (y, a, b))

where, A=2^a & B=2^b ; a and b are integers.  
```

This dagCombine is handled separately in fmulCombine (newly defined in
SIIselLowering), targeting fmul fusing it with select type operand into
ldexp.

Thus, it fixes #104900.



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