[all-commits] [llvm/llvm-project] 495816: [RISCV] Add i16->i32 G_ZEXT/G_SEXT patterns for RV64.

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 495816cbc83b0760442568da18317df0955a289f
      https://github.com/llvm/llvm-project/commit/495816cbc83b0760442568da18317df0955a289f
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2024-12-06 (Fri, 06 Dec 2024)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVGISel.td
    M llvm/test/CodeGen/RISCV/GlobalISel/rv64zbb.ll
    M llvm/test/CodeGen/RISCV/GlobalISel/rv64zbkb.ll

  Log Message:
  -----------
  [RISCV] Add i16->i32 G_ZEXT/G_SEXT patterns for RV64.

Because we support s16 and s32 types for FP some operations like
G_PHI, G_SELECT, G_FREEZE can exist with s16 and s32 operands
even when they will be assigned to the GPR reg bank. These
instructions can be surrounded with G_ZEXT and G_SEXT that convert
from s16 to s32 so we need to be able to select them.



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