[all-commits] [llvm/llvm-project] 02ad62: [RISCV] Prefer strided store for interleave store ...

[Philip Reames via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 02ad623bb560afa1a789b49f715c9a0e48ea9b16
      https://github.com/llvm/llvm-project/commit/02ad623bb560afa1a789b49f715c9a0e48ea9b16
  Author: Philip Reames <preames at rivosinc.com>
  Date:   2024-12-06 (Fri, 06 Dec 2024)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-interleaved-access.ll

  Log Message:
  -----------
  [RISCV] Prefer strided store for interleave store with one lane active (#119027)

If we're performing a segment store and all but one of the segments are
undefined, that's equivalent to performing a strided store of the one
active segment.

This is the store side of a905203b. As before, this only covers fixed
vectors.



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