[all-commits] [llvm/llvm-project] 7f4414: [AArch64] Generate zeroing forms of certain SVE2.2...

[Momchil Velikov via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 7f4414b2a1a4d9f802a03f56894c406f0fe3e9a9
      https://github.com/llvm/llvm-project/commit/7f4414b2a1a4d9f802a03f56894c406f0fe3e9a9
  Author: Momchil Velikov <momchil.velikov at arm.com>
  Date:   2024-12-06 (Fri, 06 Dec 2024)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
    M llvm/lib/Target/AArch64/SVEInstrFormats.td
    A llvm/test/CodeGen/AArch64/zeroing-forms-fcvtzsu.ll

  Log Message:
  -----------
  [AArch64] Generate zeroing forms of certain SVE2.2 instructions (4/11)  (#116830)

SVE2.2 introduces instructions with predicated forms with zeroing of
the inactive lanes. This allows in some cases to save a `movprfx` or
a `mov` instruction when emitting code for `_x` or `_z` variants of
intrinsics.

This patch adds support for emitting the zeroing forms of certain
`FCVTZS`, and `FCVTZU` instructions.



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