[all-commits] [llvm/llvm-project] 1c0b4b: [CodeGen][PM] Initialize analyses with isAnalysis=...

Akshat Oke via All-commits all-commits at lists.llvm.org
Fri Dec 6 01:50:22 PST 2024


  Branch: refs/heads/users/Akshat-Oke/12-05-_codegen_pm_initialize_analyses_with_isanalysis_true
  Home:   https://github.com/llvm/llvm-project
  Commit: 1c0b4ba5988e15e15c24d24d531dc319d6e71d7a
      https://github.com/llvm/llvm-project/commit/1c0b4ba5988e15e15c24d24d531dc319d6e71d7a
  Author: Akshat Oke <Akshat.Oke at amd.com>
  Date:   2024-12-06 (Fri, 06 Dec 2024)

  Changed paths:
    M llvm/lib/CodeGen/GCMetadata.cpp
    M llvm/lib/CodeGen/LiveDebugVariables.cpp
    M llvm/lib/CodeGen/LiveIntervals.cpp
    M llvm/lib/CodeGen/LiveRegMatrix.cpp
    M llvm/lib/CodeGen/LiveStacks.cpp
    M llvm/lib/CodeGen/SlotIndexes.cpp
    M llvm/lib/CodeGen/VirtRegMap.cpp
    M llvm/lib/Transforms/Utils/LoopSimplify.cpp

  Log Message:
  -----------
  [CodeGen][PM] Initialize analyses with isAnalysis=true

Analyses should be marked as analyses else they are prone to be ignored
by the legacy analysis cache mechanism and get scheduled redundantly.


  Commit: 6cf8e8d33e178d1d23d34833cfae777507744227
      https://github.com/llvm/llvm-project/commit/6cf8e8d33e178d1d23d34833cfae777507744227
  Author: Akshat Oke <Akshat.Oke at amd.com>
  Date:   2024-12-06 (Fri, 06 Dec 2024)

  Changed paths:
    M llvm/lib/CodeGen/SlotIndexes.cpp

  Log Message:
  -----------
  keep slot indexes as pass


Compare: https://github.com/llvm/llvm-project/compare/41aff6669780...6cf8e8d33e17

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