[all-commits] [llvm/llvm-project] f893b4: [ARM] Fix instruction selection for MVE vsbciq int...

[Oliver Stannard via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: f893b475004fdea48288f329124817325e659792
      https://github.com/llvm/llvm-project/commit/f893b475004fdea48288f329124817325e659792
  Author: Oliver Stannard <oliver.stannard at arm.com>
  Date:   2024-12-06 (Fri, 06 Dec 2024)

  Changed paths:
    M clang/include/clang/Basic/arm_mve.td
    M clang/test/CodeGen/arm-mve-intrinsics/vadc.c
    M llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
    M llvm/test/CodeGen/Thumb2/mve-intrinsics/vadc.ll
    M llvm/test/CodeGen/Thumb2/mve-vadc-vsbc-spill.ll

  Log Message:
  -----------
  [ARM] Fix instruction selection for MVE vsbciq intrinsic (#118284)

There were two bugs in the implementation of the MVE vsbciq (subtract
with carry across vector, with initial carry value) intrinsics:
* The VSBCI instruction behaves as if the carry-in is always set, but we
were selecting it when the carry-in is clear.
* The vsbciq intrinsics should generate IR with the carry-in set, but
they were leaving it clear.

These two bugs almost cancelled each other out, but resulted in
incorrect code when the vsbcq intrinsics (with a carry-in) were used,
and the carry-in was a compile time constant.



To unsubscribe from these emails, change your notification settings at https://github.com/llvm/llvm-project/settings/notifications